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pr=C From: Ayan Kumar Halder To: , , , , , , CC: Subject: [PATCH v2 2/3] xen: arm: Introduce CONFIG_PARTIAL_EMULATION Date: Mon, 18 Dec 2023 20:33:22 +0000 Message-ID: <20231218203322.1394097-1-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|DS0PR12MB7873:EE_ X-MS-Office365-Filtering-Correlation-Id: 023e7c54-eeb8-4d7d-7a7b-08dc000899db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: N8Mx+MHNnKjeu6Zp74UYCkwWdisVn+xJLwGb0kafpnPcwRljrIa2OwS+jLky4wIf2DsZN+0jBEkXcO79izp3GzPy4ms57ocsxMtzb8r2kNwKQj9wysZ4D8mdH/V2q5BZQ1HLfzgMOB/p8YVtj18/SugOWAqnfUWg+LuaaFVlD+0oct5ueaishIyUZWEft1a+3Vn0kubrXz+pOZ6SFdQKQ4IAfyzHlDs2A+fzlgmZcvpGbI3DrM5MOn4GU9b669nGfN577T1ptRmbSLyueyUQr+r8JRATsLSdXPPOgFQVlojgMv6wHGJ7557QNfibPSTgZ6O6R8d/M59ZgVPvL0LzTGMSyFHnL+tRh21OxvFMoqdBzL2ddTTKIMv1Om6vWIw0iqwWTJXaJG7uK7nisWuyEv06Ut2xAz9bmB+HvNnleIJ7rcnByIwyqesDeAtTjo0v07Us9KCztnXRpaVAakYB8pv3rDvKuJtaRUJ/C5GEfgCLZhc1KfcXxq3tOdI4mxb5wQH0/xSjNYgiiqVDexsqf6oCf7xVK3P62WsCltztZgp3I+NNSVMkcz3sbuvm2GLQUWUwPgJ6H3/ZzPmogTbpKFDikmidDsRFdEReMGiej7sTZQlvNKbg4ukFAOe7N+u6dqc/BrXbXD1VOxobU1Ei9dYvystiprt7z/6JbNvNHVM1yoOMay8eqA2Xw7WjfjYpfir0J+UpILHqrwRuyVa3kIM3NZexcpmhnU9mWdUULjoLcy35LpUrvAdPMcfXsj79h7c1CPiZ5TpBsfX0PcI7/g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(396003)(136003)(39860400002)(230922051799003)(451199024)(1800799012)(64100799003)(82310400011)(186009)(46966006)(40470700004)(36840700001)(26005)(336012)(83380400001)(426003)(2616005)(36860700001)(6636002)(1076003)(47076005)(4326008)(5660300002)(41300700001)(110136005)(2906002)(478600001)(8676002)(316002)(8936002)(6666004)(70586007)(70206006)(103116003)(86362001)(36756003)(82740400003)(356005)(81166007)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2023 20:33:31.9553 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 023e7c54-eeb8-4d7d-7a7b-08dc000899db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7873 There are can be situations when the registers cannot be emulated to its full functionality. This can be due to the complexity involved. In such cases, we can emulate those registers as RAZ/WI. A suitable example of this is DBGDTRTX_EL0 (on Arm64) and DBGDTRTXINT(on Arm32). As this register is not optional, guests may try to access this. Currently, this would result in a crash. With this patch, Xen will emulated this as RAZ/WI and the crash will be avoided. Such partial emulations will be enclosed within CONFIG_PARTIAL_EMULATION. Also "CONFIG_PARTIAL_EMULATION" is default to y, so that Xen does not need to be rebuilt in order to prevent guest from crashing while accessing registers like DBGDTRTX_EL0. Signed-off-by: Ayan Kumar Halder --- Changes from v1:- 1. New patch introduced in v2. xen/arch/arm/Kconfig | 8 ++++++++ xen/arch/arm/arm64/vsysreg.c | 3 +++ xen/arch/arm/vcpreg.c | 2 ++ 3 files changed, 13 insertions(+) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 50e9bfae1a..8f25d9cba0 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -225,6 +225,14 @@ config STATIC_EVTCHN This option enables establishing static event channel communication between domains on a dom0less system (domU-domU as well as domU-dom0). +config PARTIAL_EMULATION + bool "Enable partial emulation for registers" + default y + help + This option enabled partial emulation for registers to avoid guests + crashing when accessing registers which are not optional but has not been + emulated to its complete functionality. + endmenu menu "ARM errata workaround via the alternative framework" diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index ebeb83dd65..0fa8716884 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -188,10 +188,13 @@ void do_sysreg(struct cpu_user_regs *regs, return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 0, 1U << 29); } +#ifdef CONFIG_PARTIAL_EMULATION case HSR_SYSREG_DBGDTR_EL0: /* DBGDTR[TR]X_EL0 share the same encoding */ case HSR_SYSREG_DBGDTRTX_EL0: return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0); +#endif + HSR_SYSREG_DBG_CASES(DBGBVR): HSR_SYSREG_DBG_CASES(DBGBCR): HSR_SYSREG_DBG_CASES(DBGWVR): diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 5087125111..52a8732423 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -575,6 +575,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) case HSR_CPREG32(DBGOSLSR): return handle_ro_read_val(regs, regidx, cp32.read, hsr, 1, 1 << 3); +#ifdef CONFIG_PARTIAL_EMULATION case HSR_CPREG32(DBGDTRTXINT): { /* @@ -584,6 +585,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 0); } +#endif case HSR_CPREG32(DBGVCR): case HSR_CPREG32(DBGBVR0): From patchwork Mon Dec 18 20:33:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13497570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D24BEC35274 for ; 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bh=smYuQZK3qvIyePU2wMqadUuqF2Ed1vqa9lCU8cNIDlI=; b=j048MfKM6lNd5D1smEapVQnh8heSRVPLJes3syCQtpeu5X2rXoiMJdWObH4gZ6kYJVl+/hYUeZChSZj/2h7ACFUqsY5PRdJCBB6Z4+N8y/htfiN8igsX7frGrah1GRM1NfmBEr2eGKuDCjCur3QPbMRUUj42lLTPanXXW2Ygfes= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: , , , , , , CC: Subject: [PATCH v2 3/3] xen/arm: Introduce "partial-emulation" xen command line option Date: Mon, 18 Dec 2023 20:33:39 +0000 Message-ID: <20231218203339.1394354-1-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CC:EE_|DM6PR12MB4076:EE_ X-MS-Office365-Filtering-Correlation-Id: 9867b0e7-f1eb-47d0-9712-08dc0008a07d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2023 20:33:43.1153 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9867b0e7-f1eb-47d0-9712-08dc0008a07d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4076 This option is used to enable/disable partial emulation of registers at runtime. While CONFIG_PARTIAL_EMULATION enables support for partial emulation at compile time (ie adds code for partial emulation), this option may be enabled or disabled by Yocto or other build systems. However, customers can use scripts like Imagebuilder to generate uboot script for booting Xen. These scripts can use "partial-emulation=true" to support this at runtime. This option is set to false by default so that customers are fully aware when they enable partial emulation. They can also disable it without the need to rebuild Xen. Signed-off-by: Ayan Kumar Halder --- Changes from v1:- 1. New patch introduced in v2. docs/misc/xen-command-line.pandoc | 7 +++++++ xen/arch/arm/arm64/vsysreg.c | 5 ++++- xen/arch/arm/include/asm/regs.h | 6 ++++++ xen/arch/arm/traps.c | 3 +++ xen/arch/arm/vcpreg.c | 17 +++++++++++------ 5 files changed, 31 insertions(+), 7 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 8e65f8bd18..dd2a76fb19 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1949,6 +1949,13 @@ This option is ignored in **pv-shim** mode. > Default: `on` +### partial-emulation (arm) +> `= ` + +> Default: `false` + +Flag to enable or disable partial emulation of registers + ### pci = List of [ serr=, perr= ] diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 0fa8716884..02497c9fef 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -192,7 +192,10 @@ void do_sysreg(struct cpu_user_regs *regs, case HSR_SYSREG_DBGDTR_EL0: /* DBGDTR[TR]X_EL0 share the same encoding */ case HSR_SYSREG_DBGDTRTX_EL0: - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0); + if ( opt_partial_emulation ) + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0); + else + goto fail; #endif HSR_SYSREG_DBG_CASES(DBGBVR): diff --git a/xen/arch/arm/include/asm/regs.h b/xen/arch/arm/include/asm/regs.h index f998aedff5..b71fa20f91 100644 --- a/xen/arch/arm/include/asm/regs.h +++ b/xen/arch/arm/include/asm/regs.h @@ -13,6 +13,12 @@ #define psr_mode(psr,m) (((psr) & PSR_MODE_MASK) == (m)) +/* + * opt_partial_emulation: If true, partial emulation for registers will be + * enabled. + */ +extern bool opt_partial_emulation; + static inline bool regs_mode_is_32bit(const struct cpu_user_regs *regs) { #ifdef CONFIG_ARM_32 diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index f5ab555b19..c8c00d2dd5 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -42,6 +42,9 @@ #include #include +bool opt_partial_emulation = false; +boolean_param("partial-emulation", opt_partial_emulation); + /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in * entry.S) and struct cpu_info (which lives at the bottom of a Xen diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 52a8732423..6bf417487a 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -578,12 +578,17 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) #ifdef CONFIG_PARTIAL_EMULATION case HSR_CPREG32(DBGDTRTXINT): { - /* - * As DBGDSCRINT is emulated which is architecturally mapped to AArch64 - * register MDCCSR_EL0. MDSCR_EL1 is not emulated. So DBGDTR[TR]XINT can - * only be accessed as EL0 level. - */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 0); + if ( opt_partial_emulation ) + { + /* + * As DBGDSCRINT is emulated which is architecturally mapped to + * AArch64 register MDCCSR_EL0. MDSCR_EL1 is not emulated. So + * DBGDTR[TR]XINT can only be accessed as EL0 level. + */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 0); + } + else + goto fail; } #endif