From patchwork Thu Dec 21 09:32:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501519 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B20D24D125; Thu, 21 Dec 2023 09:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="j6+57GUf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151188; x=1734687188; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UDMw+55Cl3aF1QubHYTr8F0l7Gi7wc+yanz1auj4l2s=; b=j6+57GUfIk9UUzJnhAavrak3smVz+x7VkOIJL1ciM8LeLvLL48p11JA/ 7/W6RvG6pPaw+2tY9cD6Wt+PNZZU+yD/1YdhHI8DIuS0BlPKZu0FBOj6E DWgw5CtLA2mRtXAsznOwHQSCwoGkj500uyuKoUKNRqaXtMZUw+RXeEyWE v+hqnFj6Vxtokt3C3Fptpq6bqWrvwbmuRwTFIyymcRJwGK8Hw6IkdVzMJ T7XxoVGex0DSEyj1CunVpDYSV+kEYtifzX8Pm/+14VANdvrHdtIdF1hc/ QUaVhHbUBzWw3R3In7FdldFoL1F/CDwpgbouEFczkvru6+noXjkn+ERuD A==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188450" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188450" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918135" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918135" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:02 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 01/10] x86/tsc: Add base clock properties in clocksource structure Date: Thu, 21 Dec 2023 15:02:45 +0530 Message-Id: <20231221093254.9599-2-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-State: RFC From: Lakshmi Sowjanya D Remove convert_art_to_tsc() and convert_art_ns_to_tsc(), as this patch series introduces a generic function ktime_real_to_base_clock() to convert realtime to base clock domain. Add hardware abstraction, struct clocksource_base in clocksource. Add clocksource ID for x86 ART(Always Running Timer). Co-developed-by: Thomas Gleixner Signed-off-by: Thomas Gleixner Co-developed-by: Christopher S. Hall Signed-off-by: Christopher S. Hall Signed-off-by: Lakshmi Sowjanya D --- arch/x86/include/asm/tsc.h | 3 -- arch/x86/kernel/tsc.c | 94 +++++++-------------------------- include/linux/clocksource.h | 27 ++++++++++ include/linux/clocksource_ids.h | 1 + 4 files changed, 47 insertions(+), 78 deletions(-) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 594fce0ca744..5e36495cc821 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -27,9 +27,6 @@ static inline cycles_t get_cycles(void) } #define get_cycles get_cycles -extern struct system_counterval_t convert_art_to_tsc(u64 art); -extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns); - extern void tsc_early_init(void); extern void tsc_init(void); extern void mark_tsc_unstable(char *reason); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 868f09966b0f..b45ce594cfef 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -51,9 +51,9 @@ int tsc_clocksource_reliable; static int __read_mostly tsc_force_recalibrate; -static u32 art_to_tsc_numerator; -static u32 art_to_tsc_denominator; -static u64 art_to_tsc_offset; +static struct clocksource_base art_base_clk = { + .id = CSID_X86_ART, +}; static bool have_art; struct cyc2ns { @@ -1075,7 +1075,7 @@ core_initcall(cpufreq_register_tsc_scaling); */ static void __init detect_art(void) { - unsigned int unused[2]; + unsigned int unused; if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) return; @@ -1090,13 +1090,14 @@ static void __init detect_art(void) tsc_async_resets) return; - cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, - &art_to_tsc_numerator, unused, unused+1); + cpuid(ART_CPUID_LEAF, &art_base_clk.denominator, + &art_base_clk.numerator, &art_base_clk.freq_khz, &unused); - if (art_to_tsc_denominator < ART_MIN_DENOMINATOR) + art_base_clk.freq_khz /= KHZ; + if (art_base_clk.denominator < ART_MIN_DENOMINATOR) return; - rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset); + rdmsrl(MSR_IA32_TSC_ADJUST, art_base_clk.offset); /* Make this sticky over multiple CPU init calls */ setup_force_cpu_cap(X86_FEATURE_ART); @@ -1297,69 +1298,6 @@ int unsynchronized_tsc(void) return 0; } -/* - * Convert ART to TSC given numerator/denominator found in detect_art() - */ -struct system_counterval_t convert_art_to_tsc(u64 art) -{ - u64 tmp, res, rem; - - rem = do_div(art, art_to_tsc_denominator); - - res = art * art_to_tsc_numerator; - tmp = rem * art_to_tsc_numerator; - - do_div(tmp, art_to_tsc_denominator); - res += tmp + art_to_tsc_offset; - - return (struct system_counterval_t) { - .cs_id = have_art ? CSID_X86_TSC : CSID_GENERIC, - .cycles = res - }; -} -EXPORT_SYMBOL(convert_art_to_tsc); - -/** - * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC. - * @art_ns: ART (Always Running Timer) in unit of nanoseconds - * - * PTM requires all timestamps to be in units of nanoseconds. When user - * software requests a cross-timestamp, this function converts system timestamp - * to TSC. - * - * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set - * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check - * that this flag is set before conversion to TSC is attempted. - * - * Return: - * struct system_counterval_t - system counter value with the ID of the - * corresponding clocksource - * @cycles: System counter value - * @cs_id: Clocksource ID corresponding to system counter value. - * Used by timekeeping code to verify comparability of two - * cycle values. - */ - -struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) -{ - u64 tmp, res, rem; - - rem = do_div(art_ns, USEC_PER_SEC); - - res = art_ns * tsc_khz; - tmp = rem * tsc_khz; - - do_div(tmp, USEC_PER_SEC); - res += tmp; - - return (struct system_counterval_t) { - .cs_id = have_art ? CSID_X86_TSC : CSID_GENERIC, - .cycles = res - }; -} -EXPORT_SYMBOL(convert_art_ns_to_tsc); - - static void tsc_refine_calibration_work(struct work_struct *work); static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); /** @@ -1461,8 +1399,10 @@ static void tsc_refine_calibration_work(struct work_struct *work) if (tsc_unstable) goto unreg; - if (boot_cpu_has(X86_FEATURE_ART)) + if (boot_cpu_has(X86_FEATURE_ART)) { have_art = true; + clocksource_tsc.base = &art_base_clk; + } clocksource_register_khz(&clocksource_tsc, tsc_khz); unreg: clocksource_unregister(&clocksource_tsc_early); @@ -1487,8 +1427,10 @@ static int __init init_tsc_clocksource(void) * the refined calibration and directly register it as a clocksource. */ if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { - if (boot_cpu_has(X86_FEATURE_ART)) + if (boot_cpu_has(X86_FEATURE_ART)) { have_art = true; + clocksource_tsc.base = &art_base_clk; + } clocksource_register_khz(&clocksource_tsc, tsc_khz); clocksource_unregister(&clocksource_tsc_early); @@ -1512,10 +1454,12 @@ static bool __init determine_cpu_tsc_frequencies(bool early) if (early) { cpu_khz = x86_platform.calibrate_cpu(); - if (tsc_early_khz) + if (tsc_early_khz) { tsc_khz = tsc_early_khz; - else + } else { tsc_khz = x86_platform.calibrate_tsc(); + clocksource_tsc.freq_khz = tsc_khz; + } } else { /* We should not be here with non-native cpu calibration */ WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu); diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 1d42d4b17327..0a1110a0e660 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -21,6 +21,7 @@ #include #include +struct clocksource_base; struct clocksource; struct module; @@ -48,6 +49,7 @@ struct module; * @archdata: Optional arch-specific data * @max_cycles: Maximum safe cycle value which won't overflow on * multiplication + * @freq_khz: Clocksource frequency in khz. * @name: Pointer to clocksource name * @list: List head for registration (internal) * @rating: Rating value for selection (higher is better) @@ -70,6 +72,8 @@ struct module; * validate the clocksource from which the snapshot was * taken. * @flags: Flags describing special properties + * @base: Hardware abstraction for clock on which a clocksource + * is based * @enable: Optional function to enable the clocksource * @disable: Optional function to disable the clocksource * @suspend: Optional suspend function for the clocksource @@ -105,12 +109,14 @@ struct clocksource { struct arch_clocksource_data archdata; #endif u64 max_cycles; + u32 freq_khz; const char *name; struct list_head list; int rating; enum clocksource_ids id; enum vdso_clock_mode vdso_clock_mode; unsigned long flags; + struct clocksource_base *base; int (*enable)(struct clocksource *cs); void (*disable)(struct clocksource *cs); @@ -294,4 +300,25 @@ static inline void timer_probe(void) {} extern ulong max_cswd_read_retries; void clocksource_verify_percpu(struct clocksource *cs); +/** + * struct clocksource_base - hardware abstraction for clock on which a clocksource + * is based + * @id: Defaults to CSID_GENERIC. The id value is used for conversion + * functions which require that the current clocksource is based + * on a clocksource_base with a particular ID in certain snapshot + * functions to allow callers to validate the clocksource from + * which the snapshot was taken. + * @freq_khz: Nominal frequency of the base clock in kHz + * @offset: Offset between the base clock and the clocksource + * @numerator: Numerator of the clock ratio between base clock and the clocksource + * @denominator: Denominator of the clock ratio between base clock and the clocksource + */ +struct clocksource_base { + enum clocksource_ids id; + u32 freq_khz; + u64 offset; + u32 numerator; + u32 denominator; +}; + #endif /* _LINUX_CLOCKSOURCE_H */ diff --git a/include/linux/clocksource_ids.h b/include/linux/clocksource_ids.h index a4fa3436940c..2bb4d8c2f1b0 100644 --- a/include/linux/clocksource_ids.h +++ b/include/linux/clocksource_ids.h @@ -9,6 +9,7 @@ enum clocksource_ids { CSID_X86_TSC_EARLY, CSID_X86_TSC, CSID_X86_KVM_CLK, + CSID_X86_ART, CSID_MAX, }; From patchwork Thu Dec 21 09:32:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501520 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DC4D4D595; Thu, 21 Dec 2023 09:33:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XC4QY3a5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151195; x=1734687195; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w+aeq0HJvcCZ+KS3uPOjGfoNyocIUqM1MwjS66a3tiI=; b=XC4QY3a5A6+zQcUxTwHu1uxvDbzsWZ80OurfOOGznVs0l3rf5vfFQOrR mHNHrLnanQn1MCgttgqhnHPLr+RlaM/Hko+4hcznSJAieTHKoFse3EWdI j5l1Hg4y+RUzjPHJ58rM8zwLtH4SOCd0uVOPpaFM1G/zPR05cA8p5q8Y7 jWEk2lrEmjZK3h+lnG25x2wxKliULUFJdpNjRByH5nwQ+KFvA5riGgATn umXY4Zn2Xjw3EqlOYga2APafC0aDmmhduMz9uxNNYi2buHoS+6h90VCrT wbaT7ntxb2hvgyO4fyd3wrgH2Hh8asVv94rmBPo3PVPtRcWrU/hbvdqm5 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188474" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188474" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918161" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918161" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:08 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 02/10] timekeeping: Add function to convert realtime to base clock Date: Thu, 21 Dec 2023 15:02:46 +0530 Message-Id: <20231221093254.9599-3-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-State: RFC From: Lakshmi Sowjanya D Introduce an interface ktime_real_to_base_clock(), to convert realtime to base clock. Convert base clock to system clock using convert_base_to_cs() in get_device_system_crosststamp(). Add a helper function to check whether the current clocksource has same base clock. Co-developed-by: Thomas Gleixner Signed-off-by: Thomas Gleixner Co-developed-by: Christopher S. Hall Signed-off-by: Christopher S. Hall Signed-off-by: Lakshmi Sowjanya D --- include/linux/timekeeping.h | 6 ++ kernel/time/timekeeping.c | 112 +++++++++++++++++++++++++++++++++++- 2 files changed, 116 insertions(+), 2 deletions(-) diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index 0f00f382bb5d..2c3bc2eac974 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -274,12 +274,18 @@ struct system_device_crosststamp { * timekeeping code to verify comparability of two cycle values. * The default ID, CSID_GENERIC, does not identify a specific * clocksource. + * @nsecs: @cycles is in nanoseconds. */ struct system_counterval_t { u64 cycles; enum clocksource_ids cs_id; + bool nsecs; }; +extern bool ktime_real_to_base_clock(ktime_t treal, + enum clocksource_ids base_id, u64 *cycles); +extern bool timekeeping_clocksource_has_base(enum clocksource_ids id); + /* * Get cross timestamp between system clock and device clock */ diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index 0ff065c5d25b..e68ecd77ee34 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -1191,6 +1191,89 @@ static bool cycle_between(u64 before, u64 test, u64 after) return false; } +static bool convert_clock(u64 *val, u32 numerator, u32 denominator) +{ + u64 rem, res; + + if (numerator == 0 || denominator == 0) + return false; + + res = div64_u64_rem(*val, denominator, &rem) * numerator; + *val = res + div_u64(rem * numerator, denominator); + return true; +} + +static bool convert_base_to_cs(struct system_counterval_t *scv) +{ + struct clocksource *cs = tk_core.timekeeper.tkr_mono.clock; + struct clocksource_base *base = cs->base; + + /* The timestamp was taken from the time keeper clock source */ + if (cs->id == scv->cs_id) + return true; + + /* Check whether cs_id matches the base clock */ + if (!base || base->id != scv->cs_id) + return false; + + /* Avoid conversion to a less precise clock */ + if (scv->nsecs && cs->freq_khz != 0 && base->freq_khz < cs->freq_khz) { + if (!convert_clock(&scv->cycles, cs->freq_khz, USEC_PER_SEC)) + return false; + } else { + if (scv->nsecs) { + if (!convert_clock(&scv->cycles, base->freq_khz, USEC_PER_SEC)) + return false; + } + if (!convert_clock(&scv->cycles, base->numerator, base->denominator)) + return false; + } + scv->cycles += base->offset; + return true; +} + +static bool convert_cs_to_base(u64 *cycles, enum clocksource_ids base_id) +{ + struct clocksource *cs = tk_core.timekeeper.tkr_mono.clock; + struct clocksource_base *base = cs->base; + + /* Check whether base_id matches the base clock */ + if (!base || base->id != base_id) + return false; + + *cycles -= base->offset; + if (!convert_clock(cycles, base->denominator, base->numerator)) + return false; + return true; +} + +static u64 convert_ns_to_cs(u64 delta) +{ + struct tk_read_base *tkr = &tk_core.timekeeper.tkr_mono; + + return div_u64((delta << tkr->shift) - tkr->xtime_nsec, tkr->mult); +} + +bool ktime_real_to_base_clock(ktime_t treal, enum clocksource_ids base_id, u64 *cycles) +{ + struct timekeeper *tk = &tk_core.timekeeper; + unsigned int seq; + u64 delta; + + do { + seq = read_seqcount_begin(&tk_core.seq); + delta = (u64)treal - tk->tkr_mono.base_real; + if (delta > tk->tkr_mono.clock->max_idle_ns) + return false; + *cycles = tk->tkr_mono.cycle_last + convert_ns_to_cs(delta); + if (!convert_cs_to_base(cycles, base_id)) + return false; + } while (read_seqcount_retry(&tk_core.seq, seq)); + + return true; +} +EXPORT_SYMBOL_GPL(ktime_real_to_base_clock); + /** * get_device_system_crosststamp - Synchronously capture system/device timestamp * @get_time_fn: Callback to get simultaneous device time and @@ -1236,8 +1319,7 @@ int get_device_system_crosststamp(int (*get_time_fn) * system counter value is the same as for the currently * installed timekeeper clocksource */ - if (system_counterval.cs_id == CSID_GENERIC || - tk->tkr_mono.clock->id != system_counterval.cs_id) + if (!convert_base_to_cs(&system_counterval)) return -ENODEV; cycles = system_counterval.cycles; @@ -1304,6 +1386,32 @@ int get_device_system_crosststamp(int (*get_time_fn) } EXPORT_SYMBOL_GPL(get_device_system_crosststamp); +/** + * timekeeping_clocksource_has_base - Check whether the current clocksource + * has a base clock + * @id: The clocksource ID to check for + * + * Note: The return value is a snapshot which can become invalid right + * after the function returns. + * + * Return: true if the timekeeper clocksource has a base clock with @id, + * false otherwise + */ +bool timekeeping_clocksource_has_base(enum clocksource_ids id) +{ + unsigned int seq; + bool ret; + + do { + seq = read_seqcount_begin(&tk_core.seq); + ret = tk_core.timekeeper.tkr_mono.clock->base ? + tk_core.timekeeper.tkr_mono.clock->base->id == id : false; + } while (read_seqcount_retry(&tk_core.seq, seq)); + + return ret; +} +EXPORT_SYMBOL_GPL(timekeeping_clocksource_has_base); + /** * do_settimeofday64 - Sets the time of day. * @ts: pointer to the timespec64 variable containing the new time From patchwork Thu Dec 21 09:32:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501521 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C671F4E1C3; Thu, 21 Dec 2023 09:33:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PS9s22oN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151202; x=1734687202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PmpIlUpx7+DXd9SlbVWYDCreHkh1wtkoXMr9WfcfHRg=; b=PS9s22oNcCafNoLKz47o1xVCyQ9j9PUPSKuWE5NJeI+bCi7sGOdDOQrM HsKXqAjK9DKs2la99kAFgAjKNSg4PfDMBRga0EWfVPV7Lfj24k9REx84M ulm1KLw+o4hZ7ZrCYklv2EgJ2ocB5dEmb3Mo426eMe20VIMXYxdmqgmOI I5qRZnaLylsx7bY+TSIlNwabxJovFU+jd3oPOXBSD3UKj3MhvVsvkZTLA 9SUFnEjAbJm72ivyc2QZN63U5VYBz0FPLfmNdCBWTsdH7CPdxrTvDFnmh sf/V/4u4XL4Mj8buWOoec0+lDioNbsxOzlZwIPNSL5dj+5+M/eqBNUUYj A==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188505" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188505" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918187" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918187" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:15 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 03/10] e10002: remove convert_art_to_tsc() Date: Thu, 21 Dec 2023 15:02:47 +0530 Message-Id: <20231221093254.9599-4-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC From: Thomas Gleixner Remove convert_art_to_tsc() function call, Pass system clock cycles and clocksource ID as input to get_device_system_crosststamp(). Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/e1000e/ptp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/e1000e/ptp.c b/drivers/net/ethernet/intel/e1000e/ptp.c index 02d871bc112a..9d8be03a9827 100644 --- a/drivers/net/ethernet/intel/e1000e/ptp.c +++ b/drivers/net/ethernet/intel/e1000e/ptp.c @@ -124,7 +124,8 @@ static int e1000e_phc_get_syncdevicetime(ktime_t *device, sys_cycles = er32(PLTSTMPH); sys_cycles <<= 32; sys_cycles |= er32(PLTSTMPL); - *system = convert_art_to_tsc(sys_cycles); + system->cycles = sys_cycles; + system->cs_id = CSID_X86_ART; return 0; } From patchwork Thu Dec 21 09:32:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501522 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47F5551C26; Thu, 21 Dec 2023 09:33:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="e95KwguN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151208; x=1734687208; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FqzmFJD7Hjfw0d9iCOZZDYcOM+cgVL/B/wnjWMOn7QY=; b=e95KwguNwJeVqKo/gHrw5AfYu7+2068kw+T9iK2A+wkUq4GLTwb8fSR2 yVtIISvmdJELyd4juX/Gc7cFeFXELoAe8GGnKsnUd/XiaxT3Vhml2hEJV S2wyilF4IVHeT/d7TF8geYMp/Bchtu0EsZjPmd8Zo/WVzXmgbvxcMqRyA zWlqyJJP71LxwpMmTJLFDNxbxH2e/bBtXHiE/Qukv674oh8K17FOaiiFy pMzmhj++xDbpJsY9k0ULQDE7kIjb8osPJ6sg6XccQwBetghcBFNHQhdB9 9EuEV0cxJPopUaAX2+MJ4l23bcVG3Qr+PDFFt+/xkNrrrqbbWC4jVJ9XP A==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188551" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188551" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918202" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918202" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:21 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 04/10] igc: remove convert_art_to_tsc() Date: Thu, 21 Dec 2023 15:02:48 +0530 Message-Id: <20231221093254.9599-5-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC From: Thomas Gleixner Remove convert_art_to_tsc() function call, Pass system clock cycles and clocksource ID as input to get_device_system_crosststamp(). Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/igc/igc_ptp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index 928f38792203..11108eb075bc 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -911,7 +911,11 @@ static bool igc_is_crosststamp_supported(struct igc_adapter *adapter) static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp) { #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML) - return convert_art_ns_to_tsc(tstamp); + return (struct system_counterval_t) { + .cs_id = CSID_X86_ART, + .cycles = tstamp, + .nsecs = true, + }; #else return (struct system_counterval_t) { }; #endif From patchwork Thu Dec 21 09:32:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501523 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0C4851C36; Thu, 21 Dec 2023 09:33:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OmOLVkKa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151215; x=1734687215; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uUU6Aeoh21pgVprRQuKox95GRqR5aTWn9mMsl4N1jcQ=; b=OmOLVkKaphR3ic2AjZOGtX2O6V6ARGnMcKPfQFS70sb0hyEJGrMINUzX 6WGSX1jOd2JTcefiwx5jcLGMYTJNGsmqmRqSsYZ2wIdyMmHS45fpD0ENM Y8eSauY4YbJs3i1/PfdP3P0D/6LqAwD7NtXolGn4IpK3LOwm3XtwzBMVD F3b+aufflt5GQRDvkfYSd8V0ZxXDheAVViKa6CF4nl/svAGkuPtjjZ44f qrrTvNowoQgvZiGQoEaxCJyL/vsO4X7ShNPj6Q+HUh9nf85vA/SDdJCBP yTA3gPlPc2TdsedLAA7DmdILDvTDe638VrR2fo671Hou3e2ZMUOof4NFg A==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188563" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188563" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918208" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918208" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:27 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 05/10] stmmac: intel: remove convert_art_to_tsc() Date: Thu, 21 Dec 2023 15:02:49 +0530 Message-Id: <20231221093254.9599-6-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC From: Thomas Gleixner Remove convert_art_to_tsc() function call, Pass system clock cycles and clocksource ID as input to get_device_system_crosststamp(). Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 60283543ffc8..e73fa34237d3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -390,10 +390,11 @@ static int intel_crosststamp(ktime_t *device, *device = ns_to_ktime(ptp_time); read_unlock_irqrestore(&priv->ptp_lock, flags); get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); - *system = convert_art_to_tsc(art_time); + system->cycles = art_time; } system->cycles *= intel_priv->crossts_adj; + system->cs_id = CSID_X86_ART; priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; return 0; From patchwork Thu Dec 21 09:32:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501524 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AB88524A9; Thu, 21 Dec 2023 09:33:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HVLCm2KR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151221; x=1734687221; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C3p46caV8CRS4j/dEHJyoZnEtIablwurupbiv6nNHMI=; b=HVLCm2KRwfHbNlGfSu/LYH591800+vSaQrnt0g9YZ5jFtuRwiptsSRuZ BmEb3miCQ7foyQUp8P6Fw8r74ka0EF3bel2KbjOa5zPS3iVhbTBo9hH+R thyAgYqvsQK0rshE9SwOSN63Qy5uO/GRUL0W7ChFzQv06dAuYrwi8y/YG iOusmASy9J9YAC8KbXLmk7gj4EHdoCJNnabiizX1RNlkP1tp7RNcipb1T AH/Wz48yvl2dekLysQHSwR15WF8cR76sGe53SK30FbJgtiYuxEueS6oTA jnHv9Akb+sZBuk0SOb6H0UwPXBprAH7mjHVCmWGyb8ZjyprmrlVkt7Q99 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188585" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188585" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918215" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918215" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:34 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 06/10] ALSA: hda: remove convert_art_to_tsc() Date: Thu, 21 Dec 2023 15:02:50 +0530 Message-Id: <20231221093254.9599-7-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-State: RFC From: Thomas Gleixner Remove convert_art_to_tsc() function call, Pass system clock cycles and clocksource ID as input to get_device_system_crosststamp(). Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- sound/pci/hda/hda_controller.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index c42e9ffff9db..787521d7f3b1 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -457,7 +457,8 @@ static int azx_get_sync_time(ktime_t *device, *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) / ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate)); - *system = convert_art_to_tsc(tsc_counter); + system->cycles = tsc_counter; + system->cs_id = CSID_X86_ART; return 0; } From patchwork Thu Dec 21 09:32:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501525 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B54BE52745; Thu, 21 Dec 2023 09:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E2MLMAge" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151227; x=1734687227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+PyxmFRWe/t75785UAnv5jwKbLbVhxVPk8E+eOUGbOw=; b=E2MLMAge8cX3Z5ii1P4ACwVYlkDzJ+N24gydtW83VBdV7ZQYHjYxOTZF u/wyrgpfBCsnCY8SP9TRHj9j9uPQDxwkGIVYOKl2WuW0Zv6sIVp5y8uH3 jb7hs6q25VkiYjmvRwHJWIbykrp2bqSm2yp/Utak3dBO9+wO9J8mZ2C1U x1o8la/5utCneklOIppTQHeSk9zjzoJQCcPSGZvWUEYFUcpkP6C0hpE9f WZJlE3kOcbpGT6kCu3wSvfChVXhMas/jvWWCx1OiDYQMvFLMI3KgnL09+ 6n9Hmkg0VTFCl4EUurcL7C+Xo5RQf748Nww8J5+GcBDf3S3zdfHBEB8fg w==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188604" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188604" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918227" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918227" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:41 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 07/10] ice/ptp: remove convert_art_to_tsc() Date: Thu, 21 Dec 2023 15:02:51 +0530 Message-Id: <20231221093254.9599-8-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC From: Thomas Gleixner Remove convert_art_to_tsc() function call, Pass system clock cycles and clocksource ID as input to get_device_system_crosststamp(). Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 71f405f8a6fe..f4611a5d8c27 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -1978,7 +1978,7 @@ ice_ptp_get_syncdevicetime(ktime_t *device, hh_ts_lo = rd32(hw, GLHH_ART_TIME_L); hh_ts_hi = rd32(hw, GLHH_ART_TIME_H); hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo; - *system = convert_art_ns_to_tsc(hh_ts); + system->cycles = hh_ts; /* Read Device source clock time */ hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx)); hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx)); From patchwork Thu Dec 21 09:32:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501526 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16B715274F; Thu, 21 Dec 2023 09:33:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Xbyy/LDE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151234; x=1734687234; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g+XIios6gzuWdNxt0cjzsz4uFVCLlfg0PPk41T8TkZc=; b=Xbyy/LDE91VbntdjjIrso3GvYeQA3R2Q3VCfJ57nMQvkG0apbh6ZdCsP BIKElbJzP3g+87CRHvlkdbXKkzJHM2WS5MRmKqBpyb5o6IBPnyJA2Vn+T xCHbQDzf1OMBLmGmQArP7PYBCwafCYUe345eN84jKYg3w3m/nOuamSsCA KTDwzpS20EpjZ1HDWE3RXhml08Idn/vgbOwQZ5jvQat+H/cu6ckkzGjUP j72Jam2Y5j8fADyKTfJIvnBSd/Sp82gyrEwPA+OhAiUsDTYomaneZ0vPh ysPQOhGG7PbA69m0ExM3oblO94JmIE6XhN/p8Z1w5YPyUQHy9eNi5Xcs+ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188630" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188630" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:33:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918240" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918240" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:47 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 08/10] pps: generators: Add PPS Generator TIO Driver Date: Thu, 21 Dec 2023 15:02:52 +0530 Message-Id: <20231221093254.9599-9-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-State: RFC From: Lakshmi Sowjanya D The Intel Timed IO PPS generator driver outputs a PPS signal using dedicated hardware that is more accurate than software actuated PPS. The Timed IO hardware generates output events using the ART timer. The ART timer period varies based on platform type, but is less than 100 nanoseconds for all current platforms. Timed IO output accuracy is within 1 ART period. PPS output is enabled by writing '1' the 'enable' sysfs attribute. The driver uses hrtimers to schedule a wake-up 10 ms before each event (edge) target time. At wakeup, the driver converts the target time in terms of CLOCK_REALTIME to ART trigger time and writes this to the Timed IO hardware. The Timed IO hardware generates an event precisely at the requested system time without software involvement. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Co-developed-by: Pandith N Signed-off-by: Pandith N Co-developed-by: Thejesh Reddy T R Signed-off-by: Thejesh Reddy T R Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong Reviewed-by: Andy Shevchenko Signed-off-by: Lakshmi Sowjanya D --- drivers/pps/generators/Kconfig | 16 ++ drivers/pps/generators/Makefile | 1 + drivers/pps/generators/pps_gen_tio.c | 238 +++++++++++++++++++++++++++ 3 files changed, 255 insertions(+) create mode 100644 drivers/pps/generators/pps_gen_tio.c diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index d615e640fcad..0f090932336f 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -12,3 +12,19 @@ config PPS_GENERATOR_PARPORT If you say yes here you get support for a PPS signal generator which utilizes STROBE pin of a parallel port to send PPS signals. It uses parport abstraction layer and hrtimers to precisely control the signal. + +config PPS_GENERATOR_TIO + tristate "TIO PPS signal generator" + depends on X86 && CPU_SUP_INTEL + help + If you say yes here you get support for a PPS TIO signal generator + which generates a pulse at a prescribed time based on the system clock. + It uses time translation and hrtimers to precisely generate a pulse. + This hardware is present on 2019 and newer Intel CPUs. However, this + driver is not useful without adding highly specialized hardware outside + the Linux system to observe these pulses. + + To compile this driver as a module, choose M here: the module + will be called pps_gen_tio. + + If unsure, say N. diff --git a/drivers/pps/generators/Makefile b/drivers/pps/generators/Makefile index 2d56dd0495d5..07004cfd3996 100644 --- a/drivers/pps/generators/Makefile +++ b/drivers/pps/generators/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_PPS_GENERATOR_PARPORT) += pps_gen_parport.o +obj-$(CONFIG_PPS_GENERATOR_TIO) += pps_gen_tio.o ifeq ($(CONFIG_PPS_DEBUG),y) EXTRA_CFLAGS += -DDEBUG diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c new file mode 100644 index 000000000000..99aa98e64f86 --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.c @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2023 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) /* Safety time to set hrtimer early */ +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct hrtimer timer; + struct device *dev; + spinlock_t lock; + struct attribute_group attrs; + void __iomem *base; + bool enabled; +}; + +static inline u32 pps_ctl_read(struct pps_tio *tio) +{ + return readl(tio->base + TIOCTL); +} + +static inline void pps_ctl_write(struct pps_tio *tio, u32 value) +{ + writel(value, tio->base + TIOCTL); +} + +/* For COMPV register, It's safer to write higher 32-bit followed by lower 32-bit */ +static inline void pps_compv_write(struct pps_tio *tio, u64 value) +{ + hi_lo_writeq(value, tio->base + TIOCOMPV); +} + +static inline ktime_t first_event(struct pps_tio *tio) +{ + return ktime_set(ktime_get_real_seconds() + 1, MAGIC_CONST); +} + +static u32 pps_tio_disable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl = pps_ctl_read(tio); + pps_compv_write(tio, 0); + + ctrl &= ~TIOCTL_EN; + pps_ctl_write(tio, ctrl); + + return ctrl; +} + +static void pps_tio_direction_output(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl = pps_tio_disable(tio); + + /* We enable the device, be sure that the 'compare' value is invalid */ + pps_compv_write(tio, 0); + + ctrl &= ~(TIOCTL_DIR | TIOCTL_EP); + ctrl |= TIOCTL_EP_TOGGLE_EDGE; + pps_ctl_write(tio, ctrl); + + ctrl |= TIOCTL_EN; + pps_ctl_write(tio, ctrl); +} + +static bool pps_generate_next_pulse(struct pps_tio *tio, ktime_t expires) +{ + u64 art; + + if (!ktime_real_to_base_clock(expires, CSID_X86_ART, &art)) { + pps_tio_disable(tio); + return false; + } + + pps_compv_write(tio, art - ART_HW_DELAY_CYCLES); + return true; +} + +static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + struct pps_tio *tio = container_of(timer, struct pps_tio, timer); + ktime_t expires, now; + + guard(spinlock)(&tio->lock); + + expires = hrtimer_get_expires(timer); + now = ktime_get_real(); + + if (now - expires < SAFE_TIME_NS) { + if (!pps_generate_next_pulse(tio, expires + SAFE_TIME_NS)) + return HRTIMER_NORESTART; + } + + hrtimer_forward(timer, now, NSEC_PER_SEC / 2); + return HRTIMER_RESTART; +} + +static ssize_t enable_store(struct device *dev, struct device_attribute *attr, const char *buf, + size_t count) +{ + struct pps_tio *tio = dev_get_drvdata(dev); + bool enable; + int err; + + err = kstrtobool(buf, &enable); + if (err) + return err; + + guard(spinlock_irqsave)(&tio->lock); + if (enable && !tio->enabled) { + if (!timekeeping_clocksource_has_base(CSID_X86_ART)) { + dev_err(tio->dev, "PPS cannot be started as clock is not related to ART"); + return -EPERM; + } + pps_tio_direction_output(tio); + hrtimer_start(&tio->timer, first_event(tio), HRTIMER_MODE_ABS); + tio->enabled = true; + } else if (!enable && tio->enabled) { + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + tio->enabled = false; + } + return count; +} + +static ssize_t enable_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + struct pps_tio *tio = dev_get_drvdata(dev); + u32 ctrl; + + ctrl = pps_ctl_read(tio); + ctrl &= TIOCTL_EN; + + return sysfs_emit(buf, "%u\n", ctrl); +} +static DEVICE_ATTR_RW(enable); + +static struct attribute *pps_tio_attrs[] = { + &dev_attr_enable.attr, + NULL +}; +ATTRIBUTE_GROUPS(pps_tio); + +static int pps_tio_probe(struct platform_device *pdev) +{ + struct pps_tio *tio; + + if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && + cpu_feature_enabled(X86_FEATURE_ART))) { + dev_warn(&pdev->dev, "TSC/ART is not enabled"); + return -ENODEV; + } + + tio = devm_kzalloc(&pdev->dev, sizeof(*tio), GFP_KERNEL); + if (!tio) + return -ENOMEM; + + tio->dev = &pdev->dev; + tio->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tio->base)) + return PTR_ERR(tio->base); + + pps_tio_disable(tio); + hrtimer_init(&tio->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); + tio->timer.function = hrtimer_callback; + spin_lock_init(&tio->lock); + tio->enabled = false; + platform_set_drvdata(pdev, tio); + + return 0; +} + +static int pps_tio_remove(struct platform_device *pdev) +{ + struct pps_tio *tio = platform_get_drvdata(pdev); + + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + + return 0; +} + +static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { + { "INTC1021" }, + { "INTC1022" }, + { "INTC1023" }, + { "INTC1024" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); + +static struct platform_driver pps_tio_driver = { + .probe = pps_tio_probe, + .remove = pps_tio_remove, + .driver = { + .name = "intel-pps-generator", + .acpi_match_table = intel_pmc_tio_acpi_match, + .dev_groups = pps_tio_groups, + }, +}; +module_platform_driver(pps_tio_driver); + +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_AUTHOR("Christopher Hall "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Thejesh Reddy T R "); +MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Dec 21 09:32:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501527 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2630F5277C; Thu, 21 Dec 2023 09:34:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="3188668" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:34:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918264" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918264" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:33:53 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 09/10] Documentation: driver-api: pps: Add Intel Timed I/O PPS generator Date: Thu, 21 Dec 2023 15:02:53 +0530 Message-Id: <20231221093254.9599-10-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-State: RFC From: Lakshmi Sowjanya D Add Intel Timed I/O PPS usage instructions. Co-developed-by: Pandith N Signed-off-by: Pandith N Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Andy Shevchenko --- Documentation/driver-api/pps.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pps.rst index 78dded03e5d8..cb1e4d814d37 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -246,3 +246,25 @@ delay between assert and clear edge as small as possible to reduce system latencies. But if it is too small slave won't be able to capture clear edge transition. The default of 30us should be good enough in most situations. The delay can be selected using 'delay' pps_gen_parport module parameter. + + +Intel Timed I/O PPS signal generator +------------------------------------ + +Intel Timed I/O is a high precision device, present on 2019 and newer Intel +CPUs, that can generate PPS signal. + +Timed I/O and system time are both driven by same hardware clock, The signal +generated with a precision of ~20 nanoseconds. The generated PPS signal +is used to synchronize an external device with system clock. For example, +Share your clock with a device that receives PPS signal, generated by +Timed I/O device. There are dedicated Timed I/O pins to deliver PPS signal +to an external device. + +Usage of Intel Timed I/O as PPS generator: + +Start generating PPS signal:: + $echo 1 > /sys/devices/platform/INTCxxxx\:00/enable + +Stop generating PPS signal:: + $echo 0 > /sys/devices/platform/INTCxxxx\:00/enable From patchwork Thu Dec 21 09:32:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13501528 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 731D352F67; Thu, 21 Dec 2023 09:34:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k2RzLsD9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703151248; x=1734687248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L+k5CS5sgC8pMM6kY4u78Belg2iE72BS8zZ13TBDiEs=; b=k2RzLsD9anFS2xOvYcebFfeKXaDfc9nNThRLICBPlg8yiLXXs0+4m4wD TgVO2MZ7XQguFD1ypxgEA6iW0yr0JVsi7nE3NXwAMwmAu7GRvCWFI0Btt NB+WHjERNfoXEWGWxnRAAuOBfXLZv8wwyl+YbeZvVvT2QMoNEU+RR+jSq gzx6tJbpLp2R8t7PTW17uenPfuE+YdoqukP5NGz4Z3S13n6oqDkJw/RGl SIG7lLTbhxHcacvefEGaGZYqESrH6Jr8RA3/5UyTRq+iqG1f8S5Bx7UTm UCClW4zjQJJqsoI6vzPk11chSSJ8sh1ojnTN2q6/n28b0RX2Qgn7bQkr0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3188687" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3188687" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 01:34:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="810918311" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="810918311" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by orsmga001.jf.intel.com with ESMTP; 21 Dec 2023 01:34:00 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [RFC PATCH v2 10/10] ABI: pps: Add ABI documentation for Intel TIO Date: Thu, 21 Dec 2023 15:02:54 +0530 Message-Id: <20231221093254.9599-11-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> References: <20231221093254.9599-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-State: RFC From: Lakshmi Sowjanya D Document sysfs interface for Intel Timed I/O PPS driver Signed-off-by: Lakshmi Sowjanya D --- Documentation/ABI/testing/sysfs-platform-pps-tio | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-pps-tio diff --git a/Documentation/ABI/testing/sysfs-platform-pps-tio b/Documentation/ABI/testing/sysfs-platform-pps-tio new file mode 100644 index 000000000000..d8be3a6d5795 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-pps-tio @@ -0,0 +1,7 @@ +What: /sys/devices/platform/INTCxxxx/enable +Date: January 2024 +KernelVersion 6.8 +Contact: Lakshmi Sowjanya D +Description: + (RW) Enable or disable PPS TIO generator output, read to + see the status of hardware(Enabled/Disabled).