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Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index 27ed66cb761f..1f78dfe84c51 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -674,6 +674,9 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) struct sahara_dev *dev = dev_ptr; int err = 0; + if (!req->cryptlen) + return 0; + if (unlikely(ctx->keylen != AES_KEYSIZE_128)) return sahara_aes_fallback(req, mode); From patchwork Sat Dec 23 18:10:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ovidiu Panait X-Patchwork-Id: 13504045 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mx0b-0064b401.pphosted.com (mx0b-0064b401.pphosted.com [205.220.178.238]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C29A812B76 for ; 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Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index 1f78dfe84c51..82c3f41ea476 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -1160,8 +1160,7 @@ static int sahara_sha_import(struct ahash_request *req, const void *in) static int sahara_sha_cra_init(struct crypto_tfm *tfm) { crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), - sizeof(struct sahara_sha_reqctx) + - SHA_BUFFER_LEN + SHA256_BLOCK_SIZE); + sizeof(struct sahara_sha_reqctx)); return 0; } From patchwork Sat Dec 23 18:10:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ovidiu Panait X-Patchwork-Id: 13504046 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mx0b-0064b401.pphosted.com (mx0b-0064b401.pphosted.com [205.220.178.238]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C296A125C7 for ; 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Fix this. Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") Fixes: 5de8875281e1 ("crypto: sahara - Add driver for SAHARA2 accelerator.") Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index 82c3f41ea476..a9abf6439c4b 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -605,16 +605,17 @@ static int sahara_aes_process(struct skcipher_request *req) timeout = wait_for_completion_timeout(&dev->dma_completion, msecs_to_jiffies(SAHARA_TIMEOUT_MS)); - if (!timeout) { - dev_err(dev->device, "AES timeout\n"); - return -ETIMEDOUT; - } dma_unmap_sg(dev->device, dev->out_sg, dev->nb_out_sg, DMA_FROM_DEVICE); dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg, DMA_TO_DEVICE); + if (!timeout) { + dev_err(dev->device, "AES timeout\n"); + return -ETIMEDOUT; + } + if ((dev->flags & FLAGS_CBC) && req->iv) sahara_aes_cbc_update_iv(req); @@ -1005,15 +1006,16 @@ static int sahara_sha_process(struct ahash_request *req) timeout = wait_for_completion_timeout(&dev->dma_completion, msecs_to_jiffies(SAHARA_TIMEOUT_MS)); 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Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index a9abf6439c4b..d49659db6a48 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -985,7 +985,10 @@ static int sahara_sha_process(struct ahash_request *req) return ret; if (rctx->first) { - sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0); + ret = sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0); + if (ret) + return ret; + dev->hw_desc[0]->next = 0; rctx->first = 0; } else { @@ -993,7 +996,10 @@ static int sahara_sha_process(struct ahash_request *req) sahara_sha_hw_context_descriptor_create(dev, rctx, req, 0); dev->hw_desc[0]->next = dev->hw_phys_desc[1]; - sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1); + ret = sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1); + if (ret) + return ret; + dev->hw_desc[1]->next = 0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XWiCkAzaGNtn1krNpFeM61gWpsuGz3lPxEo/kJpBpqxeTn6GIuNZTDXLOBjgzah+iedY/dndaGUXRX0Jw2v0enZnc0lLVyqKRYv9beRWKnRGd9rr9h0vhNBR4UVEO/kN/YMmbv1m5ZeKdoDqI7xRyX66cmZVx04GQ/eLACm3bLvHeLoNi2qWTm/e2kANMVCbNnro9Ob9oPfJ0p4AjDqK2aBIxvbZ9M010rPmWHuB/O8k7qD/NqNAhiDrN5ug+qcG3uHCU3sFvdG8QS6RaJ+DeZxRB888+4pCyjcRQV8k2t3WQ70drkJTzLgZ07dfEBjQ/F3xcxxKxxonD46zPruAAjqTtkx34QDb1haRZb+lcdl4gzWIrCbA8QCca2DjY3BnNvF5xhbU8cXJIAT0Kypb7cCIyM5dOFStY9AhtJKJ+xmxXVLzBpt1p243649+GsOsPzozxUUeWkDQP27TS5+r4wNqjEEtWvSEq85bL1Jjn2UW9aRRCgxrXwaHpj4yWCZ2VFiZ9C82je0C5naGv5NBXi/YamcLrR+31keDBQE5QWsCSimfHCy3s0B1v6sDTWdxCITSnTQHg4RkungME0wM5F8PxqCQDAhrvwefD0RLzVAk1ni6VCgRSgYMt4TmqPKayb8WisTIBj4s/GYI2VW15apQekaf5auw6pWG3At4xGdvxkVPeUk5YdPrx3cLjlVrLKPi9dxUZmIs4PBNf97MQXdryub+g75wrb/qj23mYFZaziTu7+p8z+bLEuA5Ul2K+LihgtkNe9pw3qNPz+uXtBs38nXpkSOHKPEP2qrMGntODTje1l20iAFcvGqHJef1q/z8NzKlNYZuirrSaQq7UlXp4vEdrpNMDoOJIqklQeWWZrp6SAYfscurNo/Z58k+z8ti3lr6ZjwiKsju/BxMJs8ovgc3Fyvblt22tIypCemNvy5xZ9C8UpRJsWddOU3AXw0CG7/d2LSQGpZ0aKIdSo9ECtmq37Ntkdz0Npn5mLQaVlF5e6UcCX7HSQa46GKwFLNo79VNT242b3DQVISa757o+gjRmMgc5bXkjUUJUjZO/Sa1YzEsEGUDGbQUL0+2xR5OxMOto01spJ33fx0bBmrPZ39ylUk2K5MVk7XkKFI7XkXG/nmTlxdKOA1bjYruFFYUTBf4b3nZ4LnFJjT0pGkWNtF6dhiy1KwIr7g7u1VAPC4z7+ZM4o1kNTjDTCcbfux88V1vrB/uGAC40Tlk2UGapLzB79bOlR5lME+2RhQH1ce/mo1ElsnXfLHPK6yTA/tazfGqLQRjB9sbwss0H1sRvW7YEQpwYNxKIVtPylc2n2ciedSnST32aYgcqP2oafKrxgmnampd4DM/O5R9shexRVE5fBXdcHPLpubK8pI6C9m9szDX3KcfpxvT+EsGEw0oXTzEHu0bcVyWnfpjYCW8jJBGgNe+V1xYJi10Z4WpBXCE0f/1Sm8v35DSE9JKt+bFhFMi4u83nGj4eoDQD/KFNclO5SUHvbKWGPNE4U+G3TC2EGOrXVTGReABAAC440r7LUFMVng1Eyz6nvh+Gqx6TVh9DcU5mVC/U2SPT+SSMikVAOirm8we8y8F8Fg+NiNem3BdLWund6S246urqw== X-OriginatorOrg: windriver.com X-MS-Exchange-CrossTenant-Network-Message-Id: e07ffeab-a3d3-42c7-a863-08dc03e27947 X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5327.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2023 18:10:41.3281 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 8ddb2873-a1ad-4a18-ae4e-4644631433be X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VF9vMlb1RWL8meUJYAi5FvPefc3hmUsJE1YyNhk3KGb1xdZEoOssAVCswtGdrX7HXB4CABXnHUBiz+cyINx242E9QOPco9wKx1Rb4bsS5Y8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR11MB4589 X-Proofpoint-GUID: R0XWlfYx-YyCC6_5K0NhMUL6JZpDnXhB X-Proofpoint-ORIG-GUID: R0XWlfYx-YyCC6_5K0NhMUL6JZpDnXhB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-16_25,2023-11-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=920 priorityscore=1501 mlxscore=0 bulkscore=0 impostorscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312230144 From: Ovidiu Panait It's not always the case that the entire sg entry needs to be processed. Currently, when nbytes is less than sg->length, "Descriptor length" errors are encountered. To fix this, take the actual request size into account when populating the hw links. Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index d49659db6a48..321c11050457 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -774,6 +774,7 @@ static int sahara_sha_hw_links_create(struct sahara_dev *dev, int start) { struct scatterlist *sg; + unsigned int len; unsigned int i; int ret; @@ -795,12 +796,14 @@ static int sahara_sha_hw_links_create(struct sahara_dev *dev, if (!ret) return -EFAULT; + len = rctx->total; for (i = start; i < dev->nb_in_sg + start; i++) { - dev->hw_link[i]->len = sg->length; + dev->hw_link[i]->len = min(len, sg->length); dev->hw_link[i]->p = sg->dma_address; if (i == (dev->nb_in_sg + start - 1)) { dev->hw_link[i]->next = 0; } else { + len -= min(len, sg->length); dev->hw_link[i]->next = dev->hw_phys_link[i + 1]; sg = sg_next(sg); } From patchwork Sat Dec 23 18:11:00 2023 Content-Type: text/plain; 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This was traced to sahara_walk_and_recalc() resizing req->src and causing the subsequent dma_map_sg() call to fail. Now that the previous commit fixed sahara_sha_hw_links_create() to take into account the actual request size, rather than relying on sg->length values, the resize operation is no longer necessary. Therefore, remove sahara_walk_and_recalc() and simplify associated logic. Fixes: 5a2bb93f5992 ("crypto: sahara - add support for SHA1/256") Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 38 ++------------------------------------ 1 file changed, 2 insertions(+), 36 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index 321c11050457..f045591e8889 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -884,24 +884,6 @@ static int sahara_sha_hw_context_descriptor_create(struct sahara_dev *dev, return 0; } -static int sahara_walk_and_recalc(struct scatterlist *sg, unsigned int nbytes) -{ - if (!sg || !sg->length) - return nbytes; - - while (nbytes && sg) { - if (nbytes <= sg->length) { - sg->length = nbytes; - sg_mark_end(sg); - break; - } - nbytes -= sg->length; - sg = sg_next(sg); - } - - return nbytes; -} - static int sahara_sha_prepare_request(struct ahash_request *req) { struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); @@ -938,36 +920,20 @@ static int sahara_sha_prepare_request(struct ahash_request *req) hash_later, 0); } - /* nbytes should now be multiple of blocksize */ - req->nbytes = req->nbytes - hash_later; - - sahara_walk_and_recalc(req->src, req->nbytes); - + rctx->total = len - hash_later; /* have data from previous operation and current */ if (rctx->buf_cnt && req->nbytes) { sg_init_table(rctx->in_sg_chain, 2); sg_set_buf(rctx->in_sg_chain, rctx->rembuf, rctx->buf_cnt); - sg_chain(rctx->in_sg_chain, 2, req->src); - - rctx->total = req->nbytes + rctx->buf_cnt; rctx->in_sg = rctx->in_sg_chain; - - req->src = rctx->in_sg_chain; /* only data from previous operation */ } else if (rctx->buf_cnt) { - if (req->src) - rctx->in_sg = req->src; - else - rctx->in_sg = rctx->in_sg_chain; - /* buf was copied into rembuf above */ + rctx->in_sg = rctx->in_sg_chain; sg_init_one(rctx->in_sg, rctx->rembuf, rctx->buf_cnt); - rctx->total = rctx->buf_cnt; /* no data from previous operation */ } else { rctx->in_sg = req->src; - rctx->total = req->nbytes; - req->src = rctx->in_sg; } /* on next call, we only have the remaining data in the buffer */ From patchwork Sat Dec 23 18:11:01 2023 Content-Type: text/plain; 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Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 182 ++++++++++++++++++++-------------------- 1 file changed, 91 insertions(+), 91 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index f045591e8889..b024935f9d85 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -30,99 +30,99 @@ #include #include -#define SHA_BUFFER_LEN PAGE_SIZE -#define SAHARA_MAX_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE - -#define SAHARA_NAME "sahara" -#define SAHARA_VERSION_3 3 -#define SAHARA_VERSION_4 4 -#define SAHARA_TIMEOUT_MS 1000 -#define SAHARA_MAX_HW_DESC 2 -#define SAHARA_MAX_HW_LINK 20 - -#define FLAGS_MODE_MASK 0x000f -#define FLAGS_ENCRYPT BIT(0) -#define FLAGS_CBC BIT(1) - -#define SAHARA_HDR_BASE 0x00800000 -#define SAHARA_HDR_SKHA_ALG_AES 0 -#define SAHARA_HDR_SKHA_OP_ENC (1 << 2) -#define SAHARA_HDR_SKHA_MODE_ECB (0 << 3) -#define SAHARA_HDR_SKHA_MODE_CBC (1 << 3) -#define SAHARA_HDR_FORM_DATA (5 << 16) -#define SAHARA_HDR_FORM_KEY (8 << 16) -#define SAHARA_HDR_LLO (1 << 24) -#define SAHARA_HDR_CHA_SKHA (1 << 28) -#define SAHARA_HDR_CHA_MDHA (2 << 28) -#define SAHARA_HDR_PARITY_BIT (1 << 31) - -#define SAHARA_HDR_MDHA_SET_MODE_MD_KEY 0x20880000 -#define SAHARA_HDR_MDHA_SET_MODE_HASH 0x208D0000 -#define SAHARA_HDR_MDHA_HASH 0xA0850000 -#define SAHARA_HDR_MDHA_STORE_DIGEST 0x20820000 -#define SAHARA_HDR_MDHA_ALG_SHA1 0 -#define SAHARA_HDR_MDHA_ALG_MD5 1 -#define SAHARA_HDR_MDHA_ALG_SHA256 2 -#define SAHARA_HDR_MDHA_ALG_SHA224 3 -#define SAHARA_HDR_MDHA_PDATA (1 << 2) -#define SAHARA_HDR_MDHA_HMAC (1 << 3) -#define SAHARA_HDR_MDHA_INIT (1 << 5) -#define SAHARA_HDR_MDHA_IPAD (1 << 6) -#define SAHARA_HDR_MDHA_OPAD (1 << 7) -#define SAHARA_HDR_MDHA_SWAP (1 << 8) -#define SAHARA_HDR_MDHA_MAC_FULL (1 << 9) -#define SAHARA_HDR_MDHA_SSL (1 << 10) +#define SHA_BUFFER_LEN PAGE_SIZE +#define SAHARA_MAX_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE + +#define SAHARA_NAME "sahara" +#define SAHARA_VERSION_3 3 +#define SAHARA_VERSION_4 4 +#define SAHARA_TIMEOUT_MS 1000 +#define SAHARA_MAX_HW_DESC 2 +#define SAHARA_MAX_HW_LINK 20 + +#define FLAGS_MODE_MASK 0x000f +#define FLAGS_ENCRYPT BIT(0) +#define FLAGS_CBC BIT(1) + +#define SAHARA_HDR_BASE 0x00800000 +#define SAHARA_HDR_SKHA_ALG_AES 0 +#define SAHARA_HDR_SKHA_OP_ENC (1 << 2) +#define SAHARA_HDR_SKHA_MODE_ECB (0 << 3) +#define SAHARA_HDR_SKHA_MODE_CBC (1 << 3) +#define SAHARA_HDR_FORM_DATA (5 << 16) +#define SAHARA_HDR_FORM_KEY (8 << 16) +#define SAHARA_HDR_LLO (1 << 24) +#define SAHARA_HDR_CHA_SKHA (1 << 28) +#define SAHARA_HDR_CHA_MDHA (2 << 28) +#define SAHARA_HDR_PARITY_BIT (1 << 31) + +#define SAHARA_HDR_MDHA_SET_MODE_MD_KEY 0x20880000 +#define SAHARA_HDR_MDHA_SET_MODE_HASH 0x208D0000 +#define SAHARA_HDR_MDHA_HASH 0xA0850000 +#define SAHARA_HDR_MDHA_STORE_DIGEST 0x20820000 +#define SAHARA_HDR_MDHA_ALG_SHA1 0 +#define SAHARA_HDR_MDHA_ALG_MD5 1 +#define SAHARA_HDR_MDHA_ALG_SHA256 2 +#define SAHARA_HDR_MDHA_ALG_SHA224 3 +#define SAHARA_HDR_MDHA_PDATA (1 << 2) +#define SAHARA_HDR_MDHA_HMAC (1 << 3) +#define SAHARA_HDR_MDHA_INIT (1 << 5) +#define SAHARA_HDR_MDHA_IPAD (1 << 6) +#define SAHARA_HDR_MDHA_OPAD (1 << 7) +#define SAHARA_HDR_MDHA_SWAP (1 << 8) +#define SAHARA_HDR_MDHA_MAC_FULL (1 << 9) +#define SAHARA_HDR_MDHA_SSL (1 << 10) /* SAHARA can only process one request at a time */ -#define SAHARA_QUEUE_LENGTH 1 - -#define SAHARA_REG_VERSION 0x00 -#define SAHARA_REG_DAR 0x04 -#define SAHARA_REG_CONTROL 0x08 -#define SAHARA_CONTROL_SET_THROTTLE(x) (((x) & 0xff) << 24) -#define SAHARA_CONTROL_SET_MAXBURST(x) (((x) & 0xff) << 16) -#define SAHARA_CONTROL_RNG_AUTORSD (1 << 7) -#define SAHARA_CONTROL_ENABLE_INT (1 << 4) -#define SAHARA_REG_CMD 0x0C -#define SAHARA_CMD_RESET (1 << 0) -#define SAHARA_CMD_CLEAR_INT (1 << 8) -#define SAHARA_CMD_CLEAR_ERR (1 << 9) -#define SAHARA_CMD_SINGLE_STEP (1 << 10) -#define SAHARA_CMD_MODE_BATCH (1 << 16) -#define SAHARA_CMD_MODE_DEBUG (1 << 18) -#define SAHARA_REG_STATUS 0x10 -#define SAHARA_STATUS_GET_STATE(x) ((x) & 0x7) -#define SAHARA_STATE_IDLE 0 -#define SAHARA_STATE_BUSY 1 -#define SAHARA_STATE_ERR 2 -#define SAHARA_STATE_FAULT 3 -#define SAHARA_STATE_COMPLETE 4 -#define SAHARA_STATE_COMP_FLAG (1 << 2) -#define SAHARA_STATUS_DAR_FULL (1 << 3) -#define SAHARA_STATUS_ERROR (1 << 4) -#define SAHARA_STATUS_SECURE (1 << 5) -#define SAHARA_STATUS_FAIL (1 << 6) -#define SAHARA_STATUS_INIT (1 << 7) -#define SAHARA_STATUS_RNG_RESEED (1 << 8) -#define SAHARA_STATUS_ACTIVE_RNG (1 << 9) -#define SAHARA_STATUS_ACTIVE_MDHA (1 << 10) -#define SAHARA_STATUS_ACTIVE_SKHA (1 << 11) -#define SAHARA_STATUS_MODE_BATCH (1 << 16) -#define SAHARA_STATUS_MODE_DEDICATED (1 << 17) -#define SAHARA_STATUS_MODE_DEBUG (1 << 18) -#define SAHARA_STATUS_GET_ISTATE(x) (((x) >> 24) & 0xff) -#define SAHARA_REG_ERRSTATUS 0x14 -#define SAHARA_ERRSTATUS_GET_SOURCE(x) ((x) & 0xf) -#define SAHARA_ERRSOURCE_CHA 14 -#define SAHARA_ERRSOURCE_DMA 15 -#define SAHARA_ERRSTATUS_DMA_DIR (1 << 8) -#define SAHARA_ERRSTATUS_GET_DMASZ(x)(((x) >> 9) & 0x3) -#define SAHARA_ERRSTATUS_GET_DMASRC(x) (((x) >> 13) & 0x7) -#define SAHARA_ERRSTATUS_GET_CHASRC(x) (((x) >> 16) & 0xfff) -#define SAHARA_ERRSTATUS_GET_CHAERR(x) (((x) >> 28) & 0x3) -#define SAHARA_REG_FADDR 0x18 -#define SAHARA_REG_CDAR 0x1C -#define SAHARA_REG_IDAR 0x20 +#define SAHARA_QUEUE_LENGTH 1 + +#define SAHARA_REG_VERSION 0x00 +#define SAHARA_REG_DAR 0x04 +#define SAHARA_REG_CONTROL 0x08 +#define SAHARA_CONTROL_SET_THROTTLE(x) (((x) & 0xff) << 24) +#define SAHARA_CONTROL_SET_MAXBURST(x) (((x) & 0xff) << 16) +#define SAHARA_CONTROL_RNG_AUTORSD (1 << 7) +#define SAHARA_CONTROL_ENABLE_INT (1 << 4) +#define SAHARA_REG_CMD 0x0C +#define SAHARA_CMD_RESET (1 << 0) +#define SAHARA_CMD_CLEAR_INT (1 << 8) +#define SAHARA_CMD_CLEAR_ERR (1 << 9) +#define SAHARA_CMD_SINGLE_STEP (1 << 10) +#define SAHARA_CMD_MODE_BATCH (1 << 16) +#define SAHARA_CMD_MODE_DEBUG (1 << 18) +#define SAHARA_REG_STATUS 0x10 +#define SAHARA_STATUS_GET_STATE(x) ((x) & 0x7) +#define SAHARA_STATE_IDLE 0 +#define SAHARA_STATE_BUSY 1 +#define SAHARA_STATE_ERR 2 +#define SAHARA_STATE_FAULT 3 +#define SAHARA_STATE_COMPLETE 4 +#define SAHARA_STATE_COMP_FLAG (1 << 2) +#define SAHARA_STATUS_DAR_FULL (1 << 3) +#define SAHARA_STATUS_ERROR (1 << 4) +#define SAHARA_STATUS_SECURE (1 << 5) +#define SAHARA_STATUS_FAIL (1 << 6) +#define SAHARA_STATUS_INIT (1 << 7) +#define SAHARA_STATUS_RNG_RESEED (1 << 8) +#define SAHARA_STATUS_ACTIVE_RNG (1 << 9) +#define SAHARA_STATUS_ACTIVE_MDHA (1 << 10) +#define SAHARA_STATUS_ACTIVE_SKHA (1 << 11) +#define SAHARA_STATUS_MODE_BATCH (1 << 16) +#define SAHARA_STATUS_MODE_DEDICATED (1 << 17) +#define SAHARA_STATUS_MODE_DEBUG (1 << 18) +#define SAHARA_STATUS_GET_ISTATE(x) (((x) >> 24) & 0xff) +#define SAHARA_REG_ERRSTATUS 0x14 +#define SAHARA_ERRSTATUS_GET_SOURCE(x) ((x) & 0xf) +#define SAHARA_ERRSOURCE_CHA 14 +#define SAHARA_ERRSOURCE_DMA 15 +#define SAHARA_ERRSTATUS_DMA_DIR (1 << 8) +#define SAHARA_ERRSTATUS_GET_DMASZ(x) (((x) >> 9) & 0x3) +#define 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X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=913 priorityscore=1501 mlxscore=0 bulkscore=0 impostorscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312230144 From: Ovidiu Panait Where applicable, use BIT() macro instead of shift operation to improve readability. No functional change. Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 76 ++++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index b024935f9d85..ba7d3a917101 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -46,15 +46,15 @@ #define SAHARA_HDR_BASE 0x00800000 #define SAHARA_HDR_SKHA_ALG_AES 0 -#define SAHARA_HDR_SKHA_OP_ENC (1 << 2) -#define SAHARA_HDR_SKHA_MODE_ECB (0 << 3) -#define SAHARA_HDR_SKHA_MODE_CBC (1 << 3) +#define SAHARA_HDR_SKHA_MODE_ECB 0 +#define SAHARA_HDR_SKHA_OP_ENC BIT(2) +#define SAHARA_HDR_SKHA_MODE_CBC BIT(3) #define SAHARA_HDR_FORM_DATA (5 << 16) -#define SAHARA_HDR_FORM_KEY (8 << 16) -#define SAHARA_HDR_LLO (1 << 24) -#define SAHARA_HDR_CHA_SKHA (1 << 28) -#define SAHARA_HDR_CHA_MDHA (2 << 28) -#define SAHARA_HDR_PARITY_BIT (1 << 31) +#define SAHARA_HDR_FORM_KEY BIT(19) +#define SAHARA_HDR_LLO BIT(24) +#define SAHARA_HDR_CHA_SKHA BIT(28) +#define SAHARA_HDR_CHA_MDHA BIT(29) +#define SAHARA_HDR_PARITY_BIT BIT(31) #define SAHARA_HDR_MDHA_SET_MODE_MD_KEY 0x20880000 #define SAHARA_HDR_MDHA_SET_MODE_HASH 0x208D0000 @@ -64,14 +64,14 @@ #define SAHARA_HDR_MDHA_ALG_MD5 1 #define SAHARA_HDR_MDHA_ALG_SHA256 2 #define SAHARA_HDR_MDHA_ALG_SHA224 3 -#define SAHARA_HDR_MDHA_PDATA (1 << 2) -#define SAHARA_HDR_MDHA_HMAC (1 << 3) -#define SAHARA_HDR_MDHA_INIT (1 << 5) -#define SAHARA_HDR_MDHA_IPAD (1 << 6) -#define SAHARA_HDR_MDHA_OPAD (1 << 7) -#define SAHARA_HDR_MDHA_SWAP (1 << 8) -#define SAHARA_HDR_MDHA_MAC_FULL (1 << 9) -#define SAHARA_HDR_MDHA_SSL (1 << 10) +#define SAHARA_HDR_MDHA_PDATA BIT(2) +#define SAHARA_HDR_MDHA_HMAC BIT(3) +#define SAHARA_HDR_MDHA_INIT BIT(5) +#define SAHARA_HDR_MDHA_IPAD BIT(6) +#define SAHARA_HDR_MDHA_OPAD BIT(7) +#define SAHARA_HDR_MDHA_SWAP BIT(8) +#define SAHARA_HDR_MDHA_MAC_FULL BIT(9) +#define SAHARA_HDR_MDHA_SSL BIT(10) /* SAHARA can only process one request at a time */ #define SAHARA_QUEUE_LENGTH 1 @@ -81,15 +81,15 @@ #define SAHARA_REG_CONTROL 0x08 #define SAHARA_CONTROL_SET_THROTTLE(x) (((x) & 0xff) << 24) #define SAHARA_CONTROL_SET_MAXBURST(x) (((x) & 0xff) << 16) -#define SAHARA_CONTROL_RNG_AUTORSD (1 << 7) -#define SAHARA_CONTROL_ENABLE_INT (1 << 4) +#define SAHARA_CONTROL_RNG_AUTORSD BIT(7) +#define SAHARA_CONTROL_ENABLE_INT BIT(4) #define SAHARA_REG_CMD 0x0C -#define SAHARA_CMD_RESET (1 << 0) -#define SAHARA_CMD_CLEAR_INT (1 << 8) -#define SAHARA_CMD_CLEAR_ERR (1 << 9) -#define SAHARA_CMD_SINGLE_STEP (1 << 10) -#define SAHARA_CMD_MODE_BATCH (1 << 16) -#define SAHARA_CMD_MODE_DEBUG (1 << 18) +#define SAHARA_CMD_RESET BIT(0) +#define SAHARA_CMD_CLEAR_INT BIT(8) +#define SAHARA_CMD_CLEAR_ERR BIT(9) +#define SAHARA_CMD_SINGLE_STEP BIT(10) +#define SAHARA_CMD_MODE_BATCH BIT(16) +#define SAHARA_CMD_MODE_DEBUG BIT(18) #define SAHARA_REG_STATUS 0x10 #define SAHARA_STATUS_GET_STATE(x) ((x) & 0x7) #define SAHARA_STATE_IDLE 0 @@ -97,25 +97,25 @@ #define SAHARA_STATE_ERR 2 #define SAHARA_STATE_FAULT 3 #define SAHARA_STATE_COMPLETE 4 -#define SAHARA_STATE_COMP_FLAG (1 << 2) -#define SAHARA_STATUS_DAR_FULL (1 << 3) -#define SAHARA_STATUS_ERROR (1 << 4) -#define SAHARA_STATUS_SECURE (1 << 5) -#define SAHARA_STATUS_FAIL (1 << 6) -#define SAHARA_STATUS_INIT (1 << 7) -#define SAHARA_STATUS_RNG_RESEED (1 << 8) -#define SAHARA_STATUS_ACTIVE_RNG (1 << 9) -#define SAHARA_STATUS_ACTIVE_MDHA (1 << 10) -#define SAHARA_STATUS_ACTIVE_SKHA (1 << 11) -#define SAHARA_STATUS_MODE_BATCH (1 << 16) -#define SAHARA_STATUS_MODE_DEDICATED (1 << 17) -#define SAHARA_STATUS_MODE_DEBUG (1 << 18) +#define SAHARA_STATE_COMP_FLAG BIT(2) +#define SAHARA_STATUS_DAR_FULL BIT(3) +#define SAHARA_STATUS_ERROR BIT(4) +#define SAHARA_STATUS_SECURE BIT(5) +#define SAHARA_STATUS_FAIL BIT(6) +#define SAHARA_STATUS_INIT BIT(7) +#define SAHARA_STATUS_RNG_RESEED BIT(8) +#define SAHARA_STATUS_ACTIVE_RNG BIT(9) +#define SAHARA_STATUS_ACTIVE_MDHA BIT(10) +#define SAHARA_STATUS_ACTIVE_SKHA BIT(11) +#define SAHARA_STATUS_MODE_BATCH BIT(16) +#define SAHARA_STATUS_MODE_DEDICATED BIT(17) +#define SAHARA_STATUS_MODE_DEBUG BIT(18) #define SAHARA_STATUS_GET_ISTATE(x) (((x) >> 24) & 0xff) #define SAHARA_REG_ERRSTATUS 0x14 #define SAHARA_ERRSTATUS_GET_SOURCE(x) ((x) & 0xf) #define SAHARA_ERRSOURCE_CHA 14 #define SAHARA_ERRSOURCE_DMA 15 -#define SAHARA_ERRSTATUS_DMA_DIR (1 << 8) +#define SAHARA_ERRSTATUS_DMA_DIR BIT(8) #define SAHARA_ERRSTATUS_GET_DMASZ(x) (((x) >> 9) & 0x3) #define SAHARA_ERRSTATUS_GET_DMASRC(x) (((x) >> 13) & 0x7) #define SAHARA_ERRSTATUS_GET_CHASRC(x) (((x) >> 16) & 0xfff) From patchwork Sat Dec 23 18:11:03 2023 Content-Type: text/plain; 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Also, use dev_err_probe() for error reporting. Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 31 ++++++++----------------------- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index ba7d3a917101..619a1df69410 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -1352,17 +1352,15 @@ static int sahara_probe(struct platform_device *pdev) } /* clocks */ - dev->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); - if (IS_ERR(dev->clk_ipg)) { - dev_err(&pdev->dev, "Could not get ipg clock\n"); - return PTR_ERR(dev->clk_ipg); - } + dev->clk_ipg = devm_clk_get_enabled(&pdev->dev, "ipg"); + if (IS_ERR(dev->clk_ipg)) + return dev_err_probe(&pdev->dev, PTR_ERR(dev->clk_ipg), + "Could not get ipg clock\n"); - dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); - if (IS_ERR(dev->clk_ahb)) { - dev_err(&pdev->dev, "Could not get ahb clock\n"); - return PTR_ERR(dev->clk_ahb); - } + dev->clk_ahb = devm_clk_get_enabled(&pdev->dev, "ahb"); + if (IS_ERR(dev->clk_ahb)) + return dev_err_probe(&pdev->dev, PTR_ERR(dev->clk_ahb), + "Could not get ahb clock\n"); /* Allocate HW descriptors */ dev->hw_desc[0] = dmam_alloc_coherent(&pdev->dev, @@ -1422,13 +1420,6 @@ static int sahara_probe(struct platform_device *pdev) init_completion(&dev->dma_completion); - err = clk_prepare_enable(dev->clk_ipg); - if (err) - return err; - err = clk_prepare_enable(dev->clk_ahb); - if (err) - goto clk_ipg_disable; - version = sahara_read(dev, SAHARA_REG_VERSION); if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx27-sahara")) { if (version != SAHARA_VERSION_3) @@ -1466,9 +1457,6 @@ static int sahara_probe(struct platform_device *pdev) err_algs: kthread_stop(dev->kthread); dev_ptr = NULL; - clk_disable_unprepare(dev->clk_ahb); -clk_ipg_disable: - clk_disable_unprepare(dev->clk_ipg); return err; } @@ -1481,9 +1469,6 @@ static void sahara_remove(struct platform_device *pdev) sahara_unregister_algs(dev); - clk_disable_unprepare(dev->clk_ipg); - clk_disable_unprepare(dev->clk_ahb); - dev_ptr = NULL; } From patchwork Sat Dec 23 18:11:04 2023 Content-Type: text/plain; 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While at it, also remove explicit error messages from every potential -ENOMEM. Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index 619a1df69410..253a3dafdff1 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -1346,10 +1346,9 @@ static int sahara_probe(struct platform_device *pdev) err = devm_request_irq(&pdev->dev, irq, sahara_irq_handler, 0, dev_name(&pdev->dev), dev); - if (err) { - dev_err(&pdev->dev, "failed to request irq\n"); - return err; - } + if (err) + return dev_err_probe(&pdev->dev, err, + "failed to request irq\n"); /* clocks */ dev->clk_ipg = devm_clk_get_enabled(&pdev->dev, "ipg"); @@ -1366,10 +1365,8 @@ static int sahara_probe(struct platform_device *pdev) dev->hw_desc[0] = dmam_alloc_coherent(&pdev->dev, SAHARA_MAX_HW_DESC * sizeof(struct sahara_hw_desc), &dev->hw_phys_desc[0], GFP_KERNEL); - if (!dev->hw_desc[0]) { - dev_err(&pdev->dev, "Could not allocate hw descriptors\n"); + if (!dev->hw_desc[0]) return -ENOMEM; - } dev->hw_desc[1] = dev->hw_desc[0] + 1; dev->hw_phys_desc[1] = dev->hw_phys_desc[0] + sizeof(struct sahara_hw_desc); @@ -1377,10 +1374,8 @@ static int sahara_probe(struct platform_device *pdev) /* Allocate space for iv and key */ dev->key_base = dmam_alloc_coherent(&pdev->dev, 2 * AES_KEYSIZE_128, &dev->key_phys_base, GFP_KERNEL); - if (!dev->key_base) { - dev_err(&pdev->dev, "Could not allocate memory for key\n"); + if (!dev->key_base) return -ENOMEM; - } dev->iv_base = dev->key_base + AES_KEYSIZE_128; dev->iv_phys_base = dev->key_phys_base + AES_KEYSIZE_128; @@ -1388,19 +1383,15 @@ static int sahara_probe(struct platform_device *pdev) dev->context_base = dmam_alloc_coherent(&pdev->dev, SHA256_DIGEST_SIZE + 4, &dev->context_phys_base, GFP_KERNEL); - if (!dev->context_base) { - dev_err(&pdev->dev, "Could not allocate memory for MDHA context\n"); + if (!dev->context_base) return -ENOMEM; - } /* Allocate space for HW links */ dev->hw_link[0] = dmam_alloc_coherent(&pdev->dev, SAHARA_MAX_HW_LINK * sizeof(struct sahara_hw_link), &dev->hw_phys_link[0], GFP_KERNEL); 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Drop the 'active' flag and set 'first' directly in sahara_sha_init(). Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index 253a3dafdff1..cd14514a43bb 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -168,7 +168,6 @@ struct sahara_aes_reqctx { * @total: total number of bytes for transfer * @last: is this the last block * @first: is this the first block - * @active: inside a transfer */ struct sahara_sha_reqctx { u8 buf[SAHARA_MAX_SHA_BLOCK_SIZE]; @@ -184,7 +183,6 @@ struct sahara_sha_reqctx { size_t total; unsigned int last; unsigned int first; - unsigned int active; }; struct sahara_dev { @@ -1053,11 +1051,6 @@ static int sahara_sha_enqueue(struct ahash_request *req, int last) rctx->last = last; - if (!rctx->active) { - rctx->active = 1; - rctx->first = 1; - } - spin_lock_bh(&dev->queue_spinlock); ret = crypto_enqueue_request(&dev->queue, &req->base); spin_unlock_bh(&dev->queue_spinlock); @@ -1088,7 +1081,7 @@ static int sahara_sha_init(struct ahash_request *req) } rctx->context_size = rctx->digest_size + 4; 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Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index cd14514a43bb..fdae8c7e7c78 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -1440,7 +1440,6 @@ static int sahara_probe(struct platform_device *pdev) err_algs: kthread_stop(dev->kthread); - dev_ptr = NULL; return err; } @@ -1452,8 +1451,6 @@ static void sahara_remove(struct platform_device *pdev) kthread_stop(dev->kthread); sahara_unregister_algs(dev); - - dev_ptr = NULL; } static struct platform_driver sahara_driver = { From patchwork Sat Dec 23 18:11:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ovidiu Panait X-Patchwork-Id: 13504057 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mx0b-0064b401.pphosted.com (mx0b-0064b401.pphosted.com [205.220.178.238]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0359315EB0 for ; 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Signed-off-by: Ovidiu Panait --- drivers/crypto/sahara.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index fdae8c7e7c78..886395603a3a 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -682,11 +682,8 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) dev_dbg(dev->device, "nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen, !!(mode & FLAGS_ENCRYPT), !!(mode & FLAGS_CBC)); - if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE)) { - dev_err(dev->device, - "request size is not exact amount of AES blocks\n"); + if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE)) return -EINVAL; - } rctx->mode = mode; From patchwork Sat Dec 23 18:11:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ovidiu Panait X-Patchwork-Id: 13504058 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mx0b-0064b401.pphosted.com (mx0b-0064b401.pphosted.com [205.220.178.238]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96A1F168AC for ; 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Signed-off-by: Ovidiu Panait --- drivers/crypto/Kconfig | 1 + drivers/crypto/sahara.c | 326 ++++++++++++++++++---------------------- 2 files changed, 147 insertions(+), 180 deletions(-) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 79c3bb9c99c3..0991f026cb07 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -306,6 +306,7 @@ config CRYPTO_DEV_SAHARA select CRYPTO_SKCIPHER select CRYPTO_AES select CRYPTO_ECB + select CRYPTO_ENGINE help This option enables support for the SAHARA HW crypto accelerator found in some Freescale i.MX chips. diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index 886395603a3a..6f3935f450ac 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -24,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -73,9 +73,6 @@ #define SAHARA_HDR_MDHA_MAC_FULL BIT(9) #define SAHARA_HDR_MDHA_SSL BIT(10) -/* SAHARA can only process one request at a time */ -#define SAHARA_QUEUE_LENGTH 1 - #define SAHARA_REG_VERSION 0x00 #define SAHARA_REG_DAR 0x04 #define SAHARA_REG_CONTROL 0x08 @@ -191,12 +188,9 @@ struct sahara_dev { void __iomem *regs_base; struct clk *clk_ipg; struct clk *clk_ahb; - spinlock_t queue_spinlock; - struct task_struct *kthread; struct completion dma_completion; struct sahara_ctx *ctx; - struct crypto_queue queue; unsigned long flags; struct sahara_hw_desc *hw_desc[SAHARA_MAX_HW_DESC]; @@ -219,6 +213,8 @@ struct sahara_dev { int nb_in_sg; struct scatterlist *out_sg; int nb_out_sg; + + struct crypto_engine *engine; }; static struct sahara_dev *dev_ptr; @@ -671,7 +667,6 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) struct sahara_ctx *ctx = crypto_skcipher_ctx( crypto_skcipher_reqtfm(req)); struct sahara_dev *dev = dev_ptr; - int err = 0; if (!req->cryptlen) return 0; @@ -687,13 +682,7 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) rctx->mode = mode; - spin_lock_bh(&dev->queue_spinlock); - err = crypto_enqueue_request(&dev->queue, &req->base); - spin_unlock_bh(&dev->queue_spinlock); - - wake_up_process(dev->kthread); - - return err; + return crypto_transfer_skcipher_request_to_engine(dev->engine, req); } static int sahara_aes_ecb_encrypt(struct skcipher_request *req) @@ -994,45 +983,26 @@ static int sahara_sha_process(struct ahash_request *req) return 0; } -static int sahara_queue_manage(void *data) +static int sahara_do_one_request(struct crypto_engine *engine, void *areq) { - struct sahara_dev *dev = data; - struct crypto_async_request *async_req; - struct crypto_async_request *backlog; - int ret = 0; - - do { - __set_current_state(TASK_INTERRUPTIBLE); - - spin_lock_bh(&dev->queue_spinlock); - backlog = crypto_get_backlog(&dev->queue); - async_req = crypto_dequeue_request(&dev->queue); - spin_unlock_bh(&dev->queue_spinlock); - - if (backlog) - crypto_request_complete(backlog, -EINPROGRESS); - - if (async_req) { - if (crypto_tfm_alg_type(async_req->tfm) == - CRYPTO_ALG_TYPE_AHASH) { - struct ahash_request *req = - ahash_request_cast(async_req); - - ret = sahara_sha_process(req); - } else { - struct skcipher_request *req = - skcipher_request_cast(async_req); - - ret = sahara_aes_process(req); - } + struct crypto_async_request *async_req = areq; + int err; - crypto_request_complete(async_req, ret); + if (crypto_tfm_alg_type(async_req->tfm) == CRYPTO_ALG_TYPE_AHASH) { + struct ahash_request *req = ahash_request_cast(async_req); - continue; - } + err = sahara_sha_process(req); + local_bh_disable(); + crypto_finalize_hash_request(engine, req, err); + local_bh_enable(); + } else { + struct skcipher_request *req = skcipher_request_cast(async_req); - schedule(); - } while (!kthread_should_stop()); + err = sahara_aes_process(skcipher_request_cast(async_req)); + local_bh_disable(); + crypto_finalize_skcipher_request(engine, req, err); + local_bh_enable(); + } return 0; } @@ -1041,20 +1011,13 @@ static int sahara_sha_enqueue(struct ahash_request *req, int last) { struct sahara_sha_reqctx *rctx = ahash_request_ctx(req); struct sahara_dev *dev = dev_ptr; - int ret; if (!req->nbytes && !last) return 0; rctx->last = last; - spin_lock_bh(&dev->queue_spinlock); - ret = crypto_enqueue_request(&dev->queue, &req->base); - spin_unlock_bh(&dev->queue_spinlock); - - wake_up_process(dev->kthread); - - return ret; + return crypto_transfer_hash_request_to_engine(dev->engine, req); } static int sahara_sha_init(struct ahash_request *req) @@ -1132,94 +1095,114 @@ static int sahara_sha_cra_init(struct crypto_tfm *tfm) return 0; } -static struct skcipher_alg aes_algs[] = { +static struct skcipher_engine_alg aes_algs[] = { { - .base.cra_name = "ecb(aes)", - .base.cra_driver_name = "sahara-ecb-aes", - .base.cra_priority = 300, - .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, - .base.cra_blocksize = AES_BLOCK_SIZE, - .base.cra_ctxsize = sizeof(struct sahara_ctx), - .base.cra_alignmask = 0x0, - .base.cra_module = THIS_MODULE, - - .init = sahara_aes_init_tfm, - .exit = sahara_aes_exit_tfm, - .min_keysize = AES_MIN_KEY_SIZE , - .max_keysize = AES_MAX_KEY_SIZE, - .setkey = sahara_aes_setkey, - .encrypt = sahara_aes_ecb_encrypt, - .decrypt = sahara_aes_ecb_decrypt, + .base = { + .base.cra_name = "ecb(aes)", + .base.cra_driver_name = "sahara-ecb-aes", + .base.cra_priority = 300, + .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = AES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct sahara_ctx), + .base.cra_alignmask = 0x0, + .base.cra_module = THIS_MODULE, + + .init = sahara_aes_init_tfm, + .exit = sahara_aes_exit_tfm, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = sahara_aes_setkey, + .encrypt = sahara_aes_ecb_encrypt, + .decrypt = sahara_aes_ecb_decrypt, + }, + .op = { + .do_one_request = sahara_do_one_request, + }, }, { - .base.cra_name = "cbc(aes)", - .base.cra_driver_name = "sahara-cbc-aes", - .base.cra_priority = 300, - .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, - .base.cra_blocksize = AES_BLOCK_SIZE, - .base.cra_ctxsize = sizeof(struct sahara_ctx), - .base.cra_alignmask = 0x0, - .base.cra_module = THIS_MODULE, - - .init = sahara_aes_init_tfm, - .exit = sahara_aes_exit_tfm, - .min_keysize = AES_MIN_KEY_SIZE , - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = sahara_aes_setkey, - .encrypt = sahara_aes_cbc_encrypt, - .decrypt = sahara_aes_cbc_decrypt, + .base = { + .base.cra_name = "cbc(aes)", + .base.cra_driver_name = "sahara-cbc-aes", + .base.cra_priority = 300, + .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .base.cra_blocksize = AES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct sahara_ctx), + .base.cra_alignmask = 0x0, + .base.cra_module = THIS_MODULE, + + .init = sahara_aes_init_tfm, + .exit = sahara_aes_exit_tfm, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = sahara_aes_setkey, + .encrypt = sahara_aes_cbc_encrypt, + .decrypt = sahara_aes_cbc_decrypt, + }, + .op = { + .do_one_request = sahara_do_one_request, + }, } }; -static struct ahash_alg sha_v3_algs[] = { +static struct ahash_engine_alg sha_v3_algs[] = { { - .init = sahara_sha_init, - .update = sahara_sha_update, - .final = sahara_sha_final, - .finup = sahara_sha_finup, - .digest = sahara_sha_digest, - .export = sahara_sha_export, - .import = sahara_sha_import, - .halg.digestsize = SHA1_DIGEST_SIZE, - .halg.statesize = sizeof(struct sahara_sha_reqctx), - .halg.base = { - .cra_name = "sha1", - .cra_driver_name = "sahara-sha1", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_ASYNC | - CRYPTO_ALG_NEED_FALLBACK, - .cra_blocksize = SHA1_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct sahara_ctx), - .cra_alignmask = 0, - .cra_module = THIS_MODULE, - .cra_init = sahara_sha_cra_init, - } + .base = { + .init = sahara_sha_init, + .update = sahara_sha_update, + .final = sahara_sha_final, + .finup = sahara_sha_finup, + .digest = sahara_sha_digest, + .export = sahara_sha_export, + .import = sahara_sha_import, + .halg.digestsize = SHA1_DIGEST_SIZE, + .halg.statesize = sizeof(struct sahara_sha_reqctx), + .halg.base = { + .cra_name = "sha1", + .cra_driver_name = "sahara-sha1", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = SHA1_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct sahara_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + .cra_init = sahara_sha_cra_init, + } + }, + .op = { + .do_one_request = sahara_do_one_request, + }, }, }; -static struct ahash_alg sha_v4_algs[] = { +static struct ahash_engine_alg sha_v4_algs[] = { { - .init = sahara_sha_init, - .update = sahara_sha_update, - .final = sahara_sha_final, - .finup = sahara_sha_finup, - .digest = sahara_sha_digest, - .export = sahara_sha_export, - .import = sahara_sha_import, - .halg.digestsize = SHA256_DIGEST_SIZE, - .halg.statesize = sizeof(struct sahara_sha_reqctx), - .halg.base = { - .cra_name = "sha256", - .cra_driver_name = "sahara-sha256", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_ASYNC | - CRYPTO_ALG_NEED_FALLBACK, - .cra_blocksize = SHA256_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct sahara_ctx), - .cra_alignmask = 0, - .cra_module = THIS_MODULE, - .cra_init = sahara_sha_cra_init, - } + .base = { + .init = sahara_sha_init, + .update = sahara_sha_update, + .final = sahara_sha_final, + .finup = sahara_sha_finup, + .digest = sahara_sha_digest, + .export = sahara_sha_export, + .import = sahara_sha_import, + .halg.digestsize = SHA256_DIGEST_SIZE, + .halg.statesize = sizeof(struct sahara_sha_reqctx), + .halg.base = { + .cra_name = "sha256", + .cra_driver_name = "sahara-sha256", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = SHA256_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct sahara_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + .cra_init = sahara_sha_cra_init, + } + }, + .op = { + .do_one_request = sahara_do_one_request, + }, }, }; @@ -1249,57 +1232,39 @@ static irqreturn_t sahara_irq_handler(int irq, void *data) static int sahara_register_algs(struct sahara_dev *dev) { int err; - unsigned int i, j, k, l; - for (i = 0; i < ARRAY_SIZE(aes_algs); i++) { - err = crypto_register_skcipher(&aes_algs[i]); - if (err) - goto err_aes_algs; - } + err = crypto_engine_register_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); + if (err) + return err; - for (k = 0; k < ARRAY_SIZE(sha_v3_algs); k++) { - err = crypto_register_ahash(&sha_v3_algs[k]); + err = crypto_engine_register_ahashes(sha_v3_algs, + ARRAY_SIZE(sha_v3_algs)); + if (err) + goto err_aes_algs; + + if (dev->version > SAHARA_VERSION_3) { + err = crypto_engine_register_ahashes(sha_v4_algs, + ARRAY_SIZE(sha_v4_algs)); if (err) goto err_sha_v3_algs; } - if (dev->version > SAHARA_VERSION_3) - for (l = 0; l < ARRAY_SIZE(sha_v4_algs); l++) { - err = crypto_register_ahash(&sha_v4_algs[l]); - if (err) - goto err_sha_v4_algs; - } - return 0; -err_sha_v4_algs: - for (j = 0; j < l; j++) - crypto_unregister_ahash(&sha_v4_algs[j]); - err_sha_v3_algs: - for (j = 0; j < k; j++) - crypto_unregister_ahash(&sha_v3_algs[j]); + crypto_engine_unregister_ahashes(sha_v3_algs, ARRAY_SIZE(sha_v3_algs)); err_aes_algs: - for (j = 0; j < i; j++) - crypto_unregister_skcipher(&aes_algs[j]); + crypto_engine_unregister_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); return err; } static void sahara_unregister_algs(struct sahara_dev *dev) { - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(aes_algs); i++) - crypto_unregister_skcipher(&aes_algs[i]); - - for (i = 0; i < ARRAY_SIZE(sha_v3_algs); i++) - crypto_unregister_ahash(&sha_v3_algs[i]); - - if (dev->version > SAHARA_VERSION_3) - for (i = 0; i < ARRAY_SIZE(sha_v4_algs); i++) - crypto_unregister_ahash(&sha_v4_algs[i]); + crypto_engine_unregister_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); + crypto_engine_unregister_ahashes(sha_v3_algs, ARRAY_SIZE(sha_v3_algs)); + crypto_engine_unregister_ahashes(sha_v4_algs, ARRAY_SIZE(sha_v4_algs)); } static const struct of_device_id sahara_dt_ids[] = { @@ -1388,15 +1353,17 @@ static int sahara_probe(struct platform_device *pdev) dev->hw_link[i] = dev->hw_link[i - 1] + 1; } - crypto_init_queue(&dev->queue, SAHARA_QUEUE_LENGTH); - - spin_lock_init(&dev->queue_spinlock); - dev_ptr = dev; - dev->kthread = kthread_run(sahara_queue_manage, dev, "sahara_crypto"); - if (IS_ERR(dev->kthread)) { - return PTR_ERR(dev->kthread); + dev->engine = crypto_engine_alloc_init(&pdev->dev, true); + if (!dev->engine) + return -ENOMEM; + + err = crypto_engine_start(dev->engine); + if (err) { + crypto_engine_exit(dev->engine); + return dev_err_probe(&pdev->dev, err, + "Could not start crypto engine\n"); } init_completion(&dev->dma_completion); @@ -1436,7 +1403,7 @@ static int sahara_probe(struct platform_device *pdev) return 0; err_algs: - kthread_stop(dev->kthread); + crypto_engine_exit(dev->engine); return err; } @@ -1445,8 +1412,7 @@ static void sahara_remove(struct platform_device *pdev) { struct sahara_dev *dev = platform_get_drvdata(pdev); - kthread_stop(dev->kthread); - + crypto_engine_exit(dev->engine); sahara_unregister_algs(dev); }