From patchwork Thu Dec 28 12:57:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506003 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75CC179C3 for ; Thu, 28 Dec 2023 12:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hzT28vd3" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40d5b159350so19298535e9.2 for ; Thu, 28 Dec 2023 04:58:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768292; x=1704373092; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QLJJCnpqNRt9VWnjS9HQfnci/ScCBcd+pC2hzKQpxGg=; b=hzT28vd3S6H8KpN8TRyThcgbrYr6s6BlJQrvZvV4sl2+Ur7Ae3ldvMPrWqJA6Dwx01 QGY26ni0R4QkbI96nZ7w13ZtAqdoeUOkMXeGt50YapKco/fio9DDDB0UL+TwMLtNAffF 0skT/4SAQAwOJGgMbRpfURiRXaap2CLoAfGXgY3PVPHT7jw9kzxoeEhX4z9lbnU4pHMJ j8Y5kcLIUC9IWkI8hJnTCGJB0mRZoL99lRyHrJDO8JwPYDxjp18N2RtzGKSkvC7N0AUb SZiCMBRkD2D8EDO9jPNxyGXVfwzrd+LUvXOo6zNSk6pKtbZz2hiTRUcXIj4c0AnsM5NU DOPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768292; x=1704373092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QLJJCnpqNRt9VWnjS9HQfnci/ScCBcd+pC2hzKQpxGg=; b=vdj4UkOIjnFxYrlKzPD3GGO92eLyljy0zE9jW6dHU1/Ez1KbPP+KxtMdGOiuhJ4J3Y 8vOIQJiCgugbrANpJk7gjmh+vSxAGoevjNWj6+GplWT/mjTc6SJcMowO/TCnXCOm0l9K /w4zwlA+NB5rzxeC5LdI5Brpfg9e1fq9STpPWjqx7sumOHaQ2toOlN8xMwwOHSEJMJXc G45DnpG3tHWldhb5E2U3PB4aMFd1r20NMTVdXlJKvVu7JpUDTmZ4ZBfx9MyUcFVKyPlN 0GcPHIHqUOTgwbP8oM84G3PPpekJr8a6jF+M/qhEFbfia5yRyegDOV/P23AnUIzLVHdy F4cw== X-Gm-Message-State: AOJu0YyTXuraf5rvDoztOu3NPeDoCPJxDSJuaXFhA3ssjEMHkHdFxdM/ 70lGW3dttzIhtTs6d9D7jwOwuWRb0YH3gQ== X-Google-Smtp-Source: AGHT+IEWIfqSlPG7wal12kaKVDGd2xFjtk1124PETk0To6JEBlKcPa9fVYJkh+dPWOImveFQ/z8RNQ== X-Received: by 2002:a05:600c:3114:b0:40d:70c9:eb14 with SMTP id g20-20020a05600c311400b0040d70c9eb14mr248255wmo.146.1703768291416; Thu, 28 Dec 2023 04:58:11 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:10 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 01/12] dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit Date: Thu, 28 Dec 2023 12:57:54 +0000 Message-ID: <20231228125805.661725-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add dt-schema documentation for the Connectivity Peripheral 0 (PERIC0) clock management unit. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: - fix comments as per Sam's suggestion and collect his R-b tag - Rob's suggestion of renaming the clock-names to just "bus" and "ip" was not implemented as I felt it affects readability in the driver and consistency with other exynos clock drivers. I will happily update the names in the -rc phase if someone else has a stronger opinion than mine. .../bindings/clock/google,gs101-clock.yaml | 25 +++++- include/dt-bindings/clock/google,gs101.h | 81 +++++++++++++++++++ 2 files changed, 104 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 3eebc03a309b..ba54c13c55bc 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -30,14 +30,15 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-peric0 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 "#clock-cells": const: 1 @@ -88,6 +89,26 @@ allOf: - const: dout_cmu_misc_bus - const: dout_cmu_misc_sss + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Connectivity Peripheral 0 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_peric0_bus + - const: dout_cmu_peric0_ip + additionalProperties: false examples: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 21adec22387c..64e6bdc6359c 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -389,4 +389,85 @@ #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_I3C_USER 2 +#define CLK_MOUT_PERIC0_USI0_UART_USER 3 +#define CLK_MOUT_PERIC0_USI14_USI_USER 4 +#define CLK_MOUT_PERIC0_USI1_USI_USER 5 +#define CLK_MOUT_PERIC0_USI2_USI_USER 6 +#define CLK_MOUT_PERIC0_USI3_USI_USER 7 +#define CLK_MOUT_PERIC0_USI4_USI_USER 8 +#define CLK_MOUT_PERIC0_USI5_USI_USER 9 +#define CLK_MOUT_PERIC0_USI6_USI_USER 10 +#define CLK_MOUT_PERIC0_USI7_USI_USER 11 +#define CLK_MOUT_PERIC0_USI8_USI_USER 12 +#define CLK_DOUT_PERIC0_I3C 13 +#define CLK_DOUT_PERIC0_USI0_UART 14 +#define CLK_DOUT_PERIC0_USI14_USI 15 +#define CLK_DOUT_PERIC0_USI1_USI 16 +#define CLK_DOUT_PERIC0_USI2_USI 17 +#define CLK_DOUT_PERIC0_USI3_USI 18 +#define CLK_DOUT_PERIC0_USI4_USI 19 +#define CLK_DOUT_PERIC0_USI5_USI 20 +#define CLK_DOUT_PERIC0_USI6_USI 21 +#define CLK_DOUT_PERIC0_USI7_USI 22 +#define CLK_DOUT_PERIC0_USI8_USI 23 +#define CLK_GOUT_PERIC0_IP 24 +#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25 +#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26 +#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27 +#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28 +#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29 +#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66 +#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67 +#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78 +#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From patchwork Thu Dec 28 12:57:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506004 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC2BA79CB for ; Thu, 28 Dec 2023 12:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BgBq2nX2" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40d5b159497so21438985e9.1 for ; Thu, 28 Dec 2023 04:58:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768292; x=1704373092; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/LzbWE9szdRtnTR5PECxBTSqD8svHOqTLDWpgcXftXE=; b=BgBq2nX2itV8MpKeHpPQ1JDKDaEZ+S1grWWmKNTc2jSlcU+eopUT+Rr1rcDxjXJ7gX F5FCNwdG5IZDAAWgV9q3VJshMydNXBlWyaB8TuybeT51VDHZP9Q3rHs1dI/Z2pqdZQOE fga8cWWtKUl9oUCtWAjKEVaqJoA4As5cFEgLHB9Vx6b6pNmOwIDhjGtKzAHpR26yXqYQ Ln4Z2x0tOpFzTgoenm8ZFlJxxKWaGJKL0aNpldGMZ2RBcqQA2WetZftWNSORf+4NJEfh uTIGUMmuQJZWiR/uBx24fO18xotJ9vwvb3rDxCSRpvZEG/TbtNrRhOvCjjyuGN+Y/PBY SOOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768292; x=1704373092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/LzbWE9szdRtnTR5PECxBTSqD8svHOqTLDWpgcXftXE=; b=r2kkc81+D0PquObW3npHR0SjrCCARdyXjkXOZNfXXrex9JHnffbrOZpXw6yinvNCux TwQN/M0ToZFQyZm/kqkxG0wcUhjdHx4lnYVCmpRQk3KSu2nkjyAsoJllsqhCt8yP4yUf ppT+4dYN+aaOfSyE7/l1v3lrR6AC1GxWqeO3E+2IuGPg5yD2LFYDXENZgYvz+Cl7DdMh RnF337xwGK/Hh93vt8Q3cRB7hkwwVRv3BGf7vYIDb84+fQmJExfZTyZP0GRLI0wDxjg3 p2DbvcfV0+xKT+bAE7ki6faWcX1nbkFylfn7YSbHDu4OCq2MlDSnEzcyS07BkG+evDv4 R/Cg== X-Gm-Message-State: AOJu0YxY8OSM3aP9gk4z2asOYZoXlG/Lq0xWe5LUu9NNrrOIuiZP+B2o g8j79Wy8/mIsshBSpxeM0cEu8B5HuCJ/QA== X-Google-Smtp-Source: AGHT+IE7E9kPf6I6zhnXOaF+uBAHwWTIoJTK7yrN1FHwVGdUVH+mfR5uoQTW8/LH67NmXpPT96hsmA== X-Received: by 2002:a7b:c3c8:0:b0:40d:39d0:9916 with SMTP id t8-20020a7bc3c8000000b0040d39d09916mr3985455wmj.246.1703768292208; Thu, 28 Dec 2023 04:58:12 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:11 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus , Wolfram Sang , Rob Herring Subject: [PATCH v2 02/12] dt-bindings: i2c: exynos5: add google,gs101-hsi2c compatible Date: Thu, 28 Dec 2023 12:57:55 +0000 Message-ID: <20231228125805.661725-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add google,gs101-hsi2c dedicated compatible for representing I2C of Google GS101 SoC. Acked-by: Wolfram Sang Acked-by: Rob Herring Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: collect tags Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index df9c57bca2a8..cc8bba5537b9 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -33,6 +33,7 @@ properties: - const: samsung,exynos7-hsi2c - items: - enum: + - google,gs101-hsi2c - samsung,exynos850-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 From patchwork Thu Dec 28 12:57:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506005 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F1AC79F5 for ; Thu, 28 Dec 2023 12:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G0/1yfhW" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-40d3ae326f6so67625845e9.3 for ; Thu, 28 Dec 2023 04:58:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768293; x=1704373093; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qARtnmQgOAQf1WGszfbQmrcKdGUB3d5pXOUSqwXI61U=; b=G0/1yfhW9D3Z1ZtHw4UFkCpHq+Xf2Kapzg89rb5JH7GtJInJGDgvN0Kt3Q70j8Camy J63mDFCEOQYsolP+0ah4ureSW/mHmdLlnGoSaQYff8vIwj6QI65lKxxXBbNS2kJ9tPOb aFi9ZZzipXHgG/B8pyH1pzPMBBIjdRNzuGXM1ZquvkV5JWV1fPcBOjSPb0HCGoWkYNc1 d+yzwByiqB9e1CixYjm4XOyQQ7rW4ol+Vsw/Y1yv1sWpJXSBmPpdwjVGinaQ5+jNXuDs P23t8qSOyZ16nw+FdH75DNOkPruM+70gQSMTWsvUo0aMyLgWVqhIMlerNsNUe5HTt+Zg vAVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768293; x=1704373093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qARtnmQgOAQf1WGszfbQmrcKdGUB3d5pXOUSqwXI61U=; b=tApOzPn2Npdc3aiptDOiwY51OtB23QNEfaedsxbj82D/IbhGdugQHOyjo8I3UZkvI/ 5zdKl2nQbOGO/0ylq/RlUKJOietKaLyvWVcLOzPaAep81KUWa3Lnvrcbr9YyOUFC22MA FRTQeLAK9xFFp+NXjBRx2mIA6IENlBMArA8x/v52HiUv2J8C047Xtwt+I6aiWNwCqi84 7Oc5Rtep1rLnn37sk0dO1KDCPeZsP/zuDFvCTxKADzgeD8WMiIQreuq58ziEsKx238te X0pFk2JJEnH9ncr85czQCmXjS52cpPEi3P9Mhuj69TAv3+x0w09eGHu5b8BqcNwzRWRg UeMA== X-Gm-Message-State: AOJu0YySsgtOTRUwfaM04Ms79UYqIyGggxjT890JmtDH6CjBFSMR/7Hy /TV91WgOE/bq5EEbOEcJUZvbArUvyPcruA== X-Google-Smtp-Source: AGHT+IHT57QGYw7zLPX8R3bhMUgX3eDW1EDvo5Oc9TXgPSM2ZkHfeK0hm8E/vlZ6afNi/TT87YNVsA== X-Received: by 2002:a05:600c:33aa:b0:40d:3a34:82ef with SMTP id o42-20020a05600c33aa00b0040d3a3482efmr5244462wmp.136.1703768293249; Thu, 28 Dec 2023 04:58:13 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:12 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus , Krzysztof Kozlowski Subject: [PATCH v2 03/12] dt-bindings: serial: samsung: do not allow reg-io-width for gs101 Date: Thu, 28 Dec 2023 12:57:56 +0000 Message-ID: <20231228125805.661725-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 All gs101 serial ports are restricted to 32-bit register accesses. This requirement will be inferred from the compatible. Do not allow the reg-io-width property for the google,gs101-uart compatible. Suggested-by: Krzysztof Kozlowski Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: new patch Documentation/devicetree/bindings/serial/samsung_uart.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 133259ed3a34..0f0131026911 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -143,6 +143,8 @@ allOf: then: required: - samsung,uart-fifosize + properties: + reg-io-width: false unevaluatedProperties: false From patchwork Thu Dec 28 12:57:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506006 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C373A79C8 for ; Thu, 28 Dec 2023 12:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZG+VGsK6" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40d4a222818so24917425e9.0 for ; Thu, 28 Dec 2023 04:58:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768294; x=1704373094; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SnGx2wWhRndPcC4hW6Eg1f4NC40IhCfbTAv3v3EwtqA=; b=ZG+VGsK6AlEuD/3EQ44I/9ISWpyItRPwcfEe5CD3ggt2Of89P35HHpkcsv87r+OQr4 iCPSzhccIfTw8E+YRpJF5MaL3z0XLn5WHxjsA60Sd8ARn/Sw1+EdiTFw+O/zdRM6w/Ol aai9jbQu5cJHYgtbImHGPr4WFztoklo9omL54fv5CA7gEQ3lrpaIDvSufRsBKOayBHsp WN5gKe4m7Ld1oIeZBZAwd7uxajbHBkFyLgpYMxzl9aH0EDmMLsmBMFgMG6ehwWifdq0F xoAdIEAi/xGCI7vzTnh2Cd8NH2jlNyR58u+w23LKAWibXK0qit13wliC5llXxiLm9AkW 3b2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768294; x=1704373094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SnGx2wWhRndPcC4hW6Eg1f4NC40IhCfbTAv3v3EwtqA=; b=iEp8oTzlw+8nemOthJW4W4bEEopNA1XE0Ferxke2EHWHMctycUKto4z43dxJxpjcNW +qmw0HQpEOKbwvGRdcZAEBJWemHHXItztlVlt+Jww6Lliw7CG/9qrDmMq1uDC39IdQnT 8VKlb8vn1bYX3Z8NiIbOWA1pd+icQstcHMHD/6R0fRy/tdrG+1ypGTXxN3gG5JCqZDtf i+ecDar6sPfq+ed5MkyL0Oup6+YPenw2UrtPzw0JXI3eZjaS611o2JZ1uoSi+05RyuZl iEWpSsw66lFKXtAIi0NssVM+Q5nzXdTCcAbKI44U7lqyz9rUKEFJttJ231KtzJRJSY3C dlww== X-Gm-Message-State: AOJu0YyI3pSS0Ej1EYat2i5ECoU774mTu0dq7G+PIaO7w/yqcer00fzv hSGV7a2aBrhfeXACZbP2Z2STYmzwUlPQcw== X-Google-Smtp-Source: AGHT+IEkaMiusBrIbTHY7fvyqMXaIjsn5PrPxvhm/x5b+n186w76a+qsxBXgq1iWnlduba/ozspo0w== X-Received: by 2002:a05:600c:b8e:b0:40d:7196:35e6 with SMTP id fl14-20020a05600c0b8e00b0040d719635e6mr132291wmb.154.1703768294173; Thu, 28 Dec 2023 04:58:14 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:13 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 04/12] tty: serial: samsung: prepare for different IO types Date: Thu, 28 Dec 2023 12:57:57 +0000 Message-ID: <20231228125805.661725-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 GS101's Connectivity Peripheral blocks (peric0/1 blocks) which include the I3C and USI (I2C, SPI, UART) only allow 32-bit register accesses. If using 8-bit register accesses, a SError Interrupt is raised causing the system unusable. Instead of specifying the reg-io-width = 4 everywhere, for each node, the requirement should be deduced from the compatible. Prepare the samsung tty driver to allow IO types different than UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all its 8 bits are exposed to uapi. We can't make NULL checks on it to verify if it's set, thus always set it from the driver's data. Signed-off-by: Tudor Ambarus --- v2: new patch drivers/tty/serial/samsung_tty.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 66bd6c090ace..97ce4b2424af 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -72,6 +72,7 @@ struct s3c24xx_uart_info { const char *name; enum s3c24xx_port_type type; unsigned int port_type; + unsigned char iotype; unsigned int fifosize; unsigned long rx_fifomask; unsigned long rx_fifoshift; @@ -1742,7 +1743,6 @@ static void s3c24xx_serial_init_port_default(int index) { spin_lock_init(&port->lock); - port->iotype = UPIO_MEM; port->uartclk = 0; port->fifosize = 16; port->flags = UPF_BOOT_AUTOCONF; @@ -1989,6 +1989,8 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) break; } + ourport->port.iotype = ourport->info->iotype; + if (np) { of_property_read_u32(np, "samsung,uart-fifosize", &ourport->port.fifosize); @@ -2401,6 +2403,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { .name = "Samsung S3C6400 UART", .type = TYPE_S3C6400, .port_type = PORT_S3C6400, + .iotype = UPIO_MEM, .fifosize = 64, .has_divslot = 1, .rx_fifomask = S3C2440_UFSTAT_RXMASK, @@ -2430,6 +2433,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .name = "Samsung S5PV210 UART", .type = TYPE_S3C6400, .port_type = PORT_S3C6400, + .iotype = UPIO_MEM, .has_divslot = 1, .rx_fifomask = S5PV210_UFSTAT_RXMASK, .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, @@ -2459,6 +2463,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .name = "Samsung Exynos UART", \ .type = TYPE_S3C6400, \ .port_type = PORT_S3C6400, \ + .iotype = UPIO_MEM, \ .has_divslot = 1, \ .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ @@ -2519,6 +2524,7 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { .name = "Apple S5L UART", .type = TYPE_APPLE_S5L, .port_type = PORT_8250, + .iotype = UPIO_MEM, .fifosize = 16, .rx_fifomask = S3C2410_UFSTAT_RXMASK, .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, @@ -2548,6 +2554,7 @@ static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { .name = "Axis ARTPEC-8 UART", .type = TYPE_S3C6400, .port_type = PORT_S3C6400, + .iotype = UPIO_MEM, .fifosize = 64, .has_divslot = 1, .rx_fifomask = S5PV210_UFSTAT_RXMASK, From patchwork Thu Dec 28 12:57:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506007 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4F3BD275 for ; Thu, 28 Dec 2023 12:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="M47tJ9iB" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-40d60a96533so12070715e9.1 for ; Thu, 28 Dec 2023 04:58:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768295; x=1704373095; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5OWSKyLISurEYSJL0AfE6kVglHBwO6tL8w6QTNbZ9XM=; b=M47tJ9iBUUH6ifLw+VPVzidwPUoLbXy8pv6uHHe7Yfo1LWlXEzbuP74S03gzTWhpX4 j+8tEDIp70xUp2++r/CI6pibj/x11xtnuE7+WpjOKJQShR/dtg5EHcthZrFvm9CQAbMo hOq2UOueBJvzn/n1a2ybBAdVg7YzBcSX+0RQzw1QWpzhhPtb+sqygkvSNxE3RPVc+uIJ ZL21rUyCsND9Tk/gxdwF5Y0keOTZV6eXRSQcWywLMdYelr17L/zWbCpVyZpSmMOT0I2X ineu0uq2gAIKBmXeMVjvdHZptEXDi7Hlk0wF4ZRJd9gAfiBZjkjId/oF3NDZHujtjoxI MDEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768295; x=1704373095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5OWSKyLISurEYSJL0AfE6kVglHBwO6tL8w6QTNbZ9XM=; b=aaMq+cDqH4WMeF6Wiuvxlq+Dj0lrZhhLooTiW0nD2DGZkljhQcGLNhDGvfPxiQ+LT/ APzgY2gkfvYOZdLzHYmhpNWkBUlOjR1N/Ec69YsgRSy2UOgnDRSXVWsF7x+BJTzXZCgc Io5glIt0ugoBletolW747+eEtNLqIPiwCSHn4elQ1TJf+sveQrqI7opH87jjksXxln+o XzmSQGnz/2jgTRpxM+WhutiiQhMwdYLbXZpdhqC0Letm6neG74gz0x/qB4lDaZH3Zsv2 +um4vhKcEihTdkNUmoSexMhaxiF3T8THXCTXE8zoUua9wxLhKWyVjxCwhnyUEY5cvPZ3 ab1A== X-Gm-Message-State: AOJu0YxNW6HWQU7G1IV+aVeyJLUZmwjdqR5JJCpZmEy8FBWxwA6jL2Vt TlOJbtYFtJBx2ZhbEFdqP7CTZ/qn+JGZBA== X-Google-Smtp-Source: AGHT+IF+JcXUazhQEFnY8zblZiKZ0crjBJb5N4O9tWky+IPg7qflkMQr4x88vx79F00HdtQ6mesyQg== X-Received: by 2002:a05:600c:5489:b0:40d:6045:b1ff with SMTP id iv9-20020a05600c548900b0040d6045b1ffmr1167130wmb.126.1703768295262; Thu, 28 Dec 2023 04:58:15 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:14 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 05/12] tty: serial: samsung: set UPIO_MEM32 iotype for gs101 Date: Thu, 28 Dec 2023 12:57:58 +0000 Message-ID: <20231228125805.661725-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 GS101's Connectivity Peripheral blocks (peric0/1 blocks) which include the I3C and USI (I2C, SPI, UART) only allow 32-bit register accesses. Instead of specifying the reg-io-width = 4 everywhere, for each node, the requirement should be deduced from the compatible. Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible. Update the uart info name to be GS101 specific in order to differentiate from the other exynos platforms. All the other settings are not changed. exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data because the iotype restriction is gs101 specific and there was no other user of exynos_fifoszdt_serial_drv_data. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: new patch drivers/tty/serial/samsung_tty.c | 38 +++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 97ce4b2424af..938127179acf 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2497,25 +2497,43 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { .fifosize = { 256, 64, 64, 64 }, }; -/* - * Common drv_data struct for platforms that specify samsung,uart-fifosize in - * device tree. - */ -static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = { - EXYNOS_COMMON_SERIAL_DRV_DATA(), +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = { + .info = { + .name = "Google GS101 UART", + .type = TYPE_S3C6400, + .port_type = PORT_S3C6400, + .iotype = UPIO_MEM32, + .has_divslot = 1, + .rx_fifomask = S5PV210_UFSTAT_RXMASK, + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, + .rx_fifofull = S5PV210_UFSTAT_RXFULL, + .tx_fifofull = S5PV210_UFSTAT_TXFULL, + .tx_fifomask = S5PV210_UFSTAT_TXMASK, + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, + .def_clk_sel = S3C2410_UCON_CLKSEL0, + .num_clks = 1, + .clksel_mask = 0, + .clksel_shift = 0, + }, + .def_cfg = { + .ucon = S5PV210_UCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + .has_fracval = 1, + }, + /* samsung,uart-fifosize must be specified in the device tree. */ .fifosize = { 0 }, }; #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) -#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data) #else #define EXYNOS4210_SERIAL_DRV_DATA NULL #define EXYNOS5433_SERIAL_DRV_DATA NULL #define EXYNOS850_SERIAL_DRV_DATA NULL -#define EXYNOS_FIFOSZDT_DRV_DATA NULL +#define GS101_SERIAL_DRV_DATA NULL #endif #ifdef CONFIG_ARCH_APPLE @@ -2603,7 +2621,7 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, }, { .name = "gs101-uart", - .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, + .driver_data = (kernel_ulong_t)GS101_SERIAL_DRV_DATA, }, { }, }; @@ -2626,7 +2644,7 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { { .compatible = "axis,artpec8-uart", .data = ARTPEC8_SERIAL_DRV_DATA }, { .compatible = "google,gs101-uart", - .data = EXYNOS_FIFOSZDT_DRV_DATA }, + .data = GS101_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); From patchwork Thu Dec 28 12:57:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506008 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C363F79C8 for ; Thu, 28 Dec 2023 12:58:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LkHzgZxh" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40d5ac76667so16278705e9.1 for ; Thu, 28 Dec 2023 04:58:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768296; x=1704373096; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XX8RT8/KwRnpjqmauq2VuiREugBeuTfdnmzmXRQSLkY=; b=LkHzgZxhMS7RFnaXfOWocaAkiaPopljttZfgzA4qZ0DTYCGY9z6Ci15SSTFHnLhmiL ZXHCT+0V/k91HeKo0SLYciIqVLfG98glh6w+nqt4E8GK0NRGM9FbFwPthVe2Bwka7lnv Nv0AEiY//J5AjXORjw81TXD/cKhm4jFOW+Snn1CoK5F5C9scRXLbp80Nw+b3ikQMRLEL EZ3W9agXdnpQ9SrM+UxS+h/g95XkPbvO3IldMkeL4j2Tb75wUt/hp2D9X6tmUENqFuSC QpwlAj0Dt4pgN32yAE2+GiKp0XqaxGyPJnMIQtoeXkAsatPSGLDdAsmPpL/DL9IALzN5 Q18g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768296; x=1704373096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XX8RT8/KwRnpjqmauq2VuiREugBeuTfdnmzmXRQSLkY=; b=MEgAJS7FVtfCkYe2c/jPV5E585KNpUngsQw/LfszjGHH/CkGpFGm+VwJYkyA2c9aiw Y4q6UfypzrVj7C/P0Nsl4Vz+knZ6qtAUkN6uHFWiFSJm9LuQaImOnaVxIg9qvI+95kkx Rmcoft6i4/FzG+pzRK1yy8DIc8TlNbbeJlsoVxVwulhdOHsqefImEXPV6vi2S98Adls5 eciGsVQKnLLmJB9SBDbkeM3p815JMqQV9xJNoI5uRxtan4qvYxL2zrM4Dp1+dE7ah7Ck WxVGFNj9GHbbdEZ03+1eTMIRFXSE9zT6ygAWCQSaf58NJWt1qP2muJpAyHVrCaBjMgQ6 Vubg== X-Gm-Message-State: AOJu0YyQT2izdYBk5ewgyz//CESRJZnv2kkEACuh1W3VG8yoqbMQvDgS qvqI5/x83LcZUJD3wsVXByJXTY43NzuNDg== X-Google-Smtp-Source: AGHT+IEqHso+KU0TXJoWGdwqMKaajVLMSvd+/nBs9vEkdpDVBsUvd/aUEZUWWnBCnEZtLsrpzQL1bA== X-Received: by 2002:a05:600c:4f83:b0:40d:5d82:d0f4 with SMTP id n3-20020a05600c4f8300b0040d5d82d0f4mr1363489wmq.61.1703768296198; Thu, 28 Dec 2023 04:58:16 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:15 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 06/12] tty: serial: samsung: add gs101 earlycon support Date: Thu, 28 Dec 2023 12:57:59 +0000 Message-ID: <20231228125805.661725-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Always set UPIO_MEM32 iotype for the gs101 earlycon. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: update commit message drivers/tty/serial/samsung_tty.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 938127179acf..2fbaaf0e756b 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2812,6 +2812,17 @@ OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", s5pv210_early_console_setup); +static int __init gs101_early_console_setup(struct earlycon_device *device, + const char *opt) +{ + /* gs101 always expects MMIO32 register accesses. */ + device->port.iotype = UPIO_MEM32; + + return s5pv210_early_console_setup(device, opt); +} + +OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup); + /* Apple S5L */ static int __init apple_s5l_early_console_setup(struct earlycon_device *device, const char *opt) From patchwork Thu Dec 28 12:58:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506010 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32D7BFBF4 for ; Thu, 28 Dec 2023 12:58:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="k7p/gEt2" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40d5aef534eso19650315e9.0 for ; Thu, 28 Dec 2023 04:58:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768297; x=1704373097; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wnfuDF7U7vYIOHK8yZbhXUIIVxxmJixFdp00vAqeklk=; b=k7p/gEt2nW0kHPLzO6n39hXxrUI7YEggwpyY9DhSMoYMTiPL3uyf2hr3gu6HXKRbAP e6dulxpJ6vb2tNnW6/UDJhyd8akp4ckbIwkF+eerocLCFhGLQXkigcCli8ng717XDgQt gQs7EjaVSUspPCkd0hIyXk0gQ+yL6tFTpOcWhpajWqirMKl1FrkU4YD1ypooG96FsmTP Eux+K/D22/VEfbM+TpUsgB7WEjYUXTH1yyLt5QJqzlOBXIkQKBLXdkBFVhJEdu9X66tc iXAckFz+oUMv4qYQQs0npd20e4kpPthn+gqFAyVwd5Nt6dsSVFv4pqyxtJ0LKdT3dGEW nbiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768297; x=1704373097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wnfuDF7U7vYIOHK8yZbhXUIIVxxmJixFdp00vAqeklk=; b=Y2LHdMTyMgsiotz0ehY3A2AI1pmpFC0ff90aq9IdINLlcBwR22EJeUwkIHCToHwJ6H J3yijEEyHmLX/tmjiD4qBIX6X9TCym0WE1G8rt5DXIDIsZM0NbhuA+DJqhtsud9zb4Oa l+UJNRm69I+NaAvY5TNe7wMcsda9UM+7FUx0KjCRFw3MzmkWmXRxiIviIcRJdfR090dG /y8pabKPt1NprysH3e38cBbqmOWF0xartrDy6s4OiOOoPDtfye5WE3xJ/5fzASw0slil bNAGnxpsl/pIruNqHROJ7XS+Rq6yW7ic7CHKeB/TZOuM5t41o2a8C/M/VSuq28k0v1eB Uh5Q== X-Gm-Message-State: AOJu0YxgJGWEBZYXPhgZPm25bgUXRn+64eXwsBUb94vrv7q22+CkqyI9 G76nTUW6B1bnUgoqUaBRCNlZAWkcKKa+GQ== X-Google-Smtp-Source: AGHT+IF9Oi7hJPWTZCtfO2Ihelw3NrTBUh3PHlH39uQvv1BiC0J+XyQQ3dIxVwjKLKlb27c3jxYkjg== X-Received: by 2002:a05:600c:4445:b0:40c:3831:27ee with SMTP id v5-20020a05600c444500b0040c383127eemr5554007wmn.59.1703768297492; Thu, 28 Dec 2023 04:58:17 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:16 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 07/12] clk: samsung: gs101: add support for cmu_peric0 Date: Thu, 28 Dec 2023 12:58:00 +0000 Message-ID: <20231228125805.661725-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CMU_PERIC0 is the clock management unit used for the peric0 block which is used for USI and I3C. Add support for all cmu_peric0 clocks but CLK_GOUT_PERIC0_IP (not enough info in the datasheet). Few clocks are marked as critical because when either of them is disabled, the system hangs even if their clock parents are enabled. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: - update commit message - identify and mark critical clocks drivers/clk/samsung/clk-gs101.c | 583 ++++++++++++++++++++++++++++++++ 1 file changed, 583 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 0964bb11657f..68a27b78b00b 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -20,6 +20,7 @@ #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ @@ -2478,6 +2479,585 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = { .clk_name = "dout_cmu_misc_bus", }; +/* ---- CMU_PERIC0 ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10800000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 +#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 +#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c +#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c +#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 +#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 +#define QCH_CON_GPC_PERIC0_QCH 0x3028 +#define QCH_CON_GPIO_PERIC0_QCH 0x302c +#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 +#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 +#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 +#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c +#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 +#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 +#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 +#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c +#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 +#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 +#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 +#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c +#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 +#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 +#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 +#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c +#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 +#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 +#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 +#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c +#define QCH_CON_SYSREG_PERIC0_QCH 0x3080 +#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 + +static const unsigned long peric0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PERIC0_CMU_PERIC0_CONTROLLER_OPTION, + CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, + CLK_CON_BUF_CLKBUF_PERIC0_IP, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + DMYQCH_CON_PERIC0_TOP0_QCH_S1, + DMYQCH_CON_PERIC0_TOP0_QCH_S2, + DMYQCH_CON_PERIC0_TOP0_QCH_S3, + DMYQCH_CON_PERIC0_TOP0_QCH_S4, + DMYQCH_CON_PERIC0_TOP0_QCH_S5, + DMYQCH_CON_PERIC0_TOP0_QCH_S6, + DMYQCH_CON_PERIC0_TOP0_QCH_S7, + DMYQCH_CON_PERIC0_TOP0_QCH_S8, + PCH_CON_LHM_AXI_P_PERIC0_PCH, + QCH_CON_D_TZPC_PERIC0_QCH, + QCH_CON_GPC_PERIC0_QCH, + QCH_CON_GPIO_PERIC0_QCH, + QCH_CON_LHM_AXI_P_PERIC0_QCH, + QCH_CON_PERIC0_CMU_PERIC0_QCH, + QCH_CON_PERIC0_TOP0_QCH_I3C1, + QCH_CON_PERIC0_TOP0_QCH_I3C2, + QCH_CON_PERIC0_TOP0_QCH_I3C3, + QCH_CON_PERIC0_TOP0_QCH_I3C4, + QCH_CON_PERIC0_TOP0_QCH_I3C5, + QCH_CON_PERIC0_TOP0_QCH_I3C6, + QCH_CON_PERIC0_TOP0_QCH_I3C7, + QCH_CON_PERIC0_TOP0_QCH_I3C8, + QCH_CON_PERIC0_TOP0_QCH_USI1_USI, + QCH_CON_PERIC0_TOP0_QCH_USI2_USI, + QCH_CON_PERIC0_TOP0_QCH_USI3_USI, + QCH_CON_PERIC0_TOP0_QCH_USI4_USI, + QCH_CON_PERIC0_TOP0_QCH_USI5_USI, + QCH_CON_PERIC0_TOP0_QCH_USI6_USI, + QCH_CON_PERIC0_TOP0_QCH_USI7_USI, + QCH_CON_PERIC0_TOP0_QCH_USI8_USI, + QCH_CON_PERIC0_TOP1_QCH_USI0_UART, + QCH_CON_PERIC0_TOP1_QCH_USI14_UART, + QCH_CON_SYSREG_PERIC0_QCH, + QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, +}; + +/* List of parent clocks for Muxes in CMU_PERIC0 */ +PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; +PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", + mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI0_UART_USER, + "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI14_USI_USER, + "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI1_USI_USER, + "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI2_USI_USER, + "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI3_USI_USER, + "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI4_USI_USER, + "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI5_USI_USER, + "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI6_USI_USER, + "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI7_USI_USER, + "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI8_USI_USER, + "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 3), + DIV(CLK_DOUT_PERIC0_USI0_UART, + "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 3), + DIV(CLK_DOUT_PERIC0_USI14_USI, + "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI1_USI, + "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI2_USI, + "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI3_USI, + "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI4_USI, + "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI5_USI, + "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI6_USI, + "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI7_USI, + "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI8_USI, + "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 3), +}; + +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, + "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, + "gout_peric0_clk_peric0_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, + "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, + "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, + "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, + "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, + "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, + "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, + "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, + "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, + "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, + "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, + "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, + "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, + "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, + "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, + "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, + "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, + "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, + "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, + "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, + "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, + "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, + "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, + "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, + "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, + "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, + "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, + "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, + "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, + "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, + "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, + "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, + "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, + "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, + "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, + "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, + "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, + "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, + "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, + "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, + "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, + "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, + "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, + "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, + "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, + "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, + "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, + "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, + "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, + "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, + "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, + "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, + "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, + "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst = { + .mux_clks = peric0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), + .div_clks = peric0_div_clks, + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), + .gate_clks = peric0_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC0, + .clk_regs = peric0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), + .clk_name = "dout_cmu_peric0_bus", +}; + /* ---- platform_driver ----------------------------------------------------- */ static int __init gs101_cmu_probe(struct platform_device *pdev) @@ -2498,6 +3078,9 @@ static const struct of_device_id gs101_cmu_of_match[] = { }, { .compatible = "google,gs101-cmu-misc", .data = &misc_cmu_info, + }, { + .compatible = "google,gs101-cmu-peric0", + .data = &peric0_cmu_info, }, { }, }; From patchwork Thu Dec 28 12:58:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506009 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 425171078E for ; Thu, 28 Dec 2023 12:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wPYZRAo7" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40d4a7f0c4dso51866715e9.1 for ; Thu, 28 Dec 2023 04:58:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768298; x=1704373098; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IfvY3WSeE4VIMFkeLJMaH8OzmsoSjNCK+Nz4eKgeCoc=; b=wPYZRAo7QXUGA/kTIdTnIIR/+lhZF4k7xFRxU97cFJy0DbF59Ajk4knIPTZPZDW+SH R8hVBzclA31K0t0nO6yWsUW5yBdn4g85JqkMwQWcfrEqu0GeCP0+xx98s12iEgJLNCgM bRCa8MPRq8P5GtsGHqwbpPKxalvgBvMxLimtIzRQxMaXjFYo35PQ6hjpTwpVt97bpGgf hIoaJWw1N6ZJW6ElXOfDHKfQpyxCnLcl4T9suyZxApsf59EFQk/BjRGVoSLt4NmXsKvM 4TMJCNbPDDjFiiFTlXo7gWy2BP9q8p2ia5moLVHqTZn5R+DCycl8l1erYcYHMmbRtD2o cOPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768298; x=1704373098; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IfvY3WSeE4VIMFkeLJMaH8OzmsoSjNCK+Nz4eKgeCoc=; b=XS8aUf4f9G+nHK4GiwCDLSVuizY3hLJ9wgGAq1CM0LhqbqsNF3cD/U6c3u5dqJJaU7 uT98qTXwZSUcCp28VlTknOg+r6mpRTXLMuP9mXU/MSLwxjjUrIHgpqF/da58Zj0UAbBW TFGx9X1yuSOZ/VMAOjkOEcYcBGMHPxFLU3YKcTgLJzSgKMRf5PnMSp5AiAgKMfapUk5c gNYjTXKtAh1Sd6MrmbA3TAem70BX4u9RO9E9f35wf3crext6wiXgTVZP/ecm1AW4vFRG VhYhKuz/gj8XiqHNGxrizPFEUHr++LegsZDQVLX16xgJxLaS5Lrah0+1LHOCjnWxA+mh holw== X-Gm-Message-State: AOJu0YzlbLk1TNkSmvsZ2fAPDadnKKDbtAcd5DarqYW9BjPFk2wRoh4P FxS++4gw8SE2tXxXv4bV9NXfQjEMjAeW0A== X-Google-Smtp-Source: AGHT+IF55NKth7/eb18QsUtA1f9ddrzeSWtvCX/hHhNS9AwuDyV2qkCzAn6X1VS5tp90l5w01R7hBQ== X-Received: by 2002:a05:600c:748:b0:40c:53ba:1720 with SMTP id j8-20020a05600c074800b0040c53ba1720mr5454225wmn.76.1703768298710; Thu, 28 Dec 2023 04:58:18 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:17 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 08/12] arm64: dts: exynos: gs101: remove reg-io-width from serial Date: Thu, 28 Dec 2023 12:58:01 +0000 Message-ID: <20231228125805.661725-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove the reg-io-width property in order to comply with the bindings. The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: new patch arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9747cb3fa03a..2c27c3cb9237 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -366,7 +366,6 @@ usi_uart: usi@10a000c0 { serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - reg-io-width = <4>; interrupts = ; clocks = <&dummy_clk 0>, <&dummy_clk 0>; From patchwork Thu Dec 28 12:58:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506011 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438D910944 for ; Thu, 28 Dec 2023 12:58:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VGRgjEtU" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40d5d8a6730so14305705e9.1 for ; Thu, 28 Dec 2023 04:58:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768299; x=1704373099; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9P18XFXxLojrY56K1R6dgW5XgUJGd1RI2KgrEMEdbt0=; b=VGRgjEtUWQXaj45h2Kim36YsftjD3/lzrOlNAnGvcLcCCR4P1BndKG1WkmcaKn4krL KzgaB3pHKJP5hbc5SWan+JB+gmYLPxOyX0ZvE8MRoY9Davrl21fm21nEmCchRXULzMKW o61bqKoj18suCoBSNZGu59AmoTlGu1+Vmi2w3u86vVVkdKWlFCtsxLh2zJCGeAOH4G8a h6qLZNpQFjh3ZfM9bPKQTXuYX1tPdhGgj8brdvLsbotZoaViRboa3klaadVDZjkFwwS/ i/zvAYf5TjhGjqh6709tTOlvn31WrdAXNVPij7FKyfoZv5z6OQgTFCznS1qPdzmrMNx6 r74g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768299; x=1704373099; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9P18XFXxLojrY56K1R6dgW5XgUJGd1RI2KgrEMEdbt0=; b=Jpcfb1fXbkNQ2XgJV7QcW+mNf5pEGVimBSdHGirEY3J5gNkhRGT5B6v2g6MtID3AHA r9dX6/vz3QXQAlsjzz4N8fjKX5m2CtXbZth8eu/datAz4Sm9LdeT0jrKUigp7XHDxn+E z6Xz9R5xzBPMuHxRVe2N2Xx7ncZoXUxKCPk3sg+3yurH8z8eQ2mGl+klf1h4VQmAvAqo VHyl5XGBL4tlnkqxMZQyl2RY7WoI12X06I8e9RB3VbPZhEvsz2CVXGZ+9DMS5mJLyiSd FCwOnuyvet5eHll8dbkHbegUbmHl7+hj1X/R5zuvrz+E4ltF1o4RBVgivTO4Wp8VKtOL kxlw== X-Gm-Message-State: AOJu0YwTB2imcmg3BEkcq5N7okivehn0gTArARocSfJ4XL2zqzyXt3/f Nepufjjp/kOcTRUWZD0+yskkK+//nPP6jg== X-Google-Smtp-Source: AGHT+IEhfhBO50ykAwRsA55Z5OQSVWgKhNvX6SqkmYB+7qQHPv4Eq18tKnXzQa7B/fCe5uM8d1mYAg== X-Received: by 2002:a7b:ce98:0:b0:40d:5c58:fd7a with SMTP id q24-20020a7bce98000000b0040d5c58fd7amr1705829wmj.156.1703768299747; Thu, 28 Dec 2023 04:58:19 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:19 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 09/12] arm64: dts: exynos: gs101: enable cmu-peric0 clock controller Date: Thu, 28 Dec 2023 12:58:02 +0000 Message-ID: <20231228125805.661725-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable the cmu-peric0 clock controller. It feeds USI and I3c. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: collect R-b arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 2c27c3cb9237..c693791ae584 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -339,6 +339,18 @@ ppi_cluster2: interrupt-partition-2 { }; }; + cmu_peric0: clock-controller@10800000 { + compatible = "google,gs101-cmu-peric0"; + reg = <0x10800000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", + "dout_cmu_peric0_bus", + "dout_cmu_peric0_ip"; + }; + sysreg_peric0: syscon@10820000 { compatible = "google,gs101-peric0-sysreg", "syscon"; reg = <0x10820000 0x10000>; From patchwork Thu Dec 28 12:58:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506012 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B9671096A for ; Thu, 28 Dec 2023 12:58:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rzIo1duA" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40d5b159350so19299785e9.2 for ; Thu, 28 Dec 2023 04:58:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768300; x=1704373100; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fJqndlg00hz3kS0K9Xt/wzcgwz2RWYotM3QsJXJKxvc=; b=rzIo1duAxnP8EkArIztf8NaFeYQyVzaCFyqiOHwzDnvmL4l6j3bX2yfcL1SdwvfuYR R7ccEfhXp0bIyJsnyKRtocDRnhhslmCllhuhCBGgy1R/yIzvD/UX1++KTRo+i5T9HUUg Hc7Wp32lBdo5mJ98/Yga6oazzscaOYXJZq1vYBYi+uVXb+JHaV/6Mg/Q3FAWWcDcrd9Z RW6h6hebPFpTeTLZqLOQLMoH9CthW0n6vOASz7EGpaiABlpz0izIduwluhvNCFFrKJ/F eoweHjqIxIYGzQMqONqa/LAwH7ZqWOIP3QW5SGBmNOpVguvVBcr1dkZCFGglVYOaYKoY v/Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768300; x=1704373100; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fJqndlg00hz3kS0K9Xt/wzcgwz2RWYotM3QsJXJKxvc=; b=MlUUAU9Gg41imtnTsAv9BfD3c/fgznwRhkfLvSxtyGvQJFFjTA1rR/dbnZ4rdEUqk0 WM9SyvyXG/hzCfphbyt//tfP1yRYmczhpxwJKZ3ePM3R8iD3qDKBZs1Ycch6Du2k1Bi3 usgc5Jrj3OaJLT2WTBUgv2FhxNumlXd/soIxclYtS8nC/5cy+tujucxfyfSSgCGA/Ua1 JFS5En0/7Jh+bP0NX0BwQSb30v/Y/AON1NVWgTb5rkSu3FwdgVgQ5VOK0rWcL5NYhC73 qtGbviFhmoXYtubztc92EqTXIu4sqmXvi77zSIRF6HSAd+E9cCcnL8d3EOMxiri/tEvQ i9WQ== X-Gm-Message-State: AOJu0YygoIb5Y/x6qCqo2gauVxfENcNMN9X1Rm6Z7QLXxCtu84iQpSky AeoF/cZ3kzEJAE/fHu6Jb2T+ejnpFqWppQ== X-Google-Smtp-Source: AGHT+IHl5TUZZLgMiTlie5qagsHCRsc5xzAp7JZjoJ6yG5wP+nbvBqQhFQDOaktrnm5ijLKALVeCGA== X-Received: by 2002:a05:600c:2192:b0:40d:71c1:9985 with SMTP id e18-20020a05600c219200b0040d71c19985mr81689wme.29.1703768300597; Thu, 28 Dec 2023 04:58:20 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:20 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 10/12] arm64: dts: exynos: gs101: update USI UART to use peric0 clocks Date: Thu, 28 Dec 2023 12:58:03 +0000 Message-ID: <20231228125805.661725-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Get rid of the dummy clock and start using the cmu_peric0 clocks for the usi_uart and serial_0 nodes. Tested the serial at 115200, 1000000 and 3000000 baudrates, everthing went fine. Signed-off-by: Tudor Ambarus --- v2: identify and use gate clocks instead of divider clocks arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index c693791ae584..0e5b1b490b0b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -180,14 +180,6 @@ HERA_CPU_SLEEP: cpu-hera-sleep { }; }; - /* TODO replace with CCF clock */ - dummy_clk: clock-3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12345>; - clock-output-names = "pclk"; - }; - /* ect node is required to be present by bootloader */ ect { }; @@ -369,7 +361,8 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&dummy_clk>, <&dummy_clk>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; samsung,mode = ; @@ -380,7 +373,8 @@ serial_0: serial@10a00000 { reg = <0x10a00000 0xc0>; interrupts = ; - clocks = <&dummy_clk 0>, <&dummy_clk 0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled"; From patchwork Thu Dec 28 12:58:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506013 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95F65F9F8 for ; Thu, 28 Dec 2023 12:58:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mkk3Pw39" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-50e67e37661so5763158e87.0 for ; Thu, 28 Dec 2023 04:58:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768301; x=1704373101; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nshL/2BWW/EmympyN/DOS/o4W55HuW8fqdS5mFUVUCI=; b=mkk3Pw39fpmwTjMyLFLDajaq7IFSKoh6S8NF5IWmxPF0e5N6KLtL8xDyJUzfAecCrp FTpQbHEKN5xytknfDzurqYBORK8KoydCFJhkNc4hjLSOY+38T7pXN8rT6TvY4WlvDB/2 WG/a9PvTTeoMUl11PtTUV6nsArmOVZ3Beghc/2BQXiA5IS77eqjanHeci+dezSM+XAX2 XHGCAGkR/fmc6TTZE9147e7S4czbFX2ry/lXYqoItWDb6+6zW3QGxD78Hwoml/8O16OS NieEe8ks2/gcnG1uKiVJ04dBWXpsxpF5w7Y2GS2fkFIh69YDnEEDO179WGhk/rClHTYW 9uIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768301; x=1704373101; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nshL/2BWW/EmympyN/DOS/o4W55HuW8fqdS5mFUVUCI=; b=wGhJWayfP40OFje/qW3IXtvNiYPAsOGQq50BpoY8D8noiWQEGyGKIOa+87fCRtoahX Vd1MvE2TFDDVWYkBHIQrt9BGiJ2XEhhnfe2rXs+R9+pcu/fXCYDCeOkGVkFc/ZV6/H4F LhVGg0AmNwFyhVcWkh39azM99F3y6E8cyySMAByO1a+PI+hBYPK/usH5U7fyNfv5OUCQ xMvlHA+wevLB4Skwvzgd1vF39PtBjszWFgWSeNlIGS+sOfB/vdCfNUlEGKusSjlU6c8s rTSs4oZS2AsqyJXv+wuefQJUsNa9nNVl0v1eCytOG13kIe8pmCiO3d6kry3lDttKa8Pu 5Mtw== X-Gm-Message-State: AOJu0Yx2CCVYy21PP3chw7hOT5hpWmwHJrNRAkI87Y1HmCWs4x+CTvil s6zVLHzLQWGrxtLmSfx3EyxeWsMyJFErQA== X-Google-Smtp-Source: AGHT+IH1ngv6ejaU7/1CPrITKymTsj3xR3AtePeUh+QgKGYoFnMU100TN5ELJ0cgjYZTMENP3QXhKg== X-Received: by 2002:a05:6512:348c:b0:50e:7c73:f4f3 with SMTP id v12-20020a056512348c00b0050e7c73f4f3mr2253161lfr.9.1703768301689; Thu, 28 Dec 2023 04:58:21 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:21 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 11/12] arm64: dts: exynos: gs101: define USI8 with I2C configuration Date: Thu, 28 Dec 2023 12:58:04 +0000 Message-ID: <20231228125805.661725-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 USI8 I2C is used to communicate with an eeprom found on the battery connector. Define USI8 in I2C configuration. USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. Signed-off-by: Tudor Ambarus --- v2: - identify and use gate clocks instead of dividers - move cells and pinctrl properties from dts to dtsi - move IRQ type constant on the previous line arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 0e5b1b490b0b..c6ae33016992 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -354,6 +354,35 @@ pinctrl_peric0: pinctrl@10840000 { interrupts = ; }; + usi8: usi@109700c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_8: i2c@10970000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + usi_uart: usi@10a000c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi"; From patchwork Thu Dec 28 12:58:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13506014 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 960EE111A2 for ; Thu, 28 Dec 2023 12:58:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="tsm6+4s/" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-40d60c49ee7so9774515e9.0 for ; Thu, 28 Dec 2023 04:58:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703768303; x=1704373103; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T/YL/2OiXBxCX/gD6IApJPmq9GlVQJZGnRfROzab14c=; b=tsm6+4s/hz3xpEd26lt/8M4X3EVCQ0CHQE77inkpa1ZvGyHUzzxMhzn8GEOsCLVQaZ xClfMrKKs9Tobv4xSDbVXSoESRqv33+54OZK7cmlp1L/s4UyFO/zW7iWYlWc9kJpZblG Sk/9n1jsDFkDHeP725dBrh5bQmQ7yxm607qS2efQmAVLXP/Z74PuhkN2Ua+35zyCZSMT I0YvFM4QY90xKQPkFbYS4q3+HgczMl99IjQyHSWWfpL3gMHDw33JueHNZy8rIHoxrqj4 O+1lp5PB08sEuaSSmAoGQzNqEJ6nnLC4Kto0iVJ2UyQ5G1Njphr/ToJk0915JQe5ThVr hMMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703768303; x=1704373103; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T/YL/2OiXBxCX/gD6IApJPmq9GlVQJZGnRfROzab14c=; b=m3RJPnH5+22Xefr1AedBK1y0vvrFo9qhhG+EMnIrKXRMINue4NCXINGycKmBN9IUHB G4n8bY9DMkskLo492foNr0V6WMISCU3NQLM4QD0hOJ2Wg82jHdm7MOk5zU+xdokDaRbk mceNWRUSsxWB/tPTOAVq/IjAIgmdfxd+/7zgnt+fgL6pME0E4l92uEqsgjR8g1o0L05O OiZH/NiGbuodN3rmwl3jXNeRPl/q7o34NK14D/8IH1LVLHwDwgFxa8DRPBqTEalOPOt8 y4HvT0DUsOjFa16T34VqcMQragShXlDq1QoBuZjJ9z98MrCYKbaDQY6nA4lqgFM+UoDv GJAA== X-Gm-Message-State: AOJu0YxX3+kCec0PZu2c2S6WbGg2sXLmi8aebw+/UFYPZJApGbANFZkO dasPo2galJ9tvzqQJPIW9hJqN8ahs+B4TA== X-Google-Smtp-Source: AGHT+IFFojsXoPb7K03oLgZ6jOvlLwBUwXu6zQoSVyiXDmyrmZ5YE9jkYffXSKkyFMwlzu2dsPNUsQ== X-Received: by 2002:a05:600c:4ca5:b0:40d:39cb:6af6 with SMTP id g37-20020a05600c4ca500b0040d39cb6af6mr5506215wmp.28.1703768302945; Thu, 28 Dec 2023 04:58:22 -0800 (PST) Received: from ta2.c.googlers.com.com (216.131.76.34.bc.googleusercontent.com. [34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:22 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 12/12] arm64: dts: exynos: gs101: enable eeprom on gs101-oriole Date: Thu, 28 Dec 2023 12:58:05 +0000 Message-ID: <20231228125805.661725-13-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable the eeprom found on the battery connector. The selection of the USI protocol is done in the board dts file because the USI CONFIG register comes with a 0x0 reset value, meaning that USI8 does not have a default protocol (I2C, SPI, UART) at reset. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: - move cells and pinctrls properties to dtsi - collect Sam's R-b arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 4a71f752200d..cb4d17339b6b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -63,6 +63,15 @@ &ext_200m { clock-frequency = <200000000>; }; +&hsi2c_8 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + &pinctrl_far_alive { key_voldown: key-voldown-pins { samsung,pins = "gpa7-3"; @@ -99,6 +108,11 @@ &usi_uart { status = "okay"; }; +&usi8 { + samsung,mode = ; + status = "okay"; +}; + &watchdog_cl0 { timeout-sec = <30>; status = "okay";