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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099E1.mail.protection.outlook.com (10.167.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7159.9 via Frontend Transport; Sat, 30 Dec 2023 12:43:14 +0000 Received: from aiemdee.2.ozlabs.ru (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 30 Dec 2023 06:43:12 -0600 From: Alexey Kardashevskiy To: Alexey Kardashevskiy CC: , =?utf-8?q?Martin_Mare=C5=A1?= , Jonathan Cameron Subject: [PATCH pciutils 1/2] lspci: Add TEE-IO extended capability bit Date: Sat, 30 Dec 2023 23:42:38 +1100 Message-ID: <20231230124239.310927-2-aik@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231230124239.310927-1-aik@amd.com> References: <20231230124239.310927-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|PH8PR12MB6722:EE_ X-MS-Office365-Filtering-Correlation-Id: c0026c67-9ba4-4137-df86-08dc0934e42b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Alexey Kardashevskiy --- lib/header.h | 1 + ls-caps.c | 1 + 2 files changed, 2 insertions(+) diff --git a/lib/header.h b/lib/header.h index 58fe7df..47ee8a6 100644 --- a/lib/header.h +++ b/lib/header.h @@ -776,6 +776,7 @@ #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ #define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */ +#define PCI_EXP_DEVCAP_TEE_IO 0x40000000 /* TEE-IO Supported (TDISP) */ #define PCI_EXP_DEVCTL 0x8 /* Device Control */ #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ diff --git a/ls-caps.c b/ls-caps.c index 2c99812..65e92e6 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -717,6 +717,7 @@ static void cap_express_dev(struct device *d, int where, int type) printf(" SlotPowerLimit "); show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26); } + printf(" TEE-IO%c", FLAG(t, PCI_EXP_DEVCAP_TEE_IO)); printf("\n"); w = get_conf_word(d, where + PCI_EXP_DEVCTL); From patchwork Sat Dec 30 12:42:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 13506805 X-Patchwork-Delegate: bhelgaas@google.com Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2079.outbound.protection.outlook.com [40.107.93.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F4F68487 for ; Sat, 30 Dec 2023 12:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="z6KgGxid" ARC-Seal: i=1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2023 12:43:34.5779 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a7083e4-c226-4993-fc9d-08dc0934efd6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8613 IDE (Integrity & Data Encryption) Extended Capability defined in [1] implements control of the PCI link encryption. The example output is: Capabilities: [830 v1] IDE IDECap: Lnk=1 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ IDECtl: IntEn- LinkIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM 256 key size, 96b MAC' TC0 ID0 LinkIDE#0 Sta: Status=secure RecvChkFail- SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM 256 key size, 96b MAC' TC0 ID0 SelectiveIDE#0 Sta: insecure RecvChkFail- SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0 [1] PCIe r6.0.1, sections 6.33, 7.9.26 Signed-off-by: Alexey Kardashevskiy --- lib/header.h | 61 ++++++++ ls-ecaps.c | 162 ++++++++++++++++++++ 2 files changed, 223 insertions(+) diff --git a/lib/header.h b/lib/header.h index 47ee8a6..5df2f57 100644 --- a/lib/header.h +++ b/lib/header.h @@ -256,6 +256,7 @@ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ #define PCI_EXT_CAP_ID_32GT 0x2a /* Physical Layer 32.0 GT/s */ #define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */ +#define PCI_EXT_CAP_ID_IDE 0x30 /* IDE */ /*** Definitions of capabilities ***/ @@ -1416,6 +1417,66 @@ #define PCI_DOE_STS_ERROR 0x4 /* DOE Error */ #define PCI_DOE_STS_OBJECT_READY 0x80000000 /* Data Object Ready */ +/* IDE Extended Capability */ +#define PCI_IDE_CAP 0x4 +#define PCI_IDE_CAP_LINK_IDE_SUPP 0x1 /* Link IDE Stream Supported */ +#define PCI_IDE_CAP_SELECTIVE_IDE_SUPP 0x2 /* Selective IDE Streams Supported */ +#define PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP 0x4 /* Flow-Through IDE Stream Supported */ +#define PCI_IDE_CAP_PARTIAL_HEADER_ENC_SUPP 0x8 /* Partial Header Encryption Supported */ +#define PCI_IDE_CAP_AGGREGATION_SUPP 0x10 /* Aggregation Supported */ +#define PCI_IDE_CAP_PCRC_SUPP 0x20 /* PCRC Supported */ +#define PCI_IDE_CAP_IDE_KM_SUPP 0x40 /* IDE_KM Protocol Supported */ +#define PCI_IDE_CAP_ALG(x) (((x) >> 8) & 0x1f) /* Supported Algorithms */ +#define PCI_IDE_CAP_ALG_AES_GCM_256 0 /* AES-GCM 256 key size, 96b MAC */ +#define PCI_IDE_CAP_LINK_TC_NUM(x) (((x) >> 13) & 0x7) /* Number of TCs Supported for Link IDE */ +#define PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(x) (((x) >> 16) & 0xff) /* Number of Selective IDE Streams Supported */ +#define PCI_IDE_CTL 0x8 +#define PCI_IDE_CTL_FLOWTHROUGH_IDE 0x4 /* Flow-Through IDE Stream Enabled */ +#define PCI_IDE_LINK_STREAM 0xC +/* Link IDE Stream block, up to PCI_IDE_CAP_LINK_TC_NUM */ +/* Link IDE Stream Control Register */ +#define PCI_IDE_LINK_CTL_EN 0x1 /* Link IDE Stream Enable */ +#define PCI_IDE_LINK_CTL_TX_AGGR_NPR(x)(((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */ +#define PCI_IDE_LINK_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */ +#define PCI_IDE_LINK_CTL_TX_AGGR_CPL(x)(((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */ +#define PCI_IDE_LINK_CTL_PCRC_EN 0x100 /* PCRC Enable */ +#define PCI_IDE_LINK_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */ +#define PCI_IDE_LINK_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */ +#define PCI_IDE_LINK_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */ +#define PCI_IDE_LINK_CTL_ID(x) (((x) >> 24) & 0xff) /* Stream ID */ +/* Link IDE Stream Status Register */ +#define PCI_IDE_LINK_STS_STATUS(x) ((x) & 0xf) /* Link IDE Stream State */ +#define PCI_IDE_LINK_STS_RECVD_INTEGRITY_CHECK 0x80000000 /* Received Integrity Check Fail Message */ +/* Selective IDE Stream block, up to PCI_IDE_CAP_SELECTIVE_STREAMS_NUM */ +/* Selective IDE Stream Capability Register */ +#define PCI_IDE_SEL_CAP_BLOCKS_NUM(x) ((x) & 0xf) /* Number of Address Association Register Blocks */ +/* Selective IDE Stream Control Register */ +#define PCI_IDE_SEL_CTL_EN 0x1 /* Selective IDE Stream Enable */ +#define PCI_IDE_SEL_CTL_TX_AGGR_NPR(x) (((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */ +#define PCI_IDE_SEL_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */ +#define PCI_IDE_SEL_CTL_TX_AGGR_CPL(x) (((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */ +#define PCI_IDE_SEL_CTL_PCRC_EN 0x100 /* PCRC Enable */ +#define PCI_IDE_SEL_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */ +#define PCI_IDE_SEL_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */ +#define PCI_IDE_SEL_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */ +#define PCI_IDE_SEL_CTL_DEFAULT 0x400000 /* Default Stream */ +#define PCI_IDE_SEL_CTL_ID(x) (((x) >> 24) & 0xff) /* Stream ID */ +/* Selective IDE Stream Status Register */ +#define PCI_IDE_SEL_STS_STATUS(x) ((x) & 0xf) /* Selective IDE Stream State */ +#define PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK 0x80000000 /* Received Integrity Check Fail Message */ +/* IDE RID Association Register 1 */ +#define PCI_IDE_SEL_RID_1_LIMIT(x) (((x) >> 8) & 0xffff) /* RID Limit */ +/* IDE RID Association Register 2 */ +#define PCI_IDE_SEL_RID_2_VALID 0x1 /* Valid */ +#define PCI_IDE_SEL_RID_2_BASE(x) (((x) >> 8) & 0xffff) /* RID Base */ +#define PCI_IDE_SEL_RID_2_SEG_BASE(x) (((x) >> 24) & 0xff) /* Segmeng Base */ +/* Selective IDE Address Association Register Block, up to PCI_IDE_SEL_CAP_BLOCKS_NUM */ +#define PCI_IDE_SEL_ADDR_1_VALID 0x1 /* Valid */ +#define PCI_IDE_SEL_ADDR_1_BASE_LOW(x) (((x) >> 8) & 0xfff) /* Memory Base Lower */ +#define PCI_IDE_SEL_ADDR_1_LIMIT_LOW(x)(((x) >> 20) & 0xfff) /* Memory Limit Lower */ +/* IDE Address Association Register 2 is "Memory Limit Upper" */ +/* IDE Address Association Register 3 is "Memory Base Upper" */ + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/ls-ecaps.c b/ls-ecaps.c index 2d7d827..9f6c3f8 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -1468,6 +1468,165 @@ cap_doe(struct device *d, int where) FLAG(l, PCI_DOE_STS_OBJECT_READY)); } +static void +cap_ide(struct device *d, int where) +{ + const char *hdr_enc_mode[] = { "no", "17:2", "25:2", "33:2", "41:2" }; + const char *algo[] = { "AES-GCM 256 key size, 96b MAC" }; + const char *stream_state[] = { "insecure", "secure" }; + const char *aggr[] = { "-", "=2", "=4", "=8" }; + u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j; + char buf1[16], buf2[16]; + + printf("IDE\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_IDE_CAP, 8)) + { + printf("\t\t\n"); + return; + } + + l = get_conf_long(d, where + PCI_IDE_CAP); + if (l & PCI_IDE_CAP_LINK_IDE_SUPP) + linknum = PCI_IDE_CAP_LINK_TC_NUM(l) + 1; + if (l & PCI_IDE_CAP_SELECTIVE_IDE_SUPP) + selnum = PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(l) + 1; + + printf("\t\tIDECap: Lnk=%d Sel=%d FlowThru%c PartHdr%c Aggr%c PCPC%c IDE_KM%c\n", + linknum, + selnum, + FLAG(l, PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP), + FLAG(l, PCI_IDE_CAP_PARTIAL_HEADER_ENC_SUPP), + FLAG(l, PCI_IDE_CAP_AGGREGATION_SUPP), + FLAG(l, PCI_IDE_CAP_PCRC_SUPP), + FLAG(l, PCI_IDE_CAP_IDE_KM_SUPP)); + + l = get_conf_long(d, where + PCI_IDE_CTL); + printf("\t\tIDECtl: IntEn%c\n", + FLAG(l, PCI_IDE_CTL_FLOWTHROUGH_IDE)); + + // The rest of the capability is variable length arrays + off = where + PCI_IDE_CAP + PCI_IDE_LINK_STREAM; + + // Link IDE Register Block repeated 0 to 8 times + if (linknum) + { + if (!config_fetch(d, off, 8 * linknum)) + { + printf("\t\t\n"); + return; + } + for (i = 0; i < linknum; ++i) + { + // Link IDE Stream Control Register + l = get_conf_long(d, off); + off += 4; + printf("\t\tLinkIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d\n", + i, + FLAG(l, PCI_IDE_LINK_CTL_EN), + aggr[PCI_IDE_LINK_CTL_TX_AGGR_NPR(l)], + aggr[PCI_IDE_LINK_CTL_TX_AGGR_PR(l)], + aggr[PCI_IDE_LINK_CTL_TX_AGGR_CPL(l)], + FLAG(l, PCI_IDE_LINK_CTL_EN), + TABLE(hdr_enc_mode, PCI_IDE_LINK_CTL_PART_ENC(l), buf1), + TABLE(algo, PCI_IDE_LINK_CTL_ALG(l), buf2), + PCI_IDE_LINK_CTL_TC(l), + PCI_IDE_LINK_CTL_ID(l) + ); + + /* Link IDE Stream Status Register */ + l = get_conf_long(d, off); + off += 4; + printf("\t\tLinkIDE#%d Sta: Status=%s RecvChkFail%c\n", + i, + TABLE(stream_state, PCI_IDE_LINK_STS_STATUS(l), buf1), + FLAG(l, PCI_IDE_LINK_STS_RECVD_INTEGRITY_CHECK)); + } + } + + for (i = 0; i < linknum; ++i) + { + // Fetching Selective IDE Stream Capability/Control/Status/RID1/RID2 + if (!config_fetch(d, off, 20)) + { + printf("\t\t\n"); + return; + } + + // Selective IDE Stream Capability Register + l = get_conf_long(d, off); + off += 4; + addrnum = PCI_IDE_SEL_CAP_BLOCKS_NUM(l); + + // Selective IDE Stream Control Register + l = get_conf_long(d, off); + off += 4; + + printf("\t\tSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n", + i, + FLAG(l, PCI_IDE_SEL_CTL_EN), + aggr[PCI_IDE_SEL_CTL_TX_AGGR_NPR(l)], + aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)], + aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)], + FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN), + TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1), + TABLE(algo, PCI_IDE_SEL_CTL_ALG(l), buf2), + PCI_IDE_SEL_CTL_TC(l), + PCI_IDE_SEL_CTL_ID(l), + (l & PCI_IDE_SEL_CTL_DEFAULT) ? " Default" : "" + ); + + // Selective IDE Stream Status Register + l = get_conf_long(d, off); + off += 4; + + printf("\t\tSelectiveIDE#%d Sta: %s RecvChkFail%c\n", + i, + TABLE(stream_state, PCI_IDE_SEL_STS_STATUS(l), buf1), + FLAG(l, PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK)); + + // IDE RID Association Registers + l = get_conf_long(d, off); + off += 4; + l2 = get_conf_long(d, off); + off += 4; + + printf("\t\tSelectiveIDE#%d RID: Valid%c Base=%x Limit=%x SegBase=%x\n", + i, + FLAG(l2, PCI_IDE_SEL_RID_2_VALID), + PCI_IDE_SEL_RID_2_BASE(l2), + PCI_IDE_SEL_RID_1_LIMIT(l), + PCI_IDE_SEL_RID_2_SEG_BASE(l2)); + + if (!config_fetch(d, off, addrnum * 12)) + { + printf("\t\t\n"); + return; + } + + // IDE Address Association Registers + for (j = 0; j < addrnum; ++j) + { + u64 limit, base; + + l = get_conf_long(d, off); + off += 4; + limit = get_conf_long(d, off); + off += 4; + base = get_conf_long(d, off); + off += 4; + printf("\t\tSelectiveIDE#%d RID: Valid%c Base=%lx Limit=%lx\n", + i, + FLAG(l, PCI_IDE_SEL_ADDR_1_VALID), + (base << 32) | PCI_IDE_SEL_ADDR_1_BASE_LOW(l), + (limit << 32) | PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l)); + } + } +} + void show_ext_caps(struct device *d, int type) { @@ -1621,6 +1780,9 @@ show_ext_caps(struct device *d, int type) case PCI_EXT_CAP_ID_DOE: cap_doe(d, where); break; + case PCI_EXT_CAP_ID_IDE: + cap_ide(d, where); + break; default: printf("Extended Capability ID %#02x\n", id); break;