From patchwork Sun Dec 31 17:12:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 13507272 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C19538F48; Sun, 31 Dec 2023 17:13:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZCw+OL3q" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BVGnTu5001316; Sun, 31 Dec 2023 17:13:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=bQXZOBYxXu7cLMHj6wj4VjoZOKLJarfir3vcow/Dk+Q=; b=ZC w+OL3qhfF0VosVy+jJSlETeC5l+m8YvialEXUofdsoSTGNkiskwudPv+6U2G/He5 82m2GDChZeQOUwD3B4jOM3eshXni4Nf/Za8GXkJGAqtUEOblL94oE0vXGCasN0/O KtDwWNEI48UHXXetKlPaDE6BCQngKQ5RECG1WzmKh9jOPVS2BojZqfQvp8WpS1Id bxyVO0RJ2C1ZJfnh0/ZRFdnHowN1/jF+o0O9EVLhyO2DKQZQ5HnN4b70PBGwX1r3 QBGcRTDotoLKVXKUu51waTS8UB1/NbqrDJJZt5YM3GLfkuoik5IivpzzdZDjydKF 4IeexOY7U813t8Y5LXpg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vaa7ca27c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 31 Dec 2023 17:13:16 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BVHDFDj014075 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 31 Dec 2023 17:13:15 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 31 Dec 2023 09:13:02 -0800 From: Jishnu Prakash To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Rob Herring Subject: [PATCH v3 1/3] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder Date: Sun, 31 Dec 2023 22:42:35 +0530 Message-ID: <20231231171237.3322376-2-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231231171237.3322376-1-quic_jprakash@quicinc.com> References: <20231231171237.3322376-1-quic_jprakash@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: B49EthUCB7ibpb2EuuOLjvKd2OGuuX1A X-Proofpoint-ORIG-GUID: B49EthUCB7ibpb2EuuOLjvKd2OGuuX1A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 mlxscore=0 mlxlogscore=984 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312310141 There are several files containing QCOM ADC macros for channel names right now in the include/dt-bindings/iio folder. Since all of these are specifically for adc, move the files to the include/dt-bindings/iio/adc folder. Also update all affected devicetree and driver files to fix compilation errors seen with this move and update documentation files to fix dtbinding check errors for the same. Changes since v2: - Updated some more new devicetree files requiring this change. Acked-by: Lee Jones Acked-by: Rob Herring Signed-off-by: Jishnu Prakash --- .../devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml | 4 ++-- Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 2 +- .../devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml | 2 +- .../devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml | 6 +++--- arch/arm64/boot/dts/qcom/pm2250.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8953.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmi632.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmi8950.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +- arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 +- .../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 +- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 8 ++++---- drivers/iio/adc/qcom-spmi-adc5.c | 2 +- drivers/iio/adc/qcom-spmi-vadc.c | 2 +- include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h | 2 +- include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h | 2 +- .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h | 2 +- .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h | 2 +- .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h | 2 +- .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h | 0 .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h | 0 include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h | 0 42 files changed, 49 insertions(+), 49 deletions(-) rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h (98%) rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h (98%) rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h (99%) rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h (97%) rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h (95%) rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h (100%) rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h (100%) rename include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h (100%) diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index 40fa0710f1f0..6e2ce30fe0ce 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -277,8 +277,8 @@ examples: }; - | - #include - #include + #include + #include #include pmic { diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 8103fb61a16c..0c2394301ca0 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -268,7 +268,7 @@ examples: #include #include #include - #include + #include #include pmic@0 { diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml index 7541e27704ca..147126c6a564 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml @@ -112,7 +112,7 @@ additionalProperties: false examples: - | - #include + #include #include pmic { diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml index d9d2657287cb..e1b4a9fdd6af 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -165,7 +165,7 @@ additionalProperties: false examples: - | - #include + #include #include pmic { @@ -206,8 +206,8 @@ examples: }; - | - #include - #include + #include + #include #include pmic { diff --git a/arch/arm64/boot/dts/qcom/pm2250.dtsi b/arch/arm64/boot/dts/qcom/pm2250.dtsi index 5f1d15db5c99..a26466de03ad 100644 --- a/arch/arm64/boot/dts/qcom/pm2250.dtsi +++ b/arch/arm64/boot/dts/qcom/pm2250.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2023, Linaro Ltd */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index 99369a0cdb61..c10625728d23 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index ddbaf7280b03..844e77de1fa0 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index d13a1ab7c20b..208b5ec8dca6 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index 98dc04962fe3..bc5ce1ae9920 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2020, Konrad Dybcio */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 6fdbf507c262..c16dc3c4a6a3 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2020, Konrad Dybcio */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 3bf7cf5d1700..e5ea669795a3 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2022 Luca Weiss */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 3ba3ba5d8fce..5dbfebc43847 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -7,7 +7,7 @@ #include #include #include -#include +#include / { thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 1aee3270ce7b..68d612d4277d 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -4,7 +4,7 @@ * Copyright (c) 2019, Linaro Limited */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index ac08a09c64c2..a0b89a43baf0 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -4,7 +4,7 @@ * Copyright (c) 2019, Linaro Limited */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 4b2e8fb47d2d..79059b263e5f 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi index f03095779de0..33b401c9e70d 100644 --- a/arch/arm64/boot/dts/qcom/pm8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2022, Marijn Suijten */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index 1067e141be6c..5e2a7a3783b5 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index d44a95caf04a..cfa4eb5723a6 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 3f82715392c6..26f46f898eb6 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* Copyright 2018 Google LLC. */ -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index 4eb79e0ce40a..09f7af85d39b 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2023 Luca Weiss */ -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 1029f3b1bb9a..6fd1acdab640 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2019, AngeloGioacchino Del Regno -#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index dbd4b91dfe06..6d95a1352db1 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -6,7 +6,7 @@ #include #include #include -#include +#include / { thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi index 0d0a846ac8d9..9f3e4121d834 100644 --- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi +++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause #include -#include +#include &spmi_bus { pmic@0 { diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 461ad97032f7..673a8ea5b64d 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -5,7 +5,7 @@ #include #include -#include +#include #include / { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 176898c9dbbd..58d4abbd3275 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -9,8 +9,8 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 -#include -#include +#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index b5fe7356be48..1dd4aa300f7f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "sc7280-idp.dtsi" #include "pmr735a.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index a0059527d9e4..ba853a881616 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ -#include +#include #include #include "sc7280.dtsi" #include "pm7325.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index f9b96bd2477e..ecd17cbaa966 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -11,8 +11,8 @@ * Copyright 2022 Google LLC. */ -#include -#include +#include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index ddc84282f142..931a8d911229 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -7,7 +7,7 @@ #include #include #include -#include +#include / { thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index def3976bd5bb..4e4f276aebd5 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -7,9 +7,9 @@ /dts-v1/; #include -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index ade619805519..c20abdf34eb7 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index a20d5d76af35..aff019dccd46 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -6,10 +6,10 @@ /dts-v1/; #include -#include -#include -#include -#include +#include +#include +#include +#include #include #include "sm8450.dtsi" #include "pm8350.dtsi" diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index b6b612d733ff..4225952001f3 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -20,7 +20,7 @@ #include #include -#include +#include #define ADC5_USR_REVISION1 0x0 #define ADC5_USR_STATUS1 0x8 diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c index f5c6f1f27b2c..c3602c53968a 100644 --- a/drivers/iio/adc/qcom-spmi-vadc.c +++ b/drivers/iio/adc/qcom-spmi-vadc.c @@ -20,7 +20,7 @@ #include #include -#include +#include /* VADC register and bit definitions */ #define VADC_REVISION2 0x1 diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h similarity index 98% rename from include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h index 96908014e09e..f0ab57078ca4 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h @@ -10,7 +10,7 @@ #define PM7325_SID 1 #endif -#include +#include /* ADC channels for PM7325_ADC for PMIC7 */ #define PM7325_ADC7_REF_GND (PM7325_SID << 8 | ADC7_REF_GND) diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h similarity index 98% rename from include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h index 5d98f7d48a1e..ef818248ec8c 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h @@ -6,7 +6,7 @@ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H -#include +#include /* ADC channels for PM8350_ADC for PMIC7 */ #define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | ADC7_REF_GND) diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h similarity index 99% rename from include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h index 57c7977666d3..d841bf00b7b0 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h @@ -10,7 +10,7 @@ #define PM8350B_SID 3 #endif -#include +#include /* ADC channels for PM8350B_ADC for PMIC7 */ #define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | ADC7_REF_GND) diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h similarity index 97% rename from include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h index 3d1a41a22cef..161b211ec126 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h @@ -10,7 +10,7 @@ #define PMK8350_SID 0 #endif -#include +#include /* ADC channels for PMK8350_ADC for PMIC7 */ #define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | ADC7_REF_GND) diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h similarity index 95% rename from include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h index c5adfa82b20d..fedc9e3882b8 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h @@ -10,7 +10,7 @@ #define PMR735A_SID 4 #endif -#include +#include /* ADC channels for PMR735A_ADC for PMIC7 */ #define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | ADC7_REF_GND) diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h similarity index 100% rename from include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h similarity index 100% rename from include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h similarity index 100% rename from include/dt-bindings/iio/qcom,spmi-vadc.h rename to include/dt-bindings/iio/adc/qcom,spmi-vadc.h From patchwork Sun Dec 31 17:12:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 13507273 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E070BA55; Sun, 31 Dec 2023 17:14:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="MOTX/gw/" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BVGxPfr002544; Sun, 31 Dec 2023 17:13:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=070XGU68ef7NhrUzwDUUN5wvB9ePbtUjHfA+YgVZndE=; b=MO TX/gw/9Z8wmURkyRopYJ3e+981zKXY0wGL7rI7a2jHl5drviIRujT+JwYdbghpb9 EsbWrt9Tgs9IzD2pmiYRU+JAbh0U0MnTiCnytjZJ5TpiXhMqyQmi3A05AN1j2LAY SJWS8+X3k1X3tFB5U99Dfrtb5BSyjMSy6/7B6kNkMY4IRs7cis3UUOPKY/JeJmlQ WZNFERhzjJeDfnhq6Tk+kolh5cDPs7B2uagb7NkYLgVa2YBZlqhkMh4XAFSAEIUT y6q1yRKnOHJ6d+/6r07tgKIqOeVY2HifQGG40YHmZXPQzmqnRJxih5y793JwL6E+ TZK/X5goA76D2AHk7GBA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vaccs1wrk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 31 Dec 2023 17:13:25 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BVHDP8S015703 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 31 Dec 2023 17:13:25 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 31 Dec 2023 09:13:12 -0800 From: Jishnu Prakash To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Date: Sun, 31 Dec 2023 22:42:36 +0530 Message-ID: <20231231171237.3322376-3-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231231171237.3322376-1-quic_jprakash@quicinc.com> References: <20231231171237.3322376-1-quic_jprakash@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CUID-sxCUx2KD50nvs4rjKWl8_UX8InF X-Proofpoint-ORIG-GUID: CUID-sxCUx2KD50nvs4rjKWl8_UX8InF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312310141 For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS(Programmable Boot Sequence) firmware through a single register interface. This interface is implemented on an SDAM (Shared Direct Access Memory) peripheral on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC channels and virtual channels (combination of ADC channel number and PMIC SID number) per PMIC, to be used by clients of this device. Changes since v2: - Moved ADC5 Gen3 documentation into a separate new file. Changes since v1: - Updated properties separately for all compatibles to clarify usage of new properties and updates in usage of old properties for ADC5 Gen3. - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment mentioning this convention. - Used predefined channel IDs in individual PMIC channel definitions instead of numeric IDs. - Addressed other comments from reviewers. Co-developed-by: Anjelique Melendez Signed-off-by: Anjelique Melendez Signed-off-by: Jishnu Prakash --- .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 212 ++++++++++++++++++ .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 50 +++++ .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 89 ++++++++ .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++ .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 56 +++++ .../iio/adc/qcom,spmi-adc7-pmr735b.h | 2 +- .../iio/adc/qcom,spmi-adc7-smb139x.h | 2 +- include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++ 8 files changed, 512 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml new file mode 100644 index 000000000000..ed5bb53e7628 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC5 Gen3 + +maintainers: + - Jishnu Prakash + +description: | + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to + clients to read voltage. It is a 16-bit sigma-delta ADC. + It also performs the same thermal monitoring function as + the existing ADC_TM devices. + +properties: + compatible: + const: qcom,spmi-adc5-gen3 + + reg: + description: | + - Each reg corresponds to an SDAM peripheral base address that is being used for ADC. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1. This property is required for + ADC devices with channels used for TM (thermal monitoring) functionality. + + '#io-channel-cells': + const: 1 + + interrupts: + description: | + End of conversion interrupt. Interrupts are defined for each SDAM being used. + + interrupt-names: + minItems: 1 + maxItems: 10 + items: + pattern: "^adc-sdam[0-9]+$" + description: | + Names should be defined as "adc-sdam" where represents the SDAM index. + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - '#io-channel-cells' + - interrupts + - interrupt-names + +patternProperties: + "^channel@[0-9a-f]+$": + type: object + additionalProperties: false + description: | + Represents the external channels which are connected to the ADC. + + properties: + reg: + maxItems: 1 + description: | + ADC channel number. + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h + For PMIC5 Gen3 ADC, the channel numbers are specified separately + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc. + + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + ADC input of the platform as seen in the schematics. + For thermistor inputs connected to generic AMUX or GPIO inputs + these can vary across platform for the same pins. Hence select + the platform schematics name for this channel. + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + enum: [ 85, 340, 1360 ] + default: 1360 + + qcom,pre-scaling: + description: | + Used for scaling the channel input signal before the signal is + fed to VADC. The configuration for this node is to know the + pre-determined ratio and use it for post scaling. It is a pair of + integers, denoting the numerator and denominator of the fraction by which + input signal is multiplied. For example, <1 3> indicates the signal is scaled + down to 1/3 of its value before ADC measurement. + If property is not found default value depending on chip will be used. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - const: 1 + - enum: [ 1, 3, 6, 16 ] + + qcom,ratiometric: + description: | + Channel calibration type. + - If this property is specified VADC will use the VDD reference (1.875V) + and GND for channel calibration. If property is not found, channel will be + calibrated with 0V and 1.25V reference channels, also known as + absolute calibration. + type: boolean + + qcom,hw-settle-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Time between AMUX getting configured and the ADC starting + conversion. The 'hw_settle_time' is an index used from valid values + and programmed in hardware to achieve the hardware settling delay. + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, + 8000, 16000, 32000, 64000, 128000 ] + default: 15 + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Number of samples to be used for measurement. + Averaging provides the option to obtain a single measurement + from the ADC that is an average of multiple samples. The value + selected is 2^(value). + enum: [ 1, 2, 4, 8, 16 ] + default: 1 + + qcom,adc-tm: + description: | + Indicates if ADC_TM monitoring is done on this channel. + Defined for compatible property "qcom,spmi-adc5-gen3". + This is the same functionality as in the existing QCOM ADC_TM + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. + type: boolean + + required: + - reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + /* VADC node */ + pmk8550_vadc: vadc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "adc-sdam0", "adc-sdam1"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; + + /* PMK8550 Channel nodes */ + channel@3 { + reg = ; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = ; + label = "pmk8550_xo_therm"; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,adc-tm; + }; + + /* PM8550 Channel nodes */ + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + }; diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h new file mode 100644 index 000000000000..0f25ef87ed5c --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H + +#ifndef PM8550_SID +#define PM8550_SID 1 +#endif + +#include + +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ +#define PM8550_ADC5_GEN3_REF_GND (PM8550_SID << 8 | ADC5_GEN3_REF_GND) +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | ADC5_GEN3_1P25VREF) +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM) +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM) +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM) +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM) +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO) + +/* 100k pull-up */ +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) + +/* 1/3 Divider */ +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3) + +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | ADC5_GEN3_VPH_PWR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h new file mode 100644 index 000000000000..47116bbe45de --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H + +#ifndef PM8550B_SID +#define PM8550B_SID 7 +#endif + +#include + +/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */ +#define PM8550B_ADC5_GEN3_REF_GND (PM8550B_SID << 8 | ADC5_GEN3_REF_GND) +#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | ADC5_GEN3_1P25VREF) +#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO) + +#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | ADC5_GEN3_CHG_TEMP) +#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | ADC5_GEN3_USB_SNS_V_16) +#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | ADC5_GEN3_VIN_DIV16_MUX) +#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | ADC5_GEN3_VREF_BAT_THERM) +#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | ADC5_GEN3_IIN_FB) +#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | ADC5_GEN3_TEMP_ALARM_LITE) +#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | ADC5_GEN3_IIN_SMB) +#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | ADC5_GEN3_ICHG_SMB) +#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | ADC5_GEN3_ICHG_FB) + +/* 30k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_30K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_30K_PU) + +/* 100k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) + +/* 400k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_400K_PU) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_400K_PU) + +/* 1/3 Divider */ +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_DIV3) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_DIV3) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3) + +#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | ADC5_GEN3_VPH_PWR) +#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_QBG) +#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_CHGR) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_QBG) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_CHGR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h new file mode 100644 index 000000000000..360f2245d582 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H + +#include + +/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */ +#define PM8550VS_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h new file mode 100644 index 000000000000..3fc829ebdf6d --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H + +#ifndef PMK8550_SID +#define PMK8550_SID 0 +#endif + +#include + +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ +#define PMK8550_ADC5_GEN3_REF_GND (PMK8550_SID << 8 | ADC5_GEN3_REF_GND) +#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | ADC5_GEN3_1P25VREF) +#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | ADC5_GEN3_VREF_VADC) +#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | ADC5_GEN3_DIE_TEMP) + +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO) + +/* 30k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU) + +/* 100k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) + +/* 400k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */ diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h index fdb8dd9ae541..812f33872e5e 100644 --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h @@ -10,7 +10,7 @@ #define PMR735B_SID 5 #endif -#include +#include /* ADC channels for PMR735B_ADC for PMIC7 */ #define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND) diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h index c0680d1285cf..750a526af2c1 100644 --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h @@ -6,7 +6,7 @@ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H -#include +#include #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP) #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB) diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h index ef07ecd4d585..cfe653d945a4 100644 --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H @@ -300,4 +302,83 @@ #define ADC7_SBUx 0x94 #define ADC7_VBAT_2S_MID 0x96 +/* ADC channels for PMIC5 Gen3 */ + +#define ADC5_GEN3_REF_GND 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_VREF_VADC 0x02 +#define ADC5_GEN3_DIE_TEMP 0x03 + +#define ADC5_GEN3_AMUX1_THM 0x04 +#define ADC5_GEN3_AMUX2_THM 0x05 +#define ADC5_GEN3_AMUX3_THM 0x06 +#define ADC5_GEN3_AMUX4_THM 0x07 +#define ADC5_GEN3_AMUX5_THM 0x08 +#define ADC5_GEN3_AMUX6_THM 0x09 +#define ADC5_GEN3_AMUX1_GPIO 0x0a +#define ADC5_GEN3_AMUX2_GPIO 0x0b +#define ADC5_GEN3_AMUX3_GPIO 0x0c +#define ADC5_GEN3_AMUX4_GPIO 0x0d + +#define ADC5_GEN3_CHG_TEMP 0x10 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VREF_BAT_THERM 0x15 +#define ADC5_GEN3_IIN_FB 0x17 +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 +#define ADC5_GEN3_IIN_SMB 0x19 +#define ADC5_GEN3_ICHG_SMB 0x1b +#define ADC5_GEN3_ICHG_FB 0xa1 + +/* 30k pull-up1 */ +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d + +/* 100k pull-up2 */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +/* 400k pull-up3 */ +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c +#define ADC5_GEN3_AMUX4_GPIO_DIV3 0x8d + +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f + +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d + +#define ADC5_GEN3_OFFSET_EXT2 0xf8 + #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ From patchwork Sun Dec 31 17:12:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jishnu Prakash X-Patchwork-Id: 13507274 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A2028F6E; Sun, 31 Dec 2023 17:14:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IddicHZ6" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BVGxPfs002544; Sun, 31 Dec 2023 17:13:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=9S5RQYbd1NGZ1hlERIUrxzvZveb5RPYK8vyVEeTXplg=; b=Id dicHZ6sotxHR2ssssz4QfmJzOi7TW6DPKFzT46/edgB6+U155aw4u7t8h26OLheB CfJWPI996/Dlbb4aCfT3podmYbXibwx9VKy1hA9PE27iNDs2B5PeS34mqKHAg/T4 kEkbDaYpjXk4I+wwGfueNoaX6MEiOpdCKcOqNrR0QmK/59Sr8vKeU7X56o8dqUVR W2geGpK9jJQbZace8MEmbI/g953A0yZoGK9bQ2Trpgx2Cbkkd7PCNZOXDTG40OKM YzZ96Vi97g/36/K/MVZcEpiHi8tfIqkprDnzASRkwUjLsduD+VwvuNoPnlVpMfWx MjITdTlzKMJSqSxGD35Q== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vaccs1wrt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 31 Dec 2023 17:13:35 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BVHDZOu016881 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 31 Dec 2023 17:13:35 GMT Received: from hu-jprakash-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 31 Dec 2023 09:13:22 -0800 From: Jishnu Prakash To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC Date: Sun, 31 Dec 2023 22:42:37 +0530 Message-ID: <20231231171237.3322376-4-quic_jprakash@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231231171237.3322376-1-quic_jprakash@quicinc.com> References: <20231231171237.3322376-1-quic_jprakash@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jPNASMbMs7PWJ9CGmGJNKhUdHIEYSlkZ X-Proofpoint-ORIG-GUID: jPNASMbMs7PWJ9CGmGJNKhUdHIEYSlkZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312310141 The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2, with all SW communication to ADC going through PMK8550 which communicates with other PMICs through PBS. One major difference is that the register interface used here is that of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550. There may be more than one SDAM used for ADC5 Gen3 and each has eight channels, which may be used for either immediate reads (same functionality as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements (same as ADC_TM functionality). In this case, we have VADC and ADC_TM functionality combined into the same driver. By convention, we reserve the first channel of the first SDAM for all immediate reads and use the remaining channels across all SDAMs for ADC_TM monitoring functionality. Changes since v1: - Removed datashet_name usage and implemented read_label() function - In probe, updated channel property in iio_chan_spec from individual channel to virtual channel and set indexed property to 1, due to the above change. - Updated order of checks in ISR - Removed the driver remove callback and replaced with callbacks in a devm_add_action call in probe. - Addressed other comments from reviewers. Signed-off-by: Jishnu Prakash --- drivers/iio/adc/Kconfig | 25 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/qcom-spmi-adc5-gen3.c | 1198 +++++++++++++++++++++++++ 3 files changed, 1224 insertions(+) create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 4eebd5161419..4bdd5bb5b3fc 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -997,6 +997,31 @@ config QCOM_SPMI_ADC5 To compile this driver as a module, choose M here: the module will be called qcom-spmi-adc5. +config QCOM_SPMI_ADC5_GEN3 + tristate "Qualcomm Technologies Inc. SPMI PMIC5 GEN3 ADC" + depends on SPMI && THERMAL + select REGMAP_SPMI + select QCOM_VADC_COMMON + help + This is the IIO Voltage PMIC5 Gen3 ADC driver for Qualcomm Technologies Inc. PMICs. + + The driver supports reading multiple channels. The ADC is a 16-bit + sigma-delta ADC. The hardware supports calibrated results for + conversion requests and clients include reading phone power supply + voltage, on board system thermistors connected to the PMIC ADC, + PMIC die temperature, charger temperature, battery current, USB voltage + input and voltage signals connected to supported PMIC GPIO pins. The + hardware supports internal pull-up for thermistors and can choose between + a 30k, 100k or 400k ohm pull up using the ADC channels. + + In addition, the same driver supports ADC thermal monitoring devices too. + They appear as thermal zones with multiple trip points. A thermal client sets + threshold temperature for both warm and cool trips and gets updated when a + threshold is reached. + + To compile this driver as a module, choose M here: the module will + be called qcom-spmi-adc5-gen3. + config RCAR_GYRO_ADC tristate "Renesas R-Car GyroADC driver" depends on ARCH_RCAR_GEN2 || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index c0803383a7cc..539af17a668f 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_NAU7802) += nau7802.o obj-$(CONFIG_NPCM_ADC) += npcm_adc.o obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o +obj-$(CONFIG_QCOM_SPMI_ADC5_GEN3) += qcom-spmi-adc5-gen3.o obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c new file mode 100644 index 000000000000..5b5848492245 --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c @@ -0,0 +1,1198 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define ADC5_GEN3_HS 0x45 +#define ADC5_GEN3_HS_BUSY BIT(7) +#define ADC5_GEN3_HS_READY BIT(0) + +#define ADC5_GEN3_STATUS1 0x46 +#define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7) +#define ADC5_GEN3_STATUS1_THR_CROSS BIT(6) +#define ADC5_GEN3_STATUS1_EOC BIT(0) + +#define ADC5_GEN3_TM_EN_STS 0x47 +#define ADC5_GEN3_TM_HIGH_STS 0x48 +#define ADC5_GEN3_TM_LOW_STS 0x49 + +#define ADC5_GEN3_EOC_STS 0x4a +#define ADC5_GEN3_EOC_CHAN_0 BIT(0) + +#define ADC5_GEN3_EOC_CLR 0x4b +#define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c +#define ADC5_GEN3_TM_LOW_STS_CLR 0x4d +#define ADC5_GEN3_CONV_ERR_CLR 0x4e +#define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0) + +#define ADC5_GEN3_SID 0x4f +#define ADC5_GEN3_SID_MASK GENMASK(3, 0) + +#define ADC5_GEN3_PERPH_CH 0x50 +#define ADC5_GEN3_CHAN_CONV_REQ BIT(7) + +#define ADC5_GEN3_TIMER_SEL 0x51 +#define ADC5_GEN3_TIME_IMMEDIATE 0x1 + +#define ADC5_GEN3_DIG_PARAM 0x52 +#define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4) +#define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2) + +#define ADC5_GEN3_FAST_AVG 0x53 +#define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7) +#define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0) + +#define ADC5_GEN3_ADC_CH_SEL_CTL 0x54 +#define ADC5_GEN3_DELAY_CTL 0x55 +#define ADC5_GEN3_HW_SETTLE_DELAY_MASK GENMASK(3, 0) + +#define ADC5_GEN3_CH_EN 0x56 +#define ADC5_GEN3_HIGH_THR_INT_EN BIT(1) +#define ADC5_GEN3_LOW_THR_INT_EN BIT(0) + +#define ADC5_GEN3_LOW_THR0 0x57 +#define ADC5_GEN3_LOW_THR1 0x58 +#define ADC5_GEN3_HIGH_THR0 0x59 +#define ADC5_GEN3_HIGH_THR1 0x5a + +#define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2) +#define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2) + +#define ADC5_GEN3_CONV_REQ 0xe5 +#define ADC5_GEN3_CONV_REQ_REQ BIT(0) + +#define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8) +#define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0) +#define V_CHAN(x) \ + (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) \ + +enum adc5_cal_method { + ADC5_NO_CAL = 0, + ADC5_RATIOMETRIC_CAL, + ADC5_ABSOLUTE_CAL +}; + +enum adc5_time_select { + MEAS_INT_DISABLE = 0, + MEAS_INT_IMMEDIATE, + MEAS_INT_50MS, + MEAS_INT_100MS, + MEAS_INT_1S, + MEAS_INT_NONE, +}; + +struct adc5_sdam_data { + u16 base_addr; + const char *irq_name; + int irq; +}; + +/** + * struct adc5_channel_prop - ADC channel property. + * @channel: channel number, refer to the channel list. + * @cal_method: calibration method. + * @decimation: sampling rate supported for the channel. + * @sid: slave id of PMIC owning the channel. + * @prescale: channel scaling performed on the input signal. + * @hw_settle_time: the time between AMUX being configured and the + * start of conversion. + * @avg_samples: ability to provide single result from the ADC + * that is an average of multiple measurements. + * @sdam_index: Index for which SDAM this channel is on. + * @scale_fn_type: Represents the scaling function to convert voltage + * physical units desired by the client for the channel. + * @label: Channel name used in device tree. + * @chip: pointer to top-level ADC device structure. + * @adc_tm: indicates if the channel is used for TM measurements. + * @tm_chan_index: TM channel number used (ranging from 1-7). + * @timer: time period of recurring TM measurement. + * @tzd: pointer to thermal device corresponding to TM channel. + * @high_thr_en: TM high threshold crossing detection enabled. + * @low_thr_en: TM low threshold crossing detection enabled. + * @last_temp: last temperature that caused threshold violation, + * or a thermal TM channel. + * @last_temp_set: indicates if last_temp is stored. + */ +struct adc5_channel_prop { + unsigned int channel; + enum adc5_cal_method cal_method; + unsigned int decimation; + unsigned int sid; + unsigned int prescale; + unsigned int hw_settle_time; + unsigned int avg_samples; + unsigned int sdam_index; + + enum vadc_scale_fn_type scale_fn_type; + const char *label; + + struct adc5_chip *chip; + /* TM(thermal monitoring related) properties */ + bool adc_tm; + unsigned int tm_chan_index; + unsigned int timer; + struct thermal_zone_device *tzd; + bool high_thr_en; + bool low_thr_en; + int last_temp; + bool last_temp_set; +}; + +/** + * struct adc5_chip - ADC private structure. + * @regmap: SPMI ADC5 Gen3 peripheral register map field. + * @dev: SPMI ADC5 Gen3 device. + * @base: pointer to array of ADC peripheral base and interrupt. + * @num_sdams: number of SDAMs (Shared Direct Access Memory Module) being used. + * @nchannels: number of ADC channels. + * @chan_props: array of ADC channel properties. + * @iio_chans: array of IIO channels specification. + * @complete: ADC result notification after interrupt is received. + * @lock: ADC lock for access to the peripheral, to prevent concurrent + * requests from multiple clients. + * @data: software configuration data. + * @n_tm_channels: number of ADC channels used for TM measurements. + * @tm_handler_work: scheduled work for handling TM threshold violation. + */ +struct adc5_chip { + struct regmap *regmap; + struct device *dev; + struct adc5_sdam_data *base; + unsigned int num_sdams; + unsigned int nchannels; + struct adc5_channel_prop *chan_props; + struct iio_chan_spec *iio_chans; + struct completion complete; + struct mutex lock; + const struct adc5_data *data; + /* TM properties */ + unsigned int n_tm_channels; + struct work_struct tm_handler_work; +}; + +static int adc5_gen3_read(struct adc5_chip *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len) +{ + return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len); +} + +static int adc5_gen3_write(struct adc5_chip *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len) +{ + return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len); +} + +static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data, u8 sdam_index) +{ + int ret; + u8 rslt[2]; + + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), rslt, 2); + if (ret) + return ret; + + *data = get_unaligned_le16(rslt); + + if (*data == ADC5_USR_DATA_CHECK) { + dev_err(adc->dev, "Invalid data:%#x\n", *data); + return -EINVAL; + } + + dev_dbg(adc->dev, "voltage raw code:%#x\n", *data); + + return 0; +} + +static void adc5_gen3_update_dig_param(struct adc5_chip *adc, + struct adc5_channel_prop *prop, u8 *data) +{ + /* Update calibration select and decimation ratio select*/ + *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK); + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method); + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation); +} + +# define ADC5_GEN3_READ_CONFIG_REGS 7 + +static int adc5_gen3_configure(struct adc5_chip *adc, + struct adc5_channel_prop *prop) +{ + u8 sdam_index = prop->sdam_index; + u8 conv_req = 0; + u8 buf[ADC5_GEN3_READ_CONFIG_REGS]; + int ret; + + /* Reserve channel 0 of first SDAM for immediate conversions */ + if (prop->adc_tm) + sdam_index = 0; + + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret) + return ret; + + /* Write SID */ + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid); + + /* + * Use channel 0 by default for immediate conversion and + * to indicate there is an actual conversion request + */ + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | 0; + + buf[2] = ADC5_GEN3_TIME_IMMEDIATE; + + /* Digital param selection */ + adc5_gen3_update_dig_param(adc, prop, &buf[3]); + + /* Update fast average sample value */ + buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK; + buf[4] |= prop->avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] = prop->channel; + + /* Select HW settle delay for channel */ + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->hw_settle_time); + + reinit_completion(&adc->complete); + + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret) + return ret; + + conv_req = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1); +} + +/** + * Worst case delay from PBS in readying handshake bit + * can be up to 15ms, when PBS is busy running other + * simultaneous transactions, while in the best case, it is + * already ready at this point. Assigning polling delay and + * retry count accordingly. + */ + +#define ADC5_GEN3_HS_DELAY_MIN_US 100 +#define ADC5_GEN3_HS_DELAY_MAX_US 110 +#define ADC5_GEN3_HS_RETRY_COUNT 150 + +static int adc5_gen3_poll_wait_hs(struct adc5_chip *adc, + unsigned int sdam_index) +{ + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ; + u8 status = 0; + int ret, count; + + for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) { + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1); + if (ret) + return ret; + + if (status == ADC5_GEN3_HS_READY) { + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ, + &conv_req, 1); + if (ret) + return ret; + + if (!conv_req) + return 0; + } + + usleep_range(ADC5_GEN3_HS_DELAY_MIN_US, + ADC5_GEN3_HS_DELAY_MAX_US); + } + + dev_err(adc->dev, "Setting HS ready bit timed out, status:%#x\n", status); + return -ETIMEDOUT; +} + +/** + * Worst case delay from PBS for conversion time can be + * up to 500ms, when PBS has timed out twice, once for + * the initial attempt and once for a retry of the same + * transaction. + */ + +#define ADC5_GEN3_CONV_TIMEOUT_MS 501 + +static int adc5_gen3_do_conversion(struct adc5_chip *adc, + struct adc5_channel_prop *prop, + u16 *data_volt) +{ + u8 val, sdam_index = prop->sdam_index; + unsigned long rc; + int ret; + + /* Reserve channel 0 of first SDAM for immediate conversions */ + if (prop->adc_tm) + sdam_index = 0; + + mutex_lock(&adc->lock); + ret = adc5_gen3_poll_wait_hs(adc, 0); + if (ret) + goto unlock; + + ret = adc5_gen3_configure(adc, prop); + if (ret) { + dev_err(adc->dev, "ADC configure failed with %d\n", ret); + goto unlock; + } + + /* No support for polling mode at present*/ + rc = wait_for_completion_timeout(&adc->complete, + msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS)); + if (!rc) { + dev_err(adc->dev, "Reading ADC channel %s timed out\n", + prop->label); + ret = -ETIMEDOUT; + goto unlock; + } + + ret = adc5_gen3_read_voltage_data(adc, data_volt, sdam_index); + if (ret) + goto unlock; + + val = BIT(0); + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_EOC_CLR, &val, 1); + if (ret) + goto unlock; + + /* To indicate conversion request is only to clear a status */ + val = 0; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret) + goto unlock; + + val = ADC5_GEN3_CONV_REQ_REQ; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1); + +unlock: + mutex_unlock(&adc->lock); + + return ret; +} + +static int get_sdam_from_irq(struct adc5_chip *adc, int irq) +{ + int i; + + for (i = 0; i < adc->num_sdams; i++) { + if (adc->base[i].irq == irq) + return i; + } + return -ENOENT; +} + +static irqreturn_t adc5_gen3_isr(int irq, void *dev_id) +{ + struct adc5_chip *adc = dev_id; + u8 status, tm_status[2], eoc_status, val; + int ret, sdam_num; + + sdam_num = get_sdam_from_irq(adc, irq); + if (sdam_num < 0) { + dev_err(adc->dev, "adc irq %d not associated with an sdam\n", irq); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_STATUS1, &status, 1); + if (ret) { + dev_err(adc->dev, "adc read status1 failed with %d\n", ret); + return IRQ_HANDLED; + } + + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_EOC_STS, &eoc_status, 1); + if (ret) { + dev_err(adc->dev, "adc read eoc status failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { + dev_err_ratelimited(adc->dev, "Unexpected conversion fault, status:%#x, eoc_status:%#x\n", + status, eoc_status); + val = ADC5_GEN3_CONV_ERR_CLR_REQ; + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val, 1); + if (ret < 0) + return IRQ_HANDLED; + + /* To indicate conversion request is only to clear a status */ + val = 0; + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret < 0) + return IRQ_HANDLED; + + val = ADC5_GEN3_CONV_REQ_REQ; + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_CONV_REQ, &val, 1); + + return IRQ_HANDLED; + } + + /* CHAN0 is the preconfigured channel for immediate conversion */ + if (eoc_status & ADC5_GEN3_EOC_CHAN_0) + complete(&adc->complete); + + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2); + if (ret) { + dev_err(adc->dev, "adc read TM status failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (tm_status[0] || tm_status[1]) + schedule_work(&adc->tm_handler_work); + + dev_dbg(adc->dev, "Interrupt status:%#x, EOC status:%#x, high:%#x, low:%#x\n", + status, eoc_status, tm_status[0], tm_status[1]); + + return IRQ_HANDLED; +} + +static void tm_handler_work(struct work_struct *work) +{ + struct adc5_chip *adc = container_of(work, struct adc5_chip, tm_handler_work); + struct adc5_channel_prop *chan_prop; + u8 tm_status[2] = {0}; + u8 buf[16] = {0}; + u8 val; + int ret, i, sdam_index = -1; + + for (i = 0; i < adc->nchannels; i++) { + bool upper_set = false, lower_set = false; + int temp, offset; + u16 code = 0; + + chan_prop = &adc->chan_props[i]; + offset = chan_prop->tm_chan_index; + + if (!chan_prop->adc_tm) + continue; + + mutex_lock(&adc->lock); + if (chan_prop->sdam_index != sdam_index) { + sdam_index = chan_prop->sdam_index; + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS, + tm_status, 2); + if (ret) { + dev_err(adc->dev, "adc read TM status failed with %d\n", ret); + goto out; + } + + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR, + tm_status, 2); + if (ret) { + dev_err(adc->dev, "adc write TM status failed with %d\n", ret); + goto out; + } + + /* To indicate conversion request is only to clear a status */ + val = 0; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret) { + dev_err(adc->dev, "adc write status clear conv_req failed with %d\n", + ret); + goto out; + } + + val = ADC5_GEN3_CONV_REQ_REQ; + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1); + if (ret) { + dev_err(adc->dev, "adc write conv_req failed with %d\n", ret); + goto out; + } + + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), buf, + sizeof(buf)); + if (ret < 0) { + dev_err(adc->dev, "adc read data failed with %d\n", ret); + goto out; + } + } + + if ((tm_status[0] & BIT(offset)) && (chan_prop->high_thr_en)) + upper_set = true; + + if ((tm_status[1] & BIT(offset)) && (chan_prop->low_thr_en)) + lower_set = true; + + mutex_unlock(&adc->lock); + + if (!(upper_set || lower_set)) + continue; + + code = get_unaligned_le16(&buf[2 * offset]); + pr_debug("ADC_TM threshold code:%#x\n", code); + + ret = qcom_adc5_hw_scale(chan_prop->scale_fn_type, + chan_prop->prescale, adc->data, code, &temp); + if (ret) { + dev_err(adc->dev, "Invalid temperature reading, ret = %d, code=%#x\n", + ret, code); + continue; + } + + chan_prop->last_temp = temp; + chan_prop->last_temp_set = true; + thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED); + } + + return; + +out: + mutex_unlock(&adc->lock); +} + +static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev, + const struct fwnode_reference_args *iiospec) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + int i, v_channel; + + for (i = 0; i < adc->nchannels; i++) { + v_channel = V_CHAN(adc->chan_props[i]); + if (v_channel == iiospec->args[0]) + return i; + } + + return -ENOENT; +} + +static int adc5_gen3_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, int *val2, + long mask) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + struct adc5_channel_prop *prop; + u16 adc_code_volt; + int ret; + + prop = &adc->chan_props[chan->address]; + + switch (mask) { + case IIO_CHAN_INFO_PROCESSED: + ret = adc5_gen3_do_conversion(adc, prop, + &adc_code_volt); + if (ret) + return ret; + + ret = qcom_adc5_hw_scale(prop->scale_fn_type, + prop->prescale, adc->data, + adc_code_volt, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_RAW: + ret = adc5_gen3_do_conversion(adc, prop, + &adc_code_volt); + if (ret) + return ret; + *val = (int)adc_code_volt; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int adc5_gen3_read_label(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, char *label) +{ + struct adc5_chip *adc = iio_priv(indio_dev); + struct adc5_channel_prop *prop; + + prop = &adc->chan_props[chan->address]; + return sprintf(label, "%s\n", prop->label); +} + +static const struct iio_info adc5_gen3_info = { + .read_raw = adc5_gen3_read_raw, + .read_label = adc5_gen3_read_label, + .fwnode_xlate = adc5_gen3_fwnode_xlate, +}; + +static int adc_tm_gen3_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct adc5_channel_prop *prop = tz->devdata; + struct adc5_chip *adc; + u16 adc_code_volt; + int ret; + + if (!prop || !prop->chip) + return -EINVAL; + + adc = prop->chip; + + if (prop->last_temp_set) { + pr_debug("last_temp: %d\n", prop->last_temp); + prop->last_temp_set = false; + *temp = prop->last_temp; + return 0; + } + + ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt); + if (ret < 0) + return ret; + + return qcom_adc5_hw_scale(prop->scale_fn_type, + prop->prescale, adc->data, + adc_code_volt, temp); +} + +static int _adc_tm5_gen3_disable_channel(struct adc5_channel_prop *prop) +{ + struct adc5_chip *adc = prop->chip; + int ret; + u8 val; + + prop->high_thr_en = false; + prop->low_thr_en = false; + + val = MEAS_INT_DISABLE; + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_TIMER_SEL, &val, 1); + if (ret) + return ret; + + /* To indicate there is an actual conversion request */ + val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_PERPH_CH, &val, 1); + if (ret) + return ret; + + val = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &val, 1); +} + +static int adc_tm5_gen3_disable_channel(struct adc5_channel_prop *prop) +{ + return _adc_tm5_gen3_disable_channel(prop); +} + +# define ADC_TM5_GEN3_CONFIG_REGS 12 + +static int adc_tm5_gen3_configure(struct adc5_channel_prop *prop, + int low_temp, int high_temp) +{ + struct adc5_chip *adc = prop->chip; + u8 conv_req = 0, buf[ADC_TM5_GEN3_CONFIG_REGS]; + u16 adc_code; + int ret; + + ret = adc5_gen3_poll_wait_hs(adc, prop->sdam_index); + if (ret < 0) + return ret; + + ret = adc5_gen3_read(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + /* Write SID */ + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid); + + /* + * Select TM channel and indicate there is an actual + * conversion request + */ + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + + buf[2] = prop->timer; + + /* Digital param selection */ + adc5_gen3_update_dig_param(adc, prop, &buf[3]); + + /* Update fast average sample value */ + buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK; + buf[4] |= prop->avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] = prop->channel; + + /* Select HW settle delay for channel */ + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->hw_settle_time); + + /* High temperature corresponds to low voltage threshold */ + if (high_temp != INT_MAX) { + prop->low_thr_en = true; + adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp); + put_unaligned_le16(adc_code, &buf[8]); + } else { + prop->low_thr_en = false; + } + + /* Low temperature corresponds to high voltage threshold */ + if (low_temp != -INT_MAX) { + prop->high_thr_en = true; + adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp); + put_unaligned_le16(adc_code, &buf[10]); + } else { + prop->high_thr_en = false; + } + + buf[7] = 0; + if (prop->high_thr_en) + buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN; + if (prop->low_thr_en) + buf[7] |= ADC5_GEN3_LOW_THR_INT_EN; + + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + conv_req = ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1); +} + +static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz, + int low_temp, int high_temp) +{ + struct adc5_channel_prop *prop = tz->devdata; + struct adc5_chip *adc; + int ret; + + if (!prop || !prop->chip) + return -EINVAL; + + adc = prop->chip; + + dev_dbg(adc->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n", + prop->label, low_temp, high_temp); + + mutex_lock(&adc->lock); + if (high_temp == INT_MAX && low_temp <= -INT_MAX) + ret = adc_tm5_gen3_disable_channel(prop); + else + ret = adc_tm5_gen3_configure(prop, low_temp, high_temp); + mutex_unlock(&adc->lock); + + return ret; +} + +static const struct thermal_zone_device_ops adc_tm_ops = { + .get_temp = adc_tm_gen3_get_temp, + .set_trips = adc_tm5_gen3_set_trip_temp, +}; + +static int adc_tm_register_tzd(struct adc5_chip *adc) +{ + unsigned int i, channel; + struct thermal_zone_device *tzd; + + for (i = 0; i < adc->nchannels; i++) { + channel = V_CHAN(adc->chan_props[i]); + + if (!adc->chan_props[i].adc_tm) + continue; + tzd = devm_thermal_of_zone_register(adc->dev, channel, + &adc->chan_props[i], &adc_tm_ops); + + if (IS_ERR(tzd)) { + if (PTR_ERR(tzd) == -ENODEV) { + dev_warn(adc->dev, "thermal sensor on channel %d is not used\n", + channel); + continue; + } + + dev_err(adc->dev, "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), adc->chan_props[i].channel); + return PTR_ERR(tzd); + } + adc->chan_props[i].tzd = tzd; + } + + return 0; +} + +static void adc5_gen3_disable(void *data) +{ + struct adc5_chip *adc = data; + int i; + + if (adc->n_tm_channels) + cancel_work_sync(&adc->tm_handler_work); + + for (i = 0; i < adc->num_sdams; i++) + free_irq(adc->base[i].irq, adc); + + mutex_lock(&adc->lock); + /* Disable all available TM channels */ + for (i = 0; i < adc->nchannels; i++) { + if (!adc->chan_props[i].adc_tm) + continue; + adc5_gen3_poll_wait_hs(adc, adc->chan_props[i].sdam_index); + _adc_tm5_gen3_disable_channel(&adc->chan_props[i]); + } + + mutex_unlock(&adc->lock); +} + +struct adc5_channels { + unsigned int prescale_index; + enum iio_chan_type type; + long info_mask; + enum vadc_scale_fn_type scale_fn_type; +}; + +/* In these definitions, _pre refers to an index into adc5_prescale_ratios. */ +#define ADC5_CHAN(_type, _mask, _pre, _scale) \ + { \ + .prescale_index = _pre, \ + .type = _type, \ + .info_mask = _mask, \ + .scale_fn_type = _scale, \ + }, \ + +#define ADC5_CHAN_TEMP(_pre, _scale) \ + ADC5_CHAN(IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +#define ADC5_CHAN_VOLT(_pre, _scale) \ + ADC5_CHAN(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +#define ADC5_CHAN_CUR(_pre, _scale) \ + ADC5_CHAN(IIO_CURRENT, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = { + [ADC5_GEN3_REF_GND] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_PMIC_THERM_PM7) + [ADC5_GEN3_TEMP_ALARM_LITE] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_PMIC_THERM_PM7) + [ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) +}; + +static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc, + struct adc5_channel_prop *prop, + struct fwnode_handle *fwnode, + const struct adc5_data *data) +{ + const char *name = fwnode_get_name(fwnode); + const char *channel_name; + struct device *dev = adc->dev; + u32 chan, value, varr[2], sid = 0; + int ret, val; + + ret = fwnode_property_read_u32(fwnode, "reg", &chan); + if (ret < 0) + return dev_err_probe(dev, ret, "invalid channel number %s\n", name); + + /* + * Value read from "reg" is virtual channel number + * virtual channel number = sid << 8 | channel number + */ + + sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan); + chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan); + + if (chan > ADC5_GEN3_OFFSET_EXT2) + return dev_err_probe(dev, -EINVAL, "%s invalid channel number %d\n", name, chan); + + prop->channel = chan; + prop->sid = sid; + + ret = fwnode_property_read_string(fwnode, "label", &channel_name); + if (ret) + channel_name = name; + prop->label = channel_name; + + prop->decimation = ADC5_DECIMATION_DEFAULT; + ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &value); + if (!ret) { + ret = qcom_adc5_decimation_from_dt(value, data->decimation); + if (ret < 0) + return dev_err_probe(dev, ret, "%#x invalid decimation %d\n", + chan, value); + prop->decimation = ret; + } + + prop->prescale = adc->data->adc_chans[prop->channel].prescale_index; + ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2); + if (!ret) { + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); + if (ret < 0) + return dev_err_probe(dev, ret, "%#x invalid pre-scaling <%d %d>\n", + chan, varr[0], varr[1]); + prop->prescale = ret; + } + + prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; + ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value); + if (!ret) { + ret = qcom_adc5_hw_settle_time_from_dt(value, + data->hw_settle_1); + if (ret < 0) + return dev_err_probe(dev, ret, "%#x invalid hw-settle-time %d us\n", + chan, value); + prop->hw_settle_time = ret; + } + + prop->avg_samples = VADC_DEF_AVG_SAMPLES; + ret = fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value); + if (!ret) { + ret = qcom_adc5_avg_samples_from_dt(value); + if (ret < 0) + return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n", + chan, value); + prop->avg_samples = ret; + } + + if (fwnode_property_read_bool(fwnode, "qcom,ratiometric")) + prop->cal_method = ADC5_RATIOMETRIC_CAL; + else + prop->cal_method = ADC5_ABSOLUTE_CAL; + + prop->timer = MEAS_INT_IMMEDIATE; + + prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm"); + + if (prop->adc_tm) { + adc->n_tm_channels++; + if (adc->n_tm_channels > ((adc->num_sdams * 8) - 1)) + return dev_err_probe(adc->dev, -EINVAL, + "Number of TM nodes %u greater than channels supported:%u\n", + adc->n_tm_channels, (adc->num_sdams * 8) - 1); + + val = adc->n_tm_channels / 8; + prop->sdam_index = val; + prop->tm_chan_index = adc->n_tm_channels - (8*val); + + prop->timer = MEAS_INT_1S; + } + + return 0; +} + +static const struct adc5_data adc5_gen3_data_pmic = { + .full_scale_code_volt = 0x70e4, + .adc_chans = adc5_gen3_chans_pmic, + .info = &adc5_gen3_info, + .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) + {85, 340, 1360}, + .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) + {15, 100, 200, 300, 400, 500, 600, 700, + 1000, 2000, 4000, 8000, 16000, 32000, + 64000, 128000}, +}; + +static const struct of_device_id adc5_match_table[] = { + { + .compatible = "qcom,spmi-adc5-gen3", + .data = &adc5_gen3_data_pmic, + }, + { } +}; +MODULE_DEVICE_TABLE(of, adc5_match_table); + +static int adc5_get_fw_data(struct adc5_chip *adc) +{ + const struct adc5_channels *adc_chan; + struct iio_chan_spec *iio_chan; + struct adc5_channel_prop *chan_props; + struct fwnode_handle *child; + unsigned int index = 0; + int ret; + + adc->nchannels = device_get_child_node_count(adc->dev); + if (!adc->nchannels) + return -EINVAL; + + adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels, + sizeof(*adc->iio_chans), GFP_KERNEL); + if (!adc->iio_chans) + return -ENOMEM; + + adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels, + sizeof(*adc->chan_props), GFP_KERNEL); + if (!adc->chan_props) + return -ENOMEM; + + chan_props = adc->chan_props; + adc->n_tm_channels = 0; + iio_chan = adc->iio_chans; + adc->data = device_get_match_data(adc->dev); + if (!adc->data) + adc->data = &adc5_gen3_data_pmic; + + device_for_each_child_node(adc->dev, child) { + ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child, adc->data); + if (ret < 0) { + fwnode_handle_put(child); + return ret; + } + + chan_props->chip = adc; + chan_props->scale_fn_type = + adc->data->adc_chans[chan_props->channel].scale_fn_type; + adc_chan = &adc->data->adc_chans[chan_props->channel]; + iio_chan->channel = V_CHAN(*chan_props); + iio_chan->info_mask_separate = adc_chan->info_mask; + iio_chan->type = adc_chan->type; + iio_chan->address = index; + iio_chan->indexed = 1; + iio_chan++; + chan_props++; + index++; + } + + return 0; +} + +static int adc5_gen3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct adc5_chip *adc; + struct regmap *regmap; + int ret, i; + u32 *reg; + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc = iio_priv(indio_dev); + adc->regmap = regmap; + adc->dev = dev; + + ret = device_property_count_u32(dev, "reg"); + if (ret < 0) + return ret; + + adc->num_sdams = ret; + + reg = kcalloc(adc->num_sdams, sizeof(u32), GFP_KERNEL); + if (!reg) + return -ENOMEM; + + ret = device_property_read_u32_array(dev, "reg", reg, adc->num_sdams); + if (ret) + return dev_err_probe(dev, ret, "Failed to read reg property, ret = %d\n", ret); + + adc->base = devm_kcalloc(dev, adc->num_sdams, sizeof(*adc->base), GFP_KERNEL); + if (!adc->base) + return -ENOMEM; + + platform_set_drvdata(pdev, indio_dev); + init_completion(&adc->complete); + mutex_init(&adc->lock); + + for (i = 0; i < adc->num_sdams; i++) { + adc->base[i].base_addr = reg[i]; + + adc->base[i].irq_name = devm_kasprintf(dev, GFP_KERNEL, "adc-sdam%d", i); + if (!adc->base[i].irq_name) { + kfree(reg); + ret = -ENOMEM; + goto err_irq; + } + + ret = platform_get_irq_byname(pdev, adc->base[i].irq_name); + if (ret < 0) { + kfree(reg); + dev_err(dev, "Getting IRQ %d by name failed, ret = %d\n", + adc->base[i].irq, ret); + goto err_irq; + } + adc->base[i].irq = ret; + + ret = request_irq(adc->base[i].irq, adc5_gen3_isr, 0, adc->base[i].irq_name, adc); + if (ret < 0) { + kfree(reg); + dev_err(dev, "Failed to request SDAM%d irq, ret = %d\n", i, ret); + goto err_irq; + } + } + kfree(reg); + + ret = devm_add_action(dev, adc5_gen3_disable, adc); + if (ret < 0) { + dev_err(dev, "failed to register adc disablement devm action, %d\n", ret); + goto err_irq; + } + + ret = adc5_get_fw_data(adc); + if (ret < 0) { + dev_err(dev, "adc get dt data failed, ret = %d\n", ret); + goto err_irq; + } + + ret = adc_tm_register_tzd(adc); + if (ret < 0) + goto err_irq; + + if (adc->n_tm_channels) + INIT_WORK(&adc->tm_handler_work, tm_handler_work); + + indio_dev->name = pdev->name; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &adc5_gen3_info; + indio_dev->channels = adc->iio_chans; + indio_dev->num_channels = adc->nchannels; + + ret = devm_iio_device_register(dev, indio_dev); + if (!ret) + return 0; + +err_irq: + for (i = 0; i < adc->num_sdams; i++) + free_irq(adc->base[i].irq, adc); + + return ret; +} + +static struct platform_driver adc5_gen3_driver = { + .driver = { + .name = "qcom-spmi-adc5-gen3", + .of_match_table = adc5_match_table, + }, + .probe = adc5_gen3_probe, +}; +module_platform_driver(adc5_gen3_driver); + +MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver"); +MODULE_LICENSE("GPL");