From patchwork Wed Jan 3 13:28:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiri Pirko X-Patchwork-Id: 13510063 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80311199D2 for ; Wed, 3 Jan 2024 13:28:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=resnulli.us Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=resnulli.us Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=resnulli-us.20230601.gappssmtp.com header.i=@resnulli-us.20230601.gappssmtp.com header.b="kmfhbBwF" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-40b5155e154so136021685e9.3 for ; Wed, 03 Jan 2024 05:28:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=resnulli-us.20230601.gappssmtp.com; s=20230601; t=1704288522; x=1704893322; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dap6YP8FIQk3TOWEEJscoCpH52lrE/wFjU07rsqJTV8=; b=kmfhbBwF2rGem22D2FogfSrK4J7aGn3VDDTurJH1baEKdeoZgz83ZLKvX9ctgEUOh6 NHronNvVbx1mpjVam0LdTs5JhQ7fhSAkXHhWR7XrziqK2j7qCZDsVdcr83kJsvrkuXbT SWWXY7DGHmX8iSvtSt1rnMWx0ij8rkDDVLbRNi1EWGGr28WX0eOWZYmaHG5RVkmI3Mxr GqoeRidKUTgO2S5uSy6Bb04+hLCUnFCnT3f2Ee+fetI/9lbmpKSVcCsdolmTyz1wt9cR tLpZT9DDC4q+zo8De/E8aWDrlwgmdLeMDJSrXn07tJtYLJKS/Bud3wHsfMHCtCAjmuVt 47dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704288522; x=1704893322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dap6YP8FIQk3TOWEEJscoCpH52lrE/wFjU07rsqJTV8=; b=pYmNQk1Gvkw6z1B+Ej0gapvP0wAPQWnQ+qNtaRjox9D0km3OVB4Lu1o2KvxpKCOrNN 8Bat0aXUF3pXQ0EYEH+BgdwrY5kJm8hGi1EtTEVfJFtPMPGfPtxjD+y/Y/wgwXEwiX7A 1QS+GIN7AC+ODMLHptsvTnTVenbCy1FqShKusD1UF872yvT1+GxFm1ENQwMhpSnxpyrr IxYrj2mte6YJS3yeUIi/jgFMYj6eCbOUbeG5shbjlCgc4d49ecx+/l8mX3UayOsKctI6 4eTTiHhf0BO02MDSl6oH9ezdmc8vt+V/GtortbcMKZI1Sy9Tlq7Z1Lw7H1Yc63f+wJrt PacQ== X-Gm-Message-State: AOJu0YwKw7Hz0aHkLE2wrIPDKAcgR4TUUJhmG54CPRE4mlwutPDaHCmM IDmc5bMRztpG1xW20XcYUoNs5jIqzKMqelKF1dtJIyDy0rYL+w== X-Google-Smtp-Source: AGHT+IHQBL/+29hcXddFkBV5iJ6OFr0SYO/Zw8sjNVTx3MM6TSJHQg/LyRThMXNcbd8aMe3+3rlPBA== X-Received: by 2002:a7b:c5cc:0:b0:40d:8fcd:319f with SMTP id n12-20020a7bc5cc000000b0040d8fcd319fmr574309wmk.218.1704288521635; Wed, 03 Jan 2024 05:28:41 -0800 (PST) Received: from localhost ([86.61.181.4]) by smtp.gmail.com with ESMTPSA id j7-20020a05600c190700b0040d5118e42esm2310279wmq.22.2024.01.03.05.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:28:41 -0800 (PST) From: Jiri Pirko To: netdev@vger.kernel.org Cc: kuba@kernel.org, pabeni@redhat.com, davem@davemloft.net, edumazet@google.com, vadim.fedorenko@linux.dev, arkadiusz.kubalewski@intel.com, saeedm@nvidia.com, leon@kernel.org, michal.michalik@intel.com, rrameshbabu@nvidia.com Subject: [patch net-next 1/3] dpll: expose fractional frequency offset value to user Date: Wed, 3 Jan 2024 14:28:36 +0100 Message-ID: <20240103132838.1501801-2-jiri@resnulli.us> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103132838.1501801-1-jiri@resnulli.us> References: <20240103132838.1501801-1-jiri@resnulli.us> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Jiri Pirko Add a new netlink attribute to expose fractional frequency offset value for a pin. Add an op to get the value from the driver. Signed-off-by: Jiri Pirko --- Documentation/netlink/specs/dpll.yaml | 11 +++++++++++ drivers/dpll/dpll_netlink.c | 24 ++++++++++++++++++++++++ include/linux/dpll.h | 3 +++ include/uapi/linux/dpll.h | 1 + 4 files changed, 39 insertions(+) diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml index cf8abe1c0550..b14aed18065f 100644 --- a/Documentation/netlink/specs/dpll.yaml +++ b/Documentation/netlink/specs/dpll.yaml @@ -296,6 +296,16 @@ attribute-sets: - name: phase-offset type: s64 + - + name: fractional-frequency-offset + type: sint + doc: | + The FFO (Fractional Frequency Offset) between the RX and TX + symbol rate on the media associated with the pin: + (rx_frequency-tx_frequency)/rx_frequency + Value is in PPM (parts per million). + This may be implemented for example for pin of type + PIN_TYPE_SYNCE_ETH_PORT. - name: pin-parent-device subset-of: pin @@ -460,6 +470,7 @@ operations: - phase-adjust-min - phase-adjust-max - phase-adjust + - fractional-frequency-offset dump: pre: dpll-lock-dumpit diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index 21c627e9401a..3370dbddb86b 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -263,6 +263,27 @@ dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, return 0; } +static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin, + struct dpll_pin_ref *ref, + struct netlink_ext_ack *extack) +{ + const struct dpll_pin_ops *ops = dpll_pin_ops(ref); + struct dpll_device *dpll = ref->dpll; + s64 ffo; + int ret; + + if (!ops->ffo_get) + return 0; + ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin), + dpll, dpll_priv(dpll), &ffo, extack); + if (ret) { + if (ret == -ENODATA) + return 0; + return ret; + } + return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, ffo); +} + static int dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin, struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) @@ -440,6 +461,9 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, prop->phase_range.max)) return -EMSGSIZE; ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack); + if (ret) + return ret; + ret = dpll_msg_add_ffo(msg, pin, ref, extack); if (ret) return ret; if (xa_empty(&pin->parent_refs)) diff --git a/include/linux/dpll.h b/include/linux/dpll.h index b1a5f9ca8ee5..9cf896ea1d41 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -77,6 +77,9 @@ struct dpll_pin_ops { const struct dpll_device *dpll, void *dpll_priv, const s32 phase_adjust, struct netlink_ext_ack *extack); + int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_device *dpll, void *dpll_priv, + s64 *ffo, struct netlink_ext_ack *extack); }; struct dpll_pin_frequency { diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h index 715a491d2727..b4e947f9bfbc 100644 --- a/include/uapi/linux/dpll.h +++ b/include/uapi/linux/dpll.h @@ -179,6 +179,7 @@ enum dpll_a_pin { DPLL_A_PIN_PHASE_ADJUST_MAX, DPLL_A_PIN_PHASE_ADJUST, DPLL_A_PIN_PHASE_OFFSET, + DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, __DPLL_A_PIN_MAX, DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1) From patchwork Wed Jan 3 13:28:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiri Pirko X-Patchwork-Id: 13510064 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A4A119BB9 for ; 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Wed, 03 Jan 2024 05:28:42 -0800 (PST) Received: from localhost ([86.61.181.4]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b0033725783839sm12581365wrr.110.2024.01.03.05.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:28:42 -0800 (PST) From: Jiri Pirko To: netdev@vger.kernel.org Cc: kuba@kernel.org, pabeni@redhat.com, davem@davemloft.net, edumazet@google.com, vadim.fedorenko@linux.dev, arkadiusz.kubalewski@intel.com, saeedm@nvidia.com, leon@kernel.org, michal.michalik@intel.com, rrameshbabu@nvidia.com Subject: [patch net-next 2/3] net/mlx5: DPLL, Use struct to get values from mlx5_dpll_synce_status_get() Date: Wed, 3 Jan 2024 14:28:37 +0100 Message-ID: <20240103132838.1501801-3-jiri@resnulli.us> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103132838.1501801-1-jiri@resnulli.us> References: <20240103132838.1501801-1-jiri@resnulli.us> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Jiri Pirko Instead of passing separate args, introduce struct mlx5_dpll_synce_status to hold the values obtained by mlx5_dpll_synce_status_get(). Signed-off-by: Jiri Pirko Reviewed-by: Arkadiusz Kubalewski --- .../net/ethernet/mellanox/mlx5/core/dpll.c | 63 +++++++++---------- 1 file changed, 28 insertions(+), 35 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c index a7ffd61fe248..dbe09d2f2069 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c @@ -36,11 +36,15 @@ static int mlx5_dpll_clock_id_get(struct mlx5_core_dev *mdev, u64 *clock_id) return 0; } +struct mlx5_dpll_synce_status { + enum mlx5_msees_admin_status admin_status; + enum mlx5_msees_oper_status oper_status; + bool ho_acq; +}; + static int mlx5_dpll_synce_status_get(struct mlx5_core_dev *mdev, - enum mlx5_msees_admin_status *admin_status, - enum mlx5_msees_oper_status *oper_status, - bool *ho_acq) + struct mlx5_dpll_synce_status *synce_status) { u32 out[MLX5_ST_SZ_DW(msees_reg)] = {}; u32 in[MLX5_ST_SZ_DW(msees_reg)] = {}; @@ -50,11 +54,9 @@ mlx5_dpll_synce_status_get(struct mlx5_core_dev *mdev, MLX5_REG_MSEES, 0, 0); if (err) return err; - if (admin_status) - *admin_status = MLX5_GET(msees_reg, out, admin_status); - *oper_status = MLX5_GET(msees_reg, out, oper_status); - if (ho_acq) - *ho_acq = MLX5_GET(msees_reg, out, ho_acq); + synce_status->admin_status = MLX5_GET(msees_reg, out, admin_status); + synce_status->oper_status = MLX5_GET(msees_reg, out, oper_status); + synce_status->ho_acq = MLX5_GET(msees_reg, out, ho_acq); return 0; } @@ -74,14 +76,14 @@ mlx5_dpll_synce_status_set(struct mlx5_core_dev *mdev, } static enum dpll_lock_status -mlx5_dpll_lock_status_get(enum mlx5_msees_oper_status oper_status, bool ho_acq) +mlx5_dpll_lock_status_get(struct mlx5_dpll_synce_status *synce_status) { - switch (oper_status) { + switch (synce_status->oper_status) { case MLX5_MSEES_OPER_STATUS_SELF_TRACK: fallthrough; case MLX5_MSEES_OPER_STATUS_OTHER_TRACK: - return ho_acq ? DPLL_LOCK_STATUS_LOCKED_HO_ACQ : - DPLL_LOCK_STATUS_LOCKED; + return synce_status->ho_acq ? DPLL_LOCK_STATUS_LOCKED_HO_ACQ : + DPLL_LOCK_STATUS_LOCKED; case MLX5_MSEES_OPER_STATUS_HOLDOVER: fallthrough; case MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER: @@ -92,12 +94,11 @@ mlx5_dpll_lock_status_get(enum mlx5_msees_oper_status oper_status, bool ho_acq) } static enum dpll_pin_state -mlx5_dpll_pin_state_get(enum mlx5_msees_admin_status admin_status, - enum mlx5_msees_oper_status oper_status) +mlx5_dpll_pin_state_get(struct mlx5_dpll_synce_status *synce_status) { - return (admin_status == MLX5_MSEES_ADMIN_STATUS_TRACK && - (oper_status == MLX5_MSEES_OPER_STATUS_SELF_TRACK || - oper_status == MLX5_MSEES_OPER_STATUS_OTHER_TRACK)) ? + return (synce_status->admin_status == MLX5_MSEES_ADMIN_STATUS_TRACK && + (synce_status->oper_status == MLX5_MSEES_OPER_STATUS_SELF_TRACK || + synce_status->oper_status == MLX5_MSEES_OPER_STATUS_OTHER_TRACK)) ? DPLL_PIN_STATE_CONNECTED : DPLL_PIN_STATE_DISCONNECTED; } @@ -106,17 +107,14 @@ static int mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, enum dpll_lock_status *status, struct netlink_ext_ack *extack) { - enum mlx5_msees_oper_status oper_status; + struct mlx5_dpll_synce_status synce_status; struct mlx5_dpll *mdpll = priv; - bool ho_acq; int err; - err = mlx5_dpll_synce_status_get(mdpll->mdev, NULL, - &oper_status, &ho_acq); + err = mlx5_dpll_synce_status_get(mdpll->mdev, &synce_status); if (err) return err; - - *status = mlx5_dpll_lock_status_get(oper_status, ho_acq); + *status = mlx5_dpll_lock_status_get(&synce_status); return 0; } @@ -151,16 +149,14 @@ static int mlx5_dpll_state_on_dpll_get(const struct dpll_pin *pin, enum dpll_pin_state *state, struct netlink_ext_ack *extack) { - enum mlx5_msees_admin_status admin_status; - enum mlx5_msees_oper_status oper_status; + struct mlx5_dpll_synce_status synce_status; struct mlx5_dpll *mdpll = pin_priv; int err; - err = mlx5_dpll_synce_status_get(mdpll->mdev, &admin_status, - &oper_status, NULL); + err = mlx5_dpll_synce_status_get(mdpll->mdev, &synce_status); if (err) return err; - *state = mlx5_dpll_pin_state_get(admin_status, oper_status); + *state = mlx5_dpll_pin_state_get(&synce_status); return 0; } @@ -202,19 +198,16 @@ static void mlx5_dpll_periodic_work(struct work_struct *work) { struct mlx5_dpll *mdpll = container_of(work, struct mlx5_dpll, work.work); - enum mlx5_msees_admin_status admin_status; - enum mlx5_msees_oper_status oper_status; + struct mlx5_dpll_synce_status synce_status; enum dpll_lock_status lock_status; enum dpll_pin_state pin_state; - bool ho_acq; int err; - err = mlx5_dpll_synce_status_get(mdpll->mdev, &admin_status, - &oper_status, &ho_acq); + err = mlx5_dpll_synce_status_get(mdpll->mdev, &synce_status); if (err) goto err_out; - lock_status = mlx5_dpll_lock_status_get(oper_status, ho_acq); - pin_state = mlx5_dpll_pin_state_get(admin_status, oper_status); + lock_status = mlx5_dpll_lock_status_get(&synce_status); + pin_state = mlx5_dpll_pin_state_get(&synce_status); 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Wed, 03 Jan 2024 05:28:43 -0800 (PST) From: Jiri Pirko To: netdev@vger.kernel.org Cc: kuba@kernel.org, pabeni@redhat.com, davem@davemloft.net, edumazet@google.com, vadim.fedorenko@linux.dev, arkadiusz.kubalewski@intel.com, saeedm@nvidia.com, leon@kernel.org, michal.michalik@intel.com, rrameshbabu@nvidia.com Subject: [patch net-next 3/3] net/mlx5: DPLL, Implement fractional frequency offset get pin op Date: Wed, 3 Jan 2024 14:28:38 +0100 Message-ID: <20240103132838.1501801-4-jiri@resnulli.us> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103132838.1501801-1-jiri@resnulli.us> References: <20240103132838.1501801-1-jiri@resnulli.us> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Jiri Pirko Implement ffo_get() pin op filling it up to MSEED.frequency_diff value. Signed-off-by: Jiri Pirko Reviewed-by: Arkadiusz Kubalewski --- .../net/ethernet/mellanox/mlx5/core/dpll.c | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c index dbe09d2f2069..18fed2b34fb1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c @@ -40,6 +40,8 @@ struct mlx5_dpll_synce_status { enum mlx5_msees_admin_status admin_status; enum mlx5_msees_oper_status oper_status; bool ho_acq; + bool oper_freq_measure; + s32 frequency_diff; }; static int @@ -57,6 +59,8 @@ mlx5_dpll_synce_status_get(struct mlx5_core_dev *mdev, synce_status->admin_status = MLX5_GET(msees_reg, out, admin_status); synce_status->oper_status = MLX5_GET(msees_reg, out, oper_status); synce_status->ho_acq = MLX5_GET(msees_reg, out, ho_acq); + synce_status->oper_freq_measure = MLX5_GET(msees_reg, out, oper_freq_measure); + synce_status->frequency_diff = MLX5_GET(msees_reg, out, frequency_diff); return 0; } @@ -69,8 +73,10 @@ mlx5_dpll_synce_status_set(struct mlx5_core_dev *mdev, MLX5_SET(msees_reg, in, field_select, MLX5_MSEES_FIELD_SELECT_ENABLE | + MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE | MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS); MLX5_SET(msees_reg, in, admin_status, admin_status); + MLX5_SET(msees_reg, in, admin_freq_measure, true); return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_MSEES, 0, 1); } @@ -102,6 +108,16 @@ mlx5_dpll_pin_state_get(struct mlx5_dpll_synce_status *synce_status) DPLL_PIN_STATE_CONNECTED : DPLL_PIN_STATE_DISCONNECTED; } +static int +mlx5_dpll_pin_ffo_get(struct mlx5_dpll_synce_status *synce_status, + s64 *ffo) +{ + if (!synce_status->oper_freq_measure) + return -ENODATA; + *ffo = synce_status->frequency_diff; + return 0; +} + static int mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, enum dpll_lock_status *status, @@ -175,10 +191,25 @@ static int mlx5_dpll_state_on_dpll_set(const struct dpll_pin *pin, MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING); } +static int mlx5_dpll_ffo_get(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_device *dpll, void *dpll_priv, + s64 *ffo, struct netlink_ext_ack *extack) +{ + struct mlx5_dpll_synce_status synce_status; + struct mlx5_dpll *mdpll = pin_priv; + int err; + + err = mlx5_dpll_synce_status_get(mdpll->mdev, &synce_status); + if (err) + return err; + return mlx5_dpll_pin_ffo_get(&synce_status, ffo); +} + static const struct dpll_pin_ops mlx5_dpll_pins_ops = { .direction_get = mlx5_dpll_pin_direction_get, .state_on_dpll_get = mlx5_dpll_state_on_dpll_get, .state_on_dpll_set = mlx5_dpll_state_on_dpll_set, + .ffo_get = mlx5_dpll_ffo_get, }; static const struct dpll_pin_properties mlx5_dpll_pin_properties = {