From patchwork Wed Jan 3 17:28:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13510257 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 427021C283; Wed, 3 Jan 2024 17:28:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mx0b-0016f401.pphosted.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="i176oH0k" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4037XSmF020422; Wed, 3 Jan 2024 09:28:13 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=1RB523u/YzFg6ojBTR5PfGAHwNn7BQfV7Lfr+ultk7I=; b=i17 6oH0kJS+QBk/IYvdI6lLLppu6PdLqitmuCX+X12PqRPgWcnYVsCxtYqv2XnwA3wL 9kYo8rxmTu6DB48s/693jywZCECOmqqU+nFnU+EvY2fEZqCPhHWEBxIei0mQfhYW U9XWFqaIz3k17t3PecfOOtxqDPIj1Fo7777h7hjmKMLH8NlbxJgf+V8o09pomkKR NG//MqKzQoGfpVj9QuSqUPLy2p4YaiL1DZ0SKz2rzfYkC2PnDzxeB2Aiq4Tzegb7 4hsYTBxNFDmJ1jGAFPRGNJ+FPJrIroG9857LJQbRjW0u/jOtoP015fLZYuZ7pnBm 5kXBzTzqH75hAxXH1rQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3vd39qadtu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 03 Jan 2024 09:28:13 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 3 Jan 2024 09:28:11 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 3 Jan 2024 09:28:11 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 29F705B6931; Wed, 3 Jan 2024 09:28:07 -0800 (PST) From: Elad Nachman To: , , , , , , , , , , , CC: Subject: [PATCH v2 1/2] dt-bindings: mmc: add Marvell ac5 Date: Wed, 3 Jan 2024 19:28:02 +0200 Message-ID: <20240103172803.1826113-2-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240103172803.1826113-1-enachman@marvell.com> References: <20240103172803.1826113-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NfWS2ua3aNYgD7XOY9qGhS1C9f2M5O7L X-Proofpoint-GUID: NfWS2ua3aNYgD7XOY9qGhS1C9f2M5O7L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 From: Elad Nachman Add dt bindings for Marvell AC5/X/IM eMMC controller. This compatibility string covers the differences in the AC5/X version of the driver: 31-bit bus limitation and DDR memory starting at address 0x2_0000_0000, which are handled by usage of a bounce buffer plus a different DMA mask. Signed-off-by: Elad Nachman Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/mmc/marvell,xenon-sdhci.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml index 3a8e74894ae0..cfe6237716f4 100644 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml @@ -27,7 +27,9 @@ properties: - marvell,armada-ap806-sdhci - items: - - const: marvell,armada-ap807-sdhci + - enum: + - marvell,armada-ap807-sdhci + - marvell,ac5-sdhci - const: marvell,armada-ap806-sdhci - items: From patchwork Wed Jan 3 17:28:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 13510259 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09ECF1C2BB; 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Wed, 03 Jan 2024 09:28:16 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 3 Jan 2024 09:28:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 3 Jan 2024 09:28:14 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id AA88F5B6933; Wed, 3 Jan 2024 09:28:11 -0800 (PST) From: Elad Nachman To: , , , , , , , , , , , CC: Subject: [PATCH v2 2/2] arm64: dts: ac5: add mmc node and clock Date: Wed, 3 Jan 2024 19:28:03 +0200 Message-ID: <20240103172803.1826113-3-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240103172803.1826113-1-enachman@marvell.com> References: <20240103172803.1826113-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RdWnCnkYxNb3y4FkkXMh44Hr1tz6OkzZ X-Proofpoint-GUID: RdWnCnkYxNb3y4FkkXMh44Hr1tz6OkzZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 From: Elad Nachman Add mmc and mmc clock nodes to ac5 and ac5x device tree files Signed-off-by: Elad Nachman --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 31 ++++++++++++++++++- .../boot/dts/marvell/ac5-98dx35xx-rd.dts | 4 +++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index b5e042b8e929..5591939e057b 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -77,7 +77,6 @@ soc { #address-cells = <2>; #size-cells = <2>; ranges; - dma-ranges; internal-regs@7f000000 { #address-cells = <1>; @@ -204,6 +203,30 @@ gpio1: gpio@18140 { }; }; + mmc_dma: bus@80500000 { + compatible = "simple-bus"; + ranges; + #address-cells = <0x2>; + #size-cells = <0x2>; + reg = <0x0 0x80500000 0x0 0x100000>; + dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>; + dma-coherent; + + sdhci: mmc@805c0000 { + compatible = "marvell,ac5-sdhci", + "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x1000>; + interrupts = ; + clocks = <&emmc_clock>, <&cnm_clock>; + clock-names = "core", "axi"; + bus-width = <8>; + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; + /* * Dedicated section for devices behind 32bit controllers so we * can configure specific DMA mapping for them @@ -335,5 +358,11 @@ nand_clock: nand-clock { #clock-cells = <0>; clock-frequency = <400000000>; }; + + emmc_clock: emmc-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; }; diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts index f0ebdb84eec9..0c973d7a215a 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts +++ b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts @@ -99,3 +99,7 @@ parition@2 { }; }; }; + +&sdhci { + status = "okay"; +};