From patchwork Wed Jan 3 17:33:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510280 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1EA01C683 for ; Wed, 3 Jan 2024 17:33:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qX1tkok3" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-40d88fff7faso24863265e9.3 for ; Wed, 03 Jan 2024 09:33:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303230; x=1704908030; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RdsiaowAjsV2VhJV7X+uJO6SS3PjKGOvNs318qpxEnc=; b=qX1tkok3vgn86PQmQrxENNozVJcbJAb3BiCFCYVMuIMzzueCIQbbiZc14cCnFOMMJp EMcxXzTGK/J19wGNc95b+t/20aIy75gGOc2r4d+5q7mwGr2Ms37+KUKjs+urB/Z0hGRj hxela+4+U+A2Gybw09VwXbyldbKNIBDSu7666iSbcilA10/1lo/2PtSwJoWuqxX3/jfm yxE6fEmtVvfYRup0lYl9E8AHCX1h98P/zuJ9GaVmIBmqlNZNjdFY1+mn79ZXavspYznH o5FFFZIZdW7YrfbcXYMdWfY3ho4dLuzPbTO5Kpy58AL0Fh0DdwtGVs1IEBCiizOtsP2Z 15/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303230; x=1704908030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RdsiaowAjsV2VhJV7X+uJO6SS3PjKGOvNs318qpxEnc=; b=lrqun1jxb0WW06cgdAX9LynHlpjz0hydXyabTvfEHTx9uCZSzHAeD1Hk8baKhDmLPI +U2O+aPxEmlE8vLEbkv7YZPW4zZO78/jVxxx06JshiE7ZSylL67lTdEjyN6NVnXmQ2Dn LVuGuoLgpLL3R0VW3TCFPdICSdn9/MqsIpjKJW9C3hu6BGiN3gZnfWhcbMKNw+VCIJW7 WOXOM34sxFJYXws/N4bJyXYfGRTx3w8V+jFpMpVigmWQZP5JKZNGbDPlEio7XZhFWP+A jXbGdKs8UfLCvCs+EK6+5XUKxEe4zp+GabHChKVbsmgkyiBv2HS18pL7Q2xVbARtk+Ke MDmg== X-Gm-Message-State: AOJu0YxlJFB2bwoUWpxRXPYILhDaOlh5CfXDnEthUEyr1ZHqUfmIVkUz be/sUG6uB+wz/AkkN418XsGNQ7hB5suo8A== X-Google-Smtp-Source: AGHT+IGeFbtzVvu3T8oVc1zHjuCDZo+RPaHsfV4kjVznDt57AzNWaYV+gZhSH5pdHVRgX2Ots1y9PA== X-Received: by 2002:a05:600c:491e:b0:40d:5c56:5545 with SMTP id f30-20020a05600c491e00b0040d5c565545mr3022779wmp.298.1704303230107; Wed, 03 Jan 2024 09:33:50 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id s7-20020a05600c45c700b0040d8d11bf63sm2903966wmo.41.2024.01.03.09.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:49 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 6A5105F92D; Wed, 3 Jan 2024 17:33:49 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 01/43] tests/avocado: Add a test for a little-endian microblaze machine Date: Wed, 3 Jan 2024 17:33:07 +0000 Message-Id: <20240103173349.398526-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thomas Huth We've already got a test for a big endian microblaze machine, but so far we lack one for a little endian machine. Now that the QEMU advent calendar featured such an image, we can test the little endian mode, too. Signed-off-by: Thomas Huth Message-Id: <20231215161851.71508-1-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/avocado/machine_microblaze.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/avocado/machine_microblaze.py b/tests/avocado/machine_microblaze.py index 8d0efff30d2..807709cd11e 100644 --- a/tests/avocado/machine_microblaze.py +++ b/tests/avocado/machine_microblaze.py @@ -5,6 +5,8 @@ # This work is licensed under the terms of the GNU GPL, version 2 or # later. See the COPYING file in the top-level directory. +import time +from avocado_qemu import exec_command, exec_command_and_wait_for_pattern from avocado_qemu import QemuSystemTest from avocado_qemu import wait_for_console_pattern from avocado.utils import archive @@ -33,3 +35,27 @@ def test_microblaze_s3adsp1800(self): # The kernel sometimes gets stuck after the "This architecture ..." # message, that's why we don't test for a later string here. This # needs some investigation by a microblaze wizard one day... + + def test_microblazeel_s3adsp1800(self): + """ + :avocado: tags=arch:microblazeel + :avocado: tags=machine:petalogix-s3adsp1800 + """ + + self.require_netdev('user') + tar_url = ('http://www.qemu-advent-calendar.org/2023/download/' + 'day13.tar.gz') + tar_hash = '6623d5fff5f84cfa8f34e286f32eff6a26546f44' + file_path = self.fetch_asset(tar_url, asset_hash=tar_hash) + archive.extract(file_path, self.workdir) + self.vm.set_console() + self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin') + self.vm.add_args('-nic', 'user,tftp=' + self.workdir + '/day13/') + self.vm.launch() + wait_for_console_pattern(self, 'QEMU Advent Calendar 2023') + time.sleep(0.1) + exec_command(self, 'root') + time.sleep(0.1) + exec_command_and_wait_for_pattern(self, + 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', + '821cd3cab8efd16ad6ee5acc3642a8ea') From patchwork Wed Jan 3 17:33:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510284 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C53DA1C68A for ; Wed, 3 Jan 2024 17:33:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mJrnuT8k" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40d88fff7faso24863605e9.3 for ; Wed, 03 Jan 2024 09:33:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303233; x=1704908033; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qzxoAeOdiga+52AiTCmsWe8ywFNoeoZ5ZVuxsnjrTLU=; b=mJrnuT8kkI3Mqqh7TGOrb8+QTRmXqdQoZnch6fQUIESDVnnLd4DQ7IqCeYJ1vAISXd LGSuSGi6yL94p1N61avZ3UlXD+cJsoBESUwz096wAC9n+EMpt+VYKlbRXOzYTDLRUouy iZHFEDeWhml7eQ6FkexbM3lFNqNqJ2kIrqDG0JfQTBzWf3/KGVztkJGP1fIz6VESgiYQ TE/Sj/QwXj3hkL1NvjsqMRDuwV6Iiu0EuCCuvRdWp+Irv0oq1RZUdMWtD8zI7+BS2TJr EketPcTQOZqdvnvhO8T3hIm8CnuLK/rojQb4JcjWLh7lYiqR1HCZdaltHdVNduJOvFm+ P75g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303233; x=1704908033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qzxoAeOdiga+52AiTCmsWe8ywFNoeoZ5ZVuxsnjrTLU=; b=Fy6ypTka6rVp2f9bozmOUYvNwFlTXzuyUtWdH/CCLCmgaq31S/GbnCbO6hJlQ2dCgd jKrEtbn1WsCBYgd9jSrjuRAuWtHUjZTvPWLH77hs2v46RcT4Fwqan8jyBUTXFCn51YjG 9ofaj9wgEeTjOk7A1XnjUcY3mGiS3Udv32Szc8bBJ4WEjAjtKJOL6mTaSJQ4P1/O52g9 F1KcWmOXKymSYIQ0/dFwTWeMjygvcU0ot5JzpJw8guwluxMOS0QTtGvE8q9iAcoyj7Zr x0GUPEa2iRjz1qxTl2rkuns766ACmahEealN0ATzvzfo8xqpm+t/x1ydR75VX7LrSxCi dVsw== X-Gm-Message-State: AOJu0YzcRpNC+2l5n4MfAIkVIi/Y0F1UCqPMStLSQKFW3+BNp8P9wJc1 KGzXerEzwNiC/L1xjLMn0lwszwKYPxTeJA== X-Google-Smtp-Source: AGHT+IGhE7/q82Jf4z4D1OPjoyeetuf4+aSfmg/R61bfYTK6tVdLZR8E2VO87yUiQHcrTBnDAn/iZg== X-Received: by 2002:a05:600c:a0b:b0:40d:7da9:8662 with SMTP id z11-20020a05600c0a0b00b0040d7da98662mr2292525wmp.338.1704303233122; Wed, 03 Jan 2024 09:33:53 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id t12-20020adfe10c000000b00336f43fa654sm18186652wrz.22.2024.01.03.09.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:50 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 7EB765F92F; Wed, 3 Jan 2024 17:33:49 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 02/43] tests/avocado: use snapshot=on in kvm_xen_guest Date: Wed, 3 Jan 2024 17:33:08 +0000 Message-Id: <20240103173349.398526-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This ensures the rootfs is never permanently changed as we don't need persistence between tests anyway. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- tests/avocado/kvm_xen_guest.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/avocado/kvm_xen_guest.py b/tests/avocado/kvm_xen_guest.py index 5391283113e..f8cb458d5db 100644 --- a/tests/avocado/kvm_xen_guest.py +++ b/tests/avocado/kvm_xen_guest.py @@ -59,7 +59,7 @@ def common_vm_setup(self): def run_and_check(self): self.vm.add_args('-kernel', self.kernel_path, '-append', self.kernel_params, - '-drive', f"file={self.rootfs},if=none,format=raw,id=drv0", + '-drive', f"file={self.rootfs},if=none,snapshot=on,format=raw,id=drv0", '-device', 'xen-disk,drive=drv0,vdev=xvda', '-device', 'virtio-net-pci,netdev=unet', '-netdev', 'user,id=unet,hostfwd=:127.0.0.1:0-:22') From patchwork Wed Jan 3 17:33:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510282 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2251C1C290 for ; Wed, 3 Jan 2024 17:33:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="y31RNpyp" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40d88fff7faso24863385e9.3 for ; Wed, 03 Jan 2024 09:33:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303231; x=1704908031; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Aeln3++ASlFUfIwMVf5xyvW2uMLaZ4UxQn5nypBC6DU=; b=y31RNpypWJP08QG+PkfIA/wPXjF6/zGo9ihFLyKM/FNUhnErwB1Gd1QBGBRVIRssnj PysWeoBI0AgPjP+Z2cTV3ouNmqMyOEzcKCG37e6zi5o9nfXQ/QNLwo9KyNf+GmlWNvVH B2LmGZPl3taJTXUlYxAe7UdzdraoOGLe7H9vF230u4Dcpsdv5/Z8jqEAkAO9rxBJJI7j Rx8rgC9DTV3M0mVRUJ8JzrIJUX7jeTJJCJF8exlffj4iwvqtg0+4dR3DnR8Elzbl/MiN CvjX4HsboeWB485dffTObwHYFOfVP9l/+ZqPEcix9o4PcMiST6AvFyU1TImMtNTI8ZpY bpQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303231; x=1704908031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Aeln3++ASlFUfIwMVf5xyvW2uMLaZ4UxQn5nypBC6DU=; b=GKXl2kf/4wsRsQXZlg55Trawnj/JzHj25xH+NmPehha4H82C15G6NhnMxF+mNKqmBU XYctlK/KmrCVF30EoPAJu2iwaT+GqpGxQcri355xhS2MJFLfSA7tyYrXD7WBLOCBybTI vCzu6N3SVEjgbJB9AWN7dU+vhbDf6u3Oz3Ip5qhdd80kUlb8G7+4CNWIL2tRLza+I0wK N9Ubt+DgAlOOXJhV1u61UMfVwdXc9UTYIb6g5WzTwJj4rnj4J1tlKUz/ZbB12x7aH9fk rolaQB5n8T5kiRqj/wJuMaGDDaSLiFoaTZgcvQGKuWuBiSt1bbaaJgybmLhXB1eOyF9l n5EA== X-Gm-Message-State: AOJu0YzzU/pjZjrIlyunaqFnfZEToc0sqNArVz3aY2jVBJgZ2x26j1/Y ii6neB/Qv8cxMi2atweI70IFRyfohrSsWQ== X-Google-Smtp-Source: AGHT+IHtCR4hmp3Vukr9hzN46Gz71ep8bM3kzLyD4gCRhfkpq3Ia3b7dQ3Ru8mfmCaqnt5tCeWxVgQ== X-Received: by 2002:a05:600c:68d7:b0:40d:5941:f16a with SMTP id jd23-20020a05600c68d700b0040d5941f16amr3530996wmb.273.1704303231484; Wed, 03 Jan 2024 09:33:51 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id je2-20020a05600c1f8200b0040d934f48d3sm750166wmb.32.2024.01.03.09.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:50 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 93F3B5F932; Wed, 3 Jan 2024 17:33:49 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 03/43] gitlab: include microblazeel in testing Date: Wed, 3 Jan 2024 17:33:09 +0000 Message-Id: <20240103173349.398526-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This reverts aeb5f8f248e (gitlab: build the correct microblaze target) now we actually have a little-endian test in avocado thanks to this years advent calendar. Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth --- .gitlab-ci.d/buildtest.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 91663946de4..ef71dfe8665 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -41,7 +41,7 @@ build-system-ubuntu: variables: IMAGE: ubuntu2204 CONFIGURE_ARGS: --enable-docs - TARGETS: alpha-softmmu microblaze-softmmu mips64el-softmmu + TARGETS: alpha-softmmu microblazeel-softmmu mips64el-softmmu MAKE_CHECK_ARGS: check-build check-system-ubuntu: @@ -61,7 +61,7 @@ avocado-system-ubuntu: variables: IMAGE: ubuntu2204 MAKE_CHECK_ARGS: check-avocado - AVOCADO_TAGS: arch:alpha arch:microblaze arch:mips64el + AVOCADO_TAGS: arch:alpha arch:microblazeel arch:mips64el build-system-debian: extends: From patchwork Wed Jan 3 17:33:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510283 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 394141C293 for ; Wed, 3 Jan 2024 17:33:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CLKRlSit" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40d2376db79so95776635e9.0 for ; Wed, 03 Jan 2024 09:33:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303231; x=1704908031; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rOpjk5Xc89URXPry+uTcPrYjjlL9ZRbEnDqtNUUFVo4=; b=CLKRlSit49QwMjia8A9mQ/z1sP8zRCuWmyw30fJCvmdr59rEHCmgPkjkCE0rbSIEHM +fLvzkO1T8UQuCCuZKizDam0ILN0S3cJCi4msYPy1aeKarLOR2PtvMsyIluy31SzIjFe ksOztKdcWxPA/cWHP3DSGoswgPM8+Mm3bZVk4dUtcu+9PLZrChIzIUpDw+jlrdYxVUvm 1KIvVwBuPvytb+jLqSm+2evH/ohxlED0NrIs2OkvbYWLW8T0pEQtewpkXvAXmPVM+dXD 7EStLARuUrud2xWqttJhZ3gP+Q2yVTEK7qJ0Alx52sLAMeT2RoBxszthwcqU9K2daoUT qngg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303231; x=1704908031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rOpjk5Xc89URXPry+uTcPrYjjlL9ZRbEnDqtNUUFVo4=; b=NF4ZQ7rCA33JdA780k7FerIdr4vyzTUx0JDNAmjLi73zIeFgn86tSTOInL4x+4Nt6m /dsipnNrCimO11E9lgjemnL+1o6opgJf7ZQpsvk3vMX1IG2GGWAm2zEE0phK0IdHMRrg 2rxd9eji1ovSnjfYwdDsjeIwnGrNLc6YSmXwoXi/hjb0YN1p8JxvWmXiAR4YRoXcSxVQ GBJbReitKarfPqSf/0wnaMtSceiBnlQroyVyzP+likqlvc/A5D6C9amu50VuR2/c18U1 A/HYcwLGmrVygXaAcDsWAyoBAih+QFccdkeQ3uKkxDEBjlXxY5a8Naq77bObZYB7Voq3 OYAA== X-Gm-Message-State: AOJu0YwkNfncfLE5S+AsNJsF5LN46B7Wn78STxGKrfjOKBblR8wVaxsF nU6v1C0S0NjopK/O+SS8EfCyQSNv4rJ8eg== X-Google-Smtp-Source: AGHT+IEhbukIbMJxe0XeRt2lHobV2JbuWL9JZcjldNC8OY0732Jbqq6ubAvn3PMQTDTFrXUf5ogLhA== X-Received: by 2002:a05:600c:a003:b0:404:4b6f:d70d with SMTP id jg3-20020a05600ca00300b004044b6fd70dmr11754074wmb.17.1704303231383; Wed, 03 Jan 2024 09:33:51 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id fl27-20020a05600c0b9b00b0040d2dfb10e0sm2979265wmb.11.2024.01.03.09.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:50 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id AB9515F933; Wed, 3 Jan 2024 17:33:49 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 04/43] chardev: use bool for fe_is_open Date: Wed, 3 Jan 2024 17:33:10 +0000 Message-Id: <20240103173349.398526-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The function qemu_chr_fe_init already treats be->fe_open as a bool and if it acts like a bool it should be one. While we are at it make the variable name more descriptive and add kdoc decorations. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Message-Id: <20231211145959.93759-1-alex.bennee@linaro.org> --- v2 - rename to fe_is_open at f4bug's request --- include/chardev/char-fe.h | 19 ++++++++++++------- chardev/char-fe.c | 16 ++++++++-------- chardev/char.c | 2 +- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h index 0ff6f875116..ecef1828355 100644 --- a/include/chardev/char-fe.h +++ b/include/chardev/char-fe.h @@ -7,8 +7,12 @@ typedef void IOEventHandler(void *opaque, QEMUChrEvent event); typedef int BackendChangeHandler(void *opaque); -/* This is the backend as seen by frontend, the actual backend is - * Chardev */ +/** + * struct CharBackend - back end as seen by front end + * @fe_is_open: the front end is ready for IO + * + * The actual backend is Chardev + */ struct CharBackend { Chardev *chr; IOEventHandler *chr_event; @@ -17,7 +21,7 @@ struct CharBackend { BackendChangeHandler *chr_be_change; void *opaque; int tag; - int fe_open; + bool fe_is_open; }; /** @@ -156,12 +160,13 @@ void qemu_chr_fe_set_echo(CharBackend *be, bool echo); /** * qemu_chr_fe_set_open: + * @be: a CharBackend + * @is_open: the front end open status * - * Set character frontend open status. This is an indication that the - * front end is ready (or not) to begin doing I/O. - * Without associated Chardev, do nothing. + * This is an indication that the front end is ready (or not) to begin + * doing I/O. Without associated Chardev, do nothing. */ -void qemu_chr_fe_set_open(CharBackend *be, int fe_open); +void qemu_chr_fe_set_open(CharBackend *be, bool is_open); /** * qemu_chr_fe_printf: diff --git a/chardev/char-fe.c b/chardev/char-fe.c index 7789f7be9c8..20222a4cad5 100644 --- a/chardev/char-fe.c +++ b/chardev/char-fe.c @@ -211,7 +211,7 @@ bool qemu_chr_fe_init(CharBackend *b, Chardev *s, Error **errp) } } - b->fe_open = false; + b->fe_is_open = false; b->tag = tag; b->chr = s; return true; @@ -257,7 +257,7 @@ void qemu_chr_fe_set_handlers_full(CharBackend *b, bool sync_state) { Chardev *s; - int fe_open; + bool fe_open; s = b->chr; if (!s) { @@ -265,10 +265,10 @@ void qemu_chr_fe_set_handlers_full(CharBackend *b, } if (!opaque && !fd_can_read && !fd_read && !fd_event) { - fe_open = 0; + fe_open = false; remove_fd_in_watch(s); } else { - fe_open = 1; + fe_open = true; } b->chr_can_read = fd_can_read; b->chr_read = fd_read; @@ -336,7 +336,7 @@ void qemu_chr_fe_set_echo(CharBackend *be, bool echo) } } -void qemu_chr_fe_set_open(CharBackend *be, int fe_open) +void qemu_chr_fe_set_open(CharBackend *be, bool is_open) { Chardev *chr = be->chr; @@ -344,12 +344,12 @@ void qemu_chr_fe_set_open(CharBackend *be, int fe_open) return; } - if (be->fe_open == fe_open) { + if (be->fe_is_open == is_open) { return; } - be->fe_open = fe_open; + be->fe_is_open = is_open; if (CHARDEV_GET_CLASS(chr)->chr_set_fe_open) { - CHARDEV_GET_CLASS(chr)->chr_set_fe_open(chr, fe_open); + CHARDEV_GET_CLASS(chr)->chr_set_fe_open(chr, is_open); } } diff --git a/chardev/char.c b/chardev/char.c index 996a024c7a2..0653b112e92 100644 --- a/chardev/char.c +++ b/chardev/char.c @@ -750,7 +750,7 @@ static int qmp_query_chardev_foreach(Object *obj, void *data) value->label = g_strdup(chr->label); value->filename = g_strdup(chr->filename); - value->frontend_open = chr->be && chr->be->fe_open; + value->frontend_open = chr->be && chr->be->fe_is_open; QAPI_LIST_PREPEND(*list, value); From patchwork Wed Jan 3 17:33:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510286 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B0581C6B7 for ; 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Wed, 03 Jan 2024 09:33:53 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id C17AE5F936; Wed, 3 Jan 2024 17:33:49 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 05/43] qtest: bump min meson timeout to 60 seconds Date: Wed, 3 Jan 2024 17:33:11 +0000 Message-Id: <20240103173349.398526-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé Even some of the relatively fast qtests can sometimes hit the 30 second timeout in GitLab CI under high parallelism/load conditions. Bump the min to 60 seconds to give a higher margin for reliability. Reviewed-by: Thomas Huth Signed-off-by: Daniel P. Berrangé Message-ID: <20230717182859.707658-2-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-2-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 47dabf91d04..366872ed57b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,12 +1,7 @@ slow_qtests = { - 'ahci-test' : 60, 'bios-tables-test' : 120, - 'boot-serial-test' : 60, 'migration-test' : 150, 'npcm7xx_pwm-test': 150, - 'prom-env-test' : 60, - 'pxe-test' : 60, - 'qos-test' : 60, 'qom-test' : 300, 'test-hmp' : 120, } @@ -383,8 +378,8 @@ foreach dir : target_dirs env: qtest_env, args: ['--tap', '-k'], protocol: 'tap', - timeout: slow_qtests.get(test, 30), - priority: slow_qtests.get(test, 30), + timeout: slow_qtests.get(test, 60), + priority: slow_qtests.get(test, 60), suite: ['qtest', 'qtest-' + target_base]) endforeach endforeach From patchwork Wed Jan 3 17:33:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510285 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC53C1C6B2 for ; Wed, 3 Jan 2024 17:33:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="q63U7bX0" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40d894764e7so25059315e9.1 for ; Wed, 03 Jan 2024 09:33:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303234; x=1704908034; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W+Zw2YkajEPYChe7VczIaT3yCibcEp4TlrDptH8Gvrw=; b=q63U7bX0pO9dODjE54bqH3BX49x7hecNLyfhTI+8NzJ3KAaEgE0nDEjMNzAhMSRwdq aRew/92c9YXq6bUXBPjaqREfVaQ48Qruq6MI/hT3t3MAu6NK9Dwt+hiY248ZqXuGM1y1 KttyMJnX3/1WAbjQMqnv/ZJaefoDzcb1j6WtPvf/5JMc6cwclsjjl55wdqKNASaOQY2A 1+I/6SJ1Z9mtIUqZPvZXWEKkQGAG89DidAQbDvmuxNyO5f74FUxkalzoFer2HOMtDCjr Eza5vvn5mpoQltRSpFI8/Q+2TtQPn8ur4w5Z+5aVrlFSp2XrzbPcG2J2T26j5gq+crR+ Cmyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303234; x=1704908034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W+Zw2YkajEPYChe7VczIaT3yCibcEp4TlrDptH8Gvrw=; b=lMpPqQi2EeXWlNnQf65217atHhtcSmdidnNfceW45UakENnXzJWYvZNj9VwDo+qLJ3 EWyl3QB1nVYVoRRgJMStx4nogRuXudiJd2J9CPOo2WaqPYFOmRM7jgXYqNtDFDS0deV4 7UHvZGVom13MTC/4GLak5e7uGaP6sSv6pHUJjEAT+He/Zl+t9P83qUINQ8E76jMdTdGO aW4pVd2VOVSxd+eamvET/yH2im/zXTQ+HptSrG4pmMDcF+dm4luMK/M+RVHKV3YOS2+F wPgUbXdttBSVDojUzQeHB3VjSnkOgd0TA0+IQy0pq1m7s1q5456N8cJ6zAt1ELXlcbf1 MoEA== X-Gm-Message-State: AOJu0YyDtCWihS2VtfsPAeKuiW0ijwmAMKttF6W1ge/CZtjTlLpmX3MF BNWwIWq5wfbrM5IIfcXHRrJzeX0JeiiKhA== X-Google-Smtp-Source: AGHT+IHJAM/Ysaat03yPO0/Jg6Y5f2vvi2xxZpKY9OBoQnPldlvT9O3mxmIliH0RHJ++gB0qw/aiPw== X-Received: by 2002:a05:600c:511e:b0:40b:3e23:f0a0 with SMTP id o30-20020a05600c511e00b0040b3e23f0a0mr6942090wms.4.1704303234129; Wed, 03 Jan 2024 09:33:54 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id h15-20020a05600c350f00b0040d8810efc9sm2942787wmq.17.2024.01.03.09.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:53 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id D8B9B5F93B; Wed, 3 Jan 2024 17:33:49 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 06/43] qtest: bump migration-test timeout to 8 minutes Date: Wed, 3 Jan 2024 17:33:12 +0000 Message-Id: <20240103173349.398526-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The migration test should take between 1 min 30 and 2 mins on reasonably modern hardware. The test is not especially compute bound, rather its running time is dominated by the guest RAM size relative to the bandwidth cap, which forces each iteration to take at least 30 seconds. None the less under high load conditions with multiple QEMU processes spawned and competing with other parallel tests, the worst case running time might be somewhat extended. Bumping the timeout to 8 minutes gives us good headroom, while still catching stuck tests relatively quickly. Reviewed-by: Thomas Huth Signed-off-by: Daniel P. Berrangé Message-ID: <20230717182859.707658-3-berrange@redhat.com> [thuth: Bump timeout to 8 minutes to make it work on very loaded systems, too] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-3-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 366872ed57b..f184d051cfe 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,6 +1,6 @@ slow_qtests = { 'bios-tables-test' : 120, - 'migration-test' : 150, + 'migration-test' : 480, 'npcm7xx_pwm-test': 150, 'qom-test' : 300, 'test-hmp' : 120, From patchwork Wed Jan 3 17:33:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510287 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14C7C1CA90 for ; Wed, 3 Jan 2024 17:33:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ipbHbZwg" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-40d6b4e2945so55473045e9.0 for ; Wed, 03 Jan 2024 09:33:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303236; x=1704908036; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0SGlJ3OP3ZQJqIGzbf9sUE9qzVbTUWx7/uZllqYVPY0=; b=ipbHbZwgV1mLxWcQQA1pszOh3n7x9Dgd7H2kDNTeOhKm0MoEKShetnz3T0xXHKq9HI 3QAnIKo0h2VFUmmKwkxyUwYiX383QGqOBQa+H2MCu8Ky/Z5nOsBfY1vDDl+B8OTwTycs OKQLxJ5yYA8VVKzk8NyfPydEuMMWFzeWVZkLAN4ddPPgaOQPlzjj6OXADoTlf5VuBu6V Aah8Ar1YwjGa/DJMisjX9dWzOqsq0xsKns9bm9PZkZPmaVIZEHVDrViT/fn8lh3xJPip JbUGmY31cT39iVsPpLhhw9Or7fFxoKqhFk52erWSwBNkHiEu9grXSOGCb5CarZFxGD2b qq4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303236; x=1704908036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0SGlJ3OP3ZQJqIGzbf9sUE9qzVbTUWx7/uZllqYVPY0=; b=FiUpGTssLoE0oIyRmCdDfv4ctqnkwqzb7UIAdRsZ39kAI4du08DXxBSk439PvZVrMO cOqsAo8hT05J2Beh68uPw/y5cL5jU47c2epMNKdUF3d7NKGL2WgOndFBze8XyojnzPIj yaDi4zyL9tTRx30FR6dTjXs9pvDA3BjjftfkMrB+yxMgiSH+mqtKb2aD50xXxKPyasCN 2VDAP3tzRS1tpTvvU81u1dIKz2p8auvgfKnF0VHN82qs+YlltoLpV5ASTZAsVXx/2DFg PDaAYX6qt5Y6kHMNny7QrvtRFurIhTIFuNlGh1uIt3fhHazk8ooHa93CNjIBvnr43lZW RJEA== X-Gm-Message-State: AOJu0YxYCe83sHgXgLvJkFY2Ix6GooaZYq6i/+RA13uyNZH9plV9AlyU 36rWDyVUdFdQo9XwGNAF8AhqT2zX0O6n2w== X-Google-Smtp-Source: AGHT+IE/yZXkFHwcBc8Q8LFh0vqAOsE9eHgOShAhsrYooeQcfIWldwg750GrqHy32Q3/sZAOkr4FZQ== X-Received: by 2002:a05:600c:4e94:b0:40d:5f50:1268 with SMTP id f20-20020a05600c4e9400b0040d5f501268mr3399125wmq.230.1704303236202; Wed, 03 Jan 2024 09:33:56 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id r10-20020adfce8a000000b00336781490dcsm31126317wrn.69.2024.01.03.09.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:53 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id EF0895F93C; Wed, 3 Jan 2024 17:33:49 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 07/43] qtest: bump qom-test timeout to 15 minutes Date: Wed, 3 Jan 2024 17:33:13 +0000 Message-Id: <20240103173349.398526-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The qom-test is periodically hitting the 5 minute timeout when running on the aarch64 emulator under GitLab CI. With an --enable-debug build it can take over 10 minutes for arm/aarch64 targets. Setting timeout to 15 minutes gives enough headroom to hopefully make it reliable. Reviewed-by: Thomas Huth Signed-off-by: Daniel P. Berrangé Message-ID: <20230717182859.707658-4-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-4-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index f184d051cfe..000ac54b7d6 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -2,7 +2,7 @@ slow_qtests = { 'bios-tables-test' : 120, 'migration-test' : 480, 'npcm7xx_pwm-test': 150, - 'qom-test' : 300, + 'qom-test' : 900, 'test-hmp' : 120, } From patchwork Wed Jan 3 17:33:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510288 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B59D1CAA3 for ; Wed, 3 Jan 2024 17:33:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aPdrhcXo" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40d604b4b30so4332725e9.1 for ; Wed, 03 Jan 2024 09:33:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303236; x=1704908036; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CaH8a0Z2sktOk6HhcvLcaTrwfzviKqp7ItoU8rNpnow=; b=aPdrhcXoSVQyZg84OswK+WZCrAG7S3VuL1pXxz3q3gnrMi2aotoL/1Kfc6o0rdoXIO LM3Kyq91myZHEb4SgsIhats3WSV4mu1vLQsjynxbUCZJdx32y4HmL+junQBPaeE+b6oc B1M5EbiUb8N+gVz8HnJBB3KiZG2LwCWzcsX3mf5m//I8lRetWAclt4iqyrn8QYG6SMxR L8ETSOZj7CbtQEUZeIFQfzlf6/CVeXcbetWnEqb3Pmr0LXX/HtLNLsmK7hpZ+x4SKVO6 4k56y4XfwkxgWTCyAZzF4fkYSe0NskFtCoxnbJeWi+22nDf4d4gYW/EFVv6XA6s6oeya YhyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303236; x=1704908036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CaH8a0Z2sktOk6HhcvLcaTrwfzviKqp7ItoU8rNpnow=; b=q5p+649s/eIuaHf9fqL6/1mlGauRMEThlDHijofhP+Iy/jQoB+5AvfwZ/XMIyIz8Mr t15m2TZVOxTLmow7kn4KQu6lfaMXMoo/L38dykqoRdw9Uv6SaCPIq1H418L4tYXuoH2T bZTwr7NFazDUUaHSj+Tul88Yet8nrOCN+BV7SL5TW+X6IE5jSBYI1NyPPEWxJnQUuVup hQdhBdTg11oNG9WrPtflthFbGzCH62k/QgQNIrLw2Ltgul6chJL9vnpAipcwmsMddX9x plgzC0JX+fHfNXw4amNrUU5PARrpRQiNVg9FZZZiTDPlquLftzaNtj87ejtUVjOrGcqj tjzw== X-Gm-Message-State: AOJu0Yxm7wJMMoBXCTU+Q9saozBjFGGsXzFqy9XttcR4arZ1QSwh/dSO c9P/lwhMGtWWm/DaPe3du/dFbPP7X7Q9tQ== X-Google-Smtp-Source: AGHT+IFPEa4trSH1ULMWjrm1Nbo4OaNZJ4jxlMnYzVLmqTz4UW2OpRVflauqqVvOixkorfcQpuqmAQ== X-Received: by 2002:a7b:c406:0:b0:40d:77d3:8db8 with SMTP id k6-20020a7bc406000000b0040d77d38db8mr778947wmi.44.1704303236439; Wed, 03 Jan 2024 09:33:56 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id bg35-20020a05600c3ca300b0040d6ffae526sm2963001wmb.39.2024.01.03.09.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:53 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 1199A5F93E; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 08/43] qtest: bump npcm7xx_pwn-test timeout to 5 minutes Date: Wed, 3 Jan 2024 17:33:14 +0000 Message-Id: <20240103173349.398526-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The npcm7xx_pwn-test takes 3 & 1/2 minutes in a --enable-debug build. Bumping to 5 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé Reviewed-by: Thomas Huth Message-ID: <20230717182859.707658-5-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-5-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 000ac54b7d6..84cec0a847d 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,7 +1,7 @@ slow_qtests = { 'bios-tables-test' : 120, 'migration-test' : 480, - 'npcm7xx_pwm-test': 150, + 'npcm7xx_pwm-test': 300, 'qom-test' : 900, 'test-hmp' : 120, } From patchwork Wed Jan 3 17:33:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510289 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D02D1CAA8 for ; Wed, 3 Jan 2024 17:33:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="kQhqKTsu" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-40d3352b525so116667405e9.1 for ; Wed, 03 Jan 2024 09:33:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303237; x=1704908037; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c7IelmqBfCUiQPJ1PO4YXHkz0msSivdOvYJRQon3tbw=; b=kQhqKTsuxyTJ0vorc5wdhXz8ANjWrkWcA0KloBcoxwBDvSg5voRtaqT2B4e11MIswZ t+OHy/t+/zmt1f3kFLkcMcOzLJiL6RRteH0U4RCahqr5tnFRJfRnxRUujOvGh3t7aunT Fg+B1A6GJ6B2+CQx0vcwSWJWQ77YX1sIJdOXS2YILnp+I4jH9bBcnD6DzC4cmIgQgkPs X5ns+9g6NvQiCmB86QjjHIRg2sXIeyVc6VSL1OjI2HjeM2N09wEH16KO9TbP5T2TxARG /UrK+Z1+uyPKv5FP9r0TXcwB22jTZK58yff62FxDpL/BZtSQLvpTXqkdevTAHIy3qX6v hM8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303237; x=1704908037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c7IelmqBfCUiQPJ1PO4YXHkz0msSivdOvYJRQon3tbw=; b=gys7X4UzyWM7wmYlqq+7sKehq2O78LPXQ8XtM90nvGg1l6mhEpYwD2unrT/hHlYPVN 70/cJlPGHk6TYca3l0I+PRjiCzCCYrlWTq5rg0B05veSeBLPMN2DskjSNunipeW5H9hl K6cGoLce0sSYg/COiecEo50w3aBTgyHmpnnaAt3INIqrTRkpixTAfFVuabAFXt+duX5l yZ9V8fzLIeIP2aAHuu+IyEuPsXToDf+PjQ7kS91GqufqLlZ9qeLVOEiRW1O3jsOiUjF6 0rwuPUoBdc2WxJbii2iIjZ0z4lF5UMsVuKUBfldS8Mu3Wgi5NWbuYd3eW7PGEhQ+eR8y ptVA== X-Gm-Message-State: AOJu0Yx5Lh5WHpm6dgtkkaIYiiQKJifr3IeSbMv5WEP+w39OlUCFtn4u PByz+hpVIOYhkpGnlWfWPi1w+/2fyWRTcA== X-Google-Smtp-Source: AGHT+IESFF9+b5o3/ublAo/jcBFbD7HOqmfsD+g0Mklv3iiREEvayIPCsKKh6n9Wfcqv3HzjL9ElUA== X-Received: by 2002:adf:e8c2:0:b0:337:5131:4d71 with SMTP id k2-20020adfe8c2000000b0033751314d71mr1857wrn.40.1704303237615; Wed, 03 Jan 2024 09:33:57 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id t18-20020a5d4612000000b003367bb8898dsm31262714wrq.66.2024.01.03.09.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:54 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 26B495F93F; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 09/43] qtest: bump test-hmp timeout to 4 minutes Date: Wed, 3 Jan 2024 17:33:15 +0000 Message-Id: <20240103173349.398526-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The hmp test takes just under 3 minutes in a --enable-debug build. Bumping to 4 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé Reviewed-by: Thomas Huth Message-ID: <20230717182859.707658-6-berrange@redhat.com> [thuth: fix copy-n-paste error in the description] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-6-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 84cec0a847d..7a4160df046 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -3,7 +3,7 @@ slow_qtests = { 'migration-test' : 480, 'npcm7xx_pwm-test': 300, 'qom-test' : 900, - 'test-hmp' : 120, + 'test-hmp' : 240, } qtests_generic = [ From patchwork Wed Jan 3 17:33:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510290 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A52341CAAE for ; Wed, 3 Jan 2024 17:34:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SdQQrAk8" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-33678156e27so9773264f8f.1 for ; Wed, 03 Jan 2024 09:34:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303239; x=1704908039; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KQu3dEC4bAAkAiF4vI+JksTKEdmVPQCRZYwFmghpZj8=; b=SdQQrAk81xNDYpRJiLZ2KNtqnwH6zqF3bM9KYU0wbhSs+hevqCAw02LVlnCXdrgsGI zrUbxJC6/WZEsaGINsuBUsoltTYvpC+35+WRsSSnAWtKlbUUH2EiA1AJCx11NjOtALhd pf5kso3Y7Q+xQx5YlJ4JfdviyfK5Oadu+kwuvKm8sQommkl85TE1LNjPywMVkb34uWr2 AbhMW5ZVul+eAkhUPOm8AzDy6SPZMP0f33ntl+z4Ydtf31xmIPNb3qWWVq4QATTYByGm iZZkDiRUps9suMU9hFLCIsaXquwtQDfyS1adVzJLqKHiz6GB2FgqPFUEirZ4Yi1EChcf eMsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303239; x=1704908039; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KQu3dEC4bAAkAiF4vI+JksTKEdmVPQCRZYwFmghpZj8=; b=j6kZZ6XUqx33EcWrI6uprz99LgzDFKm3UaGQVJj7zF+D5azrK8AEdNQFoNCV5MpYeR XhT7zW9LqDPDoVdmTcUskZ/fl8DwKpzZn7SEIMfElbEB52YpMxSTyb2gRf/Ec/TGERCK EqveQKq4zoR5eNTdcFm6c9gCHBUDVOkt/un53N50VCgEKGkD75kQ5/2TMwPMXvYP4Q43 RH6MzpKK/RQLzVGCLXaxqVYioKKVYb0HctdEz6bOrbcNg6NeDOzzToBTE2HFlmd7x+b7 psW+GstxSdIVEfcpFcRCuV21mAnXXqTJjukAG+m8OJjid2WBzA9/cr2Z+MyoBGy3ihEC R3Cw== X-Gm-Message-State: AOJu0YyWttrF5sBSX0Fr5cyEdq+Z5L2HcsIPfYK4TytPjMuoffwyXQbO 0gWJl4d52j89f4cIAVFlaKNTRAcrAXeAmw== X-Google-Smtp-Source: AGHT+IHvYycIZso0+RNoX8bRrVZuyBR3PSZbo6WxRH0B5gzJyTbCgXGQtXc87zbj/WxsWkkJLPXsCA== X-Received: by 2002:a05:6000:1369:b0:336:6e22:672e with SMTP id q9-20020a056000136900b003366e22672emr8708289wrz.38.1704303239019; Wed, 03 Jan 2024 09:33:59 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id b7-20020adfe307000000b0033674734a58sm15715029wrj.79.2024.01.03.09.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:56 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 3CB4D5F92D; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 10/43] qtest: bump pxe-test timeout to 10 minutes Date: Wed, 3 Jan 2024 17:33:16 +0000 Message-Id: <20240103173349.398526-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The pxe-test uses the boot_sector_test() function, and that already uses a timeout of 600 seconds. So adjust the timeout on the meson side accordingly. Signed-off-by: Daniel P. Berrangé [thuth: Bump timeout to 600s and adjust commit description] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-7-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 7a4160df046..ec93d5a384f 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -4,6 +4,7 @@ slow_qtests = { 'npcm7xx_pwm-test': 300, 'qom-test' : 900, 'test-hmp' : 240, + 'pxe-test': 600, } qtests_generic = [ From patchwork Wed Jan 3 17:33:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510291 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECB411CAB7 for ; Wed, 3 Jan 2024 17:34:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NB8PUlZ6" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3373a30af67so3024799f8f.0 for ; Wed, 03 Jan 2024 09:34:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303239; x=1704908039; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T1rMPXmtlBiD25TB/VWS9sZqi6o6l7wGlXBsxO0xhRU=; b=NB8PUlZ6bVxhuhiVLj8qO1jbM+vhPVvaow3KloYWFEm06x3GC+bf77/sNoACUBxGZt ptipRvu6RXcNNBoKGCe515Xn6dBd6HW33ceS+dKwlzhUtsxnxPlG8BbVgI9mqh/d1TD6 lL3QM43QC1jm18rfOzbBeRf3gs1CoFbY4Tub/M0FWONToflvXsBi/euscxaxeNp/mKpy mVQfZhB1mhi0WY0p/2MBSHDCoexqVLL4w+wP0PlHI9m+fOaJqRoRMYoeUIfTO9347TIL 8D+PKxeyyDIZn7b4OU2rvpVbHn2u7A7O12hguabgSByd6W1jK/XztQsLtA1yV0J/wa8l P+8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303239; x=1704908039; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T1rMPXmtlBiD25TB/VWS9sZqi6o6l7wGlXBsxO0xhRU=; b=FXsyM559ugyeFpgQykyikmYLpD8s0liUd1kOvq+KzggQFPGqEFLY4Dimix2OQVLhCn oHq7cEytKzw+0fy0QqLtwowrQR6LQ4jrJ1yBuTm1rUbJsnuY+QdroZUXxqAsrT5SAq/0 KaJpLPVkI7QF0wLgWCxryWT/8zzivwaEdm+q+B2vs+WRnKc0LpEtCx51O/xsKYSJx6tm Vj0jt7Va4P0GvH+O5QToapUt4ywqRK5WUo+o5Bm/Ke875TGlWusWolPkkMEysPWMcasB axaPtTOammRG7ztPW7nwVt89IMMA0n1wnZSWLTHljS0GQ5akdCGmKyt8/I+udrtu6UZ8 csAw== X-Gm-Message-State: AOJu0Yy1gHghrVvRhycqu0QryhmgN8xRPi76jfeOz2ueolWxNFhlBvzF f64QdW7MXJQr8GH/3igeraYECDk/+bNRmQ== X-Google-Smtp-Source: AGHT+IGoegAEw8eIc6J+w1ZnlPQQhLp8Eo/JAhJe/joDQxXfuS1B+vbw8iKXZSou7llER/sVL52p+Q== X-Received: by 2002:a05:600c:4f15:b0:40d:8557:9266 with SMTP id l21-20020a05600c4f1500b0040d85579266mr2005442wmq.23.1704303239306; Wed, 03 Jan 2024 09:33:59 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id w13-20020a05600c474d00b0040c46719966sm2952760wmo.25.2024.01.03.09.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:56 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 56A705F940; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 11/43] qtest: bump prom-env-test timeout to 6 minutes Date: Wed, 3 Jan 2024 17:33:17 +0000 Message-Id: <20240103173349.398526-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The prom-env-test can take more than 5 minutes in a --enable-debug build on a loaded system. Bumping to 6 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé [thuth: Bump timeout to 6 minutes instead of 3] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-8-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index ec93d5a384f..c7944e8dbe9 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -5,6 +5,7 @@ slow_qtests = { 'qom-test' : 900, 'test-hmp' : 240, 'pxe-test': 600, + 'prom-env-test': 360, } qtests_generic = [ From patchwork Wed Jan 3 17:33:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510292 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02C9F1CF95 for ; Wed, 3 Jan 2024 17:34:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PS+SnRHm" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40d87ecf579so29155695e9.3 for ; Wed, 03 Jan 2024 09:34:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303240; x=1704908040; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wRw1//+81PB5ZNvZJSTSQFwoG2tqKVRM/U60AtyQst4=; b=PS+SnRHmk0AbRBxgpVsMVXr2/esrOEf+LErtAhcJvT/BQ9E77NL9jCpgR+cETlOQCX VBNQvK14m9R9b/Z0UxVFDz45CFTmQJPeKrf1GyWE1T3t7ZkDIU9KfNKlo3rWbNwhMp0D J5D1xM/OlhaDVi1Xr8xqanaANiMiYSNA2+f7U1xPPbGlDj8v8R2P7WSyH80tMgmYYzWX OuvNeZ90ZW9O5uz5AibxX9k2O3HS+QZfj2zeaPJAVLqkhkAqQdxlfefO2aaE6KjGTuZk C8NY+AWXgCR7Uc6tyENFSAsn5MfFOIbfoaIn87otR4kDrqThyhkQVOBcCjLLHpK1viSJ e22Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303240; x=1704908040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wRw1//+81PB5ZNvZJSTSQFwoG2tqKVRM/U60AtyQst4=; b=uqpF8Z4nJmNF/0v2oB3KAdauKm4+KyzQnL7OfxkTzROT7lLntxCM2IHvFtmMkHY7la BjyyVwqTG/K7RSGlitv3WMggfI+S9ckjVvYdV7J1LuQ71UQAASH8o25K+yrwFKZ+wIbU t5Fn6qoXejGGDpRdQN9Pg/U0ohtsQIuHtAEELtRjRattmhzTephfq+OOANIs4EFddUOj zoe1oJ9ys9bZ2s/wQcZtJS9F0WLsRhvG/qmJK+SnuKT8XaANmHQIF7du8/gOBxQXwSUN wB8cWNw9P+2pHlT3v3nRz4DMZvjLkRl5SsqIJB62NeDd3nqnfu8VNwnPusccryO8WFgv AFgg== X-Gm-Message-State: AOJu0YwjMUs0AfU29aFeVZzgkoCxMH+oZGVc/F74SGv83ToGYo/UjaU4 bqlO/T9qzf/wTXERdI8unG+Si0xpuTJxvA== X-Google-Smtp-Source: AGHT+IGRb1EG4rLPK4TuLkqwgONu+gLuVa4+cTzeg08wRExh/Gqtzz92MgVmvdmmy9ZrPufi06pGTw== X-Received: by 2002:a05:600c:354e:b0:40d:4d95:f82f with SMTP id i14-20020a05600c354e00b0040d4d95f82fmr6578918wmq.68.1704303240439; Wed, 03 Jan 2024 09:34:00 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id c1-20020a05600c0a4100b0040d81c3343bsm2942425wmq.42.2024.01.03.09.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:56 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 6B1A25F942; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 12/43] qtest: bump boot-serial-test timeout to 3 minutes Date: Wed, 3 Jan 2024 17:33:18 +0000 Message-Id: <20240103173349.398526-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The boot-serial-test takes about 1 + 1/2 minutes in a --enable-debug build. Bumping to 3 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé Reviewed-by: Thomas Huth Message-ID: <20230717182859.707658-9-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-9-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c7944e8dbe9..dc1e6da5c7b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -6,6 +6,7 @@ slow_qtests = { 'test-hmp' : 240, 'pxe-test': 600, 'prom-env-test': 360, + 'boot-serial-test': 180, } qtests_generic = [ From patchwork Wed Jan 3 17:33:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510296 Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABA711D53B for ; Wed, 3 Jan 2024 17:34:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fo8WVUpy" Received: by mail-lj1-f176.google.com with SMTP id 38308e7fff4ca-2ccbded5aa4so83785641fa.1 for ; Wed, 03 Jan 2024 09:34:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303243; x=1704908043; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G7uxGZGov81O+5jLuoaBr/C5I/uZZh1/zGx1+p9cIt8=; b=fo8WVUpyaIVxsr8IDUuJQ759QsxZYe8PvUGK488cBozqCqPqVr2BxjxvvkXiT92KSX VR6kHuGdcsUB16k5zSEAhTZRhe+KHQrdxhbhIk47sNxsAlbiXpp0qYflGd0lKbtk5+0d V5r8f5JhOQi1rHIBOStfntkLP6OPdiNmCbrweS+QdRdIuDvzqDmbnNgkhXu0Wp7981h4 EQ8P56GwVCtRvaZgmNLY9Xi6q19jAtjJ6v5MRJLuyQovUQDSjbKFAo2YyvvT+dRattiB KI9uG+D5ZewdhsgOjfeZioxfDD7Fv6E3zvA62sn1cPPFwheVV0yieSWNHCqU9yXGCRFs R8jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303243; x=1704908043; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G7uxGZGov81O+5jLuoaBr/C5I/uZZh1/zGx1+p9cIt8=; b=eNG3cdOzcdb4ciy2ds6QLPKEdcoP5mkx8OM3Rs+0viUx/z0mkYyaHq2fWGnhqndfnM cIqMA3WDgmXcc3Dbbwx7iD2aGQ/W6tn6L9vzlUpUz69mpf6sJPHfD6QoU6SH2tOc7W3n 9rBFK0gtxbdf+vzyPvBbsI5tFqyPOS2vzuQBS/ZSc+Qlz0rwIfA76mtJNhmAjIMQA8dz rlnHGMhNauheg0B4lmF1l3s1YEWLSAQm8hB/og5/3yRmeYsC2Glrwk7pr3GWquNQ7yvf e+Rzq5zNcRs6VQhrmJZekoe4U+xwIQbMeoOQpSzp9CevEUIgtyySmhZlYlX7PPyefW3j anBg== X-Gm-Message-State: AOJu0YxyZuWyDmfsx54wsXdnA3ggfiR1wUTVHoEDziyGI9whVTM8wAjz 2vrTv11wX0dtpUZ23t3MoBY+c4/UjXB0Xw== X-Google-Smtp-Source: AGHT+IFhNAa0ExWYCS2KvTjl2oi2iRsIB5/oaggT0hzzaXckkjHspuvOE576DfxADqAu/SUDJduuEQ== X-Received: by 2002:a05:651c:686:b0:2cc:d555:bc66 with SMTP id x6-20020a05651c068600b002ccd555bc66mr4899025ljb.76.1704303242728; Wed, 03 Jan 2024 09:34:02 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id q28-20020adfab1c000000b0033690139ea5sm28923405wrc.44.2024.01.03.09.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:56 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 817AB5F944; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 13/43] qtest: bump qos-test timeout to 2 minutes Date: Wed, 3 Jan 2024 17:33:19 +0000 Message-Id: <20240103173349.398526-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The qos-test takes just under 1 minute in a --enable-debug build. Bumping to 2 minutes will give more headroom. Signed-off-by: Daniel P. Berrangé Reviewed-by: Thomas Huth Message-ID: <20230717182859.707658-10-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-10-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index dc1e6da5c7b..b02ca540cff 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -7,6 +7,7 @@ slow_qtests = { 'pxe-test': 600, 'prom-env-test': 360, 'boot-serial-test': 180, + 'qos-test': 120, } qtests_generic = [ From patchwork Wed Jan 3 17:33:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510293 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5734A1CF9A for ; Wed, 3 Jan 2024 17:34:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="whVlDm+K" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-3368ac0f74dso8902680f8f.0 for ; Wed, 03 Jan 2024 09:34:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303240; x=1704908040; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vqrDXpkh9FjMlfAgHrjndIlqPg75eovfRGnZr9OF3KY=; b=whVlDm+K7xgaWHgZeSty7rlwUS4uXWCNqqhVzvO7p80hhMwys+w5H0MZ0ZO5bNXypd Q9jW/Fgu/sTPqSeEZ8SZLC3X9CVaKOK4a+KPfTbzDuLa7/1Y0RamxeYJiIW/cFAQOkY9 Ww4rWn3QwkVvaUqhi3HkDm59DThBAYGyDUXdyKbC2HpfBhJi5fs+g6Q7Jr9UTw22oipJ J3ksC8UwJ3zYOty0Udqk1fpANRniv+Tj5mFSoiOKWWJgmGhDj4XLYsTLgee9xCkWzGbJ a3kct8B5RL8xbQZyYUueMCU5KAWHq9rZbI3hlfbvmslHosyhZ73zrth8vV7QNRwtjoyh 3Y2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303240; x=1704908040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vqrDXpkh9FjMlfAgHrjndIlqPg75eovfRGnZr9OF3KY=; b=pzAD414A2ipccM9Akn8fw6zowUISt8Z34SnR7mxLbDdj3H5cu1cQvprFOs/fhjABEE h627sn1rznPNX535rcG22hk5cS+vHRVLUx6iYzH+mjXDf0M2kFDPA8Q7TjXsF2xBahY8 fvJ/Je14aVhaIC+ovmox05oXDdnFluXEYYWjSy+hfkF3+4yqTECP3mUCsnZoD0V+LNy1 wASkqd9C+XPbF2IqAF3ikk2q58hPvVy2EaNP+Bu8tpVXZCJwCPOQ+Xg4izu2DP8Lqvn/ 1uo/N7A7Xm071LHyKQO/R3e51wsJDh4GssAsL9ADFc26Kjoo3+PawLyd2P5OIA1MuKru expg== X-Gm-Message-State: AOJu0YyTAte+CSQBZrnNegG+guZ6pjXV1cNyL2XGzXkWqFijUufHEVYR oHF6jzqqUiSZd9IcZS9HsSAtavpLRt9cSQ== X-Google-Smtp-Source: AGHT+IEnYc36seB1PpcGJ/mV+1AvJpNac6K8FWM/1UmeDuOkWOqd5bHXuF6GN7+Wd+OGJrM9o3XEQA== X-Received: by 2002:a5d:684a:0:b0:336:1182:6475 with SMTP id o10-20020a5d684a000000b0033611826475mr10980107wrw.34.1704303240708; Wed, 03 Jan 2024 09:34:00 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a18-20020a5d53d2000000b0033671314440sm31256414wrw.3.2024.01.03.09.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:56 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 95FEB5F926; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 14/43] qtest: bump aspeed_smc-test timeout to 6 minutes Date: Wed, 3 Jan 2024 17:33:20 +0000 Message-Id: <20240103173349.398526-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé On a loaded system with --enable-debug, this test can take longer than 5 minutes. Raising the timeout to 6 minutes gives greater headroom for such situations. Signed-off-by: Daniel P. Berrangé [thuth: Increase the timeout to 6 minutes for very loaded systems] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-11-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index b02ca540cff..da53dd66c97 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,4 +1,5 @@ slow_qtests = { + 'aspeed_smc-test': 360, 'bios-tables-test' : 120, 'migration-test' : 480, 'npcm7xx_pwm-test': 300, From patchwork Wed Jan 3 17:33:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510294 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCD4D1D52A for ; Wed, 3 Jan 2024 17:34:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LViPya4x" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40d5d898162so51172165e9.3 for ; Wed, 03 Jan 2024 09:34:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303242; x=1704908042; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NG0GNTBkS5OA4bLgzcXFuNl7bQt30v5WL9SIW527gOo=; b=LViPya4x848JqX5CprLMs5WY2Mu2g3wTgmCOuM7gwHi0aq2x/dWxH3pZBZThZsxOMd DLUKYb6JVrOOHM7TFpaEnCfGUrEQtar4byhheX2SkFhcxxaBmr4S6ZzQbw5/HrXbgqyP FOwawgRTv97MpeUkf2mAncSKWKBqyyg+G/HGj77lUog+8I6ErEeR+8f93NzZDOt7jIsq NWtjpUcG/jM8Gb7IYQdqtRoG3uxL1LuSwDwmFIo6Zwlm9myr1F4DvtnOR7oadMJzSMWs ZrKPM32054yYwp2w0LMcpmrFP37Wy5jK8OlefHBPSar/qGO4XzkGq0jmJSHU8B6Fp79X 2h/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303242; x=1704908042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NG0GNTBkS5OA4bLgzcXFuNl7bQt30v5WL9SIW527gOo=; b=lzRNJKrPdyKkzW4ULstpydtYqqeD9te496dqsDPVdanovS6uq7XScT6ANOoQiNU0RH IBYMpAS+4ZfFG03A4p4TYUThAeJJvqaGMaRlznVSX/UBXqUGjpRteaKKAwC3AZGWXM2f +JyQl9s/XDwMaP7+dO9wdh9CQ0dlm169yVyRZzXB66r4Z4XsDuL/5ctY5E/q84vr+8vG GTV6T6kcShRSWgum6lSVzaSFCpHs2FRSilMXdJi8zk0Q76O9UPLW5q1qn2rNBAG8wg0v uqjUYl85FucheesfEw5dyiz7Bv2CGLFqeYqMSUVV9GXvv3ndzJTE4nVBuS++tPihvmkX mFPA== X-Gm-Message-State: AOJu0Yz/4LFuCnihYNMd1ttDDT2B7hWo6VPZEzvW3CqhlMev35SPopQh xwdwy2vS0W+HU/Ic3Im2MTqAxnp7ftHQbg== X-Google-Smtp-Source: AGHT+IEBcU3HIt2kk3f3ka5JNEGbknZiuar/K/H51Rdj+QmKRU4GX1U2mGMWQY7DZpu51o+Llv5W6Q== X-Received: by 2002:a05:600c:524c:b0:40d:42de:46f with SMTP id fc12-20020a05600c524c00b0040d42de046fmr11584360wmb.1.1704303242245; Wed, 03 Jan 2024 09:34:02 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id v10-20020a05600c470a00b0040d839e7bb3sm2954439wmo.19.2024.01.03.09.33.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:57 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id ACA435F946; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 15/43] qtest: bump bios-table-test timeout to 9 minutes Date: Wed, 3 Jan 2024 17:33:21 +0000 Message-Id: <20240103173349.398526-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé This is reliably hitting the current 2 minute timeout in GitLab CI, and for the TCI job, it even hits a 6 minute timeout. Reviewed-by: Thomas Huth Signed-off-by: Daniel P. Berrangé Message-ID: <20230717182859.707658-12-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-12-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index da53dd66c97..6e8d00d53cb 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,6 +1,6 @@ slow_qtests = { 'aspeed_smc-test': 360, - 'bios-tables-test' : 120, + 'bios-tables-test' : 540, 'migration-test' : 480, 'npcm7xx_pwm-test': 300, 'qom-test' : 900, From patchwork Wed Jan 3 17:33:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510295 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 141901D52E for ; Wed, 3 Jan 2024 17:34:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="P1WyARUb" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-40d87df95ddso27816205e9.0 for ; Wed, 03 Jan 2024 09:34:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303242; x=1704908042; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b7XkKmTa2rk3nK9lrhGULgV33LxXcjUpugmHNR7vUhY=; b=P1WyARUbAjWfGedwOXdGTmZX8FAwT+V7ZIaFO1HC/CLy13KIBM+HCNhXQktMyb/31w j6NgePLnr0FkXZW1FmC2nHc1g7SAYy6SbtSJhYP7UBw+CpWz2/zhh5NsZA4xMmPnIs/S 4x0H+3EGZcJU0Mgx98oK6p5mBBFJ7PSbgXwW50VLdqnSdYRaVJEUt00bjDPhvKTvjQrp ihrXDl2XTxHsgNkTVMGvGizzUrWf0xATUxpBs88Da7y7fiKUE7nkqoVVxS0s3OOW58A/ DBYQsjp8lT8//qOVMPvbdkfe7+7dkENgxbtAk+tRA+TQGVQzMrR1tT+PxJWrp3M84anh Heow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303242; x=1704908042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b7XkKmTa2rk3nK9lrhGULgV33LxXcjUpugmHNR7vUhY=; b=Ay4YQLrDvkxKrwRDNDWixLH0+rk4YpypS29dXu3GSOii0+dNE5eEnC36EyjDl+X5sV qBskeAfdMobWjVJbj0Us9r2Q0dkf3w4aFTOpiAk6IyqpmQ1SlWdN88KROpIisIn/S94w yo75lmdVNatg93fId/ny8dm0jh+PQD1T/mBIl5IPlIF41wqYh7q9xgZR0FkEA0shBfBh xITQtq/nZK2Jx32qPu+JOXqGfwTfq8XdH6XTqsy2DjW7BjKg8gQF3DzGZXeDR+xzVsaZ 70YkoE/6ZwEfnhV6i4NPrsEA7n03cBP4wMMjSWldUbzWlltKGQcRK+sEAKrMo8U5d4Cu NaMA== X-Gm-Message-State: AOJu0YxBZVST+VBo49KvJh/WKA2d2ow35uXx4/Rd9kH/mKZrM72rIIUs VuX1egM0g7Rg7BzXbvoU9kzWeZtxJ01j2Q== X-Google-Smtp-Source: AGHT+IF/L2p0zQ5EsxWm/ZeewITkxLw43+Hum/+1n38RYmruA0nJMBDcBTcvxGZi4eR6abvI1/ZlBA== X-Received: by 2002:a05:600c:154f:b0:40d:5f55:663 with SMTP id f15-20020a05600c154f00b0040d5f550663mr3068051wmg.94.1704303242496; Wed, 03 Jan 2024 09:34:02 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id q17-20020adff951000000b0033718210dd3sm14497665wrr.103.2024.01.03.09.33.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:33:57 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id C30C35F948; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 16/43] tests/qtest: Bump the device-introspect-test timeout to 12 minutes Date: Wed, 3 Jan 2024 17:33:22 +0000 Message-Id: <20240103173349.398526-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thomas Huth When running the test in slow mode on a very loaded system with the arm/aarch64 target and with --enable-debug, it can take longer than 10 minutes to finish the introspection test. Bump the timeout to twelve minutes to make sure that it also finishes in such situations. Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-13-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 6e8d00d53cb..16916ae857b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,6 +1,7 @@ slow_qtests = { 'aspeed_smc-test': 360, 'bios-tables-test' : 540, + 'device-introspect-test' : 720, 'migration-test' : 480, 'npcm7xx_pwm-test': 300, 'qom-test' : 900, From patchwork Wed Jan 3 17:33:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510363 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 576C31C29F for ; Wed, 3 Jan 2024 17:49:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="xdOrVO33" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3374eb61cbcso674716f8f.0 for ; Wed, 03 Jan 2024 09:49:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704304146; x=1704908946; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G1gJobfuOXArDzvCmnHLIGQ5mswWRXVhuXYUXNww838=; b=xdOrVO33BxFDXPdzgtlcudwPaTEe0VIN+qyJlVSvhqOG1hP24yfVmYarDF6rQbluMX cM3pJdWVNgz5I7GATzbMo6Ucsa+6EbUgfKR7Msa0ltP4gNdn4OtrEC5Ylz5Ohm/V2Htn G9AIFThJO5KizHxQ5hnMdWv0WTKbLN7hc/Q+7WtfomCtLWuGZ+Qiq6ZAH5pJv4pUOjli 5oYmYSd1jh9RSUCago2+AISRzfsZsp2V8B8RFENdZG4oYtYPZmTIkPtmlNDvWQZ4NqiO 3o8/AuaI42DX3Swv9uXcxzj3MrgA4a1MVddja/LnPoK81WVIctrEqsYPl4jiMMilke06 YIUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704304146; x=1704908946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G1gJobfuOXArDzvCmnHLIGQ5mswWRXVhuXYUXNww838=; b=YAVRnhWHvXmoqZT9UOcB4SbLQn9OsirbS3bWtOzYGsmGoyYz0Egph7ohHbEPANontq w34dx60uwPUH6b3tBAoJcAiCB+e0RAvbOy5XnzDnWAAT0B8y9ZKRzUdFRnTM++wtgTjR 615ubSVjjdXS1f/lwGZsMvdrPpB6R14/9G7Y82+4ch6mG8wOSrGchxGYjwCaT2VQqcYJ QWZlXmAkN56QBi2i3GHTb2CrKxkvDpDUmxt7+DdPag3Pcr0w792t3XBesWzMLXgYPuAX u4hJIdDIJbes6XJXrzrEU7gBpKM1PVG15C6PdTnBLEISZzkKUiIxhcZ4X3RnizHYX1EU yBQw== X-Gm-Message-State: AOJu0YypCbAl08+It7Qenq3h1G7FCyZxpJe1URZcmUKSe6hy6Au9dIpW Md0hAbfzrDO4KZBUq6gXAEms7KIAwe7Zfg== X-Google-Smtp-Source: AGHT+IGBTYNZSeJJFlrDUsZAC7ZX18VaF73k3nmFtB4HTAJAnT+qiuiHp3e6xy5HCWK1xoAdWaJkyA== X-Received: by 2002:a05:600c:538c:b0:40d:7b73:68bb with SMTP id hg12-20020a05600c538c00b0040d7b7368bbmr4470553wmb.131.1704304146689; Wed, 03 Jan 2024 09:49:06 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id c18-20020a5d4152000000b0033609b71825sm31007316wrq.35.2024.01.03.09.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:49:05 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id D9EC15F949; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 17/43] tests/unit: Bump test-aio-multithread test timeout to 2 minutes Date: Wed, 3 Jan 2024 17:33:23 +0000 Message-Id: <20240103173349.398526-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thomas Huth When running the tests in slow mode on a very loaded system and with --enable-debug, the test-aio-multithread can take longer than 1 minute. Bump the timeout to two minutes to make sure that it also passes in such situations. Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-14-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/unit/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/unit/meson.build b/tests/unit/meson.build index a05d4710904..0b0c7c14115 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -172,6 +172,7 @@ test_env.set('G_TEST_SRCDIR', meson.current_source_dir()) test_env.set('G_TEST_BUILDDIR', meson.current_build_dir()) slow_tests = { + 'test-aio-multithread' : 120, 'test-crypto-tlscredsx509': 45, 'test-crypto-tlssession': 45 } From patchwork Wed Jan 3 17:33:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510326 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54BC41C2BC for ; Wed, 3 Jan 2024 17:39:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="iMlio8Ie" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40d41555f9dso107509285e9.2 for ; Wed, 03 Jan 2024 09:39:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303548; x=1704908348; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bAHZvQIZNHRqbyqy5ojwPgGxK/S007kBQEH3xZgSzNs=; b=iMlio8IekdM3CYeTgCl4QQsdEUxarmDz3V4wa5FH7HnRqUQsY5UfoRazMvds8CXcdt j3DNIdtTNWHwt+06SmbqyjXtMzXtRl3ffvP+nyiHYM/wgMBRYVg4g89Xq1jgsXRl8QaT dy7UWJJ1j9REo8neZYcBVmd0qyWLo8ovP+9ZJqi82/SaKfTawBekFrZKKK/tWaYHDIS/ xldTEkkA1bFC1szzgR9FsoO3UsXjPXRoayFzr1+29uIuG4bf4JGl9Td1UxBDeNvX4ZMM Yf3EAgfC3hzb2GH0Ltqg6+o/F7/cCYrS8TtXajHPo8bCH8V8V9FGJwCFY/ROkzOdgyxR HvvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303548; x=1704908348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bAHZvQIZNHRqbyqy5ojwPgGxK/S007kBQEH3xZgSzNs=; b=L6Bh4na88kT6GsEryOMk118m4XxVamo2JKAJUg/bAFD05/I7PBYKQmLRK79rHrWmf0 pC3ZSxFFdAri6MH/sCaATOh7L3RyYliDSwMnVW6PHfkoXpCdFXZubiMtt0w1GXDdZRI6 eE+5wglV1kXFwBxJfo83iD7rrsIKWyrNCMjRTd2Z9IByO+ted/29yY3yTnMspGXoFWPF x2i0dvvoHp4AoUwzJj9Ed40y8feNcY4z3M1GkSo6waln3gX6UMd6Az9uvV+CEmOcmukx IY0pjb0NimTJpXN3P5wN1Qd8SZtSyBeILS+askhjag/7u1jLyrA6q0spz+ai8a2Gg5Y/ t2rg== X-Gm-Message-State: AOJu0YwcUeK0Ka+lNde/IACHwT3pEVOHp8GpJlwrsLwZWSziKwhW+OFX i/6yFbq/1MB5gKOYWMe9GNmKtddEslnVLg== X-Google-Smtp-Source: AGHT+IH+4maMIBzTJ7N1PEvrhxWa7T7vfFwtaWKzwHjzicWz5J/l15SGoM3cw1O5Yh0uqgYYBdQYRQ== X-Received: by 2002:a05:600c:3d8c:b0:40d:83c4:ff2a with SMTP id bi12-20020a05600c3d8c00b0040d83c4ff2amr3311366wmb.55.1704303548649; Wed, 03 Jan 2024 09:39:08 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id b13-20020a056000054d00b0033739c1da1dsm9906876wrf.67.2024.01.03.09.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:39:06 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id F1D055F94A; Wed, 3 Jan 2024 17:33:50 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 18/43] tests/unit: Bump test-crypto-block test timeout to 5 minutes Date: Wed, 3 Jan 2024 17:33:24 +0000 Message-Id: <20240103173349.398526-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thomas Huth When running the tests in slow mode on a very loaded system and with --enable-debug, the test-crypto-block can take longer than 4 minutes. Bump the timeout to 5 minutes to make sure that it also passes in such situations. Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-15-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/unit/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 0b0c7c14115..a99dec43120 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -173,6 +173,7 @@ test_env.set('G_TEST_BUILDDIR', meson.current_build_dir()) slow_tests = { 'test-aio-multithread' : 120, + 'test-crypto-block' : 300, 'test-crypto-tlscredsx509': 45, 'test-crypto-tlssession': 45 } From patchwork Wed Jan 3 17:33:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510327 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 570C91C69E for ; Wed, 3 Jan 2024 17:39:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NosM8vEe" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-40d60c49ee7so57992775e9.0 for ; Wed, 03 Jan 2024 09:39:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303550; x=1704908350; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oeKurO18PT1xLzL5iQamunNBev09YXep7NV+pG6wspo=; b=NosM8vEe5Ejoi99S5R6P2k6pg+5cKelJajrqY0PewR38J42QJsSY+uJpBxo8/800WZ 92OPzIjk9s88c1UrRhLm9yBcYAYePnVQDM9mUIKMjitt3BBgd042AlpK6r6OROkXYWGy oBX0m4EKUbSEWjBUnxDnc5sytRB/gCCmp839f0G2iYYEZd63TeSWwdMBYkLdj7AMIS5P 3Tw2uALud+OZnudQ1TMcW+wP/3/rrN8RKkgKTLAm4F8FrEp+hv5u6H65vYytoAsyfFMj fa0OGMhyxGyAqcGiu3Ulim13XnYj7TKzNRYIlZg24r+JKCC76uC5JhXM05b8RIJ5e5bV S16Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303550; x=1704908350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oeKurO18PT1xLzL5iQamunNBev09YXep7NV+pG6wspo=; b=UWkuLwK1nW5rbh4Ri2YQh1JboXmLNot+oeVitMNSLyCFBHqroVU2x3nm3pcvFqNxFt V32z3hlDTI3ONHqX8yQU4ra8lc4mTVhb9ayRi9CdFDGE3O2guT6JkMLeot+x0ldBYr5o v5DaZsmkC6Q24yA4+lW3Rg/qtywErimSTRP8LCioK905uT7fTX33X5XQQ19bDji+lbL8 jNP/IbSDx3TOFR6p2ckpHmYNp2Q5Uws+WZIzFrpH0O9eAs9AQC1ulhwaia3ljL9TakBM UyHuMS2sgGVnGYn/IQoyOJGSaTlT9m+c+2h3qx0/g/5y8j5Gx0IUBnzS/hEjxGRS9+mO deCw== X-Gm-Message-State: AOJu0YwnpPndJ0qq/GJDgImJb1icz+dyBgr7T37IUSWf2DpStUCpM7OG 4jwMDsRc12rGnsRl4pfOeRKxJvFKwDmu7Q== X-Google-Smtp-Source: AGHT+IFr7TkHDM4WWp1TO9UpDh2cwaH7JdhPfjki/y18qhHSL+e3Ga994DayBnr9oQrGy3VPOy05Xw== X-Received: by 2002:a05:600c:44d6:b0:40c:78c:f864 with SMTP id f22-20020a05600c44d600b0040c078cf864mr10710339wmo.16.1704303549769; Wed, 03 Jan 2024 09:39:09 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040d77ebd55csm2974477wmb.13.2024.01.03.09.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:39:08 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 12EF95F94E; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 19/43] tests/fp: Bump fp-test-mulAdd test timeout to 3 minutes Date: Wed, 3 Jan 2024 17:33:25 +0000 Message-Id: <20240103173349.398526-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thomas Huth When running the tests in slow mode with --enable-debug on a very loaded system, the fp-test-mulAdd test can take longer than 2 minutes. Bump the timeout to three minutes to make sure it passes in such situations, too. Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-16-thuth@redhat.com> Signed-off-by: Alex Bennée --- tests/fp/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/fp/meson.build b/tests/fp/meson.build index cbc17392d67..3b7fc637499 100644 --- a/tests/fp/meson.build +++ b/tests/fp/meson.build @@ -124,7 +124,7 @@ test('fp-test-mulAdd', fptest, # no fptest_rounding_args args: fptest_args + ['f16_mulAdd', 'f32_mulAdd', 'f64_mulAdd', 'f128_mulAdd'], - suite: ['softfloat-slow', 'softfloat-ops-slow', 'slow'], timeout: 90) + suite: ['softfloat-slow', 'softfloat-ops-slow', 'slow'], timeout: 180) executable( 'fp-bench', From patchwork Wed Jan 3 17:33:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510322 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9AB31C28F for ; Wed, 3 Jan 2024 17:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jUtREQz5" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-40d2e56f3a6so4405605e9.1 for ; Wed, 03 Jan 2024 09:39:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303546; x=1704908346; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0sLk9Y6V09YT5mxoKGySQqDe7AUl7PrL/RJQ+Y1wnbw=; b=jUtREQz5W4WX7PzkqkhyliAuxrjZQMCZQwJRYHRImmCDGgxne0iOXZZpUX7GnvQqra wEvIcCjmtNeNqNFMSpe5AAIH3O3zMxd3CSw2iIM4uTW8njwtbriNNGbnYaPWTn8pfKNQ ymWoSnpkPqM+UumPrf7h+PAi10++kJf3OUR1g39oPRoqzapif3LNT33v0C3uJ1wLCB7o Wh4mZkIzQ7v55biNCdSBEGtCn0ixzfQSC7lqRTHYYuDzeot7DUpIEoFXI7c67nQIP3qu es4Bkns6bwNVInv1w0tffVlNbia3U4XrbC4PHG704qW6xFe9PWrbJ6oG0CXfSCO2wYAR ulNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303546; x=1704908346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0sLk9Y6V09YT5mxoKGySQqDe7AUl7PrL/RJQ+Y1wnbw=; b=Nw4eKOO+irSQJi4HWehoQVKRO9Axnz8avAV1WiSK+Lax31H1KKPOKJyCGQJXGFMmhe yl3lg1N9ws4qQdBPfEzVhVt4ex9UBSZ6fESgxnB/cLzOpJWk5mAb03gIvT5bkl+w9VCu bZWssLDGVdQkJcxo5q69PGjYOO1rD6XNLHRsUwTF8SpqT5lUs066xOEqozlDz3aoSQJ1 0cOUCyFWBJ7i0JJ+i+IrVVsE+2tGunPR9609pNK+TBzMODNKnytAcDQdvSDzjLEzZDX9 ZZnW2LflT0BeT9W4md5U6SHEo3llz8g9aElEnjLg8tpaa7mY6Pak/oxvQ9oSWr9Fpwiq iK2g== X-Gm-Message-State: AOJu0Ywa6cNx5dHeyXu2qjsnLIzDMKkXWlLstsYYSbaQg7AdFIYu1RR6 Uj4hyvmvyUzlBycGEV7agz7dtWyhubngRA== X-Google-Smtp-Source: AGHT+IGR8Qb9ZKRyeNjw27aD8Jf1B/xnmHbcoluCD13YEs3zMnsmdYYJyBx3xpWJIG1auhT+vGCdLA== X-Received: by 2002:a05:600c:4fc7:b0:40d:3f30:a09e with SMTP id o7-20020a05600c4fc700b0040d3f30a09emr804540wmq.84.1704303546006; Wed, 03 Jan 2024 09:39:06 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id dr16-20020a5d5f90000000b003373ef060d5sm8567186wrb.113.2024.01.03.09.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:39:05 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 298A25F950; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 20/43] mtest2make: stop disabling meson test timeouts Date: Wed, 3 Jan 2024 17:33:26 +0000 Message-Id: <20240103173349.398526-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé The mtest2make.py script passes the arg '-t 0' to 'meson test' which disables all test timeouts. This is a major source of pain when running in GitLab CI and a test gets stuck. It will stall until GitLab kills the CI job. This leaves us with little easily consumable information about the stalled test. The TAP format doesn't show the test name until it is completed, and TAP output from multiple tests it interleaved. So we have to analyse the log to figure out what tests had un-finished TAP output present and thus infer which test case caused the hang. This is very time consuming and error prone. By allowing meson to kill stalled tests, we get a direct display of what test program got stuck, which lets us more directly focus in on what specific test case within the test program hung. The other issue with disabling meson test timeouts by default is that it makes it more likely that maintainers inadvertantly introduce slowdowns. For example the recent-ish change that accidentally made migrate-test take 15-20 minutes instead of around 1 minute. The main risk of this change is that the individual test timeouts might be too short to allow completion in high load scenarios. Thus, there is likely to be some short term pain where we have to bump the timeouts for certain tests to make them reliable enough. The preceeding few patches raised the timeouts for all failures that were immediately apparent in GitLab CI. Even with the possible short term instability, this should still be a net win for debuggability of failed CI pipelines over the long term. Signed-off-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230717182859.707658-13-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-17-thuth@redhat.com> Signed-off-by: Alex Bennée --- scripts/mtest2make.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/mtest2make.py b/scripts/mtest2make.py index 179dd548718..eb01a05ddbd 100644 --- a/scripts/mtest2make.py +++ b/scripts/mtest2make.py @@ -27,7 +27,8 @@ def names(self, base): .speed.slow = $(foreach s,$(sort $(filter-out %-thorough, $1)), --suite $s) .speed.thorough = $(foreach s,$(sort $1), --suite $s) -.mtestargs = --no-rebuild -t 0 +TIMEOUT_MULTIPLIER = 1 +.mtestargs = --no-rebuild -t $(TIMEOUT_MULTIPLIER) ifneq ($(SPEED), quick) .mtestargs += --setup $(SPEED) endif From patchwork Wed Jan 3 17:33:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510333 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47E921CAB0 for ; Wed, 3 Jan 2024 17:39:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LHYQRu3m" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-33674f60184so10729590f8f.1 for ; Wed, 03 Jan 2024 09:39:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303554; x=1704908354; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ciRl9sFGERSf23eviyCL0uKOJ2+yOOkqWUqo8JImKW0=; b=LHYQRu3mGG0B8IzRJOVOuwlKvWXy7mPNgxS/NBHFM2JMw6cOvuBJWhgHc/Hf7h67MJ tCvKsa1Y5xAq0FMb3lD3UNDJhevUCkVLoM9z7p1vHH4NHy4egK09ZZ+qyvAQb9bgA2zK dgC+bpgSlz3jbi+RbTknLf6iKqxaUSxCXk1WBtZCz/ynTXmP8WDSITt3p1p6PAp0+0VY V+3+FK91UC3YukKbdXXkSDE4zkHGo+o01wP07DbJ6sm5+WVInMyzPeXeMpyPEXsb7kmT 7AnnCAd5ezK5mM+5dHlXUBdSzU3B45QsD4IAQiL5/8M3bBAJKPYXk9RaSG98SnN8Ykyn YS0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303554; x=1704908354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ciRl9sFGERSf23eviyCL0uKOJ2+yOOkqWUqo8JImKW0=; b=Q3t0qo1Ua2L4H26LLVeqG8+aEOvjLc6M7YM4NeXaOnHIqNDBBwn6AZVFBNlf+AcUrv lh047SoPtISU8PDsCUJRmkdhTgN8Q1M0t8URLbYJ+cBSja/peyb6ksEk2P3uWWr3H8C7 S3qM3wTSP1avXjQfyNz+AEaFC8bS9mLpRS4sdy10O751rWxr2YrlXmKUhBuy9f5DFxR4 7DuHpgWIbRaHzaprz0Sm/w66fZVdT83+5UfMX0nXD+osLCq9X3Xs6uHa4VSbnlso3qrD YNT+ukDCaZJPH6UenFc5sTO7L6kHOr9SeUhHDZmCPwvVmWctmYhlM3+2es/C999Ch+/N SXtg== X-Gm-Message-State: AOJu0YyejFDEZkqg1egwgq5NViUfl0cZYYIXIEOigcoToSv/9Tyon85Z TqOPs3NdDeUbZFQvfL+JzrN4R+OGWL7lbw== X-Google-Smtp-Source: AGHT+IFDLpxCZNS1nZaWXFfbL0Qz+KalAUozXFnUwdorNdWC3gGHXn5UNlLNInmNypjXhCCaw7+rvA== X-Received: by 2002:a5d:4849:0:b0:336:8f9f:c69c with SMTP id n9-20020a5d4849000000b003368f9fc69cmr10597659wrs.40.1704303554593; Wed, 03 Jan 2024 09:39:14 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id x18-20020adff0d2000000b003365aa39d30sm30989513wro.11.2024.01.03.09.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:39:13 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 3FDAA5F951; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , qemu-stable@nongnu.org Subject: [PATCH v2 21/43] readthodocs: fully specify a build environment Date: Wed, 3 Jan 2024 17:33:27 +0000 Message-Id: <20240103173349.398526-22-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This is now expected by rtd so I've expanded using their example as 22.04 is one of our supported platforms. I tried to work out if there was an easy way to re-generate a requirements.txt from our pythondeps.toml but in the end went for the easier solution. Cc: Signed-off-by: Alex Bennée Message-Id: <20231221174200.2693694-1-alex.bennee@linaro.org> --- docs/requirements.txt | 2 ++ .readthedocs.yml | 19 ++++++++++++------- 2 files changed, 14 insertions(+), 7 deletions(-) create mode 100644 docs/requirements.txt diff --git a/docs/requirements.txt b/docs/requirements.txt new file mode 100644 index 00000000000..691e5218ec7 --- /dev/null +++ b/docs/requirements.txt @@ -0,0 +1,2 @@ +sphinx==5.3.0 +sphinx_rtd_theme==1.1.1 diff --git a/.readthedocs.yml b/.readthedocs.yml index 7fb7b8dd61a..0b262469ce6 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -5,16 +5,21 @@ # Required version: 2 +# Set the version of Python and other tools you might need +build: + os: ubuntu-22.04 + tools: + python: "3.11" + # Build documentation in the docs/ directory with Sphinx sphinx: configuration: docs/conf.py +# We recommend specifying your dependencies to enable reproducible builds: +# https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html +python: + install: + - requirements: docs/requirements.txt + # We want all the document formats formats: all - -# For consistency, we require that QEMU's Sphinx extensions -# run with at least the same minimum version of Python that -# we require for other Python in our codebase (our conf.py -# enforces this, and some code needs it.) -python: - version: 3.6 From patchwork Wed Jan 3 17:33:28 2024 Content-Type: text/plain; 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Wed, 03 Jan 2024 09:39:06 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id k4-20020a5d5244000000b003368c8d120fsm29995262wrc.7.2024.01.03.09.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:39:05 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 57CC25F954; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 22/43] hw/riscv: Use misa_mxl instead of misa_mxl_max Date: Wed, 3 Jan 2024 17:33:28 +0000 Message-Id: <20240103173349.398526-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki The effective MXL value matters when booting. Signed-off-by: Akihiko Odaki Message-Id: <20231213-riscv-v7-1-a760156a337f@daynix.com> Signed-off-by: Alex Bennée --- hw/riscv/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0ffca05189f..bc67c0bd189 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return harts->harts[0].env.misa_mxl_max == MXL_RV32; + return harts->harts[0].env.misa_mxl == MXL_RV32; } /* From patchwork Wed Jan 3 17:33:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510299 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C41E1DA20 for ; Wed, 3 Jan 2024 17:34:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JepahAGQ" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40d2376db79so95778345e9.0 for ; Wed, 03 Jan 2024 09:34:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303247; x=1704908047; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KAYNxNN/VIwn3brnYwBM4da3zygXAIotsdaTZu8xJew=; b=JepahAGQGSAmCTiVc7J3ZmNMZPjgzRr+kGCRzlckxopXZEtH0OpRd11CrU0t/KbGDo puMH/WqW+xetfWFYdTy3kixPmDyQMpCFp3T1oHkqJww/QSSxKbQgzYKnU4bBXCbQvP1i WjqOcwU0Gi69VNNBn2jsgkjP80P0cUtBaHnk0ne71QRKB1G3AwxT2DUKf5UVvH1a5tdn n9eofsGcCL0ps6V9YzTOCiR3kJVm2KviYaedlHHEiGY6wveNvD0wu2iZhdqUC3ZmWknx UCvwwUn+TrxGhEde5QTJ8mkNLejUiLF6Khcegm7Qqt4AJUdt05pic4k4kzj006iIQuwk DOSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303247; x=1704908047; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KAYNxNN/VIwn3brnYwBM4da3zygXAIotsdaTZu8xJew=; b=jtS/kS8H0SqPrsYNdsnlGxJIQ8jkq/ord5ogLP/fYALGzm7fWktxmFqTs3bakbVTHK B5j6Ip2vaRKPs8QItl5E8/hvHuyTCEMca/v/VIMgVxEr9+OnlZMTMrHUCH6MqP9JDICB s/+TtkbI1EXuASpoezhLie7lVnth97ZYlmzat/iY5Zlk6EBLRCGJF3fKdGfW7ArCkvj2 q3TzHcCDrTuXpkhllDBaUBb8DIAwqY64kHlwT0xZR1j0luQmaMwg7WSg2GQqN15bAqGy /Fnu+U2oDjmHVG68fZjMcuZLVUzEkB7Y02V9eqQWC14mDCmLMQY5OB265t7/1Deg72EG 4NJQ== X-Gm-Message-State: AOJu0Yz+kOYVzBZNU3pyvybTOhDiybG4YDwewQLosipDsn00wL09ueze ItNz7baJh5blQBRlnL8CYSnmo2eWYadNww== X-Google-Smtp-Source: AGHT+IEiNtW/AYEnFWgw1kuSIysK4yf5Kl2eOUr965I4B/3sWjOv3kPWjVHIGoC5zO/lkGW9NHvGjQ== X-Received: by 2002:a05:600c:3c88:b0:40d:6582:e552 with SMTP id bg8-20020a05600c3c8800b0040d6582e552mr6943624wmb.9.1704303247501; Wed, 03 Jan 2024 09:34:07 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id o21-20020a05600c511500b0040d86e89abfsm2917164wms.43.2024.01.03.09.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:34:02 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 6E5185F955; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 23/43] target/riscv: Remove misa_mxl validation Date: Wed, 3 Jan 2024 17:33:29 +0000 Message-Id: <20240103173349.398526-24-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki It is initialized with a simple assignment and there is little room for error. In fact, the validation is even more complex. Signed-off-by: Akihiko Odaki Acked-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com> Signed-off-by: Alex Bennée --- target/riscv/tcg/tcg-cpu.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a345..ee17f65afb6 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -148,7 +148,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPUClass *cc = CPU_CLASS(mcc); @@ -168,11 +168,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) default: g_assert_not_reached(); } - - if (env->misa_mxl_max != env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } } static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) @@ -673,7 +668,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu = RISCV_CPU(cs); - Error *local_err = NULL; if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name = riscv_cpu_get_name(cpu); @@ -682,14 +676,11 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) return false; } - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return false; - } + riscv_cpu_validate_misa_mxl(cpu); #ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; + Error *local_err = NULL; CPU(cs)->tcg_cflags |= CF_PCREL; From patchwork Wed Jan 3 17:33:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510331 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D2761CA86 for ; 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Wed, 03 Jan 2024 09:39:08 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 8A9695F933; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 24/43] target/riscv: Move misa_mxl_max to class Date: Wed, 3 Jan 2024 17:33:30 +0000 Message-Id: <20240103173349.398526-25-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki Message-Id: <20231213-riscv-v7-3-a760156a337f@daynix.com> Signed-off-by: Alex Bennée Acked-by: Alistair Francis --- target/riscv/cpu.h | 4 +- target/riscv/cpu.c | 118 +++++++++++++++++++------------------ target/riscv/gdbstub.c | 12 ++-- target/riscv/kvm/kvm-cpu.c | 10 ++-- target/riscv/machine.c | 7 +-- target/riscv/tcg/tcg-cpu.c | 12 ++-- target/riscv/translate.c | 3 +- 7 files changed, 87 insertions(+), 79 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be64..060b7f69a74 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -169,7 +169,6 @@ struct CPUArchState { /* RISCVMXL, but uint32_t for vmstate migration */ uint32_t misa_mxl; /* current mxl */ - uint32_t misa_mxl_max; /* max mxl for this cpu */ uint32_t misa_ext; /* current extensions */ uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t xl; /* current xlen */ @@ -450,6 +449,7 @@ struct RISCVCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; + uint32_t misa_mxl_max; /* max mxl for this cpu */ }; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -756,7 +756,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07b..2ab61df2217 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -274,9 +274,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) { - env->misa_mxl_max = env->misa_mxl = mxl; env->misa_ext_mask = env->misa_ext = ext; } @@ -378,11 +377,7 @@ static void riscv_any_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; -#if defined(TARGET_RISCV32) - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); -#elif defined(TARGET_RISCV64) - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); -#endif + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), @@ -403,16 +398,14 @@ static void riscv_max_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; - RISCVMXL mlx = MXL_RV64; -#ifdef TARGET_RISCV32 - mlx = MXL_RV32; -#endif - riscv_cpu_set_misa(env, mlx, 0); env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); +#ifdef TARGET_RISCV32 + set_satp_mode_max_supported(cpu, VM_1_10_SV32); +#else + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif #endif } @@ -420,8 +413,6 @@ static void riscv_max_cpu_init(Object *obj) static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -433,8 +424,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; - riscv_cpu_set_misa(env, MXL_RV64, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -452,7 +442,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -469,7 +459,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); env->priv_ver = PRIV_VERSION_1_11_0; cpu->cfg.ext_zfa = true; @@ -500,7 +490,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); env->priv_ver = PRIV_VERSION_1_12_0; /* Enable ISA extensions */ @@ -544,8 +534,6 @@ static void rv128_base_cpu_init(Object *obj) exit(EXIT_FAILURE); } CPURISCVState *env = &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -556,8 +544,6 @@ static void rv128_base_cpu_init(Object *obj) static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -569,8 +555,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; - riscv_cpu_set_misa(env, MXL_RV32, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -588,7 +573,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -605,7 +590,7 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -622,7 +607,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -845,7 +830,7 @@ static void riscv_cpu_reset_hold(Object *obj) mcc->parent_phases.hold(obj); } #ifndef CONFIG_USER_ONLY - env->misa_mxl = env->misa_mxl_max; + env->misa_mxl = mcc->misa_mxl_max; env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { @@ -1213,6 +1198,12 @@ static void riscv_cpu_post_init(Object *obj) static void riscv_cpu_init(Object *obj) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj); + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + + env->misa_mxl = mcc->misa_mxl_max; + #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); @@ -1657,7 +1648,7 @@ static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, visit_type_bool(v, name, &value, errp); } -static void riscv_cpu_class_init(ObjectClass *c, void *data) +static void riscv_cpu_common_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); @@ -1699,6 +1690,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } +static void riscv_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); + + mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; +} + static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { @@ -1764,18 +1762,22 @@ void riscv_cpu_list(void) g_slist_free(list); } -#define DEFINE_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_CPU, \ - .instance_init = initfn \ +#define DEFINE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name = (type_name), \ + .parent = TYPE_RISCV_CPU, \ + .instance_init = (initfn), \ + .class_init = riscv_cpu_class_init, \ + .class_data = (void *)(misa_mxl_max) \ } -#define DEFINE_DYNAMIC_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_DYNAMIC_CPU, \ - .instance_init = initfn \ +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name = (type_name), \ + .parent = TYPE_RISCV_DYNAMIC_CPU, \ + .instance_init = (initfn), \ + .class_init = riscv_cpu_class_init, \ + .class_data = (void *)(misa_mxl_max) \ } static const TypeInfo riscv_cpu_type_infos[] = { @@ -1788,29 +1790,31 @@ static const TypeInfo riscv_cpu_type_infos[] = { .instance_post_init = riscv_cpu_post_init, .abstract = true, .class_size = sizeof(RISCVCPUClass), - .class_init = riscv_cpu_class_init, + .class_init = riscv_cpu_common_class_init, }, { .name = TYPE_RISCV_DYNAMIC_CPU, .parent = TYPE_RISCV_CPU, .abstract = true, }, - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 58b3ace0fe9..365040228a1 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -49,6 +49,7 @@ static const struct TypeSize vec_lanes[] = { int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; target_ulong tmp; @@ -61,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return 0; } - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -75,12 +76,13 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; int length = 0; target_ulong tmp; - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: tmp = (int32_t)ldl_p(mem_buf); length = 4; @@ -214,11 +216,12 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; GString *s = g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize = 16 << env->misa_mxl_max; + int bitsize = 16 << mcc->misa_mxl_max; int i; #if !defined(CONFIG_USER_ONLY) @@ -310,6 +313,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; if (env->misa_ext & RVD) { @@ -326,7 +330,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) ricsv_gen_dynamic_vector_xml(cs, base_reg), "riscv-vector.xml", 0); } - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 117e33cf90f..ed86f21b8f2 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1499,14 +1499,14 @@ static void kvm_cpu_accel_register_types(void) } type_init(kvm_cpu_accel_register_types); -static void riscv_host_cpu_init(Object *obj) +static void riscv_host_cpu_class_init(ObjectClass *c, void *data) { - CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); #if defined(TARGET_RISCV32) - env->misa_mxl_max = env->misa_mxl = MXL_RV32; + mcc->misa_mxl_max = MXL_RV32; #elif defined(TARGET_RISCV64) - env->misa_mxl_max = env->misa_mxl = MXL_RV64; + mcc->misa_mxl_max = MXL_RV64; #endif } @@ -1514,7 +1514,7 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = { { .name = TYPE_RISCV_CPU_HOST, .parent = TYPE_RISCV_CPU, - .instance_init = riscv_host_cpu_init, + .class_init = riscv_host_cpu_class_init, } }; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index fdde243e040..4c8d9a66595 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -178,10 +178,9 @@ static const VMStateDescription vmstate_pointermasking = { static bool rv128_needed(void *opaque) { - RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(opaque); - return env->misa_mxl_max == MXL_RV128; + return mcc->misa_mxl_max == MXL_RV128; } static const VMStateDescription vmstate_rv128 = { @@ -372,7 +371,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), VMSTATE_UINT32(env.misa_ext, RISCVCPU), - VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UNUSED(4), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_BOOL(env.virt_enabled, RISCVCPU), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ee17f65afb6..7f6712c81a4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -152,10 +152,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPUClass *cc = CPU_CLASS(mcc); - CPURISCVState *env = &cpu->env; /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: @@ -274,6 +273,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) */ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env = &cpu->env; Error *local_err = NULL; @@ -454,7 +454,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } @@ -462,7 +462,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { @@ -470,7 +470,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } - if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { + if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; } @@ -956,7 +956,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); + riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb160..7e383c5eebf 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1167,6 +1167,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cpu_env(cs); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); uint32_t tb_flags = ctx->base.tb->flags; @@ -1188,7 +1189,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 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Wed, 03 Jan 2024 09:49:05 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id A20015F932; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 25/43] target/riscv: Validate misa_mxl_max only once Date: Wed, 3 Jan 2024 17:33:31 +0000 Message-Id: <20240103173349.398526-26-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki Message-Id: <20231213-riscv-v7-4-a760156a337f@daynix.com> Signed-off-by: Alex Bennée Acked-by: Alistair Francis --- target/riscv/cpu.c | 21 +++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2ab61df2217..b799f133604 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1247,6 +1247,26 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), }; +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) +{ + CPUClass *cc = CPU_CLASS(mcc); + + /* Validate that MISA_MXL is set properly. */ + switch (mcc->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } +} + static int riscv_validate_misa_info_idx(uint32_t bit) { int idx; @@ -1695,6 +1715,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; + riscv_cpu_validate_misa_mxl(mcc); } static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7f6712c81a4..eb243e011ca 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -148,27 +148,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) -{ - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc = CPU_CLASS(mcc); - - /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } -} - static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) { CPURISCVState *env = &cpu->env; @@ -676,8 +655,6 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) return false; } - riscv_cpu_validate_misa_mxl(cpu); - #ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; Error *local_err = NULL; From patchwork Wed Jan 3 17:33:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510335 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 216AF1CAAE for ; Wed, 3 Jan 2024 17:39:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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Wed, 03 Jan 2024 09:39:13 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id BF7F05F957; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 26/43] target/arm: Use GDBFeature for dynamic XML Date: Wed, 3 Jan 2024 17:33:32 +0000 Message-Id: <20240103173349.398526-27-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Acked-by: Richard Henderson Message-Id: <20231213-gdb-v17-1-777047380591@daynix.com> Signed-off-by: Alex Bennée --- target/arm/cpu.h | 21 +++--- target/arm/internals.h | 2 +- target/arm/gdbstub.c | 142 ++++++++++++++++++++--------------------- target/arm/gdbstub64.c | 95 +++++++++++++-------------- 4 files changed, 123 insertions(+), 137 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0282e0d281..b2f8ac81f06 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,7 @@ #include "hw/registerfields.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/gdbstub.h" #include "qapi/qapi-types-common.h" /* ARM processors have a weak memory model */ @@ -136,23 +137,21 @@ enum { */ /** - * DynamicGDBXMLInfo: - * @desc: Contains the XML descriptions. - * @num: Number of the registers in this XML seen by GDB. + * DynamicGDBFeatureInfo: + * @desc: Contains the feature descriptions. * @data: A union with data specific to the set of registers * @cpregs_keys: Array that contains the corresponding Key of * a given cpreg with the same order of the cpreg * in the XML description. */ -typedef struct DynamicGDBXMLInfo { - char *desc; - int num; +typedef struct DynamicGDBFeatureInfo { + GDBFeature desc; union { struct { uint32_t *keys; } cpregs; } data; -} DynamicGDBXMLInfo; +} DynamicGDBFeatureInfo; /* CPU state for each instance of a generic timer (in cp15 c14) */ typedef struct ARMGenericTimer { @@ -878,10 +877,10 @@ struct ArchCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; - DynamicGDBXMLInfo dyn_sysreg_xml; - DynamicGDBXMLInfo dyn_svereg_xml; - DynamicGDBXMLInfo dyn_m_systemreg_xml; - DynamicGDBXMLInfo dyn_m_secextreg_xml; + DynamicGDBFeatureInfo dyn_sysreg_feature; + DynamicGDBFeatureInfo dyn_svereg_feature; + DynamicGDBFeatureInfo dyn_m_systemreg_feature; + DynamicGDBFeatureInfo dyn_m_secextreg_feature; /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/internals.h b/target/arm/internals.h index 143d57c0fe4..1136710741f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1446,7 +1446,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) } #ifdef TARGET_AARCH64 -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 28f546a5ff9..5949adfb31a 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -26,11 +26,11 @@ #include "cpu-features.h" #include "cpregs.h" -typedef struct RegisterSysregXmlParam { +typedef struct RegisterSysregFeatureParam { CPUState *cs; - GString *s; + GDBFeatureBuilder builder; int n; -} RegisterSysregXmlParam; +} RegisterSysregFeatureParam; /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect whatever the target description contains. Due to a historical mishap @@ -216,7 +216,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) const ARMCPRegInfo *ri; uint32_t key; - key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; + key = cpu->dyn_sysreg_feature.data.cpregs.keys[reg]; ri = get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { if (cpreg_field_is_64bit(ri)) { @@ -233,34 +233,32 @@ static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, +static void arm_gen_one_feature_sysreg(GDBFeatureBuilder *builder, + DynamicGDBFeatureInfo *dyn_feature, ARMCPRegInfo *ri, uint32_t ri_key, - int bitsize, int regnum) + int bitsize, int n) { - g_string_append_printf(s, "name); - g_string_append_printf(s, " bitsize=\"%d\"", bitsize); - g_string_append_printf(s, " regnum=\"%d\"", regnum); - g_string_append_printf(s, " group=\"cp_regs\"/>"); - dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key; - dyn_xml->num++; + gdb_feature_builder_append_reg(builder, ri->name, bitsize, n, + "int", "cp_regs"); + + dyn_feature->data.cpregs.keys[n] = ri_key; } -static void arm_register_sysreg_for_xml(gpointer key, gpointer value, - gpointer p) +static void arm_register_sysreg_for_feature(gpointer key, gpointer value, + gpointer p) { uint32_t ri_key = (uintptr_t)key; ARMCPRegInfo *ri = value; - RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p; - GString *s = param->s; + RegisterSysregFeatureParam *param = p; ARMCPU *cpu = ARM_CPU(param->cs); CPUARMState *env = &cpu->env; - DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml; + DynamicGDBFeatureInfo *dyn_feature = &cpu->dyn_sysreg_feature; if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state == ARM_CP_STATE_AA64) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, - param->n++); + arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, + ri, ri_key, 64, param->n++); } } else { if (ri->state == ARM_CP_STATE_AA32) { @@ -269,32 +267,32 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, return; } if (ri->type & ARM_CP_64BIT) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, - param->n++); + arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, + ri, ri_key, 64, param->n++); } else { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32, - param->n++); + arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, + ri, ri_key, 32, param->n++); } } } } } -static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) +static GDBFeature *arm_gen_dynamic_sysreg_feature(CPUState *cs, int base_reg) { ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - RegisterSysregXmlParam param = {cs, s, base_reg}; - - cpu->dyn_sysreg_xml.num = 0; - cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); - g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m); - g_string_append_printf(s, ""); - cpu->dyn_sysreg_xml.desc = g_string_free(s, false); - return cpu->dyn_sysreg_xml.num; + RegisterSysregFeatureParam param = {cs}; + gsize num_regs = g_hash_table_size(cpu->cp_regs); + + gdb_feature_builder_init(¶m.builder, + &cpu->dyn_sysreg_feature.desc, + "org.qemu.gdb.arm.sys.regs", + "system-registers.xml", + base_reg); + cpu->dyn_sysreg_feature.data.cpregs.keys = g_new(uint32_t, num_regs); + g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_feature, ¶m); + gdb_feature_builder_end(¶m.builder); + return &cpu->dyn_sysreg_feature.desc; } #ifdef CONFIG_TCG @@ -386,31 +384,29 @@ static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) return 0; /* TODO */ } -static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg) +static GDBFeature *arm_gen_dynamic_m_systemreg_feature(CPUState *cs, + int base_reg) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - GString *s = g_string_new(NULL); - int base_reg = orig_base_reg; + GDBFeatureBuilder builder; + int reg = 0; int i; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, "\n"); + gdb_feature_builder_init(&builder, &cpu->dyn_m_systemreg_feature.desc, + "org.gnu.gdb.arm.m-system", "arm-m-system.xml", + base_reg); for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { if (arm_feature(env, m_sysreg_def[i].feature)) { - g_string_append_printf(s, - "\n", - m_sysreg_def[i].name, base_reg++); + gdb_feature_builder_append_reg(&builder, m_sysreg_def[i].name, 32, + reg++, "int", NULL); } } - g_string_append_printf(s, ""); - cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false); - cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg; + gdb_feature_builder_end(&builder); - return cpu->dyn_m_systemreg_xml.num; + return &cpu->dyn_m_systemreg_feature.desc; } #ifndef CONFIG_USER_ONLY @@ -428,31 +424,31 @@ static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) return 0; /* TODO */ } -static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg) +static GDBFeature *arm_gen_dynamic_m_secextreg_feature(CPUState *cs, + int base_reg) { ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - int base_reg = orig_base_reg; + GDBFeatureBuilder builder; + char *name; + int reg = 0; int i; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, "\n"); + gdb_feature_builder_init(&builder, &cpu->dyn_m_secextreg_feature.desc, + "org.gnu.gdb.arm.secext", "arm-m-secext.xml", + base_reg); for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { - g_string_append_printf(s, - "\n", - m_sysreg_def[i].name, base_reg++); - g_string_append_printf(s, - "\n", - m_sysreg_def[i].name, base_reg++); + name = g_strconcat(m_sysreg_def[i].name, "_ns", NULL); + gdb_feature_builder_append_reg(&builder, name, 32, reg++, + "int", NULL); + name = g_strconcat(m_sysreg_def[i].name, "_s", NULL); + gdb_feature_builder_append_reg(&builder, name, 32, reg++, + "int", NULL); } - g_string_append_printf(s, ""); - cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false); - cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg; + gdb_feature_builder_end(&builder); - return cpu->dyn_m_secextreg_xml.num; + return &cpu->dyn_m_secextreg_feature.desc; } #endif #endif /* CONFIG_TCG */ @@ -462,14 +458,14 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) ARMCPU *cpu = ARM_CPU(cs); if (strcmp(xmlname, "system-registers.xml") == 0) { - return cpu->dyn_sysreg_xml.desc; + return cpu->dyn_sysreg_feature.desc.xml; } else if (strcmp(xmlname, "sve-registers.xml") == 0) { - return cpu->dyn_svereg_xml.desc; + return cpu->dyn_svereg_feature.desc.xml; } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { - return cpu->dyn_m_systemreg_xml.desc; + return cpu->dyn_m_systemreg_feature.desc.xml; #ifndef CONFIG_USER_ONLY } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) { - return cpu->dyn_m_secextreg_xml.desc; + return cpu->dyn_m_secextreg_feature.desc.xml; #endif } return NULL; @@ -487,7 +483,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) */ #ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { - int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs); + int nreg = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs)->num_regs; gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, nreg, "sve-registers.xml", 0); @@ -533,20 +529,20 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 1, "arm-m-profile-mve.xml", 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), + arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs)->num_regs, "system-registers.xml", 0); #ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, - arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), + arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)->num_regs, "arm-m-system.xml", 0); #ifndef CONFIG_USER_ONLY if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { gdb_register_coprocessor(cs, arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, - arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs), + arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)->num_regs, "arm-m-secext.xml", 0); } #endif diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d7b79a6589b..5286d5c6043 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -247,7 +247,7 @@ int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static void output_vector_union_type(GString *s, int reg_width, +static void output_vector_union_type(GDBFeatureBuilder *builder, int reg_width, const char *name) { struct TypeSize { @@ -282,10 +282,10 @@ static void output_vector_union_type(GString *s, int reg_width, /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - g_string_append_printf(s, - "", - name, vec_lanes[i].sz, vec_lanes[i].suffix, - vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); + gdb_feature_builder_append_tag( + builder, "", + name, vec_lanes[i].sz, vec_lanes[i].suffix, + vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); } /* @@ -296,86 +296,77 @@ static void output_vector_union_type(GString *s, int reg_width, for (i = 0; i < ARRAY_SIZE(suf); i++) { int bits = 8 << i; - g_string_append_printf(s, "", name, suf[i]); + gdb_feature_builder_append_tag(builder, "", + name, suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { - g_string_append_printf(s, "", - vec_lanes[j].suffix, name, - vec_lanes[j].sz, vec_lanes[j].suffix); + gdb_feature_builder_append_tag( + builder, "", + vec_lanes[j].suffix, name, + vec_lanes[j].sz, vec_lanes[j].suffix); } } - g_string_append(s, ""); + gdb_feature_builder_append_tag(builder, ""); } /* And now the final union of unions */ - g_string_append_printf(s, "", name); + gdb_feature_builder_append_tag(builder, "", name); for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) { - g_string_append_printf(s, "", - suf[i], name, suf[i]); + gdb_feature_builder_append_tag(builder, + "", + suf[i], name, suf[i]); } - g_string_append(s, ""); + gdb_feature_builder_append_tag(builder, ""); } -int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) +GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg) { ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; int reg_width = cpu->sve_max_vq * 128; int pred_width = cpu->sve_max_vq * 16; - int base_reg = orig_base_reg; + GDBFeatureBuilder builder; + char *name; + int reg = 0; int i; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_svereg_feature.desc, + "org.gnu.gdb.aarch64.sve", "sve-registers.xml", + base_reg); /* Create the vector union type. */ - output_vector_union_type(s, reg_width, "svev"); + output_vector_union_type(&builder, reg_width, "svev"); /* Create the predicate vector type. */ - g_string_append_printf(s, - "", - pred_width / 8); + gdb_feature_builder_append_tag( + &builder, "", + pred_width / 8); /* Define the vector registers. */ for (i = 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); + name = g_strdup_printf("z%d", i); + gdb_feature_builder_append_reg(&builder, name, reg_width, reg++, + "svev", NULL); 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Wed, 03 Jan 2024 09:34:05 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id bg40-20020a05600c3ca800b0040d87b5a87csm2886253wmb.48.2024.01.03.09.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:34:02 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id D8A215F95A; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 27/43] target/ppc: Use GDBFeature for dynamic XML Date: Wed, 3 Jan 2024 17:33:33 +0000 Message-Id: <20240103173349.398526-28-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Richard Henderson Message-Id: <20231213-gdb-v17-2-777047380591@daynix.com> Signed-off-by: Alex Bennée --- target/ppc/cpu-qom.h | 1 + target/ppc/cpu.h | 4 +--- target/ppc/cpu_init.c | 4 ---- target/ppc/gdbstub.c | 51 ++++++++++++++++--------------------------- 4 files changed, 21 insertions(+), 39 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 0241609efef..8247fa23367 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -20,6 +20,7 @@ #ifndef QEMU_PPC_CPU_QOM_H #define QEMU_PPC_CPU_QOM_H +#include "exec/gdbstub.h" #include "hw/core/cpu.h" #ifdef TARGET_PPC64 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa296..f87c26f98a6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1471,8 +1471,7 @@ struct PowerPCCPUClass { int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; #ifndef CONFIG_USER_ONLY - unsigned int gdb_num_sprs; - const char *gdb_spr_xml; + GDBFeature gdb_spr; #endif const PPCHash64Options *hash64_opts; struct ppc_radix_page_info *radix_page_info; @@ -1525,7 +1524,6 @@ int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); #ifndef CONFIG_USER_ONLY hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu); const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); #endif int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 40fe14a6c25..a0178c3ce80 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6682,10 +6682,6 @@ static void init_ppc_proc(PowerPCCPU *cpu) /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ (*pcc->init_proc)(env); -#if !defined(CONFIG_USER_ONLY) - ppc_gdb_gen_spr_xml(cpu); -#endif - /* MSR bits & flags consistency checks */ if (env->msr_mask & (1 << 25)) { switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index ec5731e5d67..e3be3dbd109 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -300,15 +300,23 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) } #ifndef CONFIG_USER_ONLY -void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu) +static void gdb_gen_spr_feature(CPUState *cs) { - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); + PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - GString *xml; - char *spr_name; + GDBFeatureBuilder builder; unsigned int num_regs = 0; int i; + if (pcc->gdb_spr.xml) { + return; + } + + gdb_feature_builder_init(&builder, &pcc->gdb_spr, + "org.qemu.power.spr", "power-spr.xml", + cs->gdb_num_regs); + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; @@ -326,35 +334,13 @@ void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu) */ spr->gdb_id = num_regs; num_regs++; - } - - if (pcc->gdb_spr_xml) { - return; - } - xml = g_string_new(""); - g_string_append(xml, ""); - g_string_append(xml, ""); - - for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { - ppc_spr_t *spr = &env->spr_cb[i]; - - if (!spr->name) { - continue; - } - - spr_name = g_ascii_strdown(spr->name, -1); - g_string_append_printf(xml, ""); + gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1), + TARGET_LONG_BITS, num_regs, + "int", "spr"); } - g_string_append(xml, ""); - - pcc->gdb_num_sprs = num_regs; - pcc->gdb_spr_xml = g_string_free(xml, false); + gdb_feature_builder_end(&builder); } const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name) @@ -362,7 +348,7 @@ const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); if (strcmp(xml_name, "power-spr.xml") == 0) { - return pcc->gdb_spr_xml; + return pcc->gdb_spr.xml; } return NULL; } @@ -599,7 +585,8 @@ void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) 32, "power-vsx.xml", 0); } #ifndef CONFIG_USER_ONLY + gdb_gen_spr_feature(cs); gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, - pcc->gdb_num_sprs, "power-spr.xml", 0); + pcc->gdb_spr.num_regs, "power-spr.xml", 0); #endif } From patchwork Wed Jan 3 17:33:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510300 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 172491D69B for ; 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Wed, 03 Jan 2024 09:34:02 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id EF90E5F95C; Wed, 3 Jan 2024 17:33:51 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 28/43] target/riscv: Use GDBFeature for dynamic XML Date: Wed, 3 Jan 2024 17:33:34 +0000 Message-Id: <20240103173349.398526-29-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-3-777047380591@daynix.com> Signed-off-by: Alex Bennée --- target/riscv/cpu.h | 5 +-- target/riscv/cpu.c | 4 +-- target/riscv/gdbstub.c | 79 +++++++++++++++++++----------------------- 3 files changed, 40 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 060b7f69a74..ad7236d7547 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,6 +24,7 @@ #include "hw/registerfields.h" #include "hw/qdev-properties.h" #include "exec/cpu-defs.h" +#include "exec/gdbstub.h" #include "qemu/cpu-float.h" #include "qom/object.h" #include "qemu/int128.h" @@ -424,8 +425,8 @@ struct ArchCPU { CPURISCVState env; - char *dyn_csr_xml; - char *dyn_vreg_xml; + GDBFeature dyn_csr_feature; + GDBFeature dyn_vreg_feature; /* Configuration Settings */ RISCVCPUConfig cfg; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b799f133604..673e937a5d8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1534,9 +1534,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) RISCVCPU *cpu = RISCV_CPU(cs); if (strcmp(xmlname, "riscv-csr.xml") == 0) { - return cpu->dyn_csr_xml; + return cpu->dyn_csr_feature.xml; } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { - return cpu->dyn_vreg_xml; + return cpu->dyn_vreg_feature.xml; } return NULL; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 365040228a1..76b72a95954 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -214,13 +214,14 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) return 0; } -static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) +static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - GString *s = g_string_new(NULL); + GDBFeatureBuilder builder; riscv_csr_predicate_fn predicate; + const char *name; int bitsize = 16 << mcc->misa_mxl_max; int i; @@ -233,9 +234,9 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) bitsize = 64; } - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature, + "org.gnu.gdb.riscv.csr", "riscv-csr.xml", + base_reg); for (i = 0; i < CSR_TABLE_SIZE; i++) { if (env->priv_ver < csr_ops[i].min_priv_ver) { @@ -243,72 +244,64 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) } predicate = csr_ops[i].predicate; if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) { - if (csr_ops[i].name) { - g_string_append_printf(s, "", base_reg + i); + + gdb_feature_builder_append_reg(&builder, name, bitsize, i, + "int", NULL); } } - g_string_append_printf(s, ""); - - cpu->dyn_csr_xml = g_string_free(s, false); + gdb_feature_builder_end(&builder); #if !defined(CONFIG_USER_ONLY) env->debugger = false; #endif - return CSR_TABLE_SIZE; + return &cpu->dyn_csr_feature; } -static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) { RISCVCPU *cpu = RISCV_CPU(cs); - GString *s = g_string_new(NULL); - g_autoptr(GString) ts = g_string_new(""); + GDBFeatureBuilder builder; int reg_width = cpu->cfg.vlen; - int num_regs = 0; int i; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature, + "org.gnu.gdb.riscv.vector", "riscv-vector.xml", + base_reg); /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "%s", vec_lanes[i].id); - g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); + gdb_feature_builder_append_tag( + &builder, "", + vec_lanes[i].id, vec_lanes[i].gdb_type, count); } /* Define unions */ - g_string_append_printf(s, ""); + gdb_feature_builder_append_tag(&builder, ""); for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - g_string_append_printf(s, "", - vec_lanes[i].suffix, - vec_lanes[i].id); + gdb_feature_builder_append_tag(&builder, + "", + vec_lanes[i].suffix, vec_lanes[i].id); } - g_string_append(s, ""); + gdb_feature_builder_append_tag(&builder, ""); /* Define vector registers */ for (i = 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); - num_regs++; + gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i), + reg_width, i, "riscv_vector", "vector"); } - g_string_append_printf(s, ""); + gdb_feature_builder_end(&builder); - cpu->dyn_vreg_xml = g_string_free(s, false); - return num_regs; + return &cpu->dyn_vreg_feature; } void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) @@ -324,10 +317,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) 32, "riscv-32bit-fpu.xml", 0); } if (env->misa_ext & RVV) { - int base_reg = cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_xml(cs, base_reg), + ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs, "riscv-vector.xml", 0); } switch (mcc->misa_mxl_max) { @@ -347,9 +339,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } if (cpu->cfg.ext_zicsr) { - int base_reg = cs->gdb_num_regs; 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Wed, 3 Jan 2024 17:33:52 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 29/43] gdbstub: Use GDBFeature for gdb_register_coprocessor Date: Wed, 3 Jan 2024 17:33:35 +0000 Message-Id: <20240103173349.398526-30-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki This is a tree-wide change to introduce GDBFeature parameter to gdb_register_coprocessor(). The new parameter just replaces num_regs and xml parameters for now. GDBFeature will be utilized to simplify XML lookup in a following change. Signed-off-by: Akihiko Odaki Acked-by: Alex Bennée Message-Id: <20231213-gdb-v17-4-777047380591@daynix.com> Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 2 +- gdbstub/gdbstub.c | 13 +++++++------ target/arm/gdbstub.c | 35 +++++++++++++++++++---------------- target/hexagon/cpu.c | 3 +-- target/loongarch/gdbstub.c | 2 +- target/m68k/helper.c | 6 +++--- target/microblaze/cpu.c | 5 +++-- target/ppc/gdbstub.c | 11 ++++++----- target/riscv/gdbstub.c | 20 ++++++++++++-------- target/s390x/gdbstub.c | 28 +++++++--------------------- 10 files changed, 60 insertions(+), 65 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index d8a3c56fa2b..ac6fce99a64 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -38,7 +38,7 @@ typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); */ void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, - int num_regs, const char *xml, int g_pos); + const GDBFeature *feature, int g_pos); /** * gdbserver_start: start the gdb server diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 46d752bbc2c..068180c83c7 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -544,7 +544,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, - int num_regs, const char *xml, int g_pos) + const GDBFeature *feature, int g_pos) { GDBRegisterState *s; guint i; @@ -553,7 +553,7 @@ void gdb_register_coprocessor(CPUState *cpu, for (i = 0; i < cpu->gdb_regs->len; i++) { /* Check for duplicates. */ s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (strcmp(s->xml, xml) == 0) { + if (strcmp(s->xml, feature->xmlname) == 0) { return; } } @@ -565,17 +565,18 @@ void gdb_register_coprocessor(CPUState *cpu, g_array_set_size(cpu->gdb_regs, i + 1); s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); s->base_reg = cpu->gdb_num_regs; - s->num_regs = num_regs; + s->num_regs = feature->num_regs; s->get_reg = get_reg; s->set_reg = set_reg; - s->xml = xml; + s->xml = feature->xml; /* Add to end of list. */ - cpu->gdb_num_regs += num_regs; + cpu->gdb_num_regs += feature->num_regs; if (g_pos) { if (g_pos != s->base_reg) { error_report("Error: Bad gdb register numbering for '%s', " - "expected %d got %d", xml, g_pos, s->base_reg); + "expected %d got %d", feature->xml, + g_pos, s->base_reg); } else { cpu->gdb_num_g_regs = cpu->gdb_num_regs; } diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 5949adfb31a..f2b201d3125 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -483,14 +483,14 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) */ #ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { - int nreg = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs)->num_regs; + GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, - aarch64_gdb_set_sve_reg, nreg, - "sve-registers.xml", 0); + aarch64_gdb_set_sve_reg, feature, 0); } else { gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, aarch64_gdb_set_fpu_reg, - 34, "aarch64-fpu.xml", 0); + gdb_find_static_feature("aarch64-fpu.xml"), + 0); } /* * Note that we report pauth information via the feature name @@ -501,19 +501,22 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) if (isar_feature_aa64_pauth(&cpu->isar)) { gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, aarch64_gdb_set_pauth_reg, - 4, "aarch64-pauth.xml", 0); + gdb_find_static_feature("aarch64-pauth.xml"), + 0); } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 49, "arm-neon.xml", 0); + gdb_find_static_feature("arm-neon.xml"), + 0); } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 33, "arm-vfp3.xml", 0); + gdb_find_static_feature("arm-vfp3.xml"), + 0); } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 17, "arm-vfp.xml", 0); + gdb_find_static_feature("arm-vfp.xml"), 0); } if (!arm_feature(env, ARM_FEATURE_M)) { /* @@ -521,29 +524,29 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) * expose to gdb. */ gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg, - 2, "arm-vfp-sysregs.xml", 0); + gdb_find_static_feature("arm-vfp-sysregs.xml"), + 0); } } if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) { gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, - 1, "arm-m-profile-mve.xml", 0); + gdb_find_static_feature("arm-m-profile-mve.xml"), + 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs)->num_regs, - "system-registers.xml", 0); + arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs), + 0); #ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, - arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)->num_regs, - "arm-m-system.xml", 0); + arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs), 0); #ifndef CONFIG_USER_ONLY if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { gdb_register_coprocessor(cs, arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, - arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)->num_regs, - "arm-m-secext.xml", 0); + arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs), 0); } #endif } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 9d1ffc3b4bb..65ac9c75ad0 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -341,8 +341,7 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, hexagon_hvx_gdb_write_register, - NUM_VREGS + NUM_QREGS, - "hexagon-hvx.xml", 0); + gdb_find_static_feature("hexagon-hvx.xml"), 0); qemu_init_vcpu(cs); cpu_reset(cs); diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 5fc2f19e965..843a869450e 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -118,5 +118,5 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env, void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs) { gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu, - 41, "loongarch-fpu.xml", 0); + gdb_find_static_feature("loongarch-fpu.xml"), 0); } diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 0a1544cd68d..675f2dcd5ad 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -152,10 +152,10 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) if (m68k_feature(env, M68K_FEATURE_CF_FPU)) { gdb_register_coprocessor(cs, cf_fpu_gdb_get_reg, cf_fpu_gdb_set_reg, - 11, "cf-fp.xml", 18); + gdb_find_static_feature("cf-fp.xml"), 18); } else if (m68k_feature(env, M68K_FEATURE_FPU)) { - gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, - m68k_fpu_gdb_set_reg, 11, "m68k-fp.xml", 18); + gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, m68k_fpu_gdb_set_reg, + gdb_find_static_feature("m68k-fp.xml"), 18); } /* TODO: Add [E]MAC registers. */ } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cadd..1998f69828f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -297,8 +297,9 @@ static void mb_cpu_initfn(Object *obj) CPUMBState *env = &cpu->env; gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, - mb_cpu_gdb_write_stack_protect, 2, - "microblaze-stack-protect.xml", 0); + mb_cpu_gdb_write_stack_protect, + gdb_find_static_feature("microblaze-stack-protect.xml"), + 0); set_float_rounding_mode(float_round_nearest_even, &env->fp_status); diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index e3be3dbd109..09b852464f3 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -570,23 +570,24 @@ void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) { if (pcc->insns_flags & PPC_FLOAT) { gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, - 33, "power-fpu.xml", 0); + gdb_find_static_feature("power-fpu.xml"), 0); } if (pcc->insns_flags & PPC_ALTIVEC) { gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, - 34, "power-altivec.xml", 0); + gdb_find_static_feature("power-altivec.xml"), + 0); } if (pcc->insns_flags & PPC_SPE) { gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, - 34, "power-spe.xml", 0); + gdb_find_static_feature("power-spe.xml"), 0); } if (pcc->insns_flags2 & PPC2_VSX) { gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, - 32, "power-vsx.xml", 0); + gdb_find_static_feature("power-vsx.xml"), 0); } #ifndef CONFIG_USER_ONLY gdb_gen_spr_feature(cs); gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, - pcc->gdb_spr.num_regs, "power-spr.xml", 0); + &pcc->gdb_spr, 0); #endif } diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 76b72a95954..a879869fa1a 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -311,28 +311,32 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) CPURISCVState *env = &cpu->env; if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 32, "riscv-64bit-fpu.xml", 0); + gdb_find_static_feature("riscv-64bit-fpu.xml"), + 0); } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 32, "riscv-32bit-fpu.xml", 0); + gdb_find_static_feature("riscv-32bit-fpu.xml"), + 0); } if (env->misa_ext & RVV) { gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs, - "riscv-vector.xml", 0); + ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs), + 0); } switch (mcc->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, - 1, "riscv-32bit-virtual.xml", 0); + gdb_find_static_feature("riscv-32bit-virtual.xml"), + 0); break; case MXL_RV64: case MXL_RV128: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, - 1, "riscv-64bit-virtual.xml", 0); + gdb_find_static_feature("riscv-64bit-virtual.xml"), + 0); break; default: g_assert_not_reached(); @@ -340,7 +344,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) if (cpu->cfg.ext_zicsr) { gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)->num_regs, - "riscv-csr.xml", 0); + riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs), + 0); } } diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6fbfd41bc86..02c388dc323 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -69,8 +69,6 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* the values represent the positions in s390-acr.xml */ #define S390_A0_REGNUM 0 #define S390_A15_REGNUM 15 -/* total number of registers in s390-acr.xml */ -#define S390_NUM_AC_REGS 16 static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -98,8 +96,6 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_FPC_REGNUM 0 #define S390_F0_REGNUM 1 #define S390_F15_REGNUM 16 -/* total number of registers in s390-fpr.xml */ -#define S390_NUM_FP_REGS 17 static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -132,8 +128,6 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_V15L_REGNUM 15 #define S390_V16_REGNUM 16 #define S390_V31_REGNUM 31 -/* total number of registers in s390-vx.xml */ -#define S390_NUM_VREGS 32 static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) { @@ -172,8 +166,6 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) /* the values represent the positions in s390-cr.xml */ #define S390_C0_REGNUM 0 #define S390_C15_REGNUM 15 -/* total number of registers in s390-cr.xml */ -#define S390_NUM_C_REGS 16 #ifndef CONFIG_USER_ONLY static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) @@ -206,8 +198,6 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_VIRT_CPUTM_REGNUM 1 #define S390_VIRT_BEA_REGNUM 2 #define S390_VIRT_PREFIX_REGNUM 3 -/* total number of registers in s390-virt.xml */ -#define S390_NUM_VIRT_REGS 4 static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n) { @@ -254,8 +244,6 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_VIRT_KVM_PFT_REGNUM 1 #define S390_VIRT_KVM_PFS_REGNUM 2 #define S390_VIRT_KVM_PFC_REGNUM 3 -/* total number of registers in s390-virt-kvm.xml */ -#define S390_NUM_VIRT_KVM_REGS 4 static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, int n) { @@ -303,8 +291,6 @@ static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_GS_GSD_REGNUM 1 #define S390_GS_GSSM_REGNUM 2 #define S390_GS_GSEPLA_REGNUM 3 -/* total number of registers in s390-gs.xml */ -#define S390_NUM_GS_REGS 4 static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -322,33 +308,33 @@ void s390_cpu_gdb_init(CPUState *cs) { gdb_register_coprocessor(cs, cpu_read_ac_reg, cpu_write_ac_reg, - S390_NUM_AC_REGS, "s390-acr.xml", 0); + gdb_find_static_feature("s390-acr.xml"), 0); gdb_register_coprocessor(cs, cpu_read_fp_reg, cpu_write_fp_reg, - S390_NUM_FP_REGS, "s390-fpr.xml", 0); + gdb_find_static_feature("s390-fpr.xml"), 0); gdb_register_coprocessor(cs, cpu_read_vreg, cpu_write_vreg, - S390_NUM_VREGS, "s390-vx.xml", 0); + gdb_find_static_feature("s390-vx.xml"), 0); gdb_register_coprocessor(cs, cpu_read_gs_reg, cpu_write_gs_reg, - S390_NUM_GS_REGS, "s390-gs.xml", 0); + gdb_find_static_feature("s390-gs.xml"), 0); #ifndef CONFIG_USER_ONLY gdb_register_coprocessor(cs, cpu_read_c_reg, cpu_write_c_reg, - S390_NUM_C_REGS, "s390-cr.xml", 0); + gdb_find_static_feature("s390-cr.xml"), 0); gdb_register_coprocessor(cs, cpu_read_virt_reg, cpu_write_virt_reg, - S390_NUM_VIRT_REGS, "s390-virt.xml", 0); + gdb_find_static_feature("s390-virt.xml"), 0); if (kvm_enabled()) { gdb_register_coprocessor(cs, cpu_read_virt_kvm_reg, cpu_write_virt_kvm_reg, - S390_NUM_VIRT_KVM_REGS, "s390-virt-kvm.xml", + gdb_find_static_feature("s390-virt-kvm.xml"), 0); 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Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 30/43] gdbstub: Use GDBFeature for GDBRegisterState Date: Wed, 3 Jan 2024 17:33:36 +0000 Message-Id: <20240103173349.398526-31-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki Simplify GDBRegisterState by replacing num_regs and xml members with one member that points to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Bennée Message-Id: <20231213-gdb-v17-5-777047380591@daynix.com> Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- gdbstub/gdbstub.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 068180c83c7..a80729436b6 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -47,10 +47,9 @@ typedef struct GDBRegisterState { int base_reg; - int num_regs; gdb_get_reg_cb get_reg; gdb_set_reg_cb set_reg; - const char *xml; + const GDBFeature *feature; } GDBRegisterState; GDBState gdbserver_state; @@ -391,7 +390,7 @@ static const char *get_feature_xml(const char *p, const char **newp, g_ptr_array_add( xml, g_markup_printf_escaped("", - r->xml)); + r->feature->xmlname)); } } g_ptr_array_add(xml, g_strdup("")); @@ -513,7 +512,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) if (cpu->gdb_regs) { for (guint i = 0; i < cpu->gdb_regs->len; i++) { r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { + if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) { return r->get_reg(env, buf, reg - r->base_reg); } } @@ -534,7 +533,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) if (cpu->gdb_regs) { for (guint i = 0; i < cpu->gdb_regs->len; i++) { r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) { + if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) { return r->set_reg(env, mem_buf, reg - r->base_reg); } } @@ -553,7 +552,7 @@ void gdb_register_coprocessor(CPUState *cpu, for (i = 0; i < cpu->gdb_regs->len; i++) { /* Check for duplicates. */ s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (strcmp(s->xml, feature->xmlname) == 0) { + if (s->feature == feature) { return; } } @@ -565,10 +564,9 @@ void gdb_register_coprocessor(CPUState *cpu, g_array_set_size(cpu->gdb_regs, i + 1); s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); s->base_reg = cpu->gdb_num_regs; - s->num_regs = feature->num_regs; s->get_reg = get_reg; s->set_reg = set_reg; - s->xml = feature->xml; + s->feature = feature; /* Add to end of list. */ cpu->gdb_num_regs += feature->num_regs; From patchwork Wed Jan 3 17:33:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510301 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 973581D6A7 for ; Wed, 3 Jan 2024 17:34:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XhNPzaPN" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-40d4f5d902dso94506835e9.2 for ; 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Wed, 3 Jan 2024 17:33:52 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 31/43] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb Date: Wed, 3 Jan 2024 17:33:37 +0000 Message-Id: <20240103173349.398526-32-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the gdb_read_register and gdb_write_register members of CPUClass to allow to unify the logic to access registers of the core and coprocessors in the future. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Bennée Message-Id: <20231213-gdb-v17-6-777047380591@daynix.com> Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 4 +- target/arm/internals.h | 12 +++--- target/hexagon/internal.h | 4 +- target/microblaze/cpu.h | 4 +- gdbstub/gdbstub.c | 6 +-- target/arm/gdbstub.c | 51 ++++++++++++++++-------- target/arm/gdbstub64.c | 27 +++++++++---- target/hexagon/gdbstub.c | 10 ++++- target/loongarch/gdbstub.c | 11 ++++-- target/m68k/helper.c | 20 ++++++++-- target/microblaze/gdbstub.c | 9 ++++- target/ppc/gdbstub.c | 46 +++++++++++++++++----- target/riscv/gdbstub.c | 46 ++++++++++++++++------ target/s390x/gdbstub.c | 77 ++++++++++++++++++++++++++++--------- 14 files changed, 236 insertions(+), 91 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index ac6fce99a64..bcaab1bc750 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -24,8 +24,8 @@ typedef struct GDBFeatureBuilder { /* Get or set a register. Returns the size of the register. */ -typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg); -typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); +typedef int (*gdb_get_reg_cb)(CPUState *cpu, GByteArray *buf, int reg); +typedef int (*gdb_set_reg_cb)(CPUState *cpu, uint8_t *buf, int reg); /** * gdb_register_coprocessor() - register a supplemental set of registers diff --git a/target/arm/internals.h b/target/arm/internals.h index 1136710741f..a08f461f444 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1447,12 +1447,12 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) #ifdef TARGET_AARCH64 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); -int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index d732b6bb3c7..beb08cb7e38 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -33,8 +33,8 @@ int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n); -int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n); +int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int n); +int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n); void hexagon_debug_vreg(CPUHexagonState *env, int regnum); void hexagon_debug_qreg(CPUHexagonState *env, int regnum); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5f..1906d8f266a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -381,8 +381,8 @@ G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int reg); -int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int reg); +int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *buf, int reg); +int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *buf, int reg); static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) { diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index a80729436b6..21fea7fffae 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -502,7 +502,6 @@ const GDBFeature *gdb_find_static_feature(const char *xmlname) static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); - CPUArchState *env = cpu_env(cpu); GDBRegisterState *r; if (reg < cc->gdb_num_core_regs) { @@ -513,7 +512,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) for (guint i = 0; i < cpu->gdb_regs->len; i++) { r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) { - return r->get_reg(env, buf, reg - r->base_reg); + return r->get_reg(cpu, buf, reg - r->base_reg); } } } @@ -523,7 +522,6 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); - CPUArchState *env = cpu_env(cpu); GDBRegisterState *r; if (reg < cc->gdb_num_core_regs) { @@ -534,7 +532,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) for (guint i = 0; i < cpu->gdb_regs->len; i++) { r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) { - return r->set_reg(env, mem_buf, reg - r->base_reg); + return r->set_reg(cpu, mem_buf, reg - r->base_reg); } } } diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index f2b201d3125..059d84f98e5 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -106,9 +106,10 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +static int vfp_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu = env_archcpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; /* VFP data registers are always little-endian. */ @@ -130,9 +131,10 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) return 0; } -static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +static int vfp_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg) { - ARMCPU *cpu = env_archcpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; if (reg < nregs) { @@ -156,8 +158,11 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +static int vfp_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + switch (reg) { case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); @@ -167,8 +172,11 @@ static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) return 0; } -static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +static int vfp_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + switch (reg) { case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); @@ -180,8 +188,11 @@ static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +static int mve_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + switch (reg) { case 0: return gdb_get_reg32(buf, env->v7m.vpr); @@ -190,8 +201,11 @@ static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) } } -static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +static int mve_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + switch (reg) { case 0: env->v7m.vpr = ldl_p(buf); @@ -210,9 +224,10 @@ static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) * We return the number of bytes copied */ -static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +static int arm_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu = env_archcpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; const ARMCPRegInfo *ri; uint32_t key; @@ -228,7 +243,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) return 0; } -static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg) { return 0; } @@ -367,8 +382,11 @@ static int m_sysreg_get(CPUARMState *env, GByteArray *buf, return gdb_get_reg32(buf, *ptr); } -static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg) +static int arm_gdb_get_m_systemreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + /* * Here, we emulate MRS instruction, where CONTROL has a mix of * banked and non-banked bits. @@ -379,7 +397,7 @@ static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg) return m_sysreg_get(env, buf, reg, env->v7m.secure); } -static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_m_systemreg(CPUState *cs, uint8_t *buf, int reg) { return 0; /* TODO */ } @@ -414,12 +432,15 @@ static GDBFeature *arm_gen_dynamic_m_systemreg_feature(CPUState *cs, * For user-only, we see the non-secure registers via m_systemreg above. * For secext, encode the non-secure view as even and secure view as odd. */ -static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg) +static int arm_gdb_get_m_secextreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + return m_sysreg_get(env, buf, reg >> 1, reg & 1); } -static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_m_secextreg(CPUState *cs, uint8_t *buf, int reg) { return 0; /* TODO */ } diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 5286d5c6043..caa31ff3fa1 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -72,8 +72,11 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + switch (reg) { case 0 ... 31: { @@ -92,8 +95,11 @@ int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) } } -int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + switch (reg) { case 0 ... 31: /* 128 bit FP register */ @@ -116,9 +122,10 @@ int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) } } -int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu = env_archcpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; switch (reg) { /* The first 32 registers are the zregs */ @@ -164,9 +171,10 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) return 0; } -int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg) { - ARMCPU *cpu = env_archcpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; /* The first 32 registers are the zregs */ switch (reg) { @@ -210,8 +218,11 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + switch (reg) { case 0: /* pauth_dmask */ case 1: /* pauth_cmask */ @@ -241,7 +252,7 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) } } -int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg) { /* All pseudo registers are read-only. */ return 0; diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 54d37e006e0..6007e6462b9 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -81,8 +81,11 @@ static int gdb_get_qreg(CPUHexagonState *env, GByteArray *mem_buf, int n) return total; } -int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n) +int hexagon_hvx_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { + HexagonCPU *cpu = HEXAGON_CPU(cs); + CPUHexagonState *env = &cpu->env; + if (n < NUM_VREGS) { return gdb_get_vreg(env, mem_buf, n); } @@ -115,8 +118,11 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n) return MAX_VEC_SIZE_BYTES / 8; } -int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n) +int hexagon_hvx_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + HexagonCPU *cpu = HEXAGON_CPU(cs); + CPUHexagonState *env = &cpu->env; + if (n < NUM_VREGS) { return gdb_put_vreg(env, mem_buf, n); } diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 843a869450e..22c6889011e 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -84,9 +84,11 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return length; } -static int loongarch_gdb_get_fpu(CPULoongArchState *env, - GByteArray *mem_buf, int n) +static int loongarch_gdb_get_fpu(CPUState *cs, GByteArray *mem_buf, int n) { + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + if (0 <= n && n < 32) { return gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(0)); } else if (32 <= n && n < 40) { @@ -97,9 +99,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env, return 0; } -static int loongarch_gdb_set_fpu(CPULoongArchState *env, - uint8_t *mem_buf, int n) +static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) { + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; int length = 0; if (0 <= n && n < 32) { diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 675f2dcd5ad..a5ee4d87e32 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -69,8 +69,11 @@ void m68k_cpu_list(void) g_slist_free(list); } -static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n) +static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) { + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + if (n < 8) { float_status s; return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); @@ -86,8 +89,11 @@ static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n) return 0; } -static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) { + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + if (n < 8) { float_status s; env->fregs[n].d = float64_to_floatx80(ldq_p(mem_buf), &s); @@ -106,8 +112,11 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) return 0; } -static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n) +static int m68k_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) { + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + if (n < 8) { int len = gdb_get_reg16(mem_buf, env->fregs[n].l.upper); len += gdb_get_reg16(mem_buf, 0); @@ -125,8 +134,11 @@ static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n) return 0; } -static int m68k_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) { + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + if (n < 8) { env->fregs[n].l.upper = lduw_be_p(mem_buf); env->fregs[n].l.lower = ldq_be_p(mem_buf + 4); diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 29ac6e9c0f7..6ffc5ad0752 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -94,8 +94,10 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return gdb_get_reg32(mem_buf, val); } -int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByteArray *mem_buf, int n) +int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n) { + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; uint32_t val; switch (n) { @@ -153,8 +155,11 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 4; } -int mb_cpu_gdb_write_stack_protect(CPUMBState *env, uint8_t *mem_buf, int n) +int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *mem_buf, int n) { + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + switch (n) { case GDB_SP_SHL: env->slr = ldl_p(mem_buf); diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 09b852464f3..8ca37b6bf95 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -369,8 +369,10 @@ static int gdb_find_spr_idx(CPUPPCState *env, int n) return -1; } -static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; int reg; int len; @@ -385,8 +387,10 @@ static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) return len; } -static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; int reg; int len; @@ -403,8 +407,10 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) } #endif -static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; uint8_t *mem_buf; if (n < 32) { gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); @@ -421,8 +427,11 @@ static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) return 0; } -static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); *cpu_fpr_ptr(env, n) = ldq_p(mem_buf); @@ -436,8 +445,10 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; uint8_t *mem_buf; if (n < 32) { @@ -462,8 +473,11 @@ static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) return 0; } -static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + if (n < 32) { ppc_avr_t *avr = cpu_avr_ptr(env, n); ppc_maybe_bswap_register(env, mem_buf, 16); @@ -484,8 +498,11 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + if (n < 32) { #if defined(TARGET_PPC64) gdb_get_reg32(buf, env->gpr[n] >> 32); @@ -508,8 +525,11 @@ static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) return 0; } -static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + if (n < 32) { #if defined(TARGET_PPC64) target_ulong lo = (uint32_t)env->gpr[n]; @@ -537,8 +557,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 0; } -static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + if (n < 32) { gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); @@ -547,8 +570,11 @@ static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) return 0; } -static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a879869fa1a..68d0fdc1fd6 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -108,8 +108,11 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return length; } -static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + if (n < 32) { if (env->misa_ext & RVD) { return gdb_get_reg64(buf, env->fpr[n]); @@ -121,8 +124,11 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) return 0; } -static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + if (n < 32) { env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ return sizeof(uint64_t); @@ -130,8 +136,10 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_vector(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; @@ -146,8 +154,10 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) return 0; } -static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; @@ -160,8 +170,11 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + if (n < CSR_TABLE_SIZE) { target_ulong val = 0; int result; @@ -174,8 +187,11 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) return 0; } -static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + if (n < CSR_TABLE_SIZE) { target_ulong val = ldtul_p(mem_buf); int result; @@ -188,25 +204,31 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } -static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) +static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n) { if (n == 0) { #ifdef CONFIG_USER_ONLY return gdb_get_regl(buf, 0); #else - return gdb_get_regl(buf, cs->priv); + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + return gdb_get_regl(buf, env->priv); #endif } return 0; } -static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n) { if (n == 0) { #ifndef CONFIG_USER_ONLY - cs->priv = ldtul_p(mem_buf) & 0x3; - if (cs->priv == PRV_RESERVED) { - cs->priv = PRV_S; + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + env->priv = ldtul_p(mem_buf) & 0x3; + if (env->priv == PRV_RESERVED) { + env->priv = PRV_S; } #endif return sizeof(target_ulong); diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 02c388dc323..c1e7c59b822 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -70,8 +70,11 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) #define S390_A0_REGNUM 0 #define S390_A15_REGNUM 15 -static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_ac_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: return gdb_get_reg32(buf, env->aregs[n]); @@ -80,8 +83,11 @@ static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) } } -static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_ac_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: env->aregs[n] = ldl_p(mem_buf); @@ -97,8 +103,11 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_F0_REGNUM 1 #define S390_F15_REGNUM 16 -static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_fp_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_FPC_REGNUM: return gdb_get_reg32(buf, env->fpc); @@ -109,8 +118,11 @@ static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) } } -static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_fp_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_FPC_REGNUM: env->fpc = ldl_p(mem_buf); @@ -129,8 +141,10 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_V16_REGNUM 16 #define S390_V31_REGNUM 31 -static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_vreg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; int ret; switch (n) { @@ -148,8 +162,11 @@ static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) return ret; } -static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_vreg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_V0L_REGNUM ... S390_V15L_REGNUM: env->vregs[n][1] = ldtul_p(mem_buf + 8); @@ -168,8 +185,11 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_C15_REGNUM 15 #ifndef CONFIG_USER_ONLY -static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_c_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: return gdb_get_regl(buf, env->cregs[n]); @@ -178,8 +198,11 @@ static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) } } -static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_c_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: env->cregs[n] = ldtul_p(mem_buf); @@ -199,8 +222,11 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_VIRT_BEA_REGNUM 2 #define S390_VIRT_PREFIX_REGNUM 3 -static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n) +static int cpu_read_virt_reg(CPUState *cs, GByteArray *mem_buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_VIRT_CKC_REGNUM: return gdb_get_regl(mem_buf, env->ckc); @@ -215,24 +241,27 @@ static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n) } } -static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_virt_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_VIRT_CKC_REGNUM: env->ckc = ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_CPUTM_REGNUM: env->cputm = ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_BEA_REGNUM: env->gbea = ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_PREFIX_REGNUM: env->psa = ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; default: return 0; @@ -245,8 +274,11 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) #define S390_VIRT_KVM_PFS_REGNUM 2 #define S390_VIRT_KVM_PFC_REGNUM 3 -static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, int n) +static int cpu_read_virt_kvm_reg(CPUState *cs, GByteArray *mem_buf, int n) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + switch (n) { case S390_VIRT_KVM_PP_REGNUM: return gdb_get_regl(mem_buf, env->pp); @@ -261,8 +293,11 @@ static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, int n) } } -static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_virt_kvm_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu = S390_CPU(cs); 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Wed, 03 Jan 2024 09:34:02 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 7E2865F9CE; Wed, 3 Jan 2024 17:33:52 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 32/43] gdbstub: Simplify XML lookup Date: Wed, 3 Jan 2024 17:33:38 +0000 Message-Id: <20240103173349.398526-33-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki Now we know all instances of GDBFeature that is used in CPU so we can traverse them to find XML. This removes the need for a CPU-specific lookup function for dynamic XMLs. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Bennée Message-Id: <20231213-gdb-v17-7-777047380591@daynix.com> Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 6 +++ gdbstub/gdbstub.c | 118 +++++++++++++++++++++-------------------- hw/core/cpu-common.c | 5 +- 3 files changed, 69 insertions(+), 60 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index bcaab1bc750..82a8afa237f 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -27,6 +27,12 @@ typedef struct GDBFeatureBuilder { typedef int (*gdb_get_reg_cb)(CPUState *cpu, GByteArray *buf, int reg); typedef int (*gdb_set_reg_cb)(CPUState *cpu, uint8_t *buf, int reg); +/** + * gdb_init_cpu(): Initialize the CPU for gdbstub. + * @cpu: The CPU to be initialized. + */ +void gdb_init_cpu(CPUState *cpu); + /** * gdb_register_coprocessor() - register a supplemental set of registers * @cpu - the CPU associated with registers diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 21fea7fffae..1d5c1da1b24 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -352,6 +352,7 @@ static const char *get_feature_xml(const char *p, const char **newp, { CPUState *cpu = gdb_get_first_cpu_in_process(process); CPUClass *cc = CPU_GET_CLASS(cpu); + GDBRegisterState *r; size_t len; /* @@ -365,7 +366,6 @@ static const char *get_feature_xml(const char *p, const char **newp, /* Is it the main target xml? */ if (strncmp(p, "target.xml", len) == 0) { if (!process->target_xml) { - GDBRegisterState *r; g_autoptr(GPtrArray) xml = g_ptr_array_new_with_free_func(g_free); g_ptr_array_add( @@ -380,18 +380,12 @@ static const char *get_feature_xml(const char *p, const char **newp, g_markup_printf_escaped("%s", cc->gdb_arch_name(cpu))); } - g_ptr_array_add( - xml, - g_markup_printf_escaped("", - cc->gdb_core_xml_file)); - if (cpu->gdb_regs) { - for (guint i = 0; i < cpu->gdb_regs->len; i++) { - r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - g_ptr_array_add( - xml, - g_markup_printf_escaped("", - r->feature->xmlname)); - } + for (guint i = 0; i < cpu->gdb_regs->len; i++) { + r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + g_ptr_array_add( + xml, + g_markup_printf_escaped("", + r->feature->xmlname)); } g_ptr_array_add(xml, g_strdup("")); g_ptr_array_add(xml, NULL); @@ -400,20 +394,11 @@ static const char *get_feature_xml(const char *p, const char **newp, } return process->target_xml; } - /* Is it dynamically generated by the target? */ - if (cc->gdb_get_dynamic_xml) { - g_autofree char *xmlname = g_strndup(p, len); - const char *xml = cc->gdb_get_dynamic_xml(cpu, xmlname); - if (xml) { - return xml; - } - } - /* Is it one of the encoded gdb-xml/ files? */ - for (int i = 0; gdb_static_features[i].xmlname; i++) { - const char *name = gdb_static_features[i].xmlname; - if ((strncmp(name, p, len) == 0) && - strlen(name) == len) { - return gdb_static_features[i].xml; + /* Is it one of the features? */ + for (guint i = 0; i < cpu->gdb_regs->len; i++) { + r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (strncmp(p, r->feature->xmlname, len) == 0) { + return r->feature->xml; } } @@ -508,12 +493,10 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) return cc->gdb_read_register(cpu, buf, reg); } - if (cpu->gdb_regs) { - for (guint i = 0; i < cpu->gdb_regs->len; i++) { - r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) { - return r->get_reg(cpu, buf, reg - r->base_reg); - } + for (guint i = 0; i < cpu->gdb_regs->len; i++) { + r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) { + return r->get_reg(cpu, buf, reg - r->base_reg); } } return 0; @@ -528,51 +511,70 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) return cc->gdb_write_register(cpu, mem_buf, reg); } - if (cpu->gdb_regs) { - for (guint i = 0; i < cpu->gdb_regs->len; i++) { - r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) { - return r->set_reg(cpu, mem_buf, reg - r->base_reg); - } + for (guint i = 0; i < cpu->gdb_regs->len; i++) { + r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) { + return r->set_reg(cpu, mem_buf, reg - r->base_reg); } } return 0; } +static void gdb_register_feature(CPUState *cpu, int base_reg, + gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, + const GDBFeature *feature) +{ + GDBRegisterState s = { + .base_reg = base_reg, + .get_reg = get_reg, + .set_reg = set_reg, + .feature = feature + }; + + g_array_append_val(cpu->gdb_regs, s); +} + +void gdb_init_cpu(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + const GDBFeature *feature; + + cpu->gdb_regs = g_array_new(false, false, sizeof(GDBRegisterState)); + + if (cc->gdb_core_xml_file) { + feature = gdb_find_static_feature(cc->gdb_core_xml_file); + gdb_register_feature(cpu, 0, + cc->gdb_read_register, cc->gdb_write_register, + feature); + } + + cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; +} + void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, const GDBFeature *feature, int g_pos) { GDBRegisterState *s; guint i; + int base_reg = cpu->gdb_num_regs; - if (cpu->gdb_regs) { - for (i = 0; i < cpu->gdb_regs->len; i++) { - /* Check for duplicates. */ - s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (s->feature == feature) { - return; - } + for (i = 0; i < cpu->gdb_regs->len; i++) { + /* Check for duplicates. */ + s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (s->feature == feature) { + return; } - } else { - cpu->gdb_regs = g_array_new(false, false, sizeof(GDBRegisterState)); - i = 0; } - g_array_set_size(cpu->gdb_regs, i + 1); - s = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - s->base_reg = cpu->gdb_num_regs; - s->get_reg = get_reg; - s->set_reg = set_reg; - s->feature = feature; + gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature); /* Add to end of list. */ cpu->gdb_num_regs += feature->num_regs; if (g_pos) { - if (g_pos != s->base_reg) { + if (g_pos != base_reg) { error_report("Error: Bad gdb register numbering for '%s', " - "expected %d got %d", feature->xml, - g_pos, s->base_reg); + "expected %d got %d", feature->xml, g_pos, base_reg); } else { cpu->gdb_num_g_regs = cpu->gdb_num_regs; } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 82dae51a550..cd7903ba6e7 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -27,6 +27,7 @@ #include "qemu/main-loop.h" #include "exec/log.h" #include "exec/cpu-common.h" +#include "exec/gdbstub.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/tcg.h" @@ -238,11 +239,10 @@ static void cpu_common_unrealizefn(DeviceState *dev) static void cpu_common_initfn(Object *obj) { CPUState *cpu = CPU(obj); - CPUClass *cc = CPU_GET_CLASS(obj); + gdb_init_cpu(cpu); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; - cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; /* user-mode doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for system-mode */ cpu->nr_cores = 1; @@ -262,6 +262,7 @@ static void cpu_common_finalize(Object *obj) { CPUState *cpu = CPU(obj); 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Wed, 3 Jan 2024 17:33:52 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 33/43] gdbstub: Infer number of core registers from XML Date: Wed, 3 Jan 2024 17:33:39 +0000 Message-Id: <20240103173349.398526-34-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki GDBFeature has the num_regs member so use it where applicable to remove magic numbers. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-8-777047380591@daynix.com> Signed-off-by: Alex Bennée --- include/hw/core/cpu.h | 3 ++- target/s390x/cpu.h | 2 -- gdbstub/gdbstub.c | 5 ++++- target/arm/cpu.c | 1 - target/arm/cpu64.c | 1 - target/avr/cpu.c | 1 - target/hexagon/cpu.c | 1 - target/i386/cpu.c | 2 -- target/loongarch/cpu.c | 2 -- target/m68k/cpu.c | 1 - target/microblaze/cpu.c | 1 - target/riscv/cpu.c | 1 - target/rx/cpu.c | 1 - target/s390x/cpu.c | 1 - 14 files changed, 6 insertions(+), 17 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c0c8320413e..a6214610603 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -127,7 +127,8 @@ struct SysemuCPUOps; * @gdb_adjust_breakpoint: Callback for adjusting the address of a * breakpoint. Used by AVR to handle a gdb mis-feature with * its Harvard architecture split code and data. - * @gdb_num_core_regs: Number of core registers accessible to GDB. + * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to infer + * from @gdb_core_xml_file. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop * before the insn which triggers a watchpoint rather than after it. diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f973..2d81fbfea5c 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -491,8 +491,6 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, #define S390_R13_REGNUM 15 #define S390_R14_REGNUM 16 #define S390_R15_REGNUM 17 -/* Total Core Registers. */ -#define S390_NUM_CORE_REGS 18 static inline void setcc(S390CPU *cpu, uint64_t cc) { diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 1d5c1da1b24..801eba9a0b0 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -546,9 +546,12 @@ void gdb_init_cpu(CPUState *cpu) gdb_register_feature(cpu, 0, cc->gdb_read_register, cc->gdb_write_register, feature); + cpu->gdb_num_regs = cpu->gdb_num_g_regs = feature->num_regs; } - cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; + if (cc->gdb_num_core_regs) { + cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; + } } void gdb_register_coprocessor(CPUState *cpu, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 650e09b29c5..0a02d16220b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2498,7 +2498,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops = &arm_sysemu_ops; #endif - cc->gdb_num_core_regs = 26; cc->gdb_arch_name = arm_gdb_arch_name; cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint = true; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8e30a7993ea..869d8dd24ee 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -793,7 +793,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; - cc->gdb_num_core_regs = 34; cc->gdb_core_xml_file = "aarch64-core.xml"; cc->gdb_arch_name = aarch64_gdb_arch_name; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 999c010dedb..4bab9e22728 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -251,7 +251,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = avr_cpu_gdb_read_register; cc->gdb_write_register = avr_cpu_gdb_write_register; cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; - cc->gdb_num_core_regs = 35; cc->gdb_core_xml_file = "avr-cpu.xml"; cc->tcg_ops = &avr_tcg_ops; } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 65ac9c75ad0..71678ef9c67 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -384,7 +384,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) cc->get_pc = hexagon_cpu_get_pc; cc->gdb_read_register = hexagon_gdb_read_register; cc->gdb_write_register = hexagon_gdb_write_register; - cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS; cc->gdb_stop_before_watchpoint = true; cc->gdb_core_xml_file = "hexagon-core.xml"; cc->disas_set_info = hexagon_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 95d5f16cd5e..b14c97169cd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7969,10 +7969,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->gdb_arch_name = x86_gdb_arch_name; #ifdef TARGET_X86_64 cc->gdb_core_xml_file = "i386-64bit.xml"; - cc->gdb_num_core_regs = 66; #else cc->gdb_core_xml_file = "i386-32bit.xml"; - cc->gdb_num_core_regs = 50; #endif cc->disas_set_info = x86_disas_set_info; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 07319d6fb97..dfac51a7f60 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -851,7 +851,6 @@ static void loongarch32_cpu_class_init(ObjectClass *c, void *data) { CPUClass *cc = CPU_CLASS(c); - cc->gdb_num_core_regs = 35; cc->gdb_core_xml_file = "loongarch-base32.xml"; cc->gdb_arch_name = loongarch32_gdb_arch_name; } @@ -865,7 +864,6 @@ static void loongarch64_cpu_class_init(ObjectClass *c, void *data) { CPUClass *cc = CPU_CLASS(c); - cc->gdb_num_core_regs = 35; cc->gdb_core_xml_file = "loongarch-base64.xml"; cc->gdb_arch_name = loongarch64_gdb_arch_name; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 11c7e0a7902..a27194b2a59 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -564,7 +564,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) #endif cc->disas_set_info = m68k_cpu_disas_set_info; - cc->gdb_num_core_regs = 18; cc->tcg_ops = &m68k_tcg_ops; } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 1998f69828f..9d3fbfe1592 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -428,7 +428,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->sysemu_ops = &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); - cc->gdb_num_core_regs = 32 + 25; cc->gdb_core_xml_file = "microblaze-core.xml"; cc->disas_set_info = mb_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 673e937a5d8..a3a98230ca8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1688,7 +1688,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) cc->get_pc = riscv_cpu_get_pc; cc->gdb_read_register = riscv_cpu_gdb_read_register; cc->gdb_write_register = riscv_cpu_gdb_write_register; - cc->gdb_num_core_regs = 33; cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 9cc9d9d15ec..cf11b189116 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -231,7 +231,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) cc->gdb_write_register = rx_cpu_gdb_write_register; cc->disas_set_info = rx_cpu_disas_set_info; - cc->gdb_num_core_regs = 26; cc->gdb_core_xml_file = "rx-core.xml"; cc->tcg_ops = &rx_tcg_ops; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6acfa1c91b2..6fba9497295 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -362,7 +362,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) s390_cpu_class_init_sysemu(cc); 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Wed, 3 Jan 2024 17:33:52 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 34/43] hw/core/cpu: Remove gdb_get_dynamic_xml member Date: Wed, 3 Jan 2024 17:33:40 +0000 Message-Id: <20240103173349.398526-35-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki This function is no longer used. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Bennée Message-Id: <20231213-gdb-v17-9-777047380591@daynix.com> Signed-off-by: Alex Bennée --- include/hw/core/cpu.h | 4 ---- target/arm/cpu.h | 6 ------ target/ppc/cpu.h | 1 - target/arm/cpu.c | 1 - target/arm/gdbstub.c | 18 ------------------ target/ppc/cpu_init.c | 3 --- target/ppc/gdbstub.c | 10 ---------- target/riscv/cpu.c | 14 -------------- 8 files changed, 57 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index a6214610603..17f99adc0f4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -134,9 +134,6 @@ struct SysemuCPUOps; * before the insn which triggers a watchpoint rather than after it. * @gdb_arch_name: Optional callback that returns the architecture name known * to GDB. The caller must free the returned string with g_free. - * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the - * gdb stub. Returns a pointer to the XML contents for the specified XML file - * or NULL if the CPU doesn't have a dynamically generated content for it. * @disas_set_info: Setup architecture specific components of disassembly info * @adjust_watchpoint_address: Perform a target-specific adjustment to an * address before attempting to match it against watchpoints. @@ -167,7 +164,6 @@ struct CPUClass { const char *gdb_core_xml_file; const gchar * (*gdb_arch_name)(CPUState *cpu); - const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); void (*disas_set_info)(CPUState *cpu, disassemble_info *info); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b2f8ac81f06..c8e77440f0f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1182,12 +1182,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* Returns the dynamically generated XML for the gdb stub. - * Returns a pointer to the XML contents for the specified XML file or NULL - * if the XML name doesn't match the predefined one. - */ -const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); - int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s); int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f87c26f98a6..9f94282e13e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1524,7 +1524,6 @@ int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); #ifndef CONFIG_USER_ONLY hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); #endif int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0a02d16220b..9514edaf041 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2499,7 +2499,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->sysemu_ops = &arm_sysemu_ops; #endif cc->gdb_arch_name = arm_gdb_arch_name; - cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = arm_disas_set_info; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 059d84f98e5..a3bb73cfa7c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -474,24 +474,6 @@ static GDBFeature *arm_gen_dynamic_m_secextreg_feature(CPUState *cs, #endif #endif /* CONFIG_TCG */ -const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) -{ - ARMCPU *cpu = ARM_CPU(cs); - - if (strcmp(xmlname, "system-registers.xml") == 0) { - return cpu->dyn_sysreg_feature.desc.xml; - } else if (strcmp(xmlname, "sve-registers.xml") == 0) { - return cpu->dyn_svereg_feature.desc.xml; - } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { - return cpu->dyn_m_systemreg_feature.desc.xml; -#ifndef CONFIG_USER_ONLY - } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) { - return cpu->dyn_m_secextreg_feature.desc.xml; -#endif - } - return NULL; -} - void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) { CPUState *cs = CPU(cpu); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a0178c3ce80..909d753b022 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7380,9 +7380,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #endif cc->gdb_num_core_regs = 71; -#ifndef CONFIG_USER_ONLY - cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; -#endif #ifdef USE_APPLE_GDB cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 8ca37b6bf95..f47878a67bd 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -342,16 +342,6 @@ static void gdb_gen_spr_feature(CPUState *cs) gdb_feature_builder_end(&builder); } - -const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name) -{ - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); - - if (strcmp(xml_name, "power-spr.xml") == 0) { - return pcc->gdb_spr.xml; - } - return NULL; -} #endif #if !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a3a98230ca8..1e3ac556b33 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1529,19 +1529,6 @@ static const gchar *riscv_gdb_arch_name(CPUState *cs) } } -static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) -{ - RISCVCPU *cpu = RISCV_CPU(cs); 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Wed, 03 Jan 2024 09:49:05 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id E20355F9D1; Wed, 3 Jan 2024 17:33:52 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 35/43] gdbstub: Add members to identify registers to GDBFeature Date: Wed, 3 Jan 2024 17:33:41 +0000 Message-Id: <20240103173349.398526-36-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki These members will be used to help plugins to identify registers. The added members in instances of GDBFeature dynamically generated by CPUs will be filled in later changes. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-10-777047380591@daynix.com> Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 3 +++ gdbstub/gdbstub.c | 12 +++++++++--- target/riscv/gdbstub.c | 4 +--- scripts/feature_to_c.py | 14 +++++++++++++- 4 files changed, 26 insertions(+), 7 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 82a8afa237f..da9ddfe54c5 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -13,12 +13,15 @@ typedef struct GDBFeature { const char *xmlname; const char *xml; + const char *name; + const char * const *regs; int num_regs; } GDBFeature; typedef struct GDBFeatureBuilder { GDBFeature *feature; GPtrArray *xml; + GPtrArray *regs; int base_reg; } GDBFeatureBuilder; diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 801eba9a0b0..420ab2a3766 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -419,9 +419,10 @@ void gdb_feature_builder_init(GDBFeatureBuilder *builder, GDBFeature *feature, builder->feature = feature; builder->xml = g_ptr_array_new(); g_ptr_array_add(builder->xml, header); + builder->regs = g_ptr_array_new(); builder->base_reg = base_reg; feature->xmlname = xmlname; - feature->num_regs = 0; + feature->name = name; } void gdb_feature_builder_append_tag(const GDBFeatureBuilder *builder, @@ -440,10 +441,12 @@ void gdb_feature_builder_append_reg(const GDBFeatureBuilder *builder, const char *type, const char *group) { - if (builder->feature->num_regs < regnum) { - builder->feature->num_regs = regnum; + if (builder->regs->len <= regnum) { + g_ptr_array_set_size(builder->regs, regnum + 1); } + builder->regs->pdata[regnum] = (gpointer *)name; + if (group) { gdb_feature_builder_append_tag( builder, @@ -469,6 +472,9 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *builder) } g_ptr_array_free(builder->xml, TRUE); + + builder->feature->num_regs = builder->regs->len; + builder->feature->regs = (void *)g_ptr_array_free(builder->regs, FALSE); } const GDBFeature *gdb_find_static_feature(const char *xmlname) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 68d0fdc1fd6..d9b52ffd09b 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -266,11 +266,9 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg) } predicate = csr_ops[i].predicate; if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) { - g_autofree char *dynamic_name = NULL; name = csr_ops[i].name; if (!name) { - dynamic_name = g_strdup_printf("csr%03x", i); - name = dynamic_name; + name = g_strdup_printf("csr%03x", i); } gdb_feature_builder_append_reg(&builder, name, bitsize, i, diff --git a/scripts/feature_to_c.py b/scripts/feature_to_c.py index e04d6b2df7f..807af0e685c 100644 --- a/scripts/feature_to_c.py +++ b/scripts/feature_to_c.py @@ -50,7 +50,9 @@ def writeliteral(indent, bytes): sys.stderr.write(f'unexpected start tag: {element.tag}\n') exit(1) + feature_name = element.attrib['name'] regnum = 0 + regnames = [] regnums = [] tags = ['feature'] for event, element in events: @@ -67,6 +69,7 @@ def writeliteral(indent, bytes): if 'regnum' in element.attrib: regnum = int(element.attrib['regnum']) + regnames.append(element.attrib['name']) regnums.append(regnum) regnum += 1 @@ -85,6 +88,15 @@ def writeliteral(indent, bytes): writeliteral(8, bytes(os.path.basename(input), 'utf-8')) sys.stdout.write(',\n') writeliteral(8, read) - sys.stdout.write(f',\n {num_regs},\n }},\n') + sys.stdout.write(',\n') + writeliteral(8, bytes(feature_name, 'utf-8')) + sys.stdout.write(',\n (const char * const []) {\n') + + for index, regname in enumerate(regnames): + sys.stdout.write(f' [{regnums[index] - base_reg}] =\n') + writeliteral(16, bytes(regname, 'utf-8')) + sys.stdout.write(',\n') + + sys.stdout.write(f' }},\n {num_regs},\n }},\n') sys.stdout.write(' { NULL }\n};\n') From patchwork Wed Jan 3 17:33:42 2024 Content-Type: text/plain; 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Wed, 03 Jan 2024 09:34:08 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id k39-20020a05600c1ca700b0040d8af75e19sm2948860wms.24.2024.01.03.09.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:34:03 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 06C1B5F9D2; Wed, 3 Jan 2024 17:33:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 36/43] plugins: Use different helpers when reading registers Date: Wed, 3 Jan 2024 17:33:42 +0000 Message-Id: <20240103173349.398526-37-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki This avoids optimizations incompatible when reading registers. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-12-777047380591@daynix.com> Signed-off-by: Alex Bennée Reviewed-by: Pierrick Bouvier --- accel/tcg/plugin-helpers.h | 3 ++- include/qemu/plugin.h | 1 + accel/tcg/plugin-gen.c | 43 ++++++++++++++++++++++++++++++++++---- plugins/api.c | 12 +++++++++-- 4 files changed, 52 insertions(+), 7 deletions(-) diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h index 8e685e06545..11796436f35 100644 --- a/accel/tcg/plugin-helpers.h +++ b/accel/tcg/plugin-helpers.h @@ -1,4 +1,5 @@ #ifdef CONFIG_PLUGIN -DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb, TCG_CALL_NO_RWG | TCG_CALL_PLUGIN, void, i32, ptr) +DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb_no_wg, TCG_CALL_NO_WG | TCG_CALL_PLUGIN, void, i32, ptr) +DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb_no_rwg, TCG_CALL_NO_RWG | TCG_CALL_PLUGIN, void, i32, ptr) DEF_HELPER_FLAGS_4(plugin_vcpu_mem_cb, TCG_CALL_NO_RWG | TCG_CALL_PLUGIN, void, i32, i32, i64, ptr) #endif diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h index 7fdc3a4849f..b0c5ac68293 100644 --- a/include/qemu/plugin.h +++ b/include/qemu/plugin.h @@ -73,6 +73,7 @@ enum plugin_dyn_cb_type { enum plugin_dyn_cb_subtype { PLUGIN_CB_REGULAR, + PLUGIN_CB_REGULAR_R, PLUGIN_CB_INLINE, PLUGIN_N_CB_SUBTYPES, }; diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 78b331b2510..b37ce7683e6 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -79,6 +79,7 @@ enum plugin_gen_from { enum plugin_gen_cb { PLUGIN_GEN_CB_UDATA, + PLUGIN_GEN_CB_UDATA_R, PLUGIN_GEN_CB_INLINE, PLUGIN_GEN_CB_MEM, PLUGIN_GEN_ENABLE_MEM_HELPER, @@ -90,7 +91,10 @@ enum plugin_gen_cb { * These helpers are stubs that get dynamically switched out for calls * direct to the plugin if they are subscribed to. */ -void HELPER(plugin_vcpu_udata_cb)(uint32_t cpu_index, void *udata) +void HELPER(plugin_vcpu_udata_cb_no_wg)(uint32_t cpu_index, void *udata) +{ } + +void HELPER(plugin_vcpu_udata_cb_no_rwg)(uint32_t cpu_index, void *udata) { } void HELPER(plugin_vcpu_mem_cb)(unsigned int vcpu_index, @@ -98,7 +102,7 @@ void HELPER(plugin_vcpu_mem_cb)(unsigned int vcpu_index, void *userdata) { } -static void gen_empty_udata_cb(void) +static void gen_empty_udata_cb(void (*gen_helper)(TCGv_i32, TCGv_ptr)) { TCGv_i32 cpu_index = tcg_temp_ebb_new_i32(); TCGv_ptr udata = tcg_temp_ebb_new_ptr(); @@ -106,12 +110,22 @@ static void gen_empty_udata_cb(void) tcg_gen_movi_ptr(udata, 0); tcg_gen_ld_i32(cpu_index, tcg_env, -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)); - gen_helper_plugin_vcpu_udata_cb(cpu_index, udata); + gen_helper(cpu_index, udata); tcg_temp_free_ptr(udata); tcg_temp_free_i32(cpu_index); } +static void gen_empty_udata_cb_no_wg(void) +{ + gen_empty_udata_cb(gen_helper_plugin_vcpu_udata_cb_no_wg); +} + +static void gen_empty_udata_cb_no_rwg(void) +{ + gen_empty_udata_cb(gen_helper_plugin_vcpu_udata_cb_no_rwg); +} + /* * For now we only support addi_i64. * When we support more ops, we can generate one empty inline cb for each. @@ -192,7 +206,8 @@ static void plugin_gen_empty_callback(enum plugin_gen_from from) gen_empty_mem_helper); /* fall through */ case PLUGIN_GEN_FROM_TB: - gen_wrapped(from, PLUGIN_GEN_CB_UDATA, gen_empty_udata_cb); + gen_wrapped(from, PLUGIN_GEN_CB_UDATA, gen_empty_udata_cb_no_rwg); + gen_wrapped(from, PLUGIN_GEN_CB_UDATA_R, gen_empty_udata_cb_no_wg); gen_wrapped(from, PLUGIN_GEN_CB_INLINE, gen_empty_inline_cb); break; default: @@ -588,6 +603,12 @@ static void plugin_gen_tb_udata(const struct qemu_plugin_tb *ptb, inject_udata_cb(ptb->cbs[PLUGIN_CB_REGULAR], begin_op); } +static void plugin_gen_tb_udata_r(const struct qemu_plugin_tb *ptb, + TCGOp *begin_op) +{ + inject_udata_cb(ptb->cbs[PLUGIN_CB_REGULAR_R], begin_op); +} + static void plugin_gen_tb_inline(const struct qemu_plugin_tb *ptb, TCGOp *begin_op) { @@ -602,6 +623,14 @@ static void plugin_gen_insn_udata(const struct qemu_plugin_tb *ptb, inject_udata_cb(insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB_REGULAR], begin_op); } +static void plugin_gen_insn_udata_r(const struct qemu_plugin_tb *ptb, + TCGOp *begin_op, int insn_idx) +{ + struct qemu_plugin_insn *insn = g_ptr_array_index(ptb->insns, insn_idx); + + inject_udata_cb(insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB_REGULAR_R], begin_op); +} + static void plugin_gen_insn_inline(const struct qemu_plugin_tb *ptb, TCGOp *begin_op, int insn_idx) { @@ -721,6 +750,9 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) case PLUGIN_GEN_CB_UDATA: plugin_gen_tb_udata(plugin_tb, op); break; + case PLUGIN_GEN_CB_UDATA_R: + plugin_gen_tb_udata_r(plugin_tb, op); + break; case PLUGIN_GEN_CB_INLINE: plugin_gen_tb_inline(plugin_tb, op); break; @@ -737,6 +769,9 @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) case PLUGIN_GEN_CB_UDATA: plugin_gen_insn_udata(plugin_tb, op, insn_idx); break; + case PLUGIN_GEN_CB_UDATA_R: + plugin_gen_insn_udata_r(plugin_tb, op, insn_idx); + break; case PLUGIN_GEN_CB_INLINE: plugin_gen_insn_inline(plugin_tb, op, insn_idx); break; diff --git a/plugins/api.c b/plugins/api.c index 5521b0ad36c..ac39cdea0b3 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -89,7 +89,11 @@ void qemu_plugin_register_vcpu_tb_exec_cb(struct qemu_plugin_tb *tb, void *udata) { if (!tb->mem_only) { - plugin_register_dyn_cb__udata(&tb->cbs[PLUGIN_CB_REGULAR], + int index = flags == QEMU_PLUGIN_CB_R_REGS || + flags == QEMU_PLUGIN_CB_RW_REGS ? + PLUGIN_CB_REGULAR_R : PLUGIN_CB_REGULAR; + + plugin_register_dyn_cb__udata(&tb->cbs[index], cb, flags, udata); } } @@ -109,7 +113,11 @@ void qemu_plugin_register_vcpu_insn_exec_cb(struct qemu_plugin_insn *insn, void *udata) { if (!insn->mem_only) { - plugin_register_dyn_cb__udata(&insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB_REGULAR], + int index = flags == QEMU_PLUGIN_CB_R_REGS || + flags == QEMU_PLUGIN_CB_RW_REGS ? + PLUGIN_CB_REGULAR_R : PLUGIN_CB_REGULAR; + + plugin_register_dyn_cb__udata(&insn->cbs[PLUGIN_CB_INSN][index], cb, flags, udata); } } From patchwork Wed Jan 3 17:33:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510328 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC6301C6A4 for ; Wed, 3 Jan 2024 17:39:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="kQrw7sNW" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3367632ce7bso9142546f8f.2 for ; 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Wed, 3 Jan 2024 17:33:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 37/43] gdbstub: expose api to find registers Date: Wed, 3 Jan 2024 17:33:43 +0000 Message-Id: <20240103173349.398526-38-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Expose an internal API to QEMU to return all the registers for a vCPU. The list containing the details required to called gdb_read_register(). Based-on: <20231025093128.33116-15-akihiko.odaki@daynix.com> Cc: Akihiko Odaki Signed-off-by: Alex Bennée --- v2 - just make gdb_get_register_list return everything for a vCPU vAJB: This principle difference is the find registers is a single call which can return a) multiple registers and b) is agnostic to the gdb feature. This is because I haven't so far found any duplicate registers in the system so I thing the regname by itself should be enough. However I do expose the gdb feature name in case the caller wants to do some additional filtering. --- include/exec/gdbstub.h | 47 +++++++++++++++++++++++++++++++++++ gdbstub/gdbstub.c | 56 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index da9ddfe54c5..7bddea8259e 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -111,6 +111,53 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *builder); */ const GDBFeature *gdb_find_static_feature(const char *xmlname); +/** + * gdb_find_feature() - Find a feature associated with a CPU. + * @cpu: The CPU associated with the feature. + * @name: The feature's name. + * + * Return: The feature's number. + */ +int gdb_find_feature(CPUState *cpu, const char *name); + +/** + * gdb_find_feature_register() - Find a register associated with a CPU. + * @cpu: The CPU associated with the register. + * @feature: The feature's number returned by gdb_find_feature(). + * @name: The register's name. + * + * Return: The register's number. + */ +int gdb_find_feature_register(CPUState *cpu, int feature, const char *name); + +/** + * gdb_read_register() - Read a register associated with a CPU. + * @cpu: The CPU associated with the register. + * @buf: The buffer that the read register will be appended to. + * @reg: The register's number returned by gdb_find_feature_register(). + * + * Return: The number of read bytes. + */ +int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); + +/** + * typedef GDBRegDesc - a register description from gdbstub + */ +typedef struct { + int gdb_reg; + const char *name; + const char *feature_name; +} GDBRegDesc; + +/** + * gdb_get_register_list() - Return list of all registers for CPU + * @cpu: The CPU being searched + * + * Returns a GArray of GDBRegDesc, caller frees array but not the + * const strings. + */ +GArray *gdb_get_register_list(CPUState *cpu); + void gdb_set_stop_cpu(CPUState *cpu); /* in gdbstub-xml.c, generated by scripts/feature_to_c.py */ diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 420ab2a3766..b0230138246 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -490,7 +490,61 @@ const GDBFeature *gdb_find_static_feature(const char *xmlname) g_assert_not_reached(); } -static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) +int gdb_find_feature(CPUState *cpu, const char *name) +{ + GDBRegisterState *r; + + for (guint i = 0; i < cpu->gdb_regs->len; i++) { + r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (!strcmp(name, r->feature->name)) { + return i; + } + } + + return -1; +} + +int gdb_find_feature_register(CPUState *cpu, int feature, const char *name) +{ + GDBRegisterState *r; + + r = &g_array_index(cpu->gdb_regs, GDBRegisterState, feature); + + for (int i = 0; i < r->feature->num_regs; i++) { + if (r->feature->regs[i] && !strcmp(name, r->feature->regs[i])) { + return r->base_reg + i; + } + } + + return -1; +} + +GArray *gdb_get_register_list(CPUState *cpu) +{ + GArray *results = g_array_new(true, true, sizeof(GDBRegDesc)); + + /* registers are only available once the CPU is initialised */ + if (!cpu->gdb_regs) { + return results; + } + + for (int f = 0; f < cpu->gdb_regs->len; f++) { + GDBRegisterState *r = &g_array_index(cpu->gdb_regs, GDBRegisterState, f); + for (int i = 0; i < r->feature->num_regs; i++) { + const char *name = r->feature->regs[i]; + GDBRegDesc desc = { + r->base_reg + i, + name, + r->feature->name + }; + g_array_append_val(results, desc); + } + } + + return results; +} + +int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); GDBRegisterState *r; From patchwork Wed Jan 3 17:33:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510334 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D8A41CAB8 for ; Wed, 3 Jan 2024 17:39:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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Wed, 03 Jan 2024 09:39:13 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 3ABB35F92F; Wed, 3 Jan 2024 17:33:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 38/43] plugins: add an API to read registers Date: Wed, 3 Jan 2024 17:33:44 +0000 Message-Id: <20240103173349.398526-39-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We can only request a list of registers once the vCPU has been initialised so the user needs to use either call the get function on vCPU initialisation or during the translation phase. We don't expose the reg number to the plugin instead hiding it behind an opaque handle. This allows for a bit of future proofing should the internals need to be changed while also being hashed against the CPUClass so we can handle different register sets per-vCPU in hetrogenous situations. Having an internal state within the plugins also allows us to expand the interface in future (for example providing callbacks on register change if the translator can track changes). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706 Cc: Akihiko Odaki Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com> Signed-off-by: Alex Bennée Reviewed-by: Pierrick Bouvier --- v3 - also g_intern_string the register name - make get_registers documentation a bit less verbose v2 - use new get whole list api, and expose upwards vAJB: The main difference to Akikio's version is hiding the gdb register detail from the plugin for the reasons described above. --- include/qemu/qemu-plugin.h | 51 +++++++++++++++++- plugins/api.c | 102 +++++++++++++++++++++++++++++++++++ plugins/qemu-plugins.symbols | 2 + 3 files changed, 153 insertions(+), 2 deletions(-) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index 4daab6efd29..95380895f81 100644 --- a/include/qemu/qemu-plugin.h +++ b/include/qemu/qemu-plugin.h @@ -11,6 +11,7 @@ #ifndef QEMU_QEMU_PLUGIN_H #define QEMU_QEMU_PLUGIN_H +#include #include #include #include @@ -227,8 +228,8 @@ struct qemu_plugin_insn; * @QEMU_PLUGIN_CB_R_REGS: callback reads the CPU's regs * @QEMU_PLUGIN_CB_RW_REGS: callback reads and writes the CPU's regs * - * Note: currently unused, plugins cannot read or change system - * register state. + * Note: currently QEMU_PLUGIN_CB_RW_REGS is unused, plugins cannot change + * system register state. */ enum qemu_plugin_cb_flags { QEMU_PLUGIN_CB_NO_REGS, @@ -708,4 +709,50 @@ uint64_t qemu_plugin_end_code(void); QEMU_PLUGIN_API uint64_t qemu_plugin_entry_code(void); +/** struct qemu_plugin_register - Opaque handle for register access */ +struct qemu_plugin_register; + +/** + * typedef qemu_plugin_reg_descriptor - register descriptions + * + * @handle: opaque handle for retrieving value with qemu_plugin_read_register + * @name: register name + * @feature: optional feature descriptor, can be NULL + */ +typedef struct { + struct qemu_plugin_register *handle; + const char *name; + const char *feature; +} qemu_plugin_reg_descriptor; + +/** + * qemu_plugin_get_registers() - return register list for vCPU + * @vcpu_index: vcpu to query + * + * Returns a GArray of qemu_plugin_reg_descriptor or NULL. Caller + * frees the array (but not the const strings). + * + * Should be used from a qemu_plugin_register_vcpu_init_cb() callback + * after the vCPU is initialised. + */ +GArray * qemu_plugin_get_registers(unsigned int vcpu_index); + +/** + * qemu_plugin_read_register() - read register + * + * @vcpu: vcpu index + * @handle: a @qemu_plugin_reg_handle handle + * @buf: A GByteArray for the data owned by the plugin + * + * This function is only available in a context that register read access is + * explicitly requested. + * + * Returns the size of the read register. The content of @buf is in target byte + * order. On failure returns -1 + */ +int qemu_plugin_read_register(unsigned int vcpu, + struct qemu_plugin_register *handle, + GByteArray *buf); + + #endif /* QEMU_QEMU_PLUGIN_H */ diff --git a/plugins/api.c b/plugins/api.c index ac39cdea0b3..f8905325c43 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -8,6 +8,7 @@ * * qemu_plugin_tb * qemu_plugin_insn + * qemu_plugin_register * * Which can then be passed back into the API to do additional things. * As such all the public functions in here are exported in @@ -35,10 +36,12 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "qemu/plugin.h" #include "qemu/log.h" #include "tcg/tcg.h" #include "exec/exec-all.h" +#include "exec/gdbstub.h" #include "exec/ram_addr.h" #include "disas/disas.h" #include "plugin.h" @@ -435,3 +438,102 @@ uint64_t qemu_plugin_entry_code(void) #endif return entry; } + +/* + * Register handles + * + * The plugin infrastructure keeps hold of these internal data + * structures which are presented to plugins as opaque handles. They + * are global to the system and therefor additions to the hash table + * must be protected by the @reg_handle_lock. + * + * In order to future proof for up-coming heterogeneous work we want + * different entries for each CPU type while sharing them in the + * common case of multiple cores of the same type. + */ + +static QemuMutex reg_handle_lock; + +struct qemu_plugin_register { + const char *name; + int gdb_reg_num; +}; + +static GHashTable *reg_handles; /* hash table of PluginReg */ + +/* Generate a stable key - would xxhash be overkill? */ +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum) +{ + uintptr_t key = (uintptr_t) cs->cc; + key ^= gdb_regnum; + return GUINT_TO_POINTER(key); +} + +/* + * Create register handles. + * + * We need to create a handle for each register so the plugin + * infrastructure can call gdbstub to read a register. We also + * construct a result array with those handles and some ancillary data + * the plugin might find useful. + */ + +static GArray * create_register_handles(CPUState *cs, GArray *gdbstub_regs) { + GArray *find_data = g_array_new(true, true, sizeof(qemu_plugin_reg_descriptor)); + + WITH_QEMU_LOCK_GUARD(®_handle_lock) { + + if (!reg_handles) { + reg_handles = g_hash_table_new(g_direct_hash, g_direct_equal); + } + + for (int i=0; i < gdbstub_regs->len; i++) { + GDBRegDesc *grd = &g_array_index(gdbstub_regs, GDBRegDesc, i); + gpointer key = cpu_plus_reg_to_key(cs, grd->gdb_reg); + struct qemu_plugin_register *val = g_hash_table_lookup(reg_handles, key); + + /* Doesn't exist, create one */ + if (!val) { + val = g_new0(struct qemu_plugin_register, 1); + val->gdb_reg_num = grd->gdb_reg; + val->name = g_intern_string(grd->name); + + g_hash_table_insert(reg_handles, key, val); + } + + /* Create a record for the plugin */ + qemu_plugin_reg_descriptor desc = { + .handle = val, + .name = val->name, + .feature = g_intern_string(grd->feature_name) + }; + g_array_append_val(find_data, desc); + } + } + + return find_data; +} + +GArray * qemu_plugin_get_registers(unsigned int vcpu) +{ + CPUState *cs = qemu_get_cpu(vcpu); + if (cs) { + g_autoptr(GArray) regs = gdb_get_register_list(cs); + return regs->len ? create_register_handles(cs, regs) : NULL; + } else { + return NULL; + } +} + +int qemu_plugin_read_register(unsigned int vcpu, struct qemu_plugin_register *reg, GByteArray *buf) +{ + CPUState *cs = qemu_get_cpu(vcpu); + /* assert with debugging on? */ + return gdb_read_register(cs, buf, reg->gdb_reg_num); +} + +static void __attribute__((__constructor__)) qemu_api_init(void) +{ + qemu_mutex_init(®_handle_lock); + +} diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols index 71f6c90549d..6963585c1ea 100644 --- a/plugins/qemu-plugins.symbols +++ b/plugins/qemu-plugins.symbols @@ -3,6 +3,7 @@ qemu_plugin_end_code; qemu_plugin_entry_code; qemu_plugin_get_hwaddr; + qemu_plugin_get_registers; qemu_plugin_hwaddr_device_name; qemu_plugin_hwaddr_is_io; qemu_plugin_hwaddr_phys_addr; @@ -20,6 +21,7 @@ qemu_plugin_n_vcpus; qemu_plugin_outs; qemu_plugin_path_to_binary; + qemu_plugin_read_register; qemu_plugin_register_atexit_cb; qemu_plugin_register_flush_cb; qemu_plugin_register_vcpu_exit_cb; From patchwork Wed Jan 3 17:33:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510325 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C6C81C2AE for ; Wed, 3 Jan 2024 17:39:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WiyN934h" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-40d894764e7so25111475e9.1 for ; Wed, 03 Jan 2024 09:39:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303548; x=1704908348; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TjgnYFLBOv5uB2tWkg/kIZdJs8xT0wOiNJtUez299cQ=; b=WiyN934hFFJVgf29/LTKU1dmEE+URfFeQ7ceRCEAk7HXiaAG7ZgyqvIjFAsJ2Yaldj CdSGzlPhivRfWDId6COeDn5Ds48iAqwibdITUR3SuedhIsek+6czuWWRx3zK9IlWgz9C CoH+yaICIBlfR2ywTxmJk4mJCmk1oliUcOZm2G9IXZmMcU1ydKyzj6DHU/CNS31n4528 K2vF+9TUz0RkzT88jhqUNrV2A34KJm4uEuhk4OoDovDxJvIcVTBVa2yEXaAAQP5CZFYR Gc2iz6dq+cGWZCu0nbyAnfqQ863jINYQAxzcM7gJ18R9hmXZ3hWe1GRAFU37l7lDs3BP FdtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303548; x=1704908348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TjgnYFLBOv5uB2tWkg/kIZdJs8xT0wOiNJtUez299cQ=; b=eL7yceIvl2pl2aGd0BWdsHH3apTLsBETvnRn/jSkSzZnJgU6g7vJU/8rxu0ZFh8iZu K4jl4OTwEtpQZAO9i9cWIG5ugWHjcevQn1h+ncXH5A+dvGkg70j16iEncphgVPLfDcwI vWu/7yN91xFGsb8r75MsMHjI5cUopgkYBvbdYnZpfn/48JQFtjOqZImLDVwzPVxwkayu XaoNpOaHJdjp+U8HNhpSuIYett1DRg2XQm0txrs6zQ+DWq7669lKt0rP9TJJFNQ+PzQK +zkMtK1iA/+PmqcSS+TLes8PoJZXpojt4oFm1Fmdz4a7TI2h8WapcMacqJzuGmagrYoC WS3Q== X-Gm-Message-State: AOJu0YyO+U8fqCwR0sB8qOLgFSFwUhR61QYWhzIWdw5aPgOzCZ5ZpsF7 6x1Rg9trGbFlu46dKkaldGlwi/3YCzQUyQ== X-Google-Smtp-Source: AGHT+IECwsD+EsV7hgtfvLIigahdUQBBQ70d0NAK/wXl9lkOBh690IpgKO7C8ioQ4D+awmSxFlPX5A== X-Received: by 2002:a7b:cb92:0:b0:40d:38cd:ad5c with SMTP id m18-20020a7bcb92000000b0040d38cdad5cmr6656970wmi.263.1704303548411; Wed, 03 Jan 2024 09:39:08 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i15-20020a05600c354f00b0040d604dea3bsm2972869wmq.4.2024.01.03.09.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:39:05 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 542725F9D4; Wed, 3 Jan 2024 17:33:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 39/43] contrib/plugins: fix imatch Date: Wed, 3 Jan 2024 17:33:45 +0000 Message-Id: <20240103173349.398526-40-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We can't directly save the ephemeral imatch from argv as that memory will get recycled. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- contrib/plugins/execlog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c index 82dc2f584e2..f262e5555eb 100644 --- a/contrib/plugins/execlog.c +++ b/contrib/plugins/execlog.c @@ -199,7 +199,7 @@ static void parse_insn_match(char *match) if (!imatches) { imatches = g_ptr_array_new(); } - g_ptr_array_add(imatches, match); + g_ptr_array_add(imatches, g_strdup(match)); } static void parse_vaddr_match(char *match) From patchwork Wed Jan 3 17:33:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510336 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 509891CFA4 for ; Wed, 3 Jan 2024 17:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pzHvHtyi" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-32f8441dfb5so10215751f8f.0 for ; Wed, 03 Jan 2024 09:39:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303556; x=1704908356; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6qYxYpnr0vzCXiIKNDoO95XioKhgHwYSQEn7vMTXP0k=; b=pzHvHtyi+zKl4qKRERxp1hIIYgSLOOrDKNI9UFKr3JKPMA89TJKdLe3PTgEL7aroiq oKTcKHrcrvSUn9WiYPWQyMWlgwpTVwKd5V77J6ioXmpm6VCUGwcYc1IUKM/wIvykH88b il8qfloOtKCab8GP0F5ZVaj2/37SW+OLyZF0OPIqJcCIODjEUj1HRewyyZ5K9d5dPB/p +CqNXqBmX7G3BdvvPOV2UtMjQhsjhEUlDaiOLXtQZ9lEQpii98EHwtk/5YtOTuKRJdm+ sdhMNs8SshkpZVB0bkijEpY7W28vJmtGML7NxfWRiTADljzqfakDg4d6NUPg9jiJiru1 LfYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303556; x=1704908356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6qYxYpnr0vzCXiIKNDoO95XioKhgHwYSQEn7vMTXP0k=; b=qM8muR0lgh0DifbuH8C3VzrRg9DVKrALwAPjNK1O9veZasece7dLsnbu07jS2X81RV fS32AX0EwJ1AadoTisDc6KhcM7adoLDnCZNTBo+sTg3teN3wUy57/Lt+hGolQUb4/RTJ sllMQbs5g+1bBx08ZnDDVg13ED18f0GMsTB96OXlOKwFzHaIIqzWkKihjEY8xt/SjCMa 7PTtO++tfcAOJzPJzE8jGGmQhT1oLyPLSy2iTO5WYDL7hboukfdWxghaRW0sSJlk65cU S7hwKirpB8FGksmwqMqjvECLds2aEkhj2RHAfGvt1oVQAMmaT+jfk1Ui1NYT1J/C3BwX D2jw== X-Gm-Message-State: AOJu0YzZRX5uHYcMz/2AD3fjM4hdiUzAod51KAQDLN0lyYqfAxkB/4KE b8eICHrM0m7aq6tA/3/CzkNyWIm1v/ZldQ== X-Google-Smtp-Source: AGHT+IFirHy9EDbCpJhUcCOWZ36HyZDOq8CLVldsPYnvJBVFXEf2kuTpqZW9jVagG31llrW0iPzfwg== X-Received: by 2002:adf:e747:0:b0:336:6722:19f with SMTP id c7-20020adfe747000000b003366722019fmr10341379wrn.29.1704303556598; Wed, 03 Jan 2024 09:39:16 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a16-20020a056000101000b003366a9cb0d1sm31080983wrx.92.2024.01.03.09.39.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:39:13 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 6B2135F9D5; Wed, 3 Jan 2024 17:33:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis , Akihiko Odaki Subject: [PATCH v2 40/43] contrib/plugins: extend execlog to track register changes Date: Wed, 3 Jan 2024 17:33:46 +0000 Message-Id: <20240103173349.398526-41-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 With the new plugin register API we can now track changes to register values. Currently the implementation is fairly dumb which will slow down if a large number of register values are being tracked. This could be improved by only instrumenting instructions which mention registers we are interested in tracking. Example usage: ./qemu-aarch64 -D plugin.log -d plugin \ -cpu max,sve256=on \ -plugin contrib/plugins/libexeclog.so,reg=sp,reg=z\* \ ./tests/tcg/aarch64-linux-user/sha512-sve will display in the execlog any changes to the stack pointer (sp) and the SVE Z registers. Signed-off-by: Alex Bennée Cc: Akihiko Odaki Based-On: <20231025093128.33116-19-akihiko.odaki@daynix.com> --- v3 - prefix 0x to register value v2 - we now do the glob-like search in the plugin itself. - fix some erroneous cpus->cpu vAJB: Changes for the new API with a simpler glob based "reg" specifier which can be specified multiple times. --- docs/devel/tcg-plugins.rst | 9 +- contrib/plugins/execlog.c | 189 ++++++++++++++++++++++++++++--------- 2 files changed, 153 insertions(+), 45 deletions(-) diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index 81dcd43a612..3a0962723d7 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -497,6 +497,14 @@ arguments if required:: $ qemu-system-arm $(QEMU_ARGS) \ -plugin ./contrib/plugins/libexeclog.so,ifilter=st1w,afilter=0x40001808 -d plugin +This plugin can also dump registers when they change value. Specify the name of the +registers with multiple ``reg`` options. You can also use glob style matching if you wish:: + + $ qemu-system-arm $(QEMU_ARGS) \ + -plugin ./contrib/plugins/libexeclog.so,reg=\*_el2,reg=sp -d plugin + +Be aware that each additional register to check will slow down execution quite considerably. + - contrib/plugins/cache.c Cache modelling plugin that measures the performance of a given L1 cache @@ -583,4 +591,3 @@ The following API is generated from the inline documentation in include the full kernel-doc annotations. .. kernel-doc:: include/qemu/qemu-plugin.h - diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c index f262e5555eb..c20e88a6941 100644 --- a/contrib/plugins/execlog.c +++ b/contrib/plugins/execlog.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2021, Alexandre Iooss * - * Log instruction execution with memory access. + * Log instruction execution with memory access and register changes * * License: GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. @@ -15,30 +15,29 @@ #include +typedef struct { + struct qemu_plugin_register *handle; + GByteArray *last; + GByteArray *new; + const char *name; +} Register; + +typedef struct CPU { + /* Store last executed instruction on each vCPU as a GString */ + GString *last_exec; + /* Ptr array of Register */ + GPtrArray *registers; +} CPU; + QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION; -/* Store last executed instruction on each vCPU as a GString */ -static GPtrArray *last_exec; +static CPU *cpus; +static int num_cpus; static GRWLock expand_array_lock; static GPtrArray *imatches; static GArray *amatches; - -/* - * Expand last_exec array. - * - * As we could have multiple threads trying to do this we need to - * serialise the expansion under a lock. - */ -static void expand_last_exec(int cpu_index) -{ - g_rw_lock_writer_lock(&expand_array_lock); - while (cpu_index >= last_exec->len) { - GString *s = g_string_new(NULL); - g_ptr_array_add(last_exec, s); - } - g_rw_lock_writer_unlock(&expand_array_lock); -} +static GPtrArray *rmatches; /** * Add memory read or write information to current instruction log @@ -50,8 +49,8 @@ static void vcpu_mem(unsigned int cpu_index, qemu_plugin_meminfo_t info, /* Find vCPU in array */ g_rw_lock_reader_lock(&expand_array_lock); - g_assert(cpu_index < last_exec->len); - s = g_ptr_array_index(last_exec, cpu_index); + g_assert(cpu_index < num_cpus); + s = cpus[cpu_index].last_exec; g_rw_lock_reader_unlock(&expand_array_lock); /* Indicate type of memory access */ @@ -77,28 +76,46 @@ static void vcpu_mem(unsigned int cpu_index, qemu_plugin_meminfo_t info, */ static void vcpu_insn_exec(unsigned int cpu_index, void *udata) { - GString *s; + CPU *cpu; - /* Find or create vCPU in array */ g_rw_lock_reader_lock(&expand_array_lock); - if (cpu_index >= last_exec->len) { - g_rw_lock_reader_unlock(&expand_array_lock); - expand_last_exec(cpu_index); - g_rw_lock_reader_lock(&expand_array_lock); - } - s = g_ptr_array_index(last_exec, cpu_index); + g_assert(cpu_index < num_cpus); + cpu = &cpus[cpu_index]; g_rw_lock_reader_unlock(&expand_array_lock); /* Print previous instruction in cache */ - if (s->len) { - qemu_plugin_outs(s->str); + if (cpu->last_exec->len) { + if (cpu->registers) { + for (int n = 0; n < cpu->registers->len; n++) { + Register *reg = cpu->registers->pdata[n]; + int sz; + + g_byte_array_set_size(reg->new, 0); + sz = qemu_plugin_read_register(cpu_index, reg->handle, reg->new); + g_assert(sz == reg->last->len); + + if (memcmp(reg->last->data, reg->new->data, sz)) { + GByteArray *temp = reg->last; + g_string_append_printf(cpu->last_exec, ", %s -> 0x", reg->name); + /* TODO: handle BE properly */ + for (int i = sz; i >= 0; i--) { + g_string_append_printf(cpu->last_exec, "%02x", + reg->new->data[i]); + } + reg->last = reg->new; + reg->new = temp; + } + } + } + + qemu_plugin_outs(cpu->last_exec->str); qemu_plugin_outs("\n"); } /* Store new instruction in cache */ /* vcpu_mem will add memory access information to last_exec */ - g_string_printf(s, "%u, ", cpu_index); - g_string_append(s, (char *)udata); + g_string_printf(cpus[cpu_index].last_exec, "%u, ", cpu_index); + g_string_append(cpus[cpu_index].last_exec, (char *)udata); } /** @@ -167,8 +184,10 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) QEMU_PLUGIN_MEM_RW, NULL); /* Register callback on instruction */ - qemu_plugin_register_vcpu_insn_exec_cb(insn, vcpu_insn_exec, - QEMU_PLUGIN_CB_NO_REGS, output); + qemu_plugin_register_vcpu_insn_exec_cb( + insn, vcpu_insn_exec, + rmatches ? QEMU_PLUGIN_CB_R_REGS : QEMU_PLUGIN_CB_NO_REGS, + output); /* reset skip */ skip = (imatches || amatches); @@ -177,17 +196,86 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) } } +static Register *init_vcpu_register(int vcpu_index, + qemu_plugin_reg_descriptor *desc) +{ + Register *reg = g_new0(Register, 1); + int r; + + reg->handle = desc->handle; + reg->name = g_strdup(desc->name); + reg->last = g_byte_array_new(); + reg->new = g_byte_array_new(); + + /* read the initial value */ + r = qemu_plugin_read_register(vcpu_index, reg->handle, reg->last); + g_assert(r > 0); + return reg; +} + +static registers_init(int vcpu_index) +{ + GPtrArray *registers = g_ptr_array_new(); + g_autoptr(GArray) reg_list = qemu_plugin_get_registers(vcpu_index); + + if (reg_list && reg_list->len) { + /* + * Go through each register in the complete list and + * see if we want to track it. + */ + for (int r = 0; r < reg_list->len; r++) { + qemu_plugin_reg_descriptor *rd = &g_array_index( + reg_list, qemu_plugin_reg_descriptor, r); + for (int p = 0; p < rmatches->len; p++) { + g_autoptr(GPatternSpec) pat = g_pattern_spec_new(rmatches->pdata[p]); + if (g_pattern_match_string(pat, rd->name)) { + Register *reg = init_vcpu_register(vcpu_index, rd); + g_ptr_array_add(registers, reg); + } + } + } + } + cpus[num_cpus].registers = registers; +} + +/* + * Initialise a new vcpu/thread with: + * - last_exec tracking data + * - list of tracked registers + * - initial value of registers + * + * As we could have multiple threads trying to do this we need to + * serialise the expansion under a lock. + */ +static void vcpu_init(qemu_plugin_id_t id, unsigned int vcpu_index) +{ + g_rw_lock_writer_lock(&expand_array_lock); + + if (vcpu_index >= num_cpus) { + cpus = g_realloc_n(cpus, vcpu_index + 1, sizeof(*cpus)); + while (vcpu_index >= num_cpus) { + cpus[num_cpus].last_exec = g_string_new(NULL); + + /* Any registers to track? */ + if (rmatches && rmatches->len) { + registers_init(vcpu_index); + } + num_cpus++; + } + } + + g_rw_lock_writer_unlock(&expand_array_lock); +} + /** * On plugin exit, print last instruction in cache */ static void plugin_exit(qemu_plugin_id_t id, void *p) { guint i; - GString *s; - for (i = 0; i < last_exec->len; i++) { - s = g_ptr_array_index(last_exec, i); - if (s->str) { - qemu_plugin_outs(s->str); + for (i = 0; i < num_cpus; i++) { + if (cpus[i].last_exec->str) { + qemu_plugin_outs(cpus[i].last_exec->str); qemu_plugin_outs("\n"); } } @@ -212,6 +300,18 @@ static void parse_vaddr_match(char *match) g_array_append_val(amatches, v); } +/* + * We have to wait until vCPUs are started before we can check the + * patterns find anything. + */ +static void add_regpat(char *regpat) +{ + if (!rmatches) { + rmatches = g_ptr_array_new(); + } + g_ptr_array_add(rmatches, g_strdup(regpat)); +} + /** * Install the plugin */ @@ -224,9 +324,7 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, * we don't know the size before emulation. */ if (info->system_emulation) { - last_exec = g_ptr_array_sized_new(info->system.max_vcpus); - } else { - last_exec = g_ptr_array_new(); + cpus = g_new(CPU, info->system.max_vcpus); } for (int i = 0; i < argc; i++) { @@ -236,13 +334,16 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, parse_insn_match(tokens[1]); } else if (g_strcmp0(tokens[0], "afilter") == 0) { parse_vaddr_match(tokens[1]); + } else if (g_strcmp0(tokens[0], "reg") == 0) { + add_regpat(tokens[1]); } else { fprintf(stderr, "option parsing failed: %s\n", opt); return -1; } } - /* Register translation block and exit callbacks */ + /* Register init, translation block and exit callbacks */ + qemu_plugin_register_vcpu_init_cb(id, vcpu_init); qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans); qemu_plugin_register_atexit_cb(id, plugin_exit, NULL); From patchwork Wed Jan 3 17:33:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510330 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF59E1CA8C for ; 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Wed, 03 Jan 2024 09:39:08 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 83FBF5F9D6; Wed, 3 Jan 2024 17:33:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 41/43] contrib/plugins: optimise the register value tracking Date: Wed, 3 Jan 2024 17:33:47 +0000 Message-Id: <20240103173349.398526-42-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This adds an additional flag which attempts to optimise the register tracking by only instrumenting instructions which are likely to change its value. This relies on the disassembler showing up the register names in disassembly so is only enabled when asked for. Signed-off-by: Alex Bennée --- docs/devel/tcg-plugins.rst | 10 +- contrib/plugins/execlog.c | 189 ++++++++++++++++++++++++++++++------- 2 files changed, 165 insertions(+), 34 deletions(-) diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index 3a0962723d7..fa7421279f5 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -503,7 +503,15 @@ registers with multiple ``reg`` options. You can also use glob style matching if $ qemu-system-arm $(QEMU_ARGS) \ -plugin ./contrib/plugins/libexeclog.so,reg=\*_el2,reg=sp -d plugin -Be aware that each additional register to check will slow down execution quite considerably. +Be aware that each additional register to check will slow down +execution quite considerably. You can optimise the number of register +checks done by using the rdisas option. This will only instrument +instructions that mention the registers in question in disassembly. +This is not foolproof as some instructions implicitly change +instructions. You can use the ifilter to catch these cases: + + $ qemu-system-arm $(QEMU_ARGS) \ + -plugin ./contrib/plugins/libexeclog.so,ifilter=msr,ifilter=blr,reg=x30,reg=\*_el1,rdisas=on - contrib/plugins/cache.c diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c index c20e88a6941..a5269baf067 100644 --- a/contrib/plugins/execlog.c +++ b/contrib/plugins/execlog.c @@ -27,6 +27,7 @@ typedef struct CPU { GString *last_exec; /* Ptr array of Register */ GPtrArray *registers; + int index; } CPU; QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION; @@ -38,6 +39,9 @@ static GRWLock expand_array_lock; static GPtrArray *imatches; static GArray *amatches; static GPtrArray *rmatches; +static bool disas_assist; +static GMutex add_reg_name_lock; +static GPtrArray *all_reg_names; /** * Add memory read or write information to current instruction log @@ -72,9 +76,14 @@ static void vcpu_mem(unsigned int cpu_index, qemu_plugin_meminfo_t info, } /** - * Log instruction execution + * Log instruction execution, outputting the last one. + * + * vcpu_insn_exec() is a copy and paste of vcpu_insn_exec_with_regs() + * without the checking of register values when we've attempted to + * optimise with disas_assist. */ -static void vcpu_insn_exec(unsigned int cpu_index, void *udata) + +static CPU *get_cpu(int cpu_index) { CPU *cpu; @@ -83,39 +92,87 @@ static void vcpu_insn_exec(unsigned int cpu_index, void *udata) cpu = &cpus[cpu_index]; g_rw_lock_reader_unlock(&expand_array_lock); + return cpu; +} + +static void insn_check_regs(CPU *cpu) { + for (int n = 0; n < cpu->registers->len; n++) { + Register *reg = cpu->registers->pdata[n]; + int sz; + + g_byte_array_set_size(reg->new, 0); + sz = qemu_plugin_read_register(cpu->index, reg->handle, reg->new); + g_assert(sz == reg->last->len); + + if (memcmp(reg->last->data, reg->new->data, sz)) { + GByteArray *temp = reg->last; + g_string_append_printf(cpu->last_exec, ", %s -> 0x", reg->name); + /* TODO: handle BE properly */ + for (int i = sz; i >= 0; i--) { + g_string_append_printf(cpu->last_exec, "%02x", + reg->new->data[i]); + } + reg->last = reg->new; + reg->new = temp; + } + } +} + +/* Log last instruction while checking registers */ +static void vcpu_insn_exec_with_regs(unsigned int cpu_index, void *udata) +{ + CPU *cpu = get_cpu(cpu_index); + /* Print previous instruction in cache */ if (cpu->last_exec->len) { if (cpu->registers) { - for (int n = 0; n < cpu->registers->len; n++) { - Register *reg = cpu->registers->pdata[n]; - int sz; - - g_byte_array_set_size(reg->new, 0); - sz = qemu_plugin_read_register(cpu_index, reg->handle, reg->new); - g_assert(sz == reg->last->len); - - if (memcmp(reg->last->data, reg->new->data, sz)) { - GByteArray *temp = reg->last; - g_string_append_printf(cpu->last_exec, ", %s -> 0x", reg->name); - /* TODO: handle BE properly */ - for (int i = sz; i >= 0; i--) { - g_string_append_printf(cpu->last_exec, "%02x", - reg->new->data[i]); - } - reg->last = reg->new; - reg->new = temp; - } - } + insn_check_regs(cpu); + } + + qemu_plugin_outs(cpu->last_exec->str); + qemu_plugin_outs("\n"); + } + + /* Store new instruction in cache */ + /* vcpu_mem will add memory access information to last_exec */ + g_string_printf(cpu->last_exec, "%u, ", cpu_index); + g_string_append(cpu->last_exec, (char *)udata); +} + +/* Log last instruction while checking registers, ignore next */ +static void vcpu_insn_exec_only_regs(unsigned int cpu_index, void *udata) +{ + CPU *cpu = get_cpu(cpu_index); + + /* Print previous instruction in cache */ + if (cpu->last_exec->len) { + if (cpu->registers) { + insn_check_regs(cpu); } qemu_plugin_outs(cpu->last_exec->str); qemu_plugin_outs("\n"); } + /* reset */ + cpu->last_exec->len = 0; +} + +/* Log last instruction without checking regs, setup next */ +static void vcpu_insn_exec(unsigned int cpu_index, void *udata) +{ + CPU *cpu = get_cpu(cpu_index); + + /* Print previous instruction in cache */ + if (cpu->last_exec->len) { + qemu_plugin_outs(cpu->last_exec->str); + qemu_plugin_outs("\n"); + } + /* Store new instruction in cache */ /* vcpu_mem will add memory access information to last_exec */ - g_string_printf(cpus[cpu_index].last_exec, "%u, ", cpu_index); - g_string_append(cpus[cpu_index].last_exec, (char *)udata); + g_string_printf(cpu->last_exec, "%u, ", cpu_index); + g_string_append(cpu->last_exec, (char *)udata); } /** @@ -128,6 +185,8 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) { struct qemu_plugin_insn *insn; bool skip = (imatches || amatches); + bool check_regs_this = rmatches; + bool check_regs_next = false; size_t n = qemu_plugin_tb_n_insns(tb); for (size_t i = 0; i < n; i++) { @@ -148,7 +207,8 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) /* * If we are filtering we better check out if we have any * hits. The skip "latches" so we can track memory accesses - * after the instruction we care about. + * after the instruction we care about. Also enable register + * checking on the next instruction. */ if (skip && imatches) { int j; @@ -156,6 +216,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) char *m = g_ptr_array_index(imatches, j); if (g_str_has_prefix(insn_disas, m)) { skip = false; + check_regs_next = rmatches; } } } @@ -170,8 +231,38 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) } } + /* + * Check the disassembly to see if a register we care about + * will be affected by this instruction. This relies on the + * dissembler doing something sensible for the registers we + * care about. + */ + if (disas_assist && rmatches) { + check_regs_next = false; + gchar *args = g_strstr_len(insn_disas, -1, " "); + for (int n = 0; n < all_reg_names->len; n++) { + gchar *reg = g_ptr_array_index(all_reg_names, n); + if (g_strrstr(args, reg)) { + check_regs_next = true; + skip = false; + } + } + } + + /* + * We now have 3 choices: + * + * Log this instruction normally + * Log this instruction checking for register changes + * Don't log this instruction but check for register changes from the last one + */ + if (skip) { - g_free(insn_disas); + if (check_regs_this) { + qemu_plugin_register_vcpu_insn_exec_cb(insn, + vcpu_insn_exec_only_regs, + QEMU_PLUGIN_CB_R_REGS, NULL); + } } else { uint32_t insn_opcode; insn_opcode = *((uint32_t *)qemu_plugin_insn_data(insn)); @@ -184,15 +275,28 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) QEMU_PLUGIN_MEM_RW, NULL); /* Register callback on instruction */ - qemu_plugin_register_vcpu_insn_exec_cb( - insn, vcpu_insn_exec, - rmatches ? QEMU_PLUGIN_CB_R_REGS : QEMU_PLUGIN_CB_NO_REGS, - output); + if (check_regs_this) { + qemu_plugin_register_vcpu_insn_exec_cb( + insn, vcpu_insn_exec_with_regs, + QEMU_PLUGIN_CB_R_REGS, + output); + } else { + qemu_plugin_register_vcpu_insn_exec_cb( + insn, vcpu_insn_exec, + QEMU_PLUGIN_CB_NO_REGS, + output); + } /* reset skip */ skip = (imatches || amatches); } + /* set regs for next */ + if (disas_assist && rmatches) { + check_regs_this = check_regs_next; + } + + g_free(insn_disas); } } @@ -200,10 +304,11 @@ static Register *init_vcpu_register(int vcpu_index, qemu_plugin_reg_descriptor *desc) { Register *reg = g_new0(Register, 1); + g_autofree gchar *lower = g_utf8_strdown(desc->name, -1); int r; reg->handle = desc->handle; - reg->name = g_strdup(desc->name); + reg->name = g_intern_string(lower); reg->last = g_byte_array_new(); reg->new = g_byte_array_new(); @@ -213,7 +318,7 @@ static Register *init_vcpu_register(int vcpu_index, return reg; } -static registers_init(int vcpu_index) +static void registers_init(int vcpu_index) { GPtrArray *registers = g_ptr_array_new(); g_autoptr(GArray) reg_list = qemu_plugin_get_registers(vcpu_index); @@ -228,9 +333,20 @@ static registers_init(int vcpu_index) reg_list, qemu_plugin_reg_descriptor, r); for (int p = 0; p < rmatches->len; p++) { g_autoptr(GPatternSpec) pat = g_pattern_spec_new(rmatches->pdata[p]); - if (g_pattern_match_string(pat, rd->name)) { + g_autofree gchar *rd_lower = g_utf8_strdown(rd->name, -1); + if (g_pattern_match_string(pat, rd->name) || + g_pattern_match_string(pat, rd_lower)) { Register *reg = init_vcpu_register(vcpu_index, rd); g_ptr_array_add(registers, reg); + + /* we need a list of regnames at TB translation time */ + if (disas_assist) { + g_mutex_lock(&add_reg_name_lock); + if (!g_ptr_array_find(all_reg_names, reg->name, NULL)) { + g_ptr_array_add(all_reg_names, reg->name); + } + g_mutex_unlock(&add_reg_name_lock); + } } } } @@ -254,6 +370,7 @@ static void vcpu_init(qemu_plugin_id_t id, unsigned int vcpu_index) if (vcpu_index >= num_cpus) { cpus = g_realloc_n(cpus, vcpu_index + 1, sizeof(*cpus)); while (vcpu_index >= num_cpus) { + cpus[num_cpus].index = vcpu_index; cpus[num_cpus].last_exec = g_string_new(NULL); /* Any registers to track? */ @@ -336,6 +453,12 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, parse_vaddr_match(tokens[1]); } else if (g_strcmp0(tokens[0], "reg") == 0) { add_regpat(tokens[1]); + } else if (g_strcmp0(tokens[0], "rdisas") == 0) { + if (!qemu_plugin_bool_parse(tokens[0], tokens[1], &disas_assist)) { + fprintf(stderr, "boolean argument parsing failed: %s\n", opt); + return -1; + } + all_reg_names = g_ptr_array_new(); } else { fprintf(stderr, "option parsing failed: %s\n", opt); return -1; From patchwork Wed Jan 3 17:33:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510324 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 303111C290 for ; Wed, 3 Jan 2024 17:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ymG/a4gS" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40d88fff7faso24918075e9.3 for ; Wed, 03 Jan 2024 09:39:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704303546; x=1704908346; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8xNYPWzXiJVejiOzH0lqPZBPc9FMUdMG5VHkvS57+tg=; b=ymG/a4gSaRy8JaljhTTVeFWtrfO25HWC4BBqTT/SdJJd2xowuK8kCaPjMA5U/5wnsv IMnruiYXgrrPlaShiUE6ezqq03D4Uo4MVU8GXK1C3BAUGLE37NjJl0T53Dex4qUKp/uB XgzcTKXeXY/QDDTnv4lZkAF9AcMaxGQv6oSiqYvOoQ3xkuIbscQxYEjE9Q8KjrcpEBNd yoSdTQb6grpJvpPuQYV7WDpyzmLYWwRjL0YWnwS4Rpl753F2CPpjbAgHRcAWLt+I/poI 6iNH5DB64wplzoKcGOlRzPAeCAy/OndkMKPmoKfnip6NBm5SI0DhADpV5NWTkjp/6loG SJsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303546; x=1704908346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8xNYPWzXiJVejiOzH0lqPZBPc9FMUdMG5VHkvS57+tg=; b=dRMgsAx5BCw+3GaEnG3QNxaec7IgaetNkmz/ltAV8kkGnMX13A/ZH14iJxuedjavpG I6HruVi8X2tyM+jBhWNByZWlljxysNcZDTN/C4pER/IiOFmzFN6pFSW7lHu+iSzTNcJt bmsCR7kAPBbVv7gmBFEbcNe2EhiE0BK1f9WICHfbM9+v//zotX/QCI11pEmqspvtoMOV mEXfWoFcb/w5yAZYEPXVDhpZPygRBiftmUiIsohdMYKk/fN5lVBNvAL4jvRcRmbl1dNV DELgKcqXqKLgFDUP/KUAHwV1rjOqZ1p469ynf7J/yekQWYdT6Pg1IZyhmCS+50d7nBUD S8lA== X-Gm-Message-State: AOJu0YzwlyrppRKDllZkMCpoLQxzAYe1ybxg7/CV5IAClzSMNFIxGL/n CCyAfF/denEx71UPurDlrVW3giEl7YSdsg== X-Google-Smtp-Source: AGHT+IH6oUVPIjcqWyhSJB2yGsQGHuXcBqAGxA30oE5c9ZUEOh+o9kgjc494ZEeNCFmoTVtGbVsERw== X-Received: by 2002:a05:600c:2988:b0:40c:657d:cf12 with SMTP id r8-20020a05600c298800b0040c657dcf12mr5061241wmd.111.1704303546516; Wed, 03 Jan 2024 09:39:06 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040d77ebd55csm2974446wmb.13.2024.01.03.09.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:39:05 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 9C6095F9D7; Wed, 3 Jan 2024 17:33:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 42/43] docs/devel: lift example and plugin API sections up Date: Wed, 3 Jan 2024 17:33:48 +0000 Message-Id: <20240103173349.398526-43-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This makes them a bit more visible in the TCG emulation menu rather than hiding them away bellow the ToC limit. Signed-off-by: Alex Bennée Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé --- docs/devel/tcg-plugins.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index fa7421279f5..535a74684c5 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -143,7 +143,7 @@ requested. The plugin isn't completely uninstalled until the safe work has executed while all vCPUs are quiescent. Example Plugins ---------------- +=============== There are a number of plugins included with QEMU and you are encouraged to contribute your own plugins plugins upstream. There is a @@ -591,8 +591,8 @@ The plugin has a number of arguments, all of them are optional: configuration arguments implies ``l2=on``. (default: N = 2097152 (2MB), B = 64, A = 16) -API ---- +Plugin API +========== The following API is generated from the inline documentation in ``include/qemu/qemu-plugin.h``. Please ensure any updates to the API From patchwork Wed Jan 3 17:33:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 13510361 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BAF71C296 for ; Wed, 3 Jan 2024 17:49:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JwS8TueL" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-33723ad790cso4126822f8f.1 for ; Wed, 03 Jan 2024 09:49:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704304146; x=1704908946; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6SqdFcQlAJfCo/zD79U6TVq3bxpUqFYpwmC4QorajEA=; b=JwS8TueL+UtKELeg5mu79+APQavdn9Z/ZdGQ5TCZ7OuSxV6B7tGxVffN2bypXp5R3Y tDWQLADgoy890HpWTaA/m0hq+9e/Q9Pj8RVgxhiiFLU60Lp1VaxphG1GxUO8IKFutXxB dqo2+QPHTi/a3oz9nL+t5YWZh4ayrXU4po2GHqQX0H/JlTAXXMQqO+qrm1LWwWFMgQga FPyVCT6lRLCtTzMS7OAPS5MFt7Jvw43KQcpdeBq2yhsaHXxd535PnLQ2K0AyrT5zIZRl Xj6MFvsSGb6h1l+rJ0Y4840naFScXWO+H/sASXH+yQ8zs15BF+DBT+BPIgK9o9QM537X Hdww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704304146; x=1704908946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6SqdFcQlAJfCo/zD79U6TVq3bxpUqFYpwmC4QorajEA=; b=AcTnfkfke5Fg0H1UE6pyVkkA0kN+CNRCBxo7JZj8jvSmmNvZmvyC/ex3wu9D0/OoOa oynLxgy6qPjq3mtDhcp1DppJJAP1sdwsOvI5RCkZ1Z2P05RIcDTfGc3mclq8pLXrcKAU EAQvgzDjZpTJgkYhEFNxygZMrhn5emnYtF6sVfbmaPz27zWXlAKgJfY7n0ZHUbw42jWu tLs5o9h7kTTwlbU7U9GwtSfrY0aRfooQUyANYEeunJ9f6PlisY7FVuLuIYNLrfVxUKzx rWaMqVVWI8HRjS/XO9l5IhVinIzm7NrGGZkqeFY4wnL7OW3vRgbSoCLLXocBdPjlDPJS J/KQ== X-Gm-Message-State: AOJu0Yw/sWmyG0SiobOjHR4qy28MnnYWRkotdmden5GOFRebDi4n/gzt IUGIDaEgVSyGRBHFx+rrPAeOPBqIbepouw== X-Google-Smtp-Source: AGHT+IEJ8pbxuaW2ajiIhIsjZLjKvMEndaRM5euTVk/mz6c4/+Ko8TKlGfHnO3Mdder+FMkZ6TvagA== X-Received: by 2002:a5d:47ac:0:b0:337:4a09:b7d8 with SMTP id 12-20020a5d47ac000000b003374a09b7d8mr916886wrb.211.1704304146266; Wed, 03 Jan 2024 09:49:06 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id b15-20020a5d4b8f000000b00336a0c083easm26789106wrt.53.2024.01.03.09.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:49:05 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id B41EC5F9D8; Wed, 3 Jan 2024 17:33:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , Song Gao , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Hildenbrand , Aurelien Jarno , Yoshinori Sato , Yanan Wang , Bin Meng , Laurent Vivier , Michael Rolnik , Alexandre Iooss , David Woodhouse , Laurent Vivier , Paolo Bonzini , Brian Cain , Daniel Henrique Barboza , Beraldo Leal , Paul Durrant , Mahmoud Mandour , Thomas Huth , Liu Zhiwei , Cleber Rosa , kvm@vger.kernel.org, Peter Maydell , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Daniel Henrique Barboza , Nicholas Piggin , Palmer Dabbelt , Marcel Apfelbaum , Ilya Leoshkevich , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Eduardo Habkost , Pierrick Bouvier , qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v2 43/43] docs/devel: document some plugin assumptions Date: Wed, 3 Jan 2024 17:33:49 +0000 Message-Id: <20240103173349.398526-44-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240103173349.398526-1-alex.bennee@linaro.org> References: <20240103173349.398526-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 While we attempt to hide implementation details from the plugin we shouldn't be totally obtuse. Let the user know what they can and can't expect with the various instrumentation options. Signed-off-by: Alex Bennée Reviewed-by: Pierrick Bouvier --- docs/devel/tcg-plugins.rst | 49 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index 535a74684c5..9cc09d8c3da 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -112,6 +112,55 @@ details are opaque to plugins. The plugin is able to query select details of instructions and system configuration only through the exported *qemu_plugin* functions. +However the following assumptions can be made: + +Translation Blocks +++++++++++++++++++ + +All code will go through a translation phase although not all +translations will be necessarily be executed. You need to instrument +actual executions to track what is happening. + +It is quite normal to see the same address translated multiple times. +If you want to track the code in system emulation you should examine +the underlying physical address (``qemu_plugin_insn_haddr``) to take +into account the effects of virtual memory although if the system does +paging this will change too. + +Not all instructions in a block will always execute so if its +important to track individual instruction execution you need to +instrument them directly. However asynchronous interrupts will not +change control flow mid-block. + +Instructions +++++++++++++ + +Instruction instrumentation runs before the instruction executes. You +can be can be sure the instruction will be dispatched, but you can't +be sure it will complete. Generally this will be because of a +synchronous exception (e.g. SIGILL) triggered by the instruction +attempting to execute. If you want to be sure you will need to +instrument the next instruction as well. See the ``execlog.c`` plugin +for examples of how to track this and finalise details after execution. + +Memory Accesses ++++++++++++++++ + +Memory callbacks are called after a successful load or store. +Unsuccessful operations (i.e. faults) will not be visible to memory +instrumentation although the execution side effects can be observed +(e.g. entering a exception handler). + +System Idle and Resume States ++++++++++++++++++++++++++++++ + +The ``qemu_plugin_register_vcpu_idle_cb`` and +``qemu_plugin_register_vcpu_resume_cb`` functions can be used to track +when CPUs go into and return from sleep states when waiting for +external I/O. Be aware though that these may occur less frequently +than in real HW due to the inefficiencies of emulation giving less +chance for the CPU to idle. + Internals ---------