From patchwork Thu Jan 4 23:00:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511610 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3804A2D60A for ; Thu, 4 Jan 2024 23:00:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Hq1elv5O" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704409245; x=1735945245; h=subject:from:to:cc:date:message-id:mime-version: content-transfer-encoding; bh=5oVHEKSVeqJ5V9NFft7Okq63JdBPytenPTERDHI/xZk=; b=Hq1elv5O68jBuaI6dZCr9Qbs/uJ//z3gFqvAljWBacSWlfNooiQPR0Z5 zD3qxFE8gafeiIVtsjedq7aoY/Mbtw97Y9DEdE+/ZMPvWQ0/+A25YHPLr 9T97dPXnan3Lg7nuYihAxxNFFWwsbinO2saD9F1w2ceZF5z+uIvPR/vFN GEJDGq9Py5bRAger2/BVCvFrcKX/hf32wmN4ZYbzwKEkOwsXkJ5cxVMoY OKRvkCsOyhsNva5Arv1N10S1eAo09dKCkGcXCQ1RamoiXP6EcXggCmqqC 3ZLYc2RpKG5BlkXfHzVJyKv1/GyiwWzeuFF2A0j6OAoVAXWMbWpyTTbHQ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="387831510" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="387831510" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:00:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="924060527" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="924060527" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:00:43 -0800 Subject: [PATCH v3 1/4] cxl: Add check for NULL ptr after calling find_cxl_root() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 16:00:43 -0700 Message-ID: <170440924347.3570725.6271367271629367301.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In cxl_port_perf_data_calculate, the function fails to check for NULL ptr after calling find_cxl_root(). Add check to avoid NULL ptr dereferencing. Fixes: 7a4f148dd8d5 ("cxl: Compute the entire CXL path latency and bandwidth data") Signed-off-by: Dave Jiang --- drivers/cxl/core/cdat.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index cd84d87f597a..3dce4a201ddd 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -176,6 +176,9 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, } root_port = find_cxl_root(port); + if (!root_port) + return -ENODEV; + cxl_root = to_cxl_root(root_port); if (!cxl_root->ops || !cxl_root->ops->qos_class) return -EOPNOTSUPP; From patchwork Thu Jan 4 23:00:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511611 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 999BD2D03D for ; Thu, 4 Jan 2024 23:00:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A7r7lOnl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704409250; x=1735945250; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u/F9usMiwF4Ru0j9nvIR5fNOEh0aoZ141cb1CBnDeAo=; b=A7r7lOnlCATTD3ymrl44bYO1zHtjUgcN6r/XP7lcXaM9gftfWVcUckvL h7cNz/iJfM4j7bHIlwKpC877DxZMkUM3wWJcYzVGez9cbcrRWm4gfyy/1 HyESNW1wOMCRE2nDPfsPoovL6vAn236Vfz6ZdXdHADf2TK+1eY4W9lqGz zzYbO3TUN+sosk9JZ/9akOtxaTaFCWnnFJT3U/AokXy218BG/ZihPd3Si YyI3upZ1LsFU8E5YI8O6Ie4LcTVfMG3kgYA+zXi/znIN2cwiZ56MRXNJq YQ2rgMq0MS7ze+yeCM7TKJ35bQkkHr3hQAsyliLLpcXtqoRVsf4hQE0b9 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="387831525" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="387831525" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:00:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="846392333" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="846392333" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:00:49 -0800 Subject: [PATCH v3 2/4] cxl: Add missing device dereference after find_cxl_root() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 16:00:49 -0700 Message-ID: <170440924930.3570725.10428771109298188521.stgit@djiang5-mobl3> In-Reply-To: <170440924347.3570725.6271367271629367301.stgit@djiang5-mobl3> References: <170440924347.3570725.6271367271629367301.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 find_cxl_root() takes a reference on the 'struct device' before returning. A put_device() is needed when once the root port is no longer needed. cxl_port_perf_data_calculate() fails to dereference device. Add a __free() call to make sure the device reference is decremented when done. Fixes: 7a4f148dd8d5 ("cxl: Compute the entire CXL path latency and bandwidth data") Signed-off-by: Dave Jiang --- v3: - Declare root_port at the allocation point. --- drivers/cxl/core/cdat.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 3dce4a201ddd..c5031e90bb96 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -162,7 +162,6 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, struct xarray *dsmas_xa) { struct access_coordinate c; - struct cxl_port *root_port; struct cxl_root *cxl_root; struct dsmas_entry *dent; int valid_entries = 0; @@ -175,7 +174,8 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, return rc; } - root_port = find_cxl_root(port); + struct cxl_port *root_port __free(put_device) = find_cxl_root(port); + if (!root_port) return -ENODEV; From patchwork Thu Jan 4 23:00:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511612 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66B822D02F for ; Thu, 4 Jan 2024 23:00:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Cg/lu8Mh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704409256; x=1735945256; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2Es4ejT9sleoHotEBCE40z7GdBdyilnAj+LR4S/+zqg=; b=Cg/lu8MhtLnU0wtelMAgwEgXNyG+i6Kr4ZcHJWExp9aoXpJZVT1Zz/Vo RftQXPv/5RfrT8Wf7O6Xi++UV7UI7aQ8f85E1hS+cy75IHw6T5c3bG44J mHsjE8/P7mcmnvo6JSPoisD1dtJZz34OVsEGJVYJ6y0QG5gb6BWfTqg5M rxS8xm0wOGJvEEsHkcDbc0oTvYQnEeoyjeXk6hhaC9anNQdYqGP9ZNk1d ryxgXxnHKJPlyZuL7msxIFS/Cy5Yd4UkACLWpzyc+4nzqA/n2zdRwL+0Y NEtoUvNG0LDJY22uMS0hJQqYEZcdYTLH9GIdecPpja1jOELT5zw+aAPPL g==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="387831548" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="387831548" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:00:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="846392346" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="846392346" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:00:55 -0800 Subject: [PATCH v3 3/4] cxl: Refactor usages of cxl_root from being referenced indirectly From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Dan Williams , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 16:00:55 -0700 Message-ID: <170440925509.3570725.9669871754496155658.stgit@djiang5-mobl3> In-Reply-To: <170440924347.3570725.6271367271629367301.stgit@djiang5-mobl3> References: <170440924347.3570725.6271367271629367301.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Commit 790815902ec6 ("cxl: Add support for _DSM Function for retrieving QTG ID") introduced 'struct cxl_root', however all usages have been worked indirectly through cxl_port. Refactor code such as find_cxl_root() function to use 'struct cxl_root' directly. Suggested-by: Dan Williams Signed-off-by: Dave Jiang --- drivers/cxl/acpi.c | 3 ++- drivers/cxl/core/cdat.c | 19 ++++++++++--------- drivers/cxl/core/pmem.c | 6 ++++-- drivers/cxl/core/port.c | 4 ++-- drivers/cxl/cxl.h | 14 +++++++------- drivers/cxl/port.c | 12 ++++++++---- 6 files changed, 33 insertions(+), 25 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index afc712264d1c..37cfd5516024 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -295,10 +295,11 @@ cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord, return rc; } -static int cxl_acpi_qos_class(struct cxl_port *root_port, +static int cxl_acpi_qos_class(struct cxl_root *cxl_root, struct access_coordinate *coord, int entries, int *qos_class) { + struct cxl_port *root_port = &cxl_root->port; acpi_handle handle; struct device *dev; diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index c5031e90bb96..280ca1508f21 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -162,7 +162,6 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, struct xarray *dsmas_xa) { struct access_coordinate c; - struct cxl_root *cxl_root; struct dsmas_entry *dent; int valid_entries = 0; unsigned long index; @@ -174,12 +173,10 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, return rc; } - struct cxl_port *root_port __free(put_device) = find_cxl_root(port); - - if (!root_port) + struct cxl_root *cxl_root __free(put_device) = find_cxl_root(port); + if (!cxl_root) return -ENODEV; - cxl_root = to_cxl_root(root_port); if (!cxl_root->ops || !cxl_root->ops->qos_class) return -EOPNOTSUPP; @@ -196,7 +193,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, dent->coord.write_bandwidth); dent->entries = 1; - rc = cxl_root->ops->qos_class(root_port, &dent->coord, 1, &qos_class); + rc = cxl_root->ops->qos_class(cxl_root, &dent->coord, 1, &qos_class); if (rc != 1) continue; @@ -352,15 +349,19 @@ static int cxl_qos_class_verify(struct cxl_memdev *cxlmd) { struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); - struct cxl_port *root_port __free(put_device) = NULL; LIST_HEAD(__discard); struct list_head *discard __free(dpa_perf) = &__discard; + struct cxl_port *root_port; int rc; - root_port = find_cxl_root(cxlmd->endpoint); - if (!root_port) + struct cxl_root *cxl_root __free(put_device) = + find_cxl_root(cxlmd->endpoint); + + if (!cxl_root) return -ENODEV; + root_port = &cxl_root->port; + /* Check that the QTG IDs are all sane between end device and root decoders */ cxl_qos_match(root_port, &mds->ram_perf_list, discard); cxl_qos_match(root_port, &mds->pmem_perf_list, discard); diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c index fc94f5240327..da92a901b9e8 100644 --- a/drivers/cxl/core/pmem.c +++ b/drivers/cxl/core/pmem.c @@ -64,12 +64,14 @@ static int match_nvdimm_bridge(struct device *dev, void *data) struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) { - struct cxl_port *port = find_cxl_root(cxlmd->endpoint); + struct cxl_root *cxl_root = find_cxl_root(cxlmd->endpoint); + struct cxl_port *port; struct device *dev; - if (!port) + if (!cxl_root) return NULL; + port = &cxl_root->port; dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge); put_device(&port->dev); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 8c00fd6be730..b8af09464363 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -972,7 +972,7 @@ static bool dev_is_cxl_root_child(struct device *dev) return false; } -struct cxl_port *find_cxl_root(struct cxl_port *port) +struct cxl_root *find_cxl_root(struct cxl_port *port) { struct cxl_port *iter = port; @@ -982,7 +982,7 @@ struct cxl_port *find_cxl_root(struct cxl_port *port) if (!iter) return NULL; get_device(&iter->dev); - return iter; + return to_cxl_root(iter); } EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 492dbf63935f..8f43a06c4f72 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -617,12 +617,6 @@ struct cxl_port { long pci_latency; }; -struct cxl_root_ops { - int (*qos_class)(struct cxl_port *root_port, - struct access_coordinate *coord, int entries, - int *qos_class); -}; - /** * struct cxl_root - logical collection of root cxl_port items * @@ -640,6 +634,12 @@ to_cxl_root(const struct cxl_port *port) return container_of(port, struct cxl_root, port); } +struct cxl_root_ops { + int (*qos_class)(struct cxl_root *cxl_root, + struct access_coordinate *coord, int entries, + int *qos_class); +}; + static inline struct cxl_dport * cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) { @@ -734,7 +734,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct cxl_dport *parent_dport); struct cxl_root *devm_cxl_add_root(struct device *host, const struct cxl_root_ops *ops); -struct cxl_port *find_cxl_root(struct cxl_port *port); +struct cxl_root *find_cxl_root(struct cxl_port *port); int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); void cxl_bus_drain(void); diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index da3c3a08bd62..656f2e03d2ea 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -94,8 +94,8 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) struct cxl_endpoint_dvsec_info info = { .port = port }; struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); struct cxl_dev_state *cxlds = cxlmd->cxlds; + struct cxl_port *root_port; struct cxl_hdm *cxlhdm; - struct cxl_port *root; int rc; rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info); @@ -130,14 +130,18 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) * This can't fail in practice as CXL root exit unregisters all * descendant ports and that in turn synchronizes with cxl_port_probe() */ - root = find_cxl_root(port); + struct cxl_root *cxl_root __free(put_device) = find_cxl_root(port); + + if (!cxl_root) + return -ENODEV; + + root_port = &cxl_root->port; /* * Now that all endpoint decoders are successfully enumerated, try to * assemble regions from committed decoders */ - device_for_each_child(&port->dev, root, discover_region); - put_device(&root->dev); + device_for_each_child(&root_port->dev, root_port, discover_region); return 0; } From patchwork Thu Jan 4 23:01:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511613 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2727B2D021 for ; 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a="387831554" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="387831554" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:01:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="846392358" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="846392358" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:01:01 -0800 Subject: [PATCH v3 4/4] cxl: Introduce put_cxl_root() helper function to have symmetry of find_cxl_root() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Robert Richter , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 16:01:00 -0700 Message-ID: <170440926084.3570725.9962332024836108779.stgit@djiang5-mobl3> In-Reply-To: <170440924347.3570725.6271367271629367301.stgit@djiang5-mobl3> References: <170440924347.3570725.6271367271629367301.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a helper function put_cxl_root() to maintain symmetry for find_cxl_root() function instead of relying on open coding of the put_device() in order to dereference the 'struct device' that happens via get_device() in find_cxl_root(). Add cleanups for all code paths that calls put_device() after find_cxl_root(). Suggested-by: Robert Richter Signed-off-by: Dave Jiang --- v3: - Adjust for cxl_root as parameter for find_cxl_root() - Add NULL ptr check fore __free(). (Dan) - Fix DEFINE_FREE() macro to name it put_cxl_root (Dan) - Cleanup all functions calling put_cxl_root() and related calls. (Dan) v2: - Make put_cxl_root() an exported function to be symmetric to find_cxl_root(). (Robert) --- drivers/cxl/core/cdat.c | 5 +++-- drivers/cxl/core/pmem.c | 4 ++-- drivers/cxl/core/port.c | 9 +++++++++ drivers/cxl/cxl.h | 3 +++ drivers/cxl/port.c | 2 +- 5 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 280ca1508f21..260cf2d621cd 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -173,7 +173,8 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, return rc; } - struct cxl_root *cxl_root __free(put_device) = find_cxl_root(port); + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port); + if (!cxl_root) return -ENODEV; @@ -354,7 +355,7 @@ static int cxl_qos_class_verify(struct cxl_memdev *cxlmd) struct cxl_port *root_port; int rc; - struct cxl_root *cxl_root __free(put_device) = + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(cxlmd->endpoint); if (!cxl_root) diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c index da92a901b9e8..df3d11257511 100644 --- a/drivers/cxl/core/pmem.c +++ b/drivers/cxl/core/pmem.c @@ -64,7 +64,8 @@ static int match_nvdimm_bridge(struct device *dev, void *data) struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) { - struct cxl_root *cxl_root = find_cxl_root(cxlmd->endpoint); + struct cxl_root *cxl_root __free(put_cxl_root) = + find_cxl_root(cxlmd->endpoint); struct cxl_port *port; struct device *dev; @@ -73,7 +74,6 @@ struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) port = &cxl_root->port; dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge); - put_device(&port->dev); if (!dev) return NULL; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index b8af09464363..63a4e3c2baed 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -986,6 +986,15 @@ struct cxl_root *find_cxl_root(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL); +void put_cxl_root(struct cxl_root *cxl_root) +{ + if (!cxl_root) + return; + + put_device(&cxl_root->port.dev); +} +EXPORT_SYMBOL_NS_GPL(put_cxl_root, CXL); + static struct cxl_dport *find_dport(struct cxl_port *port, int id) { struct cxl_dport *dport; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 8f43a06c4f72..3a5004aab97a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -735,6 +735,9 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct cxl_root *devm_cxl_add_root(struct device *host, const struct cxl_root_ops *ops); struct cxl_root *find_cxl_root(struct cxl_port *port); +void put_cxl_root(struct cxl_root *cxl_root); +DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T)) + int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); void cxl_bus_drain(void); diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 656f2e03d2ea..27b7b45476e3 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -130,7 +130,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) * This can't fail in practice as CXL root exit unregisters all * descendant ports and that in turn synchronizes with cxl_port_probe() */ - struct cxl_root *cxl_root __free(put_device) = find_cxl_root(port); + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port); if (!cxl_root) return -ENODEV;