From patchwork Thu Jan 4 23:48:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511617 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5517D2D600 for ; Thu, 4 Jan 2024 23:48:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C7PF2A5U" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704412104; x=1735948104; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=url24CLh1PXmjzNkYYq8gFMkF74u6JeDBRKwjMyaZTg=; b=C7PF2A5UnCYTmSEvP6cOsa/Zo48/GUn3S+w2F5w5cQ7m1Juyw9b+KAkK 0uyCFA3aJuWsuvwedae0J/BTEVfmPfu/9unchhY0duC8Hob0QJ2jDTv4P YWn0yv3aGOi7ESYPze9+unlL+F4y9x3bSHM/uWpmQou4gj3rdfo4P4xzn ms9heV6bh3i60EboMmKoZU/ScKXTKoUBMWoAtRQY/9RwMpl7JhsSPr8o8 m8XvYV9ZqocVdxIcBr65GiPCGWRO8MqTykAvMFtPxPZjCTQ1JeGqfjDTl zjBa2Euw9ykztPlZcXFZaei7Hrf762ZGajSVnWZbNrU1E1F7HUABecmc3 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="382369859" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="382369859" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:48:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="871087837" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="871087837" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:48:23 -0800 Subject: [PATCH v3 1/3] cxl/region: Calculate performance data for a region From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Jonathan Cameron , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net Date: Thu, 04 Jan 2024 16:48:23 -0700 Message-ID: <170441210328.3574076.8557138214621981436.stgit@djiang5-mobl3> In-Reply-To: <170441200977.3574076.13110207881243626581.stgit@djiang5-mobl3> References: <170441200977.3574076.13110207881243626581.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Calculate and store the performance data for a CXL region. Find the worst read and write latency for all the included ranges from each of the devices that attributes to the region and designate that as the latency data. Sum all the read and write bandwidth data for each of the device region and that is the total bandwidth for the region. The perf list is expected to be constructed before the endpoint decoders are registered and thus there should be no early reading of the entries from the region assemble action. The calling of the region qos calculate function is under the protection of cxl_dpa_rwsem and will ensure that all DPA associated work has completed. Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- v3: - Clarify calculated data is same base as the coordinates computed from the HMAT tables. (Jonathan) --- drivers/cxl/core/cdat.c | 53 +++++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/core/region.c | 2 ++ drivers/cxl/cxl.h | 5 ++++ 3 files changed, 60 insertions(+) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index cd84d87f597a..78e1cdcb9d89 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -515,3 +515,56 @@ void cxl_switch_parse_cdat(struct cxl_port *port) EXPORT_SYMBOL_NS_GPL(cxl_switch_parse_cdat, CXL); MODULE_IMPORT_NS(CXL); + +void cxl_region_perf_data_calculate(struct cxl_region *cxlr, + struct cxl_endpoint_decoder *cxled) +{ + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); + struct range dpa = { + .start = cxled->dpa_res->start, + .end = cxled->dpa_res->end, + }; + struct list_head *perf_list; + struct cxl_dpa_perf *perf; + bool found = false; + + switch (cxlr->mode) { + case CXL_DECODER_RAM: + perf_list = &mds->ram_perf_list; + break; + case CXL_DECODER_PMEM: + perf_list = &mds->pmem_perf_list; + break; + default: + return; + } + + list_for_each_entry(perf, perf_list, list) { + if (range_contains(&perf->dpa_range, &dpa)) { + found = true; + break; + } + } + + if (!found) + return; + + /* Get total bandwidth and the worst latency for the cxl region */ + cxlr->coord.read_latency = max_t(unsigned int, + cxlr->coord.read_latency, + perf->coord.read_latency); + cxlr->coord.write_latency = max_t(unsigned int, + cxlr->coord.write_latency, + perf->coord.write_latency); + cxlr->coord.read_bandwidth += perf->coord.read_bandwidth; + cxlr->coord.write_bandwidth += perf->coord.write_bandwidth; + + /* + * Convert latency to nanosec from picosec to be consistent with the + * resulting latency coordinates computed by HMAT code. + */ + cxlr->coord.read_latency = DIV_ROUND_UP(cxlr->coord.read_latency, 1000); + cxlr->coord.write_latency = DIV_ROUND_UP(cxlr->coord.write_latency, 1000); +} diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 57a5901d5a60..7f19b533c5ae 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1722,6 +1722,8 @@ static int cxl_region_attach(struct cxl_region *cxlr, return -EINVAL; } + cxl_region_perf_data_calculate(cxlr, cxled); + if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) { int i; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 492dbf63935f..4639d0d6ef54 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -519,6 +519,7 @@ struct cxl_region_params { * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge * @flags: Region state flags * @params: active + config params for the region + * @coord: QoS access coordinates for the region */ struct cxl_region { struct device dev; @@ -529,6 +530,7 @@ struct cxl_region { struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; + struct access_coordinate coord; }; struct cxl_nvdimm_bridge { @@ -879,6 +881,9 @@ void cxl_switch_parse_cdat(struct cxl_port *port); int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, struct access_coordinate *coord); +void cxl_region_perf_data_calculate(struct cxl_region *cxlr, + struct cxl_endpoint_decoder *cxled); + /* * Unit test builds overrides this to __weak, find the 'strong' version * of these symbols in tools/testing/cxl/. From patchwork Thu Jan 4 23:48:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511618 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C5142D600 for ; Thu, 4 Jan 2024 23:48:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SLp3Kay0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704412110; x=1735948110; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R4PMFQKvONeN0b9X7GD6XJOMAlA1pLMhHxptCqmezyQ=; b=SLp3Kay0BTjJ9Eg11H1cWqqh24HbjAdblS13tmynCKuYPmxC4L3n4M25 kCkkGGgQkeYbF1OBoRegUqK0ToDEpT1+N7yb73qQtsMZtOy77Qnb9rqW+ mayF6DADXmZOHYILhynrNLw5Bt3a30KHC0YgAGl3RkwM26IWWrpu5vnMw Q+l60u/qt0s5tJ/9ZMJRtNaDDttDFkbDSD83FxTFCBHbESOxYlv91XO5f chmUfSPhTC0KESY3IuBIwk4hh5qw1k7jEWpcPZmQWLVU72eIgZ+C+YEi5 S43OjleMUv2JYdwboSJ702MHU3cHeWUfk/hxbYXMJlj3pESCqu048iI55 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="382369878" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="382369878" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:48:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="871087850" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="871087850" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:48:29 -0800 Subject: [PATCH v3 2/3] cxl/region: Add sysfs attribute for locality attributes of CXL regions From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net Date: Thu, 04 Jan 2024 16:48:28 -0700 Message-ID: <170441210897.3574076.3084661576808646327.stgit@djiang5-mobl3> In-Reply-To: <170441200977.3574076.13110207881243626581.stgit@djiang5-mobl3> References: <170441200977.3574076.13110207881243626581.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add read/write latencies and bandwidth sysfs attributes for the enabled CXL region. The bandwidth is the aggregated bandwidth of all devices that contribute to the CXL region. The latency is the worst latency of the device amongst all the devices that contribute to the CXL region. Signed-off-by: Dave Jiang --- v3: - Make attribs not visible if no data (Jonathan) - Check against coord.attrib (Jonathan) - Fix documentation verbiage (Jonathan) --- Documentation/ABI/testing/sysfs-bus-cxl | 60 +++++++++++++++++++++++++++++++ drivers/cxl/core/region.c | 40 +++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index fff2581b8033..86d3dbe12129 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -552,3 +552,63 @@ Description: attribute is only visible for devices supporting the capability. The retrieved errors are logged as kernel events when cxl_poison event tracing is enabled. + + +What: /sys/bus/cxl/devices/regionZ/read_bandwidth +Date: Jan, 2024 +KernelVersion: v6.9 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The aggregated read bandwidth of the region. The number is + the accumulated read bandwidth of all CXL memory devices that + contributes to the region in MB/s. Should be equivalent to + attributes in + /sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth. + See Documentation/ABI/stable/sysfs-devices-node. The generic + target bandwidth that is part of the whole path calculation is + the best performance latency provided by the HMAT SSLBIS table. + + +What: /sys/bus/cxl/devices/regionZ/write_bandwidth +Date: Jan, 2024 +KernelVersion: v6.9 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The aggregated write bandwidth of the region. The number is + the accumulated write bandwidth of all CXL memory devices that + contributes to the region in MB/s. Should be equivalent to + attributes in + /sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth. + See Documentation/ABI/stable/sysfs-devices-node. The generic + target bandwidth that is part of the whole path calculation is + the best performance latency provided by the HMAT SSLBIS table. + + +What: /sys/bus/cxl/devices/regionZ/read_latency +Date: Jan, 2024 +KernelVersion: v6.9 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The read latency of the region. The number is + the worst read latency of all CXL memory devices that + contributes to the region in nanoseconds. Should be + equivalent to attributes in + /sys/devices/system/node/nodeX/accessY/initiators/read_latency. + See Documentation/ABI/stable/sysfs-devices-node. The generic + target latency that is part of the whole path calculation is + the best performance latency provided by the HMAT SSLBIS table. + + +What: /sys/bus/cxl/devices/regionZ/write_latency +Date: Jan, 2024 +KernelVersion: v6.9 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The write latency of the region. The number is + the worst write latency of all CXL memory devices that + contributes to the region in nanoseconds. Should be + equivalent to attributes in + /sys/devices/system/node/nodeX/accessY/initiators/write_latency. + See Documentation/ABI/stable/sysfs-devices-node. The generic + target latency that is part of the whole path calculation is + the best performance latency provided by the HMAT SSLBIS table. diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 7f19b533c5ae..d28d24524d41 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -343,6 +343,25 @@ static ssize_t commit_show(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR_RW(commit); +#define ACCESS_ATTR(attrib) \ +static ssize_t attrib##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct cxl_region *cxlr = to_cxl_region(dev); \ + \ + if (cxlr->coord.attrib == 0) \ + return -ENOENT; \ + \ + return sysfs_emit(buf, "%u\n", cxlr->coord.attrib); \ +} \ +static DEVICE_ATTR_RO(attrib) + +ACCESS_ATTR(read_bandwidth); +ACCESS_ATTR(read_latency); +ACCESS_ATTR(write_bandwidth); +ACCESS_ATTR(write_latency); + static umode_t cxl_region_visible(struct kobject *kobj, struct attribute *a, int n) { @@ -355,6 +374,23 @@ static umode_t cxl_region_visible(struct kobject *kobj, struct attribute *a, */ if (a == &dev_attr_uuid.attr && cxlr->mode != CXL_DECODER_PMEM) return 0444; + + if (a == &dev_attr_read_latency.attr && + cxlr->coord.read_latency == 0) + return 0; + + if (a == &dev_attr_write_latency.attr && + cxlr->coord.write_latency == 0) + return 0; + + if (a == &dev_attr_read_bandwidth.attr && + cxlr->coord.read_bandwidth == 0) + return 0; + + if (a == &dev_attr_write_bandwidth.attr && + cxlr->coord.write_bandwidth == 0) + return 0; + return a->mode; } @@ -654,6 +690,10 @@ static struct attribute *cxl_region_attrs[] = { &dev_attr_resource.attr, &dev_attr_size.attr, &dev_attr_mode.attr, + &dev_attr_read_bandwidth.attr, + &dev_attr_write_bandwidth.attr, + &dev_attr_read_latency.attr, + &dev_attr_write_latency.attr, NULL, }; From patchwork Thu Jan 4 23:48:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511619 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 681C22D606 for ; Thu, 4 Jan 2024 23:48:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EilHPM7t" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704412117; x=1735948117; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f6xaO1GGEthfMuhwJc7WawlCklJrGXxRIzWxhWnGvII=; b=EilHPM7tbdGNUpLX2Z1EHN7NDrVeGQbmyo7wbjEHu6kfPwqhofEGVHG/ OL3duK1chzGWPrk3eOL+xXKggVi282xc9JzFfciQg0r47MC/MPk1wfC8L dCZkg3ZVMBSGT+6Yt85MNT1bJw97zkv4yvCJ9+VvW7I3gAlPF9dGfk9Lf rpvVKH+T+g7YCdIgXUTqfHX7c5I+TXwI6nB9Ul6QQ6o3vFJEq19JLTqEu KA1of0yW6qbuM+TvsvlkYOmVhywoyjiQGCFyrKF/Grg6ABPZ64ymX79// W3ihi38qtq1BrTZ8k8M4pZu3je4gxlKUCjzEftwQjRsqbhNVuBdTOv/3Z w==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="382369915" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="382369915" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:48:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="871087869" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="871087869" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 15:48:35 -0800 Subject: [PATCH v3 3/3] cxl: Add memory hotplug notifier for cxl region From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Greg Kroah-Hartman , "Rafael J. Wysocki" , "Huang, Ying" , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net Date: Thu, 04 Jan 2024 16:48:34 -0700 Message-ID: <170441211484.3574076.5894396662836000435.stgit@djiang5-mobl3> In-Reply-To: <170441200977.3574076.13110207881243626581.stgit@djiang5-mobl3> References: <170441200977.3574076.13110207881243626581.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When the CXL region is formed, the driver would computed the performance data for the region. However this data is not available at the node data collection that has been populated by the HMAT during kernel initialization. Add a memory hotplug notifier to update the performance data to the node hmem_attrs to expose the newly calculated region performance data. The CXL region is created under specific CFMWS. The node for the CFMWS is created during SRAT parsing by acpi_parse_cfmws(). Additional regions may overwrite the initial data, but since this is for the same proximity domain it's a don't care for now. node_set_perf_attrs() symbol is exported to allow update of perf attribs for a node. The sysfs path of /sys/devices/system/node/nodeX/access0/initiators/* is created by ndoe_set_perf_attrs() for the various attributes where nodeX is matched to the proximity domain of the CXL region. Cc: Greg Kroah-Hartman Cc: Rafael J. Wysocki Reviewed-by: "Huang, Ying" Signed-off-by: Dave Jiang --- v3: - Change EXPORT_SYMBOL_NS_GPL(,CXL) to EXPORT_SYMBOL_GPL() (Jonathan) - use read_bandwidth as check for valid coords (Jonathan) - Remove setting of coord access level 1. (Jonathan) --- drivers/base/node.c | 1 + drivers/cxl/core/region.c | 42 ++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 3 +++ 3 files changed, 46 insertions(+) diff --git a/drivers/base/node.c b/drivers/base/node.c index cb2b6cc7f6e6..48e5cb292765 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -215,6 +215,7 @@ void node_set_perf_attrs(unsigned int nid, struct access_coordinate *coord, } } } +EXPORT_SYMBOL_GPL(node_set_perf_attrs); /** * struct node_cache_info - Internal tracking for memory node caches diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index d28d24524d41..bee65f535d6c 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -2972,6 +2973,42 @@ static int is_system_ram(struct resource *res, void *arg) return 1; } +static int cxl_region_perf_attrs_callback(struct notifier_block *nb, + unsigned long action, void *arg) +{ + struct cxl_region *cxlr = container_of(nb, struct cxl_region, + memory_notifier); + struct cxl_region_params *p = &cxlr->params; + struct cxl_endpoint_decoder *cxled = p->targets[0]; + struct cxl_decoder *cxld = &cxled->cxld; + struct memory_notify *mnb = arg; + int nid = mnb->status_change_nid; + int region_nid; + + if (nid == NUMA_NO_NODE || action != MEM_ONLINE) + return NOTIFY_DONE; + + region_nid = phys_to_target_node(cxld->hpa_range.start); + if (nid != region_nid) + return NOTIFY_DONE; + + /* Don't set if there's no coordinate information */ + if (!cxlr->coord.write_bandwidth) + return NOTIFY_DONE; + + node_set_perf_attrs(nid, &cxlr->coord, 0); + node_set_perf_attrs(nid, &cxlr->coord, 1); + + return NOTIFY_OK; +} + +static void remove_coord_notifier(void *data) +{ + struct cxl_region *cxlr = data; + + unregister_memory_notifier(&cxlr->memory_notifier); +} + static int cxl_region_probe(struct device *dev) { struct cxl_region *cxlr = to_cxl_region(dev); @@ -2997,6 +3034,11 @@ static int cxl_region_probe(struct device *dev) goto out; } + cxlr->memory_notifier.notifier_call = cxl_region_perf_attrs_callback; + cxlr->memory_notifier.priority = HMAT_CALLBACK_PRI; + register_memory_notifier(&cxlr->memory_notifier); + rc = devm_add_action_or_reset(&cxlr->dev, remove_coord_notifier, cxlr); + /* * From this point on any path that changes the region's state away from * CXL_CONFIG_COMMIT is also responsible for releasing the driver. diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4639d0d6ef54..2498086c8edc 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -520,6 +521,7 @@ struct cxl_region_params { * @flags: Region state flags * @params: active + config params for the region * @coord: QoS access coordinates for the region + * @memory_notifier: notifier for setting the access coordinates to node */ struct cxl_region { struct device dev; @@ -531,6 +533,7 @@ struct cxl_region { unsigned long flags; struct cxl_region_params params; struct access_coordinate coord; + struct notifier_block memory_notifier; }; struct cxl_nvdimm_bridge {