From patchwork Fri Jan 5 01:18:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511643 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B21F41854 for ; Fri, 5 Jan 2024 01:18:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bVmFjtcP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704417497; x=1735953497; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bglEbeQZSQXXIC/7SNQvwolDwsdqF3fEx33zsU+Jt7A=; b=bVmFjtcPzuqlX5qHRCkquBNN3ZzssdbInnR1lPs+YWsXUsPxK9wJwS5b 5OcBIR1J5a85/5sZrT4p5XawIfjKOgUxYi8T7f3C8tD5owsmwd2SH40ay od1fO2UhddC3wpMHCBxCOr/A8+msT39355ERdXJ1OErgu9gQm4YtSUtXp Rh89S59SeVVXNVbKX8GXpunhTnkXLCbgAh69WXU6k4/fe5C8hE5W822qC WhW/4nnwq+6fmBH3tiCPa2SVsvr7cpq8uofeSymA6IZVbAfOfiBuySuJr m6vhqwwTiVlgyXljqcN8gxutTI3bdoUqsvd0TUKR2am9LvR5vBJy4pMIg A==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="463802180" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="463802180" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="1027613261" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="1027613261" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:09 -0800 Subject: [PATCH v4 1/6] cxl: Introduce put_cxl_root() helper From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Robert Richter , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 18:18:08 -0700 Message-ID: <170441748869.3632067.1712163433527825314.stgit@djiang5-mobl3> In-Reply-To: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> References: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a helper function put_cxl_root() to maintain symmetry for find_cxl_root() function instead of relying on open coding of the put_device() in order to dereference the 'struct device' that happens via get_device() in find_cxl_root(). Add cleanups for all code paths that calls put_device() after find_cxl_root(). Suggested-by: Robert Richter Signed-off-by: Dave Jiang --- v4: - Adjust ordering of this patch to front. (Dan) v3: - Adjust for cxl_root as parameter for find_cxl_root() - Add NULL ptr check fore __free(). (Dan) - Fix DEFINE_FREE() macro to name it put_cxl_root (Dan) - Cleanup all functions calling put_cxl_root() and related calls. (Dan) v2: - Make put_cxl_root() an exported function to be symmetric to find_cxl_root(). (Robert) --- drivers/cxl/core/cdat.c | 5 +++-- drivers/cxl/core/port.c | 9 +++++++++ drivers/cxl/cxl.h | 3 +++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index cd84d87f597a..c1085fcc5428 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -349,12 +349,13 @@ static int cxl_qos_class_verify(struct cxl_memdev *cxlmd) { struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); - struct cxl_port *root_port __free(put_device) = NULL; LIST_HEAD(__discard); struct list_head *discard __free(dpa_perf) = &__discard; int rc; - root_port = find_cxl_root(cxlmd->endpoint); + struct cxl_port *root_port __free(put_cxl_root) = + find_cxl_root(cxlmd->endpoint); + if (!root_port) return -ENODEV; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 8c00fd6be730..f66650bb6128 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -986,6 +986,15 @@ struct cxl_port *find_cxl_root(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL); +void put_cxl_root(struct cxl_port *port) +{ + if (!port) + return; + + put_device(&port->dev); +} +EXPORT_SYMBOL_NS_GPL(put_cxl_root); + static struct cxl_dport *find_dport(struct cxl_port *port, int id) { struct cxl_dport *dport; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 492dbf63935f..4e53604de041 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -735,6 +735,9 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct cxl_root *devm_cxl_add_root(struct device *host, const struct cxl_root_ops *ops); struct cxl_port *find_cxl_root(struct cxl_port *port); +void put_cxl_root(struct cxl_port *port); +DEFINE_FREE(put_cxl_root, struct cxl_port *, if (_T) put_cxl_root(_T)) + int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); void cxl_bus_drain(void); From patchwork Fri Jan 5 01:18:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511644 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E4F31860 for ; Fri, 5 Jan 2024 01:18:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OQ83peCX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704417499; x=1735953499; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Vj9rJKI85BEtA/Pm2urZFc3YXyZFQo/wBE5rIQ3T6LY=; b=OQ83peCXCC/J+8E3ZgPlHB1K9elYiVSRVj6PWiM8ogS9R3YtRVbckzq1 AM/EUjjK3tUBPDvC66NHZoVxcJBtnkw/NHkEs58kLwjLj74+KClqXz5Up whG1hx7VLoXEMAaDu8VM8UoeaLzSN8AwC2+qKsm+MREqOhJJPcPQk1tvg NNhPeDqx/688aDdGdAmAB/7IMBie5yA4zRzRgjaDBTUpPLeNZA7EUvjBp uxr3gMJqUEcWU/QzqAHkMM3Jys5VkkgoyF8LyMJeA4TAu3Wg/x4kT1eJ5 Gdz6NhNCobq0C4FEO3Azwil06Tqa5RjZQhkaV7Tk0wLGJWAzEzZywRSvg g==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="463802186" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="463802186" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="1027613290" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="1027613290" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:14 -0800 Subject: [PATCH v4 2/6] cxl: Convert find_cxl_root() to return a 'struct cxl_root *' From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Dan Williams , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 18:18:14 -0700 Message-ID: <170441749454.3632067.9603741384368361001.stgit@djiang5-mobl3> In-Reply-To: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> References: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Commit 790815902ec6 ("cxl: Add support for _DSM Function for retrieving QTG ID") introduced 'struct cxl_root', however all usages have been worked indirectly through cxl_port. Refactor code such as find_cxl_root() function to use 'struct cxl_root' directly. Suggested-by: Dan Williams Signed-off-by: Dave Jiang --- v4: - Adjust ordering of patches to move this to 2nd place. (Dan) --- drivers/cxl/core/cdat.c | 14 ++++++++------ drivers/cxl/core/pmem.c | 8 +++++--- drivers/cxl/core/port.c | 12 ++++++------ drivers/cxl/cxl.h | 6 +++--- drivers/cxl/port.c | 10 ++++++---- 5 files changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index c1085fcc5428..f9bc386f3043 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -162,7 +162,6 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, struct xarray *dsmas_xa) { struct access_coordinate c; - struct cxl_port *root_port; struct cxl_root *cxl_root; struct dsmas_entry *dent; int valid_entries = 0; @@ -175,8 +174,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, return rc; } - root_port = find_cxl_root(port); - cxl_root = to_cxl_root(root_port); + cxl_root = find_cxl_root(port); if (!cxl_root->ops || !cxl_root->ops->qos_class) return -EOPNOTSUPP; @@ -193,7 +191,8 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, dent->coord.write_bandwidth); dent->entries = 1; - rc = cxl_root->ops->qos_class(root_port, &dent->coord, 1, &qos_class); + rc = cxl_root->ops->qos_class(&cxl_root->port, &dent->coord, 1, + &qos_class); if (rc != 1) continue; @@ -351,14 +350,17 @@ static int cxl_qos_class_verify(struct cxl_memdev *cxlmd) struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); LIST_HEAD(__discard); struct list_head *discard __free(dpa_perf) = &__discard; + struct cxl_port *root_port; int rc; - struct cxl_port *root_port __free(put_cxl_root) = + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(cxlmd->endpoint); - if (!root_port) + if (!cxl_root) return -ENODEV; + root_port = &cxl_root->port; + /* Check that the QTG IDs are all sane between end device and root decoders */ cxl_qos_match(root_port, &mds->ram_perf_list, discard); cxl_qos_match(root_port, &mds->pmem_perf_list, discard); diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c index fc94f5240327..57b777a088f6 100644 --- a/drivers/cxl/core/pmem.c +++ b/drivers/cxl/core/pmem.c @@ -64,14 +64,16 @@ static int match_nvdimm_bridge(struct device *dev, void *data) struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) { - struct cxl_port *port = find_cxl_root(cxlmd->endpoint); + struct cxl_root *cxl_root = find_cxl_root(cxlmd->endpoint); + struct cxl_port *port; struct device *dev; - if (!port) + if (!cxl_root) return NULL; + port = &cxl_root->port; dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge); - put_device(&port->dev); + put_cxl_root(cxl_root); if (!dev) return NULL; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index f66650bb6128..63a4e3c2baed 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -972,7 +972,7 @@ static bool dev_is_cxl_root_child(struct device *dev) return false; } -struct cxl_port *find_cxl_root(struct cxl_port *port) +struct cxl_root *find_cxl_root(struct cxl_port *port) { struct cxl_port *iter = port; @@ -982,18 +982,18 @@ struct cxl_port *find_cxl_root(struct cxl_port *port) if (!iter) return NULL; get_device(&iter->dev); - return iter; + return to_cxl_root(iter); } EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL); -void put_cxl_root(struct cxl_port *port) +void put_cxl_root(struct cxl_root *cxl_root) { - if (!port) + if (!cxl_root) return; - put_device(&port->dev); + put_device(&cxl_root->port.dev); } -EXPORT_SYMBOL_NS_GPL(put_cxl_root); +EXPORT_SYMBOL_NS_GPL(put_cxl_root, CXL); static struct cxl_dport *find_dport(struct cxl_port *port, int id) { diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4e53604de041..70d5e6363399 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -734,9 +734,9 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct cxl_dport *parent_dport); struct cxl_root *devm_cxl_add_root(struct device *host, const struct cxl_root_ops *ops); -struct cxl_port *find_cxl_root(struct cxl_port *port); -void put_cxl_root(struct cxl_port *port); -DEFINE_FREE(put_cxl_root, struct cxl_port *, if (_T) put_cxl_root(_T)) +struct cxl_root *find_cxl_root(struct cxl_port *port); +void put_cxl_root(struct cxl_root *cxl_root); +DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T)) int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index da3c3a08bd62..ddbb42f0fd70 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -95,7 +95,8 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_hdm *cxlhdm; - struct cxl_port *root; + struct cxl_root *cxl_root; + struct cxl_port *root_port; int rc; rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info); @@ -130,14 +131,15 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) * This can't fail in practice as CXL root exit unregisters all * descendant ports and that in turn synchronizes with cxl_port_probe() */ - root = find_cxl_root(port); + cxl_root = find_cxl_root(port); + root_port = &cxl_root->port; /* * Now that all endpoint decoders are successfully enumerated, try to * assemble regions from committed decoders */ - device_for_each_child(&port->dev, root, discover_region); - put_device(&root->dev); + device_for_each_child(&root_port->dev, root_port, discover_region); + put_cxl_root(cxl_root); return 0; } From patchwork Fri Jan 5 01:18:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511645 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56D091876 for ; Fri, 5 Jan 2024 01:18:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ifCx8T7y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704417502; x=1735953502; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VnVuwFMPi7OnCPXq7ErryhpmMyExxcFExv/HaPYgKm0=; b=ifCx8T7yhMoXSZICylaELcqqmjon8VkanIXxOVi1JXizTHyL/lBzW/nU THbw7vw3Eef3apOfwkrryv59PqTFCIarUr9N23SLuBH7gBfsmtyKugj1A +x2/N4qlZyFlPQmeVkenAJhtFt4DBQ6ezdKy8te377V9Mo3eZ16mpPuso 53uO/j0gA34wMoKRpmFb5/CXPLmBYwP7OtAqJcEd3Oc02YsqVn//cud+Y NmHyv+HaTAbNqH7LtylbFjgx961lKERHpLMyCVch/9iKcWrlPqadJ6mRL 9EliDJyaNZHoqFn7+LaNMpJ4AvaXBbY8y81ZwUO5LzCzLIphMLpampUgd g==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="463802239" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="463802239" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="1027613342" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="1027613342" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:20 -0800 Subject: [PATCH v4 3/6] cxl: Convert qos_class() to use 'struct cxl_root *' directly From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 18:18:20 -0700 Message-ID: <170441750038.3632067.659502106120894365.stgit@djiang5-mobl3> In-Reply-To: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> References: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 ->qos_class() is expected to take a 'struct cxl_root *' instead of a 'struct cxl_port *'. Convert to directly accepting a 'struct cxl_root *' to ensure that the root port device is passed in. Signed-off-by: Dave Jiang --- drivers/cxl/acpi.c | 6 ++---- drivers/cxl/core/cdat.c | 2 +- drivers/cxl/cxl.h | 12 ++++++------ 3 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index afc712264d1c..dcf2b39e1048 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -295,14 +295,12 @@ cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord, return rc; } -static int cxl_acpi_qos_class(struct cxl_port *root_port, +static int cxl_acpi_qos_class(struct cxl_root *cxl_root, struct access_coordinate *coord, int entries, int *qos_class) { + struct device *dev = cxl_root->port.uport_dev; acpi_handle handle; - struct device *dev; - - dev = root_port->uport_dev; if (!dev_is_platform(dev)) return -ENODEV; diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index f9bc386f3043..0df5379cf02f 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -191,7 +191,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, dent->coord.write_bandwidth); dent->entries = 1; - rc = cxl_root->ops->qos_class(&cxl_root->port, &dent->coord, 1, + rc = cxl_root->ops->qos_class(cxl_root, &dent->coord, 1, &qos_class); if (rc != 1) continue; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 70d5e6363399..3a5004aab97a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -617,12 +617,6 @@ struct cxl_port { long pci_latency; }; -struct cxl_root_ops { - int (*qos_class)(struct cxl_port *root_port, - struct access_coordinate *coord, int entries, - int *qos_class); -}; - /** * struct cxl_root - logical collection of root cxl_port items * @@ -640,6 +634,12 @@ to_cxl_root(const struct cxl_port *port) return container_of(port, struct cxl_root, port); } +struct cxl_root_ops { + int (*qos_class)(struct cxl_root *cxl_root, + struct access_coordinate *coord, int entries, + int *qos_class); +}; + static inline struct cxl_dport * cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) { From patchwork Fri Jan 5 01:18:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511646 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50FF51FAD for ; Fri, 5 Jan 2024 01:18:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YS7lk4HM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704417507; x=1735953507; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GPYlDuuUQfp5C8aj7jb9ockFHkCLSnVK6kwS2BOOxeg=; b=YS7lk4HMydqMPeF0yc2J/PMEgdifOXDU7M4rTryuhXZ78stlZbVS433P qrv1brVd1JY7wVX+FNBs/SKR11Xx2r53vfLiOsn81wGT+WXd28fUuZZFN Vh1nBj1qlns+JcLCQZn0kvAEhln4bmcm8Xt88TFayOXLT1sP3Slqg7lyZ Ub8Ruq1rZoNr0z3LGRLnVuiTj9DnEU84wjoXNDOQtfjq6RHm7zburKJ1D jx2rJxe7rB6JR+GYgxaREpBTXLdRSO/RVftWqGfpY1t6F+P3Ds4IRGNMC 2HtvrB2iD+waQNbgWU/14HPFFn8pRDqCWIT4EtEde9EjZQxql26fbxhsz g==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="463802274" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="463802274" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="1027613369" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="1027613369" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:26 -0800 Subject: [PATCH v4 4/6] cxl: Fix missing dereference of 'struct device' in cxl_port_perf_data_calculate() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 18:18:26 -0700 Message-ID: <170441750612.3632067.3372196682717758963.stgit@djiang5-mobl3> In-Reply-To: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> References: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 cxl_port_perf_data_calculate() calls find_cxl_root() and does not dereference the 'struct device' in the cxl_root->port. find_cxl_root() calls get_device() and takes a reference on the port 'struct device' member. Use the __free() macro to ensure the dereference happens. Fixes: 7a4f148dd8d5 ("cxl: Compute the entire CXL path latency and bandwidth data") Signed-off-by: Dave Jiang --- drivers/cxl/core/cdat.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 0df5379cf02f..c6208aab452f 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -162,7 +162,6 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, struct xarray *dsmas_xa) { struct access_coordinate c; - struct cxl_root *cxl_root; struct dsmas_entry *dent; int valid_entries = 0; unsigned long index; @@ -174,7 +173,11 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, return rc; } - cxl_root = find_cxl_root(port); + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port); + + if (!cxl_root) + return -ENODEV; + if (!cxl_root->ops || !cxl_root->ops->qos_class) return -EOPNOTSUPP; From patchwork Fri Jan 5 01:18:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511647 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 947EF1860 for ; Fri, 5 Jan 2024 01:20:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IScGFLap" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704417646; x=1735953646; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mMuaGbOHyJt6sZ7HNy8/09Hlwh6D+SNqr9gXoaXlj5Q=; b=IScGFLapDJCaksWQY4Fv1NlU6Q9HqJYWhS0xJtFgr/rp3y5A0pSJTPyE JsdhTnbK2mj+alAgAN3ouR4pRfLLDkX0g1W0oYsGncViGeUIlkSGvUrgr /lYftzWSAFC9tfSXjO7ydzXDOvQJzK7RnN3QykBHv8OIzNlAr7/ngkrL+ pEBLJe/LrqiXJy3R+sj5a0RFyR5aKjhwawfibahzgVqc3uo50shxSrsjQ HBycO4YelyDqCsGTm4qj259YosDtgcpsUSKYZONge16lsR8wJZ/WdsYQ/ CuqlS2VyHvUhX6yWSnUr0izaVUIzJbiAOOEk1cz4yfiWhShSCzmSZs3JX Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="461708805" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="461708805" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="904006766" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="904006766" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:32 -0800 Subject: [PATCH v4 5/6] cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_bridge() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 18:18:31 -0700 Message-ID: <170441751181.3632067.5542037427417510907.stgit@djiang5-mobl3> In-Reply-To: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> References: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use scope-based resource management __free() macro to make cxl_root allocation safer in cxl_find_nvdimm_bridge(). Signed-off-by: Dave Jiang --- drivers/cxl/core/pmem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c index 57b777a088f6..df3d11257511 100644 --- a/drivers/cxl/core/pmem.c +++ b/drivers/cxl/core/pmem.c @@ -64,7 +64,8 @@ static int match_nvdimm_bridge(struct device *dev, void *data) struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) { - struct cxl_root *cxl_root = find_cxl_root(cxlmd->endpoint); + struct cxl_root *cxl_root __free(put_cxl_root) = + find_cxl_root(cxlmd->endpoint); struct cxl_port *port; struct device *dev; @@ -73,7 +74,6 @@ struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) port = &cxl_root->port; dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge); - put_cxl_root(cxl_root); if (!dev) return NULL; From patchwork Fri Jan 5 01:18:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13511648 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 582D9185B for ; Fri, 5 Jan 2024 01:20:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JP3kX4er" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704417648; x=1735953648; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8d+yZXMHnByfoCbCIgAmBBTnZo+J+B13YMbRoqLlIEQ=; b=JP3kX4erY4AZsGxykT1JUonvuzzWL7bSibR3GgQ/2JLgZN0lGJFmk3Wx 62WSqfh6Jm9eCN3QJPZA9xQ7gpF8OzAdbIkY5sQwjPgezso4rQJN99BHS DadZ8Nx4YMOMwIlUGPYRoL1mFad/o3c5hCxYqRMCp341Bfm9H8lRtLjPt exGjculuY6sTQODu+URQYmnp8sF5ia8iZiWTSWaCYYImjkVvsy8JL63Dx RtcI7mDxDavF0rTjKPQop8GVe/OmDOtxeHeQiTU784nb3jie2ga8TiwQg xFHSgbj5krO5XjWBlBTBL5vVZUVaGE3FKFZaKptCVzuGxYM2Qb9zen5TP g==; X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="461708845" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="461708845" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10943"; a="904006801" X-IronPort-AV: E=Sophos;i="6.04,332,1695711600"; d="scan'208";a="904006801" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.121.50]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2024 17:18:38 -0800 Subject: [PATCH v4 6/6] cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_probe() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Thu, 04 Jan 2024 18:18:38 -0700 Message-ID: <170441751817.3632067.18926893176028509.stgit@djiang5-mobl3> In-Reply-To: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> References: <170441738812.3632067.2103652995360101907.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use scope-based resource management __free() macro to make cxl_root allocation simpler and safer in cxl_endpoint_port_probe(). Signed-off-by: Dave Jiang --- v4: - Don't check return value of find_cxl_root() per comment. (Dan) --- drivers/cxl/port.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index ddbb42f0fd70..89d303f048e7 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -95,7 +95,6 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_hdm *cxlhdm; - struct cxl_root *cxl_root; struct cxl_port *root_port; int rc; @@ -131,7 +130,8 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) * This can't fail in practice as CXL root exit unregisters all * descendant ports and that in turn synchronizes with cxl_port_probe() */ - cxl_root = find_cxl_root(port); + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port); + root_port = &cxl_root->port; /* @@ -139,7 +139,6 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) * assemble regions from committed decoders */ device_for_each_child(&root_port->dev, root_port, discover_region); - put_cxl_root(cxl_root); return 0; }