From patchwork Fri Jan 5 10:59:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Korsgaard X-Patchwork-Id: 13511961 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4C1F2C84F for ; Fri, 5 Jan 2024 11:00:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=korsgaard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=48ers.dk Received: by mail.gandi.net (Postfix) with ESMTPSA id 07EADE0012; Fri, 5 Jan 2024 11:00:05 +0000 (UTC) Received: from peko by dell.be.48ers.dk with local (Exim 4.96) (envelope-from ) id 1rLhvp-005kSX-0C; Fri, 05 Jan 2024 12:00:05 +0100 From: Peter Korsgaard To: Vinod Koul , dmaengine@vger.kernel.org Cc: Michal Simek , Peter Korsgaard Subject: [PATCH] dmaengine: xilinx_dma: check for invalid vdma interleaved parameters Date: Fri, 5 Jan 2024 11:59:56 +0100 Message-Id: <20240105105956.1370220-1-peter@korsgaard.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: peter@korsgaard.com The VDMA HSIZE register (corresponding to sgl[0].size) is only 16bit wide / the VSIZE register (corresponding to numf) is only 13bit wide, so reject requests not fitting within that rather than silently transferring too little data. Signed-off-by: Peter Korsgaard Reviewed-by: Radhey Shyam Pandey --- drivers/dma/xilinx/xilinx_dma.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index e40696f6f864..5eb51ae93e89 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -112,7 +112,9 @@ /* Register Direct Mode Registers */ #define XILINX_DMA_REG_VSIZE 0x0000 +#define XILINX_DMA_VSIZE_MASK GENMASK(12, 0) #define XILINX_DMA_REG_HSIZE 0x0004 +#define XILINX_DMA_HSIZE_MASK GENMASK(15, 0) #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 @@ -2050,6 +2052,10 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, if (!xt->numf || !xt->sgl[0].size) return NULL; + if (xt->numf & ~XILINX_DMA_VSIZE_MASK || + xt->sgl[0].size & ~XILINX_DMA_HSIZE_MASK) + return NULL; + if (xt->frame_size != 1) return NULL;