From patchwork Fri Jan 5 18:03:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13512428 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97A1E328D1 for ; Fri, 5 Jan 2024 18:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Bd3SHHUC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704477790; x=1736013790; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iUQKC+xWl3Cm421NX8SqPJWZh4sLOPHbebX7wyaYebM=; b=Bd3SHHUCI8Cw/iTtvvfuaSe0f/S4YWVtyNHAjp8NOu1NVh4ReudoxA5t +1E6oIKUHbO/SIHHPTheG8qbBehN8bKGbyluiNf6BGDWh7KnFMnmsHK1N At3R70mN9Ky+v1mDieSvLWgS+V1iNqCkD5h8GVA1pJuh9UxPphynEK3Wb GxOsdjkZ/TYbBv03HNI5Z7pp3La2ejZ1COxUi6aifj3Lwu2IRDK1Ls0BS 0xXyzQFfDDgubojSj12NyM4uVIzW/DnrIMfBIkaAnfj2pbKVlzk2Oa4B8 N3BveU1B5kRTKlNlJbuESnpUyRZ4utDrnKe5xHreoguXiBdkdrO9YiOVc A==; X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="377047560" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="377047560" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="773905572" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="773905572" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.109.135]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:05 -0800 Subject: [PATCH v5 1/5] cxl: Introduce put_cxl_root() helper From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Robert Richter , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Fri, 05 Jan 2024 11:03:04 -0700 Message-ID: <170447778486.3687480.17502575591619841802.stgit@djiang5-mobl3> In-Reply-To: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> References: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a helper function put_cxl_root() to maintain symmetry for find_cxl_root() function instead of relying on open coding of the put_device() in order to dereference the 'struct device' that happens via get_device() in find_cxl_root(). Suggested-by: Robert Richter Signed-off-by: Dave Jiang --- v5: - Move out usages for follow on cleanup. (Dan) v4: - Adjust ordering of this patch to front. (Dan) v3: - Adjust for cxl_root as parameter for find_cxl_root() - Add NULL ptr check fore __free(). (Dan) - Fix DEFINE_FREE() macro to name it put_cxl_root (Dan) - Cleanup all functions calling put_cxl_root() and related calls. (Dan) v2: - Make put_cxl_root() an exported function to be symmetric to find_cxl_root(). (Robert) --- drivers/cxl/core/port.c | 9 +++++++++ drivers/cxl/cxl.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 8c00fd6be730..64f30d5fe1f6 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -986,6 +986,15 @@ struct cxl_port *find_cxl_root(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL); +void put_cxl_root(struct cxl_root *cxl_root) +{ + if (!cxl_root) + return; + + put_device(&cxl_root->port.dev); +} +EXPORT_SYMBOL_NS_GPL(put_cxl_root, CXL); + static struct cxl_dport *find_dport(struct cxl_port *port, int id) { struct cxl_dport *dport; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 492dbf63935f..ffa56af7b0d4 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -735,6 +735,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct cxl_root *devm_cxl_add_root(struct device *host, const struct cxl_root_ops *ops); struct cxl_port *find_cxl_root(struct cxl_port *port); +void put_cxl_root(struct cxl_root *cxl_root); int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); void cxl_bus_drain(void); From patchwork Fri Jan 5 18:03:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13512429 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1210F328C7 for ; Fri, 5 Jan 2024 18:03:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="U6KTelN7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704477793; x=1736013793; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ywqCwEvHbsgxF1g23CjQyaJ43yoFnOwM/SiUVUGKwvk=; b=U6KTelN7xufrU9WeckPV18YG2aPayphwFABJjMSxQcKalPSSjYULaL91 R106v8aKzwT6uEvq/hNiD0SuliixO1n7wyfNKWBvq+Os4hZyUyQs3hU71 X0auP9FJMxEk013Fettc76I80ejoM8oVInxHrfLFujKKyOQc5ElLBXswN 2ZUXEkyu1qwsSY9aMVs9X9Hrm3eQmSb7zx91L289y2PmuzApkmHIUgm+u kjUnvlwcwz/zMDaLTQJSS+VsxkognLPm5BFkR9UzhlIglSKD9j6GJwSkN 5qCJvjrXohSajalw9qNv+L5Ka0Zyek7gi81ThshFYpJvWNWhurPI1Nid6 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="377047638" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="377047638" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="773905642" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="773905642" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.109.135]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:11 -0800 Subject: [PATCH v5 2/5] cxl: Convert find_cxl_root() to return a 'struct cxl_root *' From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Dan Williams , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Fri, 05 Jan 2024 11:03:11 -0700 Message-ID: <170447779141.3687480.15105851741898155480.stgit@djiang5-mobl3> In-Reply-To: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> References: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Commit 790815902ec6 ("cxl: Add support for _DSM Function for retrieving QTG ID") introduced 'struct cxl_root', however all usages have been worked indirectly through cxl_port. Refactor code such as find_cxl_root() function to use 'struct cxl_root' directly. Suggested-by: Dan Williams Signed-off-by: Dave Jiang --- v5: - Squash in v4 3/6 to update the qos_class to cxl_root. (Dan) - Moved the introduction of __free() for cxl_root_put from v4 1/6 to here. (Dan) v4: - Adjust ordering of patches to move this to 2nd place. (Dan) --- drivers/cxl/acpi.c | 6 ++---- drivers/cxl/core/cdat.c | 17 ++++++++++------- drivers/cxl/core/pmem.c | 8 +++++--- drivers/cxl/core/port.c | 4 ++-- drivers/cxl/cxl.h | 16 +++++++++------- drivers/cxl/port.c | 10 ++++++---- 6 files changed, 34 insertions(+), 27 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index afc712264d1c..dcf2b39e1048 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -295,14 +295,12 @@ cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord, return rc; } -static int cxl_acpi_qos_class(struct cxl_port *root_port, +static int cxl_acpi_qos_class(struct cxl_root *cxl_root, struct access_coordinate *coord, int entries, int *qos_class) { + struct device *dev = cxl_root->port.uport_dev; acpi_handle handle; - struct device *dev; - - dev = root_port->uport_dev; if (!dev_is_platform(dev)) return -ENODEV; diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index cd84d87f597a..0df5379cf02f 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -162,7 +162,6 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, struct xarray *dsmas_xa) { struct access_coordinate c; - struct cxl_port *root_port; struct cxl_root *cxl_root; struct dsmas_entry *dent; int valid_entries = 0; @@ -175,8 +174,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, return rc; } - root_port = find_cxl_root(port); - cxl_root = to_cxl_root(root_port); + cxl_root = find_cxl_root(port); if (!cxl_root->ops || !cxl_root->ops->qos_class) return -EOPNOTSUPP; @@ -193,7 +191,8 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, dent->coord.write_bandwidth); dent->entries = 1; - rc = cxl_root->ops->qos_class(root_port, &dent->coord, 1, &qos_class); + rc = cxl_root->ops->qos_class(cxl_root, &dent->coord, 1, + &qos_class); if (rc != 1) continue; @@ -349,15 +348,19 @@ static int cxl_qos_class_verify(struct cxl_memdev *cxlmd) { struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); - struct cxl_port *root_port __free(put_device) = NULL; LIST_HEAD(__discard); struct list_head *discard __free(dpa_perf) = &__discard; + struct cxl_port *root_port; int rc; - root_port = find_cxl_root(cxlmd->endpoint); - if (!root_port) + struct cxl_root *cxl_root __free(put_cxl_root) = + find_cxl_root(cxlmd->endpoint); + + if (!cxl_root) return -ENODEV; + root_port = &cxl_root->port; + /* Check that the QTG IDs are all sane between end device and root decoders */ cxl_qos_match(root_port, &mds->ram_perf_list, discard); cxl_qos_match(root_port, &mds->pmem_perf_list, discard); diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c index fc94f5240327..57b777a088f6 100644 --- a/drivers/cxl/core/pmem.c +++ b/drivers/cxl/core/pmem.c @@ -64,14 +64,16 @@ static int match_nvdimm_bridge(struct device *dev, void *data) struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) { - struct cxl_port *port = find_cxl_root(cxlmd->endpoint); + struct cxl_root *cxl_root = find_cxl_root(cxlmd->endpoint); + struct cxl_port *port; struct device *dev; - if (!port) + if (!cxl_root) return NULL; + port = &cxl_root->port; dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge); - put_device(&port->dev); + put_cxl_root(cxl_root); if (!dev) return NULL; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 64f30d5fe1f6..63a4e3c2baed 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -972,7 +972,7 @@ static bool dev_is_cxl_root_child(struct device *dev) return false; } -struct cxl_port *find_cxl_root(struct cxl_port *port) +struct cxl_root *find_cxl_root(struct cxl_port *port) { struct cxl_port *iter = port; @@ -982,7 +982,7 @@ struct cxl_port *find_cxl_root(struct cxl_port *port) if (!iter) return NULL; get_device(&iter->dev); - return iter; + return to_cxl_root(iter); } EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index ffa56af7b0d4..3a5004aab97a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -617,12 +617,6 @@ struct cxl_port { long pci_latency; }; -struct cxl_root_ops { - int (*qos_class)(struct cxl_port *root_port, - struct access_coordinate *coord, int entries, - int *qos_class); -}; - /** * struct cxl_root - logical collection of root cxl_port items * @@ -640,6 +634,12 @@ to_cxl_root(const struct cxl_port *port) return container_of(port, struct cxl_root, port); } +struct cxl_root_ops { + int (*qos_class)(struct cxl_root *cxl_root, + struct access_coordinate *coord, int entries, + int *qos_class); +}; + static inline struct cxl_dport * cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) { @@ -734,8 +734,10 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct cxl_dport *parent_dport); struct cxl_root *devm_cxl_add_root(struct device *host, const struct cxl_root_ops *ops); -struct cxl_port *find_cxl_root(struct cxl_port *port); +struct cxl_root *find_cxl_root(struct cxl_port *port); void put_cxl_root(struct cxl_root *cxl_root); +DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T)) + int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); void cxl_bus_drain(void); diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index da3c3a08bd62..ddbb42f0fd70 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -95,7 +95,8 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_hdm *cxlhdm; - struct cxl_port *root; + struct cxl_root *cxl_root; + struct cxl_port *root_port; int rc; rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info); @@ -130,14 +131,15 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) * This can't fail in practice as CXL root exit unregisters all * descendant ports and that in turn synchronizes with cxl_port_probe() */ - root = find_cxl_root(port); + cxl_root = find_cxl_root(port); + root_port = &cxl_root->port; /* * Now that all endpoint decoders are successfully enumerated, try to * assemble regions from committed decoders */ - device_for_each_child(&port->dev, root, discover_region); - put_device(&root->dev); + device_for_each_child(&root_port->dev, root_port, discover_region); + put_cxl_root(cxl_root); return 0; } From patchwork Fri Jan 5 18:03:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13512430 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13976328C7 for ; Fri, 5 Jan 2024 18:03:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ThDre2DR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704477800; x=1736013800; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fUnmACVf8I1K1+10srbk/em5Y/LaLCkGPEZWRZlVYCs=; b=ThDre2DR2N5xpk1lgq3Ej+gjerC8/rabn6UvtOJRF3gX4usMiWXF4+0H zOPYDR94GZQ1yWmse6mKmg7UpTLO+MHHuLEd4vQXRoimOSz8vtde4Ifq2 rEFhaiZlbYwoP+BhQp0s79fYYF3c4mr7s+KPBK9iQysfmZw+Ck2ypkNPW VjAvTRueQ2I0lJCX/gRXEO7MIrXUKqxRxoioq5hS5ric60G48CbTgNpN2 M453zfcM6gOnXJmyg2HyI33OuBwrmc04yoo6GG9ImMvBor1/civHIUGuu ojlARsfvJVreGfZ747Lk8fN3Hch4jcK2aimh3KZm4dzYONfLGPXuu1lYN w==; X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="19067962" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="19067962" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="773905688" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="773905688" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.109.135]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:18 -0800 Subject: [PATCH v5 3/5] cxl: Fix device reference leak in cxl_port_perf_data_calculate() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Fri, 05 Jan 2024 11:03:17 -0700 Message-ID: <170447779772.3687480.17784838254725684393.stgit@djiang5-mobl3> In-Reply-To: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> References: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 cxl_port_perf_data_calculate() calls find_cxl_root() and does not dereference the 'struct device' in the cxl_root->port. find_cxl_root() calls get_device() and takes a reference on the port 'struct device' member. Use the __free() macro to ensure the dereference happens. Fixes: 7a4f148dd8d5 ("cxl: Compute the entire CXL path latency and bandwidth data") Signed-off-by: Dave Jiang --- v5: - Update patch title (Dan) --- drivers/cxl/core/cdat.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 0df5379cf02f..c6208aab452f 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -162,7 +162,6 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, struct xarray *dsmas_xa) { struct access_coordinate c; - struct cxl_root *cxl_root; struct dsmas_entry *dent; int valid_entries = 0; unsigned long index; @@ -174,7 +173,11 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port, return rc; } - cxl_root = find_cxl_root(port); + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port); + + if (!cxl_root) + return -ENODEV; + if (!cxl_root->ops || !cxl_root->ops->qos_class) return -EOPNOTSUPP; From patchwork Fri Jan 5 18:03:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13512431 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B94F3328BD for ; Fri, 5 Jan 2024 18:03:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WiACTKhn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704477805; x=1736013805; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Esv3MnknffmPqdGLatDPw9oWAzQh8iD1kz9bAD0+SQ8=; b=WiACTKhn1SSoQb4VmgLif4u4AHxYcu4Q15EJXgOlgKnsjEDQevQcRGKL 4TzrOOJhj/nfXkiT0khSX4Y9GR6GuDT4poelFBGzq7yoLYzt/BaDbf6ow gUl8Gyh+FNlHYkPnZ0/aLY9WW1V20tc0ifjBegHAjYVKHVD/b+UdPlGAn D9nTR6LEOXJBFAMJ3hduIGs+NZ+vrPWI8Vzi9UHy+CbSBdLjuf39a/YzJ S2QFZFevEW1jrRMNFndSydgT3EZ8jWnZwpsgDgJakEt/aVy735zMuepdP CXf0M06DZVyF1TQVL9XlreZt56qrk0savZ9u7XagHSDkuDTFLWn++BtHt g==; X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="382528528" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="382528528" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="924277928" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="924277928" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.109.135]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:24 -0800 Subject: [PATCH v5 4/5] cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_bridge() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Fri, 05 Jan 2024 11:03:23 -0700 Message-ID: <170447780395.3687480.12988681766480964910.stgit@djiang5-mobl3> In-Reply-To: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> References: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use scope-based resource management __free() macro to drop the open coded put_device() in cxl_find_nvdimm_bridge(). Signed-off-by: Dave Jiang --- v5 - Update commit log (Dan) --- drivers/cxl/core/pmem.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c index 57b777a088f6..e69625a8d6a1 100644 --- a/drivers/cxl/core/pmem.c +++ b/drivers/cxl/core/pmem.c @@ -64,16 +64,14 @@ static int match_nvdimm_bridge(struct device *dev, void *data) struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) { - struct cxl_root *cxl_root = find_cxl_root(cxlmd->endpoint); - struct cxl_port *port; + struct cxl_root *cxl_root __free(put_cxl_root) = + find_cxl_root(cxlmd->endpoint); struct device *dev; if (!cxl_root) return NULL; - port = &cxl_root->port; - dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge); - put_cxl_root(cxl_root); + dev = device_find_child(&cxl_root->port.dev, NULL, match_nvdimm_bridge); if (!dev) return NULL; From patchwork Fri Jan 5 18:03:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13512432 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C76D2328DB for ; Fri, 5 Jan 2024 18:03:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="haHms+f5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704477815; x=1736013815; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gqQZIYXV9POTcvvHbk3IALeSkmdMIpoUQIvSnJBtoAE=; b=haHms+f5YKdie1mbf1OyhnOHr/t+cIJaNaAnw+qZhk5eSJo0vGhxSkeD zQ+Y+Vikx/zPOR8TwXh1RdirXKhAjHiIgMLJu+Suo/uCtkYGXrBPrt5gS P56a2p0KonIC2EF2/IHnRuc/cog8fht2usTqIs1L6jKMhMrajhLurxyU8 5wRn73bZX9NUAIRUfVJe/NtJv2M2/szo2OMrLrEvOfl4B+Mq3sTyTigmv eI2CpP96LYCbQlnmG0loBcbvLCM/vdiHEnE+i/14RY8oxWWernI8PrYjz 31VSNPxuT3nkZSqzPSQknYHF5+57JN84CoXix3FzmHhlQXY4hZy0jv1eA g==; X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="382528549" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="382528549" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="924277951" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="924277951" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.109.135]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 10:03:33 -0800 Subject: [PATCH v5 5/5] cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_probe() From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, dave@stgolabs.net, rrichter@amd.com Date: Fri, 05 Jan 2024 11:03:29 -0700 Message-ID: <170447780994.3687480.10026614511779346820.stgit@djiang5-mobl3> In-Reply-To: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> References: <170447769575.3687480.11698914923419362733.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use scope-based resource management __free() macro to drop the open coded put_device() in cxl_endpoint_port_probe(). Signed-off-by: Dave Jiang --- v5: - Update commit log (Dan) v4: - Don't check return value of find_cxl_root() per comment. (Dan) --- drivers/cxl/port.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index ddbb42f0fd70..89d303f048e7 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -95,7 +95,6 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_hdm *cxlhdm; - struct cxl_root *cxl_root; struct cxl_port *root_port; int rc; @@ -131,7 +130,8 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) * This can't fail in practice as CXL root exit unregisters all * descendant ports and that in turn synchronizes with cxl_port_probe() */ - cxl_root = find_cxl_root(port); + struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port); + root_port = &cxl_root->port; /* @@ -139,7 +139,6 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) * assemble regions from committed decoders */ device_for_each_child(&root_port->dev, root_port, discover_region); - put_cxl_root(cxl_root); return 0; }