From patchwork Mon Jan 8 14:19:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13513544 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE5894777C for ; Mon, 8 Jan 2024 14:19:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SzZADC1E" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-55753dc5cf0so2179407a12.0 for ; Mon, 08 Jan 2024 06:19:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704723572; x=1705328372; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Tk8GMEH2iDgp9+UcEh38jMqbbPsEGwY6PJWrF1vIMYc=; b=SzZADC1Ettq4Doq8F9twzSawnQGxLL7hd7kPOzdEZ7uyehBUSaKPruafMbIXgAsgwA Jc0JseD7f1p3BCHv07fftIJI3tW/7sp1chNvOrquF2FaFcxpGNFC4SJd4ka1S1LxXkyJ IyTueYyE4JPyJXfJ4XkobqSrb4anRAZiHoI4VNsntG6AMezRmfo7gUUojkqK9mDTGw03 EqHFYIqsqan+Bz+QQzC1jUcU9LlJX3s1pzplVPXBwy4ozew3zW2dLxKa7jIbvv9hCMtx gYK02+kgUUUvoB8Io2KHcXhZBxAiobHXQ/qIxhTjbj2NCuyfb/ZTiaBa1S7DkChVdMe/ z+tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704723572; x=1705328372; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tk8GMEH2iDgp9+UcEh38jMqbbPsEGwY6PJWrF1vIMYc=; b=HiGORA+dyzjDdwSAC5qwGzeNzg3UOC+20M8SPIsIjjx+C3LzHgu7JaYC+9fiUTZguJ ZKdW3UGgFOC82JDxnS6XHFa/PPgTmGYWljypYG8d9cQXjykAS4XhfW4+erpjnmsoKa7r ABKR/cLYZ2WJfHA9qS9oF9IxTjCAoZMHdqqSRBr1/F7+HNn0zlA5CGi6zm4gyhtP0GL1 MqjCm5LRW6CFtKYw/1U6e4ybsMVxySdOQaJh7yeqHB6WE0EBfGMjTgHJMnMNh10MEjSE hQzdLqP8HE7zLoOcDWtGL+Nrjh9JcipURqSUfQpOQY/ucCXBrFFKsIsQ3ebfNmfu97kn acnA== X-Gm-Message-State: AOJu0YywrIj5M5TRR/5zKp0vZdAgMSJqXMjhlRL7GBrnNdBSRQWyBRTL gO5P5oRp6TuAHLUwrKtjhGjrzJVh2Ai9/w== X-Google-Smtp-Source: AGHT+IEP1+7nubU1S6k3PB+PGx8xMcpRq2jDDpjENbnqKpbbbZ8f4SsdkUXllSfRjzc6bAeM/fDmdg== X-Received: by 2002:a05:6402:1495:b0:557:5162:4ffb with SMTP id e21-20020a056402149500b0055751624ffbmr1902788edv.50.1704723572106; Mon, 08 Jan 2024 06:19:32 -0800 (PST) Received: from [127.0.1.1] ([178.197.223.112]) by smtp.gmail.com with ESMTPSA id cm25-20020a0564020c9900b00556ee10cfe3sm4319832edb.92.2024.01.08.06.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 06:19:31 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 08 Jan 2024 15:19:14 +0100 Subject: [PATCH 1/6] dt-bindings: PCI: qcom,pcie-sm8550: move SM8550 to dedicated schema Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240108-dt-bindings-pci-qcom-split-v1-1-d541f05f4de0@linaro.org> References: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> In-Reply-To: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=10959; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=DpJSGu2wnJYHtYBQ7iL7qyP67ihLXzxaqzTmEpv8wfo=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlnARrKyEbA+zAgkx0eM2qKj+/X6ebGbdWdu8YY ZxwKqEUtm6JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZZwEawAKCRDBN2bmhouD 10LQD/wMDQRJKaZFLCGuKhbyRMJY0bSlIt6e+Gyzig9d6dQf4dsBawT0ngZz32BC7eHINlTz4ej LNf4NxdW0dCrV5VfVxL2nbTh8YOZFvZlyQ92xUJ6ixF2fJF/Vzb/a/eJ2eJY/0rasFbZw5lSVdB PKHFiGx4znaPeRbR+p3IRPfTlI8BvVz4Z4+qfTgHbaRlLWdMZp2mtCClrDYY5iD+fth0uUBKudI mh0KM2QdUa3kVMZwkG1vaJX2gWaaQvDlvOlQDIH1SEqDBYjgJYGdZDbbdSlVMSxkl3CJs3CQZPZ BbQE/1as+C3od+i+/C7YAFpM+Zc/PdPDoXkoLZj9tlLALFybInYt+sYTOlhhhzTrntr8fFSSceX v7LTVbrIA8avQiacQYiVGVmWh0LRxaF77Ph0F7PJv51zXRQc0YSMQswodT9kvFT9pq7nv4u1snC yylBpyguAREI5XVtENDvreR3hfGlLm8GLAxQrRiUX9rs7C7kUnbRyrXbIYTEWpeulZb1hDDfrV1 SFsnWLqQNKpZ7irSjhVf4unvzDX7iyodUJ5W7XlGsYyr/N1G4n0ED1x2D2i6MJwh/UN1IdxAawF CsjEGJgneD11EyH6kad4sXBeg4L6E2GUunt+54eOK9VkbQiOX0LligseI3nELiztgs+Oh2wo6nC d54iN5Tmxa4P2XA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The qcom,pcie.yaml binding file containing all possible Qualcomm SoC PCIe root complexes gets quite complicated with numerous if:then: conditions customizing clocks, interrupts, regs and resets. Adding and reviewing new devices is difficult, so simplify it by having shared common binding and file with only one group of compatible devices: 1. Copy all common qcom,pcie.yaml properties (so everything except supplies) to a new shared qcom,pcie-common.yaml schema. 2. Move SM8550 PCIe compatible devices to dedicated binding file. This creates equivalent SM8550 schema file, except missing required compatible which is actually redundant. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 98 ++++++++++++ .../devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 171 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 38 ----- 3 files changed, 269 insertions(+), 38 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml new file mode 100644 index 000000000000..125136176f93 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCI Express Root Complex Common Properties + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +properties: + reg: + minItems: 4 + maxItems: 6 + + reg-names: + minItems: 4 + maxItems: 6 + + interrupts: + minItems: 1 + maxItems: 8 + + interrupt-names: + minItems: 1 + maxItems: 8 + + iommu-map: + minItems: 1 + maxItems: 16 + + clocks: + minItems: 3 + maxItems: 13 + + clock-names: + minItems: 3 + maxItems: 13 + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: pcie-mem + - const: cpu-pcie + + phys: + maxItems: 1 + + phy-names: + items: + - const: pciephy + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 12 + + reset-names: + minItems: 1 + maxItems: 12 + + perst-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + +required: + - reg + - reg-names + - interrupt-map-mask + - interrupt-map + - clocks + - clock-names + +anyOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + - msi-map-mask + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml new file mode 100644 index 000000000000..b6d025f153bc --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + oneOf: + - const: qcom,pcie-sm8550 + - items: + - enum: + - qcom,pcie-sm8650 + - const: qcom,pcie-sm8550 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 7 + maxItems: 8 + + clock-names: + minItems: 7 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8550"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr"; + + dma-coherent; + + interrupts = ; + interrupt-names = "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..3b7dd9a4ef60 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -40,11 +40,6 @@ properties: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 - - items: - - enum: - - qcom,pcie-sm8650 - - const: qcom,pcie-sm8550 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -226,7 +221,6 @@ allOf: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: properties: reg: @@ -715,37 +709,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8550 - then: - properties: - clocks: - minItems: 7 - maxItems: 8 - clock-names: - minItems: 7 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr # Aggre NoC PCIe AXI clock - - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock - resets: - minItems: 1 - maxItems: 2 - reset-names: - minItems: 1 - items: - - const: pci # PCIe core reset - - const: link_down # PCIe link down reset - - if: properties: compatible: @@ -883,7 +846,6 @@ allOf: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: oneOf: - properties: From patchwork Mon Jan 8 14:19:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13513545 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A756146B96 for ; Mon, 8 Jan 2024 14:19:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lGcTLKij" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-5534dcfdd61so3304016a12.0 for ; Mon, 08 Jan 2024 06:19:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704723574; x=1705328374; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+78zlVt1FV8yyOp2vqGnSaeurNFRzarHLtyM2gLYMeI=; b=lGcTLKijVCDp7HFFp0s3Sq+fr1iPKFo6jjiwsplCKH8X7Q/Quy9VkmxoRnRdUkJCV7 SfQ9r1tHb6nDU7KqFjXTeLemL7Jbka7oHGm7lbv7gLOosyflbpzYEoSedeTr8Y7ePEK3 sdUB1U2a/aN+/Y/fCq6ma7WT3pi0Cq5lDxUmqMbVPIq1u723ujdJVwDqwYj29AsNjnBB KvgRaHGKZV3VKNu0cZve8x3b1VF9hyVV+Zdba5r9u7jB9QF8fLvlAeb1bMSrT5LdEwr0 y3bTH52tjg9N5Hng1iS3r369WpUxkc2r6O7t0ErxM3Tn8OMvl8tBFFB8eskscFidHsLy LUcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704723574; x=1705328374; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+78zlVt1FV8yyOp2vqGnSaeurNFRzarHLtyM2gLYMeI=; b=pKdW231bryJ4keyPU17uaL/HXcJXHEzUNci1Iws0RCHaIeaNomjysPcVGO8xKtLwQ1 doxO2Xeqlh9jlaX0NOU3hGKTCF/Fp2R4hQG/8CwxNSomCpzmBzXonkl9XafQhhdkCJ7F iGNI4FfrzjACsbR+GudVONRR2XU/1MXKAn5z2aOUN6wekzSSehDAvcu2A0XW0bQC23pX hTBRI/vNPJJFB19r6ECz1+i8iGhfQJw/iwJ4CP1efu0UL0b82JBmnKnLauX04zA4uUZs A96fNKM85kkusAWnoYLUURQ5IS6xazYG/2msqFJDgJ2KS4OLKskErQyfk5HMR1wePVPh hNVg== X-Gm-Message-State: AOJu0YxhQIkxrKdNHLuPtfmQnm8di4VH5Dgj3TjShxRgaWIrR+VZ39m1 4EdCvWFtA7fi+WcqtDyLRG++Mj3iPavO4w== X-Google-Smtp-Source: AGHT+IGXx4D8W9yRqemsnU4p+Rf0h4Dvj7Du3AEs2vn2cgRufRWQtRHd3g6m7U4mPrYJGg3XkIw6TQ== X-Received: by 2002:a50:9f62:0:b0:556:86ae:48cc with SMTP id b89-20020a509f62000000b0055686ae48ccmr3455741edf.3.1704723573891; Mon, 08 Jan 2024 06:19:33 -0800 (PST) Received: from [127.0.1.1] ([178.197.223.112]) by smtp.gmail.com with ESMTPSA id cm25-20020a0564020c9900b00556ee10cfe3sm4319832edb.92.2024.01.08.06.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 06:19:33 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 08 Jan 2024 15:19:15 +0100 Subject: [PATCH 2/6] dt-bindings: PCI: qcom,pcie-sm8450: move SM8450 to dedicated schema Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240108-dt-bindings-pci-qcom-split-v1-2-d541f05f4de0@linaro.org> References: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> In-Reply-To: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=10937; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=tpvQUXvg5E9u86IBOEmNel446qGis5zrjX+q7vXISSk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlnARsx69OmRrKdYl3w2pSnLG+UpmH+GF05InmJ 9iJUx+jfuiJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZZwEbAAKCRDBN2bmhouD 13jcD/9CXd9QJR2rI8j6JwI5dvbq6iXerljPjdkpfkAtlZuk5eh8APlApOz/wL1MFKtZx2vNomI Ooawu3qliH4X3I4XRqvP17mudthyOOKYdhmj42k0vIRAYjsk9mMQU5ncc3bzE2DTJLgJEsqdc9P g0hGWWaW6ObNsWe3jPGAh0ZqPlI7Dq8EV5fLHza0gnZZ5X8NjzhuSN4GGKNdCoiRSjT5U2a6dE2 Z7YrcRJvAkEBHsxhjdw3ATB89Khs2nHOhcYFzROc4kOzw/EjCaH7UutogwT/Sys/er5DQSz7R0y Ynjiylcty/tN5SaIEPUeuGnLIm27mR7wyc5HTregOGXuBBJhFWOdYAoPu9+XARW0/n/yBkIjLaf ZafUGuz+XZfZTFOBgniWEsn/OBpvGJmky31tHcT9GclNEKETxzM56cPKqnu8SMt0MRxsJkZoRl4 QhYRjD5qRVukXrHGEDaaFaq5kLaFe9+/yMPi/ZEeWaoArB0QWe25IQj0mnEUBfLoi5uY2rmj3VG Cd182GKSDwW4g9vRZnUJEk1AIQCmvzD6F1Xop0SPoxqEAJRiCqZvdJdbKgFl6NUw0+BguzRkLgN lPkk995V+UvXtDSidcY9xN29Ft7obTRFNl12EM0IR6Ui56GXCQFzpJcIPirDwHhqYI8fpI7LPSA IlOipCF5gkY+c8Q== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8450 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except missing required compatible which is actually redundant. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 215 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 67 ------- 2 files changed, 215 insertions(+), 67 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml new file mode 100644 index 000000000000..59ba809b6204 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -0,0 +1,215 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 11 + maxItems: 12 + + clock-names: + minItems: 11 + maxItems: 12 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8450-pcie0 + then: + properties: + clocks: + minItems: 12 + maxItems: 12 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8450-pcie1 + then: + properties: + clocks: + minItems: 11 + maxItems: 11 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8450-pcie0"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + msi-map = <0x0 &gic_its 0x5981 0x1>, + <0x100 &gic_its 0x5980 0x1>; + msi-map-mask = <0xff00>; + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 3b7dd9a4ef60..791ddab8ddc7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -38,8 +38,6 @@ properties: - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -219,8 +217,6 @@ allOf: - qcom,pcie-sdx55 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 then: properties: reg: @@ -648,67 +644,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie0 - then: - properties: - clocks: - minItems: 12 - maxItems: 12 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie1 - then: - properties: - clocks: - minItems: 11 - maxItems: 11 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -844,8 +779,6 @@ allOf: - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 then: oneOf: - properties: From patchwork Mon Jan 8 14:19:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13513546 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49DCC4778D for ; Mon, 8 Jan 2024 14:19:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="x23WcbYw" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-556c3f0d6c5so2148448a12.2 for ; Mon, 08 Jan 2024 06:19:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704723575; x=1705328375; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AYUdL9LhigCUuNxpKQSG3orhjjUgFykStJlKLI4UJXQ=; b=x23WcbYwVeBYtT/wsCVJ+n21Nuq3uLER2CGigxmZNcpAMVpRjx/J1AnP5cwTV1QUC2 tIog/oLV5CP7gr3jUbzpT7XK0Jjs87GP0YCKIj9HUKZ9BpaqTeXl4Yfwhp4SKUyNZY3t CfCRltstRaQ8xLzkVfgBHb/Yc+giRNrolP7w7ixdDjeovBoTHtLDNOYxd58sU8BO1yQW ZpuMsnt3IZ97a3EJQnKkM1BrlMRWqjXS6Gd4qxDioEk8w3M351qBAte9kWId4YUO1nDe k6g4gGMdP0iGhMxVFJC9utWAhTOEBjoSHHpk5SqawDAgozErHQW+rRsy61qiFi7ksWng CiRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704723575; x=1705328375; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AYUdL9LhigCUuNxpKQSG3orhjjUgFykStJlKLI4UJXQ=; b=iIAsId+W/ZXelJrLE43nNFrYEhOL3wMnlgFEXxuTIfSiFKi6f5S8tYsi7Q5U3DipPs scrxmpyPJOjrgVyusgFfymNGBWZTeUrofIu3mS+Q1FDn2AI2o2xdKdiJJDsHpbtZ4LuI wxJrxq0DVPy5AUuc+WL+Uf8HhJfB26ogbKwmgwWEUBNQkzrc/1R6ZL0XuqAPTmhgcRaR p/Q1Yt1LNX+Aulknnps5nq0yRZ+7grwdne/8zVj3gVviZ2fHzbbTMC1QeJGITI4G/MA0 qwe1+wxznen1UWdIVjtIADLH4jOFgs6G8AtVAW5t9EDhrLeAVLHbzq3aDUxIyzlCnn4U IKOg== X-Gm-Message-State: AOJu0YyusISewb8O6uG2k4AOt9f7A6NqAFMPAcFBSMtjrCP0yrxOkMj1 2cGQjtAlXjBm1J6LsAIMz6fNwRSoNxkDcA== X-Google-Smtp-Source: AGHT+IHodgCGxlYFECuk7tEpv9qqfelHDER75/CPSDGqne5zTsKnw2Ne2K/eSeSVyJde46rcFDGYEg== X-Received: by 2002:a50:d602:0:b0:555:5879:ac50 with SMTP id x2-20020a50d602000000b005555879ac50mr1286331edi.117.1704723575687; Mon, 08 Jan 2024 06:19:35 -0800 (PST) Received: from [127.0.1.1] ([178.197.223.112]) by smtp.gmail.com with ESMTPSA id cm25-20020a0564020c9900b00556ee10cfe3sm4319832edb.92.2024.01.08.06.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 06:19:35 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 08 Jan 2024 15:19:16 +0100 Subject: [PATCH 3/6] dt-bindings: PCI: qcom,pcie-sm8250: move SM8250 to dedicated schema Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240108-dt-bindings-pci-qcom-split-v1-3-d541f05f4de0@linaro.org> References: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> In-Reply-To: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9582; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=n+U3UP1WPgFwGBXXZYHM6zXxzBW41C5KWTwWZh4Wlww=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlnARtbAn8FvKzZd0s9O0WHt1pOMGQ1bj3oyWxi 1C5AS4HBs2JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZZwEbQAKCRDBN2bmhouD 14+sEACX13p5qiDBDTJ8pnItvqtp5Bed1/J5IhvgyhjwpWRtJBV7AOjs86lJzgqsfrNBV84UVK4 FH/Zt+5nS+t74mWtDJ4f+gTgswT0zvCyUDT+8FdYn1afvI+RBfhqlTTBUOdXslWfz4PJQZazWwQ 3VyJDXakUOTSRKtepOPpslHA4eanCfLzqn6Vt5dWMhka0ztsL7h6GQ8H+5eJugi2NDJK1L9iz0N fjxgBdRptdaf2H/w0R+2EEMzZZuOIvtxnYnZMnUUnWOYq7PDupkE/5qSTqFpklC57HemYwjAav2 i/6NUq+AidL9fVQt30rK7J2H5u9mFQB4kKWhOl+a+gV/fJjnM5E63N140wX4n88hdddCi2Bl5O/ LfVocwK0bF7TGNcnr2eO5SXPdMx7xVnGzHFEDNPyf5ckAFQgEp/400bvPPU0oI2ni0/+n4iVGfZ /8h4yJZfSfmgAOaYPHAf7wmC9lSS9xROwWxeiSX99P7IrUnZnAgp3Hr5bwFpESnlt4rzalCI6pb hxiQBGuQRFgvLCAfYjuvlPXp9gmofR07x7bIJ14OkUD1N22CLEgeJGq2HdMktutWyZLHJHswEuN 7riRjWkIIGKQ+AkkUJxf/QWeZHcf5B61oFqTBO0zhLSfpmZPPrDT4TqT5U5WTy8sTJuXcUjPwXU U125aN7ywTCbbxA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8250 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except missing required compatible which is actually redundant. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie-sm8250.yaml | 180 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 48 ------ 2 files changed, 180 insertions(+), 48 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml new file mode 100644 index 000000000000..f668f0f2e497 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8250 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + # Unfortunately the "optional" ref clock is used in the middle of the list + oneOf: + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8250"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + dma-coherent; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 791ddab8ddc7..14341d210063 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -36,7 +36,6 @@ properties: - qcom,pcie-sdm845 - qcom,pcie-sdx55 - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 @@ -215,7 +214,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdx55 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 then: properties: @@ -570,51 +568,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8250 - then: - oneOf: - # Unfortunately the "optional" ref clock is used in the middle of the list - - properties: - clocks: - minItems: 9 - maxItems: 9 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ref # REFERENCE clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - properties: - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -777,7 +730,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sdm845 - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 then: oneOf: From patchwork Mon Jan 8 14:19:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13513547 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 315764A9A0 for ; Mon, 8 Jan 2024 14:19:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qFsW/zte" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-5571e662b93so1555868a12.2 for ; Mon, 08 Jan 2024 06:19:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704723577; x=1705328377; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mVpt434jNRVRohV7kr2LuWzc6/sexF7PFmFs+zIPX64=; b=qFsW/zte+lkO0Gyn1sGKXxu4zzMJC8zi6sWexxUIDoKy8d14M0Ao+KBLy3QGPGzkfp GwtFY1hQq+Yc4cFLKzOvIXvZK1V5ote8d8ly/yFndrQ6JovL24D27RgyQqzlZAOGXIuy enH5b78tj1pmTR3lWY9fWHPWQh+dZhK32LT+LLOV03udkD3kg9lDC8GUrOHGQgf9hIJT MCVO+TdFq8Lx8pc6QlxrCPdxsNeRdkNFEMZinpy0Aj3JmjcDZoJ2tIeQQXFzYBDkmmKd wFsMEkd/I6JtWhp4PNmSu5xJXfwHQ3ASygn3PyuIyeFs2Xk3O9GkPiLt7YgwzOSl8oOR VBrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704723577; x=1705328377; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mVpt434jNRVRohV7kr2LuWzc6/sexF7PFmFs+zIPX64=; b=pKbpnE0yUGlfqPDiazR0j/Gxv3D3HFGqQLan9C7/+3aU8sRvQHM5y46zNyZ7b8JOpI MDBMlzK89gm0Wj4/cdV1efTGXvvbenWdCXbHmmpYu4wIVMHAdoohcF5s4z17W50K6G6i jYTEoK7V0sSieS4Q05o9juqItnipwzF4R2pqasA1pJsL0RFoztV39haS93lCZNGMOqaQ OzP/cBFgt+lY1wuoE2RFIpuI5lzp23IfMjBthC3CBP0mKvwKIX8HgWtbsYS3Q7VJZREU YQ0wty28jLZWk3IVeSw9qXbipLDxveDH1fZNvpQEOCXif6D2JSCFS5/w1jVGw+CReX1m kr2A== X-Gm-Message-State: AOJu0YwL8Uk1pJa7Ll7YvYzQSM28MyOOui3km4oFIFwOzEhzi1Lnz8wz CGqfQPnB5v1uT4ENtpHuTuVkAJOhtW24Dg== X-Google-Smtp-Source: AGHT+IHibpWAtiMj6g/1Ub2GoYdmfVeIcmSM1yTtzc72S9QHGlRzY1/1p0TUACoKTJHjbSVzf4VyZw== X-Received: by 2002:a05:6402:22fa:b0:552:1ca9:3d51 with SMTP id dn26-20020a05640222fa00b005521ca93d51mr1926375edb.15.1704723577565; Mon, 08 Jan 2024 06:19:37 -0800 (PST) Received: from [127.0.1.1] ([178.197.223.112]) by smtp.gmail.com with ESMTPSA id cm25-20020a0564020c9900b00556ee10cfe3sm4319832edb.92.2024.01.08.06.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 06:19:37 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 08 Jan 2024 15:19:17 +0100 Subject: [PATCH 4/6] dt-bindings: PCI: qcom,pcie-sm8150: move SM8150 to dedicated schema Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240108-dt-bindings-pci-qcom-split-v1-4-d541f05f4de0@linaro.org> References: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> In-Reply-To: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=7378; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=Nqn0ZdTHTBHxb1tUaI+NvAqCuySp7YX/Q+1216+S1Pg=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlnARuGJz4E//2l+Z1a64pBG1KvUptgo9pD5QwP OSasXEFt6GJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZZwEbgAKCRDBN2bmhouD 1+UdD/9oyLqrY5UtxAUDoU5GsFDdfL0DDOWTGP7m05AhA9sVra6wp9sU4kSm3TLT4+2tkANJikB viH361X3yjWudTNnD+BQuGmcL20K474isue9fNmR6ktRVR6oWHXe3lhmnXT51W5mqa82Hnyez7b gCoH/dpAnelYCz58ywFshqJaerWex/eBg2IjbybSScy9pnl7Vna6Egmm9d1RGV3JFrL3sc53yKi 7Bvfez/ae+5XKaxr1Tsp4Ri25J2wrRe+1LH1MG6srgqcV9XMXfWyfwCFZY1Kac+j/Bn2rW9uNHH tW6M8DAcKFiDG+/VzZIFOIsaodwrf4qYo9/MEnD85P34v3ZmWkDMdZ/omuM5p+DGUAaZ7f6dXTj lrfb9oHYgXS2dGDNrz8gdtFy+i3b3LAKQUJXzeY7xgac3PfOjrheyhBRylMnlsJ0+Ia7rc8y1z5 0MzQuQRsz7FF4LKkduP4z7VYt3fsAIfnMu/0KTqcUVt20VDTxJtsG8eCinriLLhW9rUCYHcgajb pUnJn4dhDOH6goHOamGwDOn6s1/Zgkm0kfo2jB6VYQW0blUM2YM8sQPUSNPSa/39scfRuoqIoZE 7fyeaIwnehVwk+oUeCPA86ukq4tz2WPLT3cb+TIzVHO5zP4BTP3w9Zo9EEyI3RL2B/p+w4zygvs lO7GbUwC2yx7rJg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8150 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except missing required compatible which is actually redundant. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 157 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ---- 2 files changed, 157 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml new file mode 100644 index 000000000000..acb69501e81c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8150 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ref # REFERENCE clock + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@1c00000 { + compatible = "qcom,pcie-sm8150"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ref"; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 14341d210063..47888b5b1a13 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -35,7 +35,6 @@ properties: - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - - qcom,pcie-sm8150 - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 @@ -541,33 +540,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8150 - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ref # REFERENCE clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -729,7 +701,6 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 - - qcom,pcie-sm8150 - qcom,pcie-sm8350 then: oneOf: From patchwork Mon Jan 8 14:19:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13513548 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E063846424 for ; Mon, 8 Jan 2024 14:19:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ulg+YgN4" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-554fe147ddeso2117198a12.3 for ; Mon, 08 Jan 2024 06:19:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704723579; x=1705328379; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mMYVSsOQIqa0el4b7dJvhvf3UUspYxYiQhj5yhxNFQ0=; b=ulg+YgN4rV6WEd/ZPNLeV7rK9Qb/kTq8SWohy44CQCVRYQE8XoOQQVrPZGipVLMA/n eXdMxaVFYwOmn7BP97i/+9sLU0yRXctbbvJtz8UKr9+vJfw7BCjUT5Qy6YWtA0NhLtFo CWkAJrr460/UZ89bXh301RSHD7kIXSAJzTzsHCJ4aauzWgQXqR2qq0cJAots1sG8/MCm eLpePOgYuxX2pkn20tPtihB0zNPDlSFJZDr8eOShw4H4XbiZyWpKXqVbgFMsbWwhLFj9 20Xnnrihu0SXd1WUMhIkpVusH2+Lw6VvFp/tmzRQ5HcegeaWxc/E/WwaNneY6rCitoHM 31jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704723579; x=1705328379; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mMYVSsOQIqa0el4b7dJvhvf3UUspYxYiQhj5yhxNFQ0=; b=h0/7pQ667bpl5i9Kib8Hr81kGwqqW94FZGa1y2LFB4pgf+SZx70CLRWf1U50cFUnwv OI/k98xsaBRIHy/efm7Tc+W176VnwIUNRth/Kelf6sp3wI9DSCZWBljamrOIG+5mGN7z 31MXVKZj0Fntqy85V/NjpmfHRTiuLwaJllkAsjVw0MZl/5jJyAvONNvLzkjKne7z8jXs qxgOfUCAS4gUoTj72vBuaIlo3Y0Bu3dkfJ14v0YPz/KhUq6+bR/Z3EViLQJfeLrm3Gic I7VI2R2BJ7jwdQLrYskvxHcFfLRjU3vhPvT31u1tpLoNmpu6+yYBG5+tqCTH96AU1JR7 byTg== X-Gm-Message-State: AOJu0YwyuHqCo2Ni+ze25bEHHT479eg6YDlpaIslQP8SFait5h3/fGme YsJr2UHhBRilGxrr6uGNpCpxr3Sr874aAwM3gqwfXr9kxHs= X-Google-Smtp-Source: AGHT+IGrgNFaoPrqUSkG9Oax5ackYDjZhZWCPgGBhRTwDsSxrmD5YWf3D9nrXohPJlBL/Gz5gra9LA== X-Received: by 2002:aa7:df0c:0:b0:557:dd8:253c with SMTP id c12-20020aa7df0c000000b005570dd8253cmr1386080edy.1.1704723579367; Mon, 08 Jan 2024 06:19:39 -0800 (PST) Received: from [127.0.1.1] ([178.197.223.112]) by smtp.gmail.com with ESMTPSA id cm25-20020a0564020c9900b00556ee10cfe3sm4319832edb.92.2024.01.08.06.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 06:19:38 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 08 Jan 2024 15:19:18 +0100 Subject: [PATCH 5/6] dt-bindings: PCI: qcom,pcie-sm8350: move SM8350 to dedicated schema Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240108-dt-bindings-pci-qcom-split-v1-5-d541f05f4de0@linaro.org> References: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> In-Reply-To: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=8406; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=YQxKIcZdGuD+BAZ0c00nt7v4FpqcshDqK8AOGuh0NqE=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlnARvFt4yZVwodqFKCLZEr7QsVgu+mfV47Rm89 pI/ha5TkXqJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZZwEbwAKCRDBN2bmhouD 13uWEACMcyfY6Dk/pAfsUECsQcBhVAYBJYcjVkc/t9lqe0OPfGDc0tNM1X/6XEGupxSgIjY+5QR Gz9kfR8L0yfNHJ8sZNk40ad7BSA0CS0U/f1zkdu1OYi2dOJgfcl+PUuj/d35jBwfl6utMuySwAN MJXwDhDPahLUT30sVYeDj6dIHvjOcLJ02KNwXOK8vEURYaJyXXGgZ2qdMzI0XcTYHL0ZdLmwOhH EHZa29frjTJCiONcVx1P/HHIKs20dWmpW7q5ltwgyAY01ZrerQpIObz1ypIzN5XymMw/WEudBno XITJfqBL4QlTMG3UP4ZbCbTV42JD4jKwKmBvBA+ZsrWtlOQm2t383Hsp44Ww278dgxGPoDk5w6z LphrJsqrN7L6wF35D6Q8Prf6HDe/S3DmRxGqqiIkhO553ByQogOREX5UoIjxglvTV/JITqHIhzW J4R+M3ZWAFmSi2oYOl2SSi3hw/ruzAmUCleSxEIftwQ4U1uzhQhIVzWL1xaIR2p+u1FjXTNQDBX NUMgyDzYBdv/q9SDnfrC/Lrc2FN+xZnUMZm4P4xxyd8vygsfyQFcUlnirt4DU2tHMSrs1fL+tAz sRMU0xdRVlcsUGvclqnRAccX0HSMZQlC+mElbdJS6+BEY3tNHLwT+IyGoNNTCoKTM21NxMFWrSa SrP1sXdNE33OLcg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8350 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except missing required compatible which is actually redundant. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie-sm8350.yaml | 169 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 32 ---- 2 files changed, 169 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml new file mode 100644 index 000000000000..fea41340b2c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8350 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1", + "aggre0"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 47888b5b1a13..6e03a1bce5d4 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -35,7 +35,6 @@ properties: - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -213,7 +212,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdx55 - - qcom,pcie-sm8350 then: properties: reg: @@ -540,35 +538,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8350 - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -701,7 +670,6 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 - - qcom,pcie-sm8350 then: oneOf: - properties: From patchwork Mon Jan 8 14:19:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13513549 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09B1D5103A for ; Mon, 8 Jan 2024 14:19:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eAjcPQCo" Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-50e835800adso1660360e87.0 for ; Mon, 08 Jan 2024 06:19:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704723581; x=1705328381; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=zJIr3gLxozsh7CrXcoARrwWHbGQibktk/tx+W6SEOMk=; b=eAjcPQCoABPBvTmhBccIsIIXWorb7W8R+ECv+z4v4rVoiMo4F4iN/Nafz2bAP/kdpV bljSF/cqwLBaA9yh4VQNgRTWx0V8jzt4WbRoGz48a4tv0wTwedseTijoXeCAwzPQzYPB PT+TVvaGbRm2szaxqJKjhh82o+K8oqyDsXUvMzwIbOkFQuA1qnZTkOwDodGKPnAwO/Qh EOszQXiE3LP1HYAyDSDQOe9oRpQU59uM9qI/OqccG+yAra/RbwB52b6ny/IefZtdqWsp g1RbEUMX24AlesPEQSl2MNkSgll6tXk9K0qsQTyTwnxLBl/EtxewJjAjjvEMJqp62CJN maAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704723581; x=1705328381; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zJIr3gLxozsh7CrXcoARrwWHbGQibktk/tx+W6SEOMk=; b=ClI0QPcbb9qAfYxbdQSSakHf34IcwQa1QInL3PTysmWdIdo7kCTmnEuFBLk21ubGKD ytIZOIg6gHywqQSgB3aUIH3wJsZylgNblRAga/SZMd4cMhAvmnMU07op9qOLXFwUFPiH 2bUAw2cWWfM2AyqkTiRAdhVFSTfAJEe9ZAcKssxbtjff62SsInnhTrSxsvq7WyU5BY4+ R0VBwGRYJHdZHAz+7HHxkedeGIumj+XjnwCXh610u9+1/7jOnYpGPhFOVysB07QlVIKk 4E2YYdzgd+2+wiZv7O47jb46ZS/l29g4kEl9Ab9OMkV5Frz53oBGzRqyGjsM2jxa99qf l26A== X-Gm-Message-State: AOJu0Yz8sWnsXsbNOHffScYfNHN2JTiJCOA/Fof8h9CSjOuMtYDHXSui /g3vA9095FE729yHUXS/OJefa+eo7h1jRg== X-Google-Smtp-Source: AGHT+IF6BF3WEmz+iyt90io9cKDJUXePQXotDy57DSR1o8XX/a4S2qlPJsh8wZxYkt7svMovVscD5Q== X-Received: by 2002:a05:6512:3c98:b0:50e:9872:ae78 with SMTP id h24-20020a0565123c9800b0050e9872ae78mr1212160lfv.196.1704723581042; Mon, 08 Jan 2024 06:19:41 -0800 (PST) Received: from [127.0.1.1] ([178.197.223.112]) by smtp.gmail.com with ESMTPSA id cm25-20020a0564020c9900b00556ee10cfe3sm4319832edb.92.2024.01.08.06.19.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 06:19:40 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 08 Jan 2024 15:19:19 +0100 Subject: [PATCH 6/6] dt-bindings: PCI: qcom,pcie-sc8280xp: move SC8280XP to dedicated schema Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240108-dt-bindings-pci-qcom-split-v1-6-d541f05f4de0@linaro.org> References: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> In-Reply-To: <20240108-dt-bindings-pci-qcom-split-v1-0-d541f05f4de0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9760; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=KUGAXveuGUxtLUDN9Q/9x0zJbEyqON8MU6FY9snIhUA=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlnARwxAW+ymdGztyYbyrxrHfjah6+4fz4ZjDHB 3is/3+4Z7aJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZZwEcAAKCRDBN2bmhouD 11I+D/sHtyMZ7xKrBk9rTRBibxvh30ude8J7B9O3qHoGJ47tubPvVCgwTviGhiAFRf+98+NcJ+j 0POGYhbCDf+jElbHshaGxnYMzjoHCo1tHoTUma1YCXIPYVaNaJ+362rU6UTlp3r10SJy/HxM82Y LdQ4RBKKIAYFH4dr3mn5xo2FiqSNvjUiY6kpNiufeEOInNseTcho9tJADSgKVP2pJa43yF5VFqM ke7TTj7t8SJ1KRtUOugpinL4t6dJLc0+W+6Q/g1N9DGqOuhGB/5Wca0ktDIlODc5CfBbxy+y36a ZlWjdlEGl5sRcXuEuBDI1yaDi4cTD99hBEkflOuwHGdaCrwv7TrLMUEVOUIQO2oFzXeXNuFNCY+ akD1iMGaYTfAXo+9oI/NrR41VZ/y2Yn2EbNQVewdBy+az5x5DNz7jRQXl68eC1aYjFSA0yGYiLR Vym74BIafRrU81Lkv0omfXsJLKsLCFtEh1wTRcWFRsK8Goybm1hEwCTTeAUOQae3A7tbEBX0xFi HrLYkk6nVIfhOJ8qU1reCzeDO8c9bMWwXyEGpUtljo7xKMKD/darIv1/zPs3+POa7qD6GRCAL6A ZWxQZO9nI2lpCpSfa848RMI26JJDeUDRT922WZJz+hD6FVLeud8F7zEws/w90zhWoTHET0p0XVO ilIEfX5RededRmw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SC8280XP compatible PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except missing required compatible which is actually redundant. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/pci/qcom,pcie-sc8280xp.yaml | 180 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 54 ------- 2 files changed, 180 insertions(+), 54 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml new file mode 100644 index 000000000000..25c9f13ae977 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sa8540p + - qcom,pcie-sc8280xp + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr_4 # NoC aggregate 4 clock + - const: noc_aggr_south_sf # NoC aggregate South SF clock + - const: cnoc_qx # Configuration NoC QX clock + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + + vddpe-3v3-supply: + description: A phandle to the PCIe endpoint power supply + +required: + - interconnects + - interconnect-names + +allOf: + - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c20000 { + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x3c000000 0x0 0xf1d>, + <0x0 0x3c000f20 0x0 0xa8>, + <0x0 0x3c001000 0x0 0x1000>, + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <2>; + num-lanes = <4>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; + assigned-clock-rates = <19200000>; + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + dma-coherent; + + interrupts = , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie2a_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie2a_default>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_2A_GDSC>; + + resets = <&gcc GCC_PCIE_2A_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&vreg_nvme>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 6e03a1bce5d4..c8f36978a94c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -28,11 +28,9 @@ properties: - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - items: @@ -210,7 +208,6 @@ allOf: - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdx55 then: properties: @@ -538,36 +535,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8540p - - qcom,pcie-sc8280xp - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr_4 # NoC aggregate 4 clock - - const: noc_aggr_south_sf # NoC aggregate South SF clock - - const: cnoc_qx # Configuration NoC QX clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -623,9 +590,7 @@ allOf: compatible: contains: enum: - - qcom,pcie-sa8540p - qcom,pcie-sa8775p - - qcom,pcie-sc8280xp then: required: - interconnects @@ -692,24 +657,6 @@ allOf: - const: msi6 - const: msi7 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc8280xp - then: - properties: - interrupts: - minItems: 4 - maxItems: 4 - interrupt-names: - items: - - const: msi0 - - const: msi1 - - const: msi2 - - const: msi3 - - if: properties: compatible: @@ -724,7 +671,6 @@ allOf: - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p then: properties: interrupts: