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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D1.mail.protection.outlook.com (10.167.242.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.12 via Frontend Transport; Tue, 9 Jan 2024 03:48:11 +0000 Received: from ethanolx50f7host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 8 Jan 2024 21:48:06 -0600 From: Smita Koralahalli To: , , CC: Ard Biesheuvel , Alison Schofield , Vishal Verma , "Ira Weiny" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Smita Koralahalli Subject: [PATCH v2 1/4] acpi/ghes, cxl: Create a common CXL struct to handle different CXL CPER records Date: Tue, 9 Jan 2024 03:47:52 +0000 Message-ID: <20240109034755.100555-2-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240109034755.100555-1-Smita.KoralahalliChannabasappa@amd.com> References: <20240109034755.100555-1-Smita.KoralahalliChannabasappa@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D1:EE_|CYXPR12MB9442:EE_ X-MS-Office365-Filtering-Correlation-Id: 03470624-80b6-47d5-08d5-08dc10c5cd50 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 03:48:11.6600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03470624-80b6-47d5-08d5-08dc10c5cd50 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9442 Currently defined cxl_cper_callback interface between CXL subsystem and GHES module is just confined to handling CXL Component errors only. Extend this callback to process CXL Protocol errors as well. Achieve by defining a new struct cxl_cper_event_info to include cxl_cper_event_rec and other fields of CXL protocol errors which will be defined in future patches. Signed-off-by: Smita Koralahalli --- v2: cxl_cper_rec_data -> cxl_cper_event_info data -> info --- drivers/acpi/apei/ghes.c | 6 +++++- drivers/cxl/pci.c | 8 ++++---- include/linux/cxl-event.h | 6 +++++- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index aed465d2fd68..60b615d361d3 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -693,6 +693,10 @@ static cxl_cper_callback cper_callback; static void cxl_cper_post_event(enum cxl_event_type event_type, struct cxl_cper_event_rec *rec) { + struct cxl_cper_event_info info; + + info.rec = *(struct cxl_cper_event_rec *)rec; + if (rec->hdr.length <= sizeof(rec->hdr) || rec->hdr.length > sizeof(*rec)) { pr_err(FW_WARN "CXL CPER Invalid section length (%u)\n", @@ -707,7 +711,7 @@ static void cxl_cper_post_event(enum cxl_event_type event_type, guard(rwsem_read)(&cxl_cper_rw_sem); if (cper_callback) - cper_callback(event_type, rec); + cper_callback(event_type, &info); } int cxl_cper_register_callback(cxl_cper_callback callback) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index b14237f824cf..1ad240ead4fd 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -972,9 +972,9 @@ static struct pci_driver cxl_pci_driver = { #define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0) static void cxl_cper_event_call(enum cxl_event_type ev_type, - struct cxl_cper_event_rec *rec) + struct cxl_cper_event_info *info) { - struct cper_cxl_event_devid *device_id = &rec->hdr.device_id; + struct cper_cxl_event_devid *device_id = &info->rec.hdr.device_id; struct pci_dev *pdev __free(pci_dev_put) = NULL; enum cxl_event_log_type log_type; struct cxl_dev_state *cxlds; @@ -996,11 +996,11 @@ static void cxl_cper_event_call(enum cxl_event_type ev_type, return; /* Fabricate a log type */ - hdr_flags = get_unaligned_le24(rec->event.generic.hdr.flags); + hdr_flags = get_unaligned_le24(info->rec.event.generic.hdr.flags); log_type = FIELD_GET(CXL_EVENT_HDR_FLAGS_REC_SEVERITY, hdr_flags); cxl_event_trace_record(cxlds->cxlmd, log_type, ev_type, - &uuid_null, &rec->event); + &uuid_null, &info->rec.event); } static int __init cxl_pci_driver_init(void) diff --git a/include/linux/cxl-event.h b/include/linux/cxl-event.h index 17eadee819b6..6ce839c59749 100644 --- a/include/linux/cxl-event.h +++ b/include/linux/cxl-event.h @@ -141,8 +141,12 @@ struct cxl_cper_event_rec { union cxl_event event; } __packed; +struct cxl_cper_event_info { + struct cxl_cper_event_rec rec; +}; + typedef void (*cxl_cper_callback)(enum cxl_event_type type, - struct cxl_cper_event_rec *rec); + struct cxl_cper_event_info *info); #ifdef CONFIG_ACPI_APEI_GHES int cxl_cper_register_callback(cxl_cper_callback callback); From patchwork Tue Jan 9 03:47:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 13514270 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2079.outbound.protection.outlook.com [40.107.92.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1425610A; 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Mon, 8 Jan 2024 21:48:07 -0600 From: Smita Koralahalli To: , , CC: Ard Biesheuvel , Alison Schofield , Vishal Verma , "Ira Weiny" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Smita Koralahalli Subject: [PATCH v2 2/4] efi/cper, cxl: Make definitions and structures global Date: Tue, 9 Jan 2024 03:47:53 +0000 Message-ID: <20240109034755.100555-3-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240109034755.100555-1-Smita.KoralahalliChannabasappa@amd.com> References: <20240109034755.100555-1-Smita.KoralahalliChannabasappa@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D1:EE_|MN2PR12MB4552:EE_ X-MS-Office365-Filtering-Correlation-Id: 1de3f251-1605-4364-f025-08dc10c5cdb8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 03:48:12.3943 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1de3f251-1605-4364-f025-08dc10c5cdb8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4552 In preparation to add tracepoint support, move protocol error UUID definition to a common location and make CXL RAS capability struct global for use across different modules. Signed-off-by: Smita Koralahalli Reviewed-by: Jonathan Cameron Acked-by: Ard Biesheuvel --- v2: No change. --- drivers/firmware/efi/cper_cxl.c | 11 ----------- drivers/firmware/efi/cper_cxl.h | 7 ++----- include/linux/cper.h | 4 ++++ include/linux/cxl-event.h | 11 +++++++++++ 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cxl.c index a55771b99a97..4fd8d783993e 100644 --- a/drivers/firmware/efi/cper_cxl.c +++ b/drivers/firmware/efi/cper_cxl.c @@ -18,17 +18,6 @@ #define PROT_ERR_VALID_DVSEC BIT_ULL(5) #define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6) -/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */ -struct cxl_ras_capability_regs { - u32 uncor_status; - u32 uncor_mask; - u32 uncor_severity; - u32 cor_status; - u32 cor_mask; - u32 cap_control; - u32 header_log[16]; -}; - static const char * const prot_err_agent_type_strs[] = { "Restricted CXL Device", "Restricted CXL Host Downstream Port", diff --git a/drivers/firmware/efi/cper_cxl.h b/drivers/firmware/efi/cper_cxl.h index 86bfcf7909ec..6f8c00495708 100644 --- a/drivers/firmware/efi/cper_cxl.h +++ b/drivers/firmware/efi/cper_cxl.h @@ -7,14 +7,11 @@ * Author: Smita Koralahalli */ +#include + #ifndef LINUX_CPER_CXL_H #define LINUX_CPER_CXL_H -/* CXL Protocol Error Section */ -#define CPER_SEC_CXL_PROT_ERR \ - GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \ - 0x4B, 0x77, 0x10, 0x48) - #pragma pack(1) /* Compute Express Link Protocol Error Section, UEFI v2.10 sec N.2.13 */ diff --git a/include/linux/cper.h b/include/linux/cper.h index c1a7dc325121..2cbf0a93785a 100644 --- a/include/linux/cper.h +++ b/include/linux/cper.h @@ -89,6 +89,10 @@ enum { #define CPER_NOTIFY_DMAR \ GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \ 0x72, 0x2D, 0xEB, 0x41) +/* CXL Protocol Error Section */ +#define CPER_SEC_CXL_PROT_ERR \ + GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \ + 0x4B, 0x77, 0x10, 0x48) /* * Flags bits definitions for flags in struct cper_record_header diff --git a/include/linux/cxl-event.h b/include/linux/cxl-event.h index 6ce839c59749..3a41dd5723e8 100644 --- a/include/linux/cxl-event.h +++ b/include/linux/cxl-event.h @@ -141,6 +141,17 @@ struct cxl_cper_event_rec { union cxl_event event; } __packed; +/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */ +struct cxl_ras_capability_regs { + u32 uncor_status; + u32 uncor_mask; + u32 uncor_severity; + u32 cor_status; + u32 cor_mask; + u32 cap_control; + u32 header_log[16]; +}; + struct cxl_cper_event_info { struct cxl_cper_event_rec rec; }; From patchwork Tue Jan 9 03:47:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 13514271 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2088.outbound.protection.outlook.com [40.107.223.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B40026106; Tue, 9 Jan 2024 03:48:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; 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Date: Tue, 9 Jan 2024 03:47:54 +0000 Message-ID: <20240109034755.100555-4-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240109034755.100555-1-Smita.KoralahalliChannabasappa@amd.com> References: <20240109034755.100555-1-Smita.KoralahalliChannabasappa@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D2:EE_|PH0PR12MB5647:EE_ X-MS-Office365-Filtering-Correlation-Id: 5972f506-ed0c-44a7-277c-08dc10c5ce14 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hMMbs/Dhyj3wdDL0MOld5ssxdYYGRHCfgQm6mqyETiDloWOcSqafpe15nSEx2WDV111y0OeB/RR4NY45V9B9qqd+k7pAVIrOIRawPYhzBqFoSr78K7K8bkwkzLGwnFPLHGdmb+cPZ9eEe9Jcaxof9IRME9VZsZJqhv5DcOpbHvCCmUsnZ2uUSx2A45vjbib8tAk1P2dBKlLOlKC7boZh1FurWHxJdTmAqvyLqwAIp5TMRyXuS5MKg62ZTgpiL+qV2Gnf13Wf+CXeY6g5qGM2SrFcTnMEMab0+b/5cFm9ovuAipTyInNcYvTHjkrDvTEF5PQhHy4e6urQ+jbzSh9IZluejjapYzqOLdNZxkm0tsEBVedbhRFsfwd7TN8JLna9sVIzOCWNC/3nUC9rTz2QxRrJ3RS86HInB/Hc/Z8hCMSQ4V6HlsgwcEjkpa+tt7fgLrY/0upftcjDdsEzbJfavR5R5YkQYW4kGHYTLXvfKD8MZmcLz7Tpc7SeyQydUd3wk1SM99w+KlylORvNtBLEn/7NayBrArTWNn8wGWAKfhDbcx/jj+K4hfY00opj1u647X1FrMsSl4r0qPETElupTblDV9JHnPROzIEXvUyhijl/wZWtcS4Jm4OKChG06DS82nCc6R26MpdV3B1o8D6XTmW1h1A5vCU/3/LEA2e0l38F4LEKw7AgQYlzBk9Kogtlmw9+atqK5CW2sQU9stAJRchbTCMl9IgU6ah1+v+7JgLy3vWGrGhbDQ8ZZu1Fv/fO471tHR8fEDWA1XnwUFcuiuHvF/a2FZCIlVvc6vLx+XYzhWQ6CXxlYa5MI/s3OJ+j X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(136003)(396003)(346002)(230922051799003)(230273577357003)(230173577357003)(64100799003)(82310400011)(186009)(451199024)(1800799012)(40470700004)(36840700001)(46966006)(47076005)(81166007)(82740400003)(356005)(36756003)(40480700001)(40460700003)(86362001)(6666004)(7696005)(316002)(8676002)(478600001)(4326008)(54906003)(26005)(336012)(1076003)(16526019)(36860700001)(2616005)(426003)(70586007)(110136005)(70206006)(83380400001)(8936002)(41300700001)(5660300002)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 03:48:13.0390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5972f506-ed0c-44a7-277c-08dc10c5ce14 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5647 UEFI v2.10 section N.2.13 defines a CPER record for CXL Protocol errors. Add GHES support to detect CXL CPER Protocol record and cache error severity, device_id, serial number and CXL RAS capability struct in struct cxl_cper_event_info. Signed-off-by: Smita Koralahalli --- v2: Change to sub-struct for protocol error specific elemenets. Set serial number unconditionally. Copy entire cxl_ras_capability_regs struct rather than pointer. Calculate error severity in efi/cper and change to enum. --- drivers/acpi/apei/ghes.c | 11 ++++++ drivers/firmware/efi/cper_cxl.c | 68 +++++++++++++++++++++++++++++++++ include/linux/cxl-event.h | 13 +++++++ 3 files changed, 92 insertions(+) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 60b615d361d3..1d4f3d68a0bc 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -714,6 +714,14 @@ static void cxl_cper_post_event(enum cxl_event_type event_type, cper_callback(event_type, &info); } +void cxl_cper_handle_prot_err(struct acpi_hest_generic_data *gdata) +{ + struct cxl_cper_event_info info; + + if (cxl_cper_handle_prot_err_info(gdata, &info)) + return; +} + int cxl_cper_register_callback(cxl_cper_callback callback) { guard(rwsem_write)(&cxl_cper_rw_sem); @@ -768,6 +776,9 @@ static bool ghes_do_proc(struct ghes *ghes, else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { queued = ghes_handle_arm_hw_error(gdata, sev); } + else if (guid_equal(sec_type, &CPER_SEC_CXL_PROT_ERR)) { + cxl_cper_handle_prot_err(gdata); + } else if (guid_equal(sec_type, &CPER_SEC_CXL_GEN_MEDIA_GUID)) { struct cxl_cper_event_rec *rec = acpi_hest_get_payload(gdata); diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cxl.c index 4fd8d783993e..9b9b8c8f1157 100644 --- a/drivers/firmware/efi/cper_cxl.c +++ b/drivers/firmware/efi/cper_cxl.c @@ -8,6 +8,7 @@ */ #include +#include #include "cper_cxl.h" #define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0) @@ -44,6 +45,17 @@ enum { USP, /* CXL Upstream Switch Port */ }; +static enum cxl_aer_err_type cper_severity_cxl_aer(int cper_severity) +{ + switch (cper_severity) { + case CPER_SEV_RECOVERABLE: + case CPER_SEV_FATAL: + return CXL_AER_UNCORRECTABLE; + default: + return CXL_AER_CORRECTABLE; + } +} + void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_err) { if (prot_err->valid_bits & PROT_ERR_VALID_AGENT_TYPE) @@ -176,3 +188,59 @@ void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_e sizeof(cxl_ras->header_log), 0); } } + +int cxl_cper_handle_prot_err_info(struct acpi_hest_generic_data *gdata, + struct cxl_cper_event_info *info) +{ + struct cper_sec_prot_err *prot_err = acpi_hest_get_payload(gdata); + struct cper_cxl_event_devid *device_id = &info->rec.hdr.device_id; + struct cper_cxl_event_sn *dev_serial_num = &info->rec.hdr.dev_serial_num; + size_t size = sizeof(*prot_err) + prot_err->dvsec_len; + + if (!(prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG)) { + pr_err(FW_WARN "Not a valid protocol error log\n"); + return -EINVAL; + } + + if (!(prot_err->valid_bits & PROT_ERR_VALID_DEVICE_ID)) { + pr_err(FW_WARN "Not a valid Device ID\n"); + return -EINVAL; + } + + /* + * Set device serial number unconditionally. + * + * Print a warning message if it is not valid. The device serial + * number is considered valid for CXL 1.1 device, CXL 2.0 device, + * CXL 2.0 Logical device, or CXL 2.0 Fabric Manager Managed + * Logical Device. + */ + if (!(prot_err->valid_bits & PROT_ERR_VALID_SERIAL_NUMBER) || + prot_err->agent_type > 0x4 || prot_err->agent_type == RCH_DP) + pr_warn(FW_WARN "Not a valid serial number\n"); + + dev_serial_num->lower_dw = prot_err->dev_serial_num.lower_dw; + dev_serial_num->upper_dw = prot_err->dev_serial_num.upper_dw; + + /* + * The device ID or agent address is only valid for CXL 1.1 device, + * CXL 2.0 device, CXL 2.0 Logical device, CXL 2.0 Fabric Manager + * Managed Logical Device, CXL Root Port, CXL Downstream Switch + * Port, or CXL Upstream Switch Port. + */ + if (prot_err->agent_type <= 0x7 && prot_err->agent_type != RCH_DP) { + device_id->segment_num = prot_err->agent_addr.segment; + device_id->bus_num = prot_err->agent_addr.bus; + device_id->device_num = prot_err->agent_addr.device; + device_id->func_num = prot_err->agent_addr.function; + } else { + pr_err(FW_WARN "Not a valid agent type\n"); + return -EINVAL; + } + + info->p_err.cxl_ras = *(struct cxl_ras_capability_regs *)((long)prot_err + size); + + info->p_err.severity = cper_severity_cxl_aer(gdata->error_severity); + + return 0; +} diff --git a/include/linux/cxl-event.h b/include/linux/cxl-event.h index 3a41dd5723e8..08e3979de9a3 100644 --- a/include/linux/cxl-event.h +++ b/include/linux/cxl-event.h @@ -152,13 +152,26 @@ struct cxl_ras_capability_regs { u32 header_log[16]; }; +enum cxl_aer_err_type { + CXL_AER_UNCORRECTABLE, + CXL_AER_CORRECTABLE, +}; + struct cxl_cper_event_info { struct cxl_cper_event_rec rec; + struct cxl_cper_prot_err { + struct cxl_ras_capability_regs cxl_ras; + int severity; + } p_err; }; typedef void (*cxl_cper_callback)(enum cxl_event_type type, struct cxl_cper_event_info *info); +struct acpi_hest_generic_data; +int cxl_cper_handle_prot_err_info(struct acpi_hest_generic_data *gdata, + struct cxl_cper_event_info *info); + #ifdef CONFIG_ACPI_APEI_GHES int cxl_cper_register_callback(cxl_cper_callback callback); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 03:48:13.6443 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f052e536-862c-458f-84a4-08dc10c5ce70 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8046 When PCIe AER is in FW-First, OS should process CXL Protocol errors from CPER records. These CPER records obtained from GHES module, will rely on a registered callback to be notified to the CXL subsystem in order to be processed. Call the existing cxl_cper_callback to notify the CXL subsystem on a Protocol error. The defined trace events cxl_aer_uncorrectable_error and cxl_aer_correctable_error currently trace native CXL AER errors. Reuse them to trace FW-First Protocol Errors. Signed-off-by: Smita Koralahalli --- v2: Added warning for serial number check. Moved severity determination to previous patch. --- drivers/acpi/apei/ghes.c | 5 +++++ drivers/cxl/core/pci.c | 29 +++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 +++ drivers/cxl/pci.c | 5 +++++ include/linux/cxl-event.h | 1 + 5 files changed, 43 insertions(+) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 1d4f3d68a0bc..4318b602e797 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -716,10 +716,15 @@ static void cxl_cper_post_event(enum cxl_event_type event_type, void cxl_cper_handle_prot_err(struct acpi_hest_generic_data *gdata) { + enum cxl_event_type event_type = CXL_CPER_EVENT_PROT_ERR; struct cxl_cper_event_info info; if (cxl_cper_handle_prot_err_info(gdata, &info)) return; + + guard(rwsem_read)(&cxl_cper_rw_sem); + if (cper_callback) + cper_callback(event_type, &info); } int cxl_cper_register_callback(cxl_cper_callback callback) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 37e1652afbc7..bde8ebf5e4b3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -836,6 +836,35 @@ void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport) } EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_dport, CXL); +void cxl_prot_err_trace_record(struct cxl_dev_state *cxlds, + struct cxl_cper_event_info *info) +{ + struct cper_cxl_event_sn *dev_serial_num = &info->rec.hdr.dev_serial_num; + u32 status, fe; + + if (((u64)dev_serial_num->upper_dw << 32 | + dev_serial_num->lower_dw) != cxlds->serial) + pr_warn("The device serial number in CPER differs or isn't valid\n"); + + if (info->p_err.severity == CXL_AER_CORRECTABLE) { + status = info->p_err.cxl_ras.cor_status & ~info->p_err.cxl_ras.cor_mask; + + trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + } else { + status = info->p_err.cxl_ras.uncor_status & ~info->p_err.cxl_ras.uncor_mask; + + if (hweight32(status) > 1) + fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, + info->p_err.cxl_ras.cap_control)); + else + fe = status; + + trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, + info->p_err.cxl_ras.header_log); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_prot_err_trace_record, CXL); + static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 0fa4799ea316..216003d4aec1 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -93,4 +93,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +struct cxl_cper_event_info; +void cxl_prot_err_trace_record(struct cxl_dev_state *cxlds, + struct cxl_cper_event_info *info); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 1ad240ead4fd..515983e7df10 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -995,6 +995,11 @@ static void cxl_cper_event_call(enum cxl_event_type ev_type, if (!cxlds) return; + if (ev_type == CXL_CPER_EVENT_PROT_ERR) { + cxl_prot_err_trace_record(cxlds, info); + return; + } + /* Fabricate a log type */ hdr_flags = get_unaligned_le24(info->rec.event.generic.hdr.flags); log_type = FIELD_GET(CXL_EVENT_HDR_FLAGS_REC_SEVERITY, hdr_flags); diff --git a/include/linux/cxl-event.h b/include/linux/cxl-event.h index 08e3979de9a3..96cc88aa04f3 100644 --- a/include/linux/cxl-event.h +++ b/include/linux/cxl-event.h @@ -113,6 +113,7 @@ enum cxl_event_type { CXL_CPER_EVENT_GEN_MEDIA, CXL_CPER_EVENT_DRAM, CXL_CPER_EVENT_MEM_MODULE, + CXL_CPER_EVENT_PROT_ERR, }; #define CPER_CXL_DEVICE_ID_VALID BIT(0)