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Tue, 9 Jan 2024 11:24:08 -0800 From: Besar Wicaksono To: , , , , , , , , , , , , , , , , CC: , , , , , , Besar Wicaksono Subject: [PATCH v1 1/3] arm64: Add Neoverse-V2 part Date: Tue, 9 Jan 2024 13:23:08 -0600 Message-ID: <20240109192310.16234-2-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240109192310.16234-1-bwicaksono@nvidia.com> References: <20240109192310.16234-1-bwicaksono@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|DM6PR12MB4370:EE_ X-MS-Office365-Filtering-Correlation-Id: 1666ad53-a8b3-428c-d65b-08dc11489bd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MC28ZejVDVqkw9nRk+GGmIQqsYYfmLgEyOCu9u+iBlWb7uPfMLqRfAZKOwm8UI3vu8pj1L4Os/JTW5iMTDDgo/ocY5RAyCaTidOidJdcrnTMQ3zFD+WIMuyWBylHEjUd0E87L5/nOvEeAWhbjIariKzPmMx8C6qrZT0Dn3sxZJAvnjtwB3pZUcneGb7qCta6cSlINxmyQ75B4xjgc4qTDmZM7HJbcRn94yqSGbZtksVEPPLo2ENStzGD1VLRxesy+RzNc8VokqmwG694+OuJZEB84f08zXdQ6ed9FmFGOpGbqWUCCIb9ZirL5q4VJv9sFqnSDJYjYtdjZojDKaiUVjRtiya2MnpgMXdG5ovsxBUGemegfATglH0KaS6txZPORB+v1ZKgCiUSEJT2+3kpm7DatGqh1Ltk5tqO+SJcxPGFjBBtdFXkCNWUXFoKVwWBrk38zZ7o6cqqj3Y+iRGg3smLJOVfksj+8QG2UtDn14+SoCQ1ha7CArlzZBsLRY3tMNop3ZTU1OC8ntD5Thl45eK33TBTOHkegTjiyqlTGitMFSYT0A0joXOEJn+rcavyCn+3BW+IQ6IzWPRYR3dah3/ONzJvA/3XxEMKvjYAu2pFRMd3g5M5i4QoKwdrhnJweBwkkgR1cuMMugejChM2sF9pv1pZPIdPdnCwuapk/oSTq8l7mGVcGBeDGpGWPbB4nSIDGbiH8KjCEGovuQP2TnxCUvu3EQgeXXZparr81Dpd1R8NUSDqGunxNJ+c6atf4c3eXWlIMPTK36CrJ5Lt9DlU4AYOf4G8rlAYev2VnUZVXSo88ji3GCs0rzArxvg1 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(346002)(136003)(396003)(230922051799003)(1800799012)(186009)(82310400011)(64100799003)(451199024)(46966006)(36840700001)(40470700004)(26005)(2616005)(1076003)(336012)(426003)(478600001)(7696005)(47076005)(107886003)(316002)(5660300002)(41300700001)(7416002)(2906002)(70586007)(6636002)(70206006)(110136005)(54906003)(4326008)(8676002)(8936002)(356005)(921011)(82740400003)(36860700001)(36756003)(7636003)(86362001)(40460700003)(40480700001)(2101003)(83996005);DIR:OUT;SFP:1101; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the part number and MIDR for Neoverse-V2 Signed-off-by: Besar Wicaksono --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 7c7493cb571f..fe13a25fa082 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -85,6 +85,7 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define APM_CPU_PART_XGENE 0x000 #define APM_CPU_VAR_POTENZA 0x00 @@ -156,6 +157,7 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) +#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) From patchwork Tue Jan 9 19:23:09 2024 Content-Type: text/plain; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the part number and MIDR for Neoverse-V2. Signed-off-by: Besar Wicaksono --- tools/arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h index 7c7493cb571f..fe13a25fa082 100644 --- a/tools/arch/arm64/include/asm/cputype.h +++ b/tools/arch/arm64/include/asm/cputype.h @@ -85,6 +85,7 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define APM_CPU_PART_XGENE 0x000 #define APM_CPU_VAR_POTENZA 0x00 @@ -156,6 +157,7 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) +#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) From patchwork Tue Jan 9 19:23:10 2024 Content-Type: text/plain; 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Tue, 9 Jan 2024 11:25:27 -0800 From: Besar Wicaksono To: , , , , , , , , , , , , , , , , CC: , , , , , , Besar Wicaksono Subject: [PATCH v1 3/3] perf arm-spe: Add Neoverse-V2 to neoverse list Date: Tue, 9 Jan 2024 13:23:10 -0600 Message-ID: <20240109192310.16234-4-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240109192310.16234-1-bwicaksono@nvidia.com> References: <20240109192310.16234-1-bwicaksono@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E8:EE_|SA1PR12MB8599:EE_ X-MS-Office365-Filtering-Correlation-Id: 977489fd-c5a1-4355-5d6d-08dc1148c9b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RLPglGza1Zzzy4ur4P1WiVhhxOC8mDpifUtUT2YKoeKY1mQfBF+l0Jd6k6G29TglmWG4vK9fOIq2L0jgSsEwyndMfPGCKNGOXTW/HkQu9t8uB/AWLAzdMCZSk+6RxrVjUdKwwpB1on+GKKMJf0a87d/7DZG44OTe+3KcCUZ2TSKfvulwkbDUi0nEovzhYRmRAdXgpGrmKZHIFXY5JON/9Ew2NLQMWAzxuv+L2ga/hOUSramxqgdBV783DaRkWX6PVcAkxrZ9hIPOAOS1RgLmkZnUjeoC+w/Z1Cx/0GuiA0YcJf7qr3y5bTAz/3Ls7uxmXBP6NQoW12IIXwP+eG9qgEnFQYbiYbQJc8YRzUyVtMZfUrP2PDfRfY2K0dOLBhEHdQibWlyIkCnRZZh1IBQuWai0qfE4M+niLUfF0btbbG9LhfwRd8dUQnaq8/fpX7Elpq+dyj2CaxGCg9TFhMC61waaep/9e50mtaujMKzgGb7FdteecXNlDQrWnGLHU4Bmg9G24muzzHvBm95OS+tFYCxXP5HxDs5IqqKnCN5uElpjXnBbkN6uqYX93CGKv65J1HLnIZYK2kT/WLKDgBNfLjiySmMY7XLs/J2jSzLHILlEXPdptqFVu6HVu8YWBAnTCeeadp+HVTaFtKG0BbAYzphT6GxRU+8E8DUDUAu2O8p9kb9WROGqeOgDA97I39COwTiNBs2BQOJM/swYJuGekEUd92bMF/Bl4A3ujzrUDos5pJb1ucD6a9RVtZunkGRB38MHfqzD8+hekWvOc0MyHUjVO6Z6oxD0YcdFbN2DSAyeJ+KYU7nd/2+0QmIf8J2b X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(376002)(136003)(230922051799003)(64100799003)(451199024)(186009)(82310400011)(1800799012)(36840700001)(40470700004)(46966006)(40460700003)(40480700001)(336012)(426003)(1076003)(2616005)(26005)(478600001)(6666004)(7696005)(82740400003)(921011)(36756003)(86362001)(7636003)(356005)(7416002)(4744005)(70586007)(5660300002)(41300700001)(47076005)(36860700001)(107886003)(2906002)(110136005)(8936002)(54906003)(316002)(70206006)(6636002)(4326008)(8676002)(2101003)(83996005);DIR:OUT;SFP:1101; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Neoverse-V2 MIDR to neoverse_spe range list. Signed-off-by: Besar Wicaksono Reviewed-by: Leo Yan --- tools/perf/util/arm-spe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index afbd5869f6bf..936d2222e6d7 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -413,6 +413,7 @@ static const struct midr_range neoverse_spe[] = { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), {}, };