From patchwork Tue Jan 9 21:51:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A2D2C4707B for ; Tue, 9 Jan 2024 21:52:30 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665010.1035181 (Exim 4.92) (envelope-from ) id 1rNK1E-0007mP-4g; Tue, 09 Jan 2024 21:52:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665010.1035181; Tue, 09 Jan 2024 21:52:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1E-0007mG-1W; Tue, 09 Jan 2024 21:52:20 +0000 Received: by outflank-mailman (input) for mailman id 665010; Tue, 09 Jan 2024 21:52:19 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1D-0007gG-4Z for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:52:19 +0000 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on20600.outbound.protection.outlook.com [2a01:111:f403:2416::600]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 5818697a-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:52:13 +0100 (CET) Received: from BL0PR02CA0083.namprd02.prod.outlook.com (2603:10b6:208:51::24) by CH2PR12MB4859.namprd12.prod.outlook.com (2603:10b6:610:62::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:52:08 +0000 Received: from BL6PEPF0001AB4B.namprd04.prod.outlook.com (2603:10b6:208:51:cafe::18) by BL0PR02CA0083.outlook.office365.com (2603:10b6:208:51::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23 via Frontend Transport; Tue, 9 Jan 2024 21:52:08 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4B.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:52:08 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:52:07 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:52:04 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5818697a-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=naPLih+ZtP45yilDZ4jO1X9eF/iT1DhmMtMTqWLRfX1XwhggKaxPJY13FDeIxeTbzW1zVR8fSLZGFkBQhzjozuX5x7Nf/1kYkAyG8W17Uf3GeuI2fIDCN2tMlnvDaTL2lIzdPp/KsGOWnI8OjGMtUsekCFYNy3uTzPMLiH7Eo4L9LZP2tKkYjeRXmucgZzCNRHljS8i3f2f3OlkKDKicACHCIe8KKSYGMnyAhXtG1ZVRn1ZguLtg9fnlMF4A2LfMlf/bEnX1S8055IEj18M/jxhKrZmFu09r9+2ao1tT+xczWwqWuxyJnQ7DglQZ+gOabEjXiykX8M6PsdruFhNlKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RL158H3zLFXBqit8wLF1yDE7o053DsgxgnYdW9a1plc=; b=PcfJURML/GgDkXEy8NC214aZI6BAK8ZdU3tAQiUt4dtSg607avmYpaJH5TNW8FxU/TYKggjiGBDQ4rAJ0n+tKebPxrxci8PSZcDU6NWGeKbiPLwA/F3iXKKij9NhgoBe2WU+Doj7xaxWNMXZ1dGSQYXUDe3hfCWLhFywg2OHDCJyYo5rTdK8bktlRPxruzclb0h/XxTdJIZ3hskdgU13ynL4ZKRTtdSmo3flw5rNnlR63Hu/KsLlFabwffmB0omRwY+5xLTXhjJfDQ/ItOEjIkr4LV4r9EkiB4ObECHxt1PISfF0jrn5oae4kpxjQzemei6Kq7A5C7yBdsFDAl2WBw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RL158H3zLFXBqit8wLF1yDE7o053DsgxgnYdW9a1plc=; b=X7bpmR0HJMxodqAYJglhYDDI1jFGxKofwbUAHZuFOASjo8MqghY+q9R4/wwY9FwbfI2VtredLyIBMO2cd2L7pC0FWg/Il5W4sYVJk34TupjHaPSiiH+kN+gnimAZKRWsZzHi1qn+JRNSfXUEX2IR7ZhVaFEp3XvVeAYPXkHitSc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , George Dunlap , Julien Grall , Stefano Stabellini , Jun Nakajima , Kevin Tian , Paul Durrant , Volodymyr Babchuk , "Stewart Hildebrand" Subject: [PATCH v12 01/15] vpci: use per-domain PCI lock to protect vpci structure Date: Tue, 9 Jan 2024 16:51:16 -0500 Message-ID: <20240109215145.430207-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4B:EE_|CH2PR12MB4859:EE_ X-MS-Office365-Filtering-Correlation-Id: b3085e0f-5073-4dd2-11b4-08dc115d39e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 98EHorli8UHBwW8fVmiO863ZSbr5w73jSv7TKQQW2s+P8KenVIURHrE4nj/7nVDtNnifM6cXHcTu0m03q1x+pySHSg+LtIi6MsLNr69rgyDiVVTrvpMdN+wCxsey6lmtxiWz3dqsrMGnjV68ePbahX9l8YI53Lav+Wa0WL/1+6Y/oPfSK0qZiqKdJilcG99AClqBVtn7oy+dUhEDtzl+BwhDbQGU+gWjLXiibNFN0BzDi/uZXIHItYXarEXH/SCeF2pcvL7J914B3/foFIICfrwStB4VlPfiLc7Di9/TawpHSQmzKPKGJW8Hbwql6eOXFMYw+Go0vzk+H9p9agVANEnD+4GHRHAEmCeA3OoJ6FVuu5yJ3+S6G43/Ie7QHiKbeSyIRmE5fIP0pfsBbV5/AskK7b29e7BgIj5rbpBWj3qnCh74x47tp06zbHwatODCIE2Sl8OB4lJ2ZyguQBxa/vlkLS4QBI/aO9xj1IVWuRP/YHO3Hm7aneG1prpNodWIICUGQMzhM6IIpkPLOXzoEtnROwT1oP1pHQQML3SnGHvcW84upoCy2G+vXzDwiM+dfYkXKruT9U85OYNuBDOzc8EwO+yAB2wy5vbnKcFRe2rZd2eQFU6F+UJ9YZBMvuYLHn261UIBGR5pevg2XYjoPjN+Hc7cOdSs8BZaA4OPCGA7tq/hikZ8DEXFR9sc8bRETLa2+9vE9Dbn3/heq1EtKL+sYSpj2DvoXY+j4cyjACvE/IzT1GKC1KXbJyUiWMrnfD/04qFzbLNfxYjccpdauzzCyZS81I7hBo/pucfdXt0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(346002)(396003)(376002)(230922051799003)(1800799012)(82310400011)(186009)(451199024)(64100799003)(46966006)(40470700004)(36840700001)(30864003)(7416002)(41300700001)(81166007)(2906002)(5660300002)(82740400003)(54906003)(44832011)(40460700003)(36756003)(36860700001)(86362001)(356005)(6916009)(40480700001)(6666004)(316002)(8676002)(8936002)(4326008)(70586007)(70206006)(47076005)(83380400001)(336012)(1076003)(26005)(478600001)(426003)(2616005)(36900700001)(309714004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:52:08.0308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3085e0f-5073-4dd2-11b4-08dc115d39e6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4859 From: Oleksandr Andrushchenko Use a previously introduced per-domain read/write lock to check whether vpci is present, so we are sure there are no accesses to the contents of the vpci struct if not. This lock can be used (and in a few cases is used right away) so that vpci removal can be performed while holding the lock in write mode. Previously such removal could race with vpci_read for example. When taking both d->pci_lock and pdev->vpci->lock, they should be taken in this exact order: d->pci_lock then pdev->vpci->lock to avoid possible deadlock situations. 1. Per-domain's pci_lock is used to protect pdev->vpci structure from being removed. 2. Writing the command register and ROM BAR register may trigger modify_bars to run, which in turn may access multiple pdevs while checking for the existing BAR's overlap. The overlapping check, if done under the read lock, requires vpci->lock to be acquired on both devices being compared, which may produce a deadlock. It is not possible to upgrade read lock to write lock in such a case. So, in order to prevent the deadlock, use d->pci_lock instead. All other code, which doesn't lead to pdev->vpci destruction and does not access multiple pdevs at the same time, can still use a combination of the read lock and pdev->vpci->lock. 3. Drop const qualifier where the new rwlock is used and this is appropriate. 4. Do not call process_pending_softirqs with any locks held. For that unlock prior the call and re-acquire the locks after. After re-acquiring the lock there is no need to check if pdev->vpci exists: - in apply_map because of the context it is called (no race condition possible) - for MSI/MSI-X debug code because it is called at the end of pdev->vpci access and no further access to pdev->vpci is made 5. Use d->pci_lock around for_each_pdev and pci_get_pdev_by_domain while accessing pdevs in vpci code. Suggested-by: Roger Pau Monné Suggested-by: Jan Beulich Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand Reviewed-by: Roger Pau Monné --- Changes in v12: - s/pci_rwlock/pci_lock/ in commit message - expand comment about scope of pci_lock in sched.h - in vpci_{read,write}, if hwdom is trying to access a device assigned to dom_xen, holding hwdom->pci_lock is sufficient (no need to hold dom_xen->pci_lock) - reintroduce ASSERT in vmx_pi_update_irte() - reintroduce ASSERT in __pci_enable_msi{x}() - delete note 6. in commit message about removing ASSERTs since we have reintroduced them Changes in v11: - Fixed commit message regarding possible spinlocks - Removed parameter from allocate_and_map_msi_pirq(), which was added in the prev version. Now we are taking pcidevs_lock in physdev_map_pirq() - Returned ASSERT to pci_enable_msi - Fixed case when we took read lock instead of write one - Fixed label indentation Changes in v10: - Moved printk pas locked area - Returned back ASSERTs - Added new parameter to allocate_and_map_msi_pirq() so it knows if it should take the global pci lock - Added comment about possible improvement in vpci_write - Changed ASSERT(rw_is_locked()) to rw_is_write_locked() in appropriate places - Renamed release_domain_locks() to release_domain_write_locks() - moved domain_done label in vpci_dump_msi() to correct place Changes in v9: - extended locked region to protect vpci_remove_device and vpci_add_handlers() calls - vpci_write() takes lock in the write mode to protect potential call to modify_bars() - renamed lock releasing function - removed ASSERT()s from msi code - added trylock in vpci_dump_msi Changes in v8: - changed d->vpci_lock to d->pci_lock - introducing d->pci_lock in a separate patch - extended locked region in vpci_process_pending - removed pcidevs_lockis vpci_dump_msi() - removed some changes as they are not needed with the new locking scheme - added handling for hwdom && dom_xen case --- xen/arch/x86/hvm/vmsi.c | 22 +++++++-------- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/irq.c | 8 +++--- xen/arch/x86/msi.c | 14 +++++----- xen/arch/x86/physdev.c | 2 ++ xen/drivers/passthrough/pci.c | 9 +++--- xen/drivers/vpci/header.c | 18 ++++++++++++ xen/drivers/vpci/msi.c | 28 +++++++++++++++++-- xen/drivers/vpci/msix.c | 52 ++++++++++++++++++++++++++++++----- xen/drivers/vpci/vpci.c | 28 ++++++++++++++++--- xen/include/xen/sched.h | 3 +- 11 files changed, 144 insertions(+), 42 deletions(-) diff --git a/xen/arch/x86/hvm/vmsi.c b/xen/arch/x86/hvm/vmsi.c index 128f23636279..03caf91beefc 100644 --- a/xen/arch/x86/hvm/vmsi.c +++ b/xen/arch/x86/hvm/vmsi.c @@ -468,7 +468,7 @@ int msixtbl_pt_register(struct domain *d, struct pirq *pirq, uint64_t gtable) struct msixtbl_entry *entry, *new_entry; int r = -EINVAL; - ASSERT(pcidevs_locked()); + ASSERT(pcidevs_locked() || rw_is_locked(&d->pci_lock)); ASSERT(rw_is_write_locked(&d->event_lock)); if ( !msixtbl_initialised(d) ) @@ -538,7 +538,7 @@ void msixtbl_pt_unregister(struct domain *d, struct pirq *pirq) struct pci_dev *pdev; struct msixtbl_entry *entry; - ASSERT(pcidevs_locked()); + ASSERT(pcidevs_locked() || rw_is_locked(&d->pci_lock)); ASSERT(rw_is_write_locked(&d->event_lock)); if ( !msixtbl_initialised(d) ) @@ -684,7 +684,7 @@ static int vpci_msi_update(const struct pci_dev *pdev, uint32_t data, { unsigned int i; - ASSERT(pcidevs_locked()); + ASSERT(rw_is_locked(&pdev->domain->pci_lock)); if ( (address & MSI_ADDR_BASE_MASK) != MSI_ADDR_HEADER ) { @@ -725,8 +725,8 @@ void vpci_msi_arch_update(struct vpci_msi *msi, const struct pci_dev *pdev) int rc; ASSERT(msi->arch.pirq != INVALID_PIRQ); + ASSERT(rw_is_locked(&pdev->domain->pci_lock)); - pcidevs_lock(); for ( i = 0; i < msi->vectors && msi->arch.bound; i++ ) { struct xen_domctl_bind_pt_irq unbind = { @@ -745,7 +745,6 @@ void vpci_msi_arch_update(struct vpci_msi *msi, const struct pci_dev *pdev) msi->arch.bound = !vpci_msi_update(pdev, msi->data, msi->address, msi->vectors, msi->arch.pirq, msi->mask); - pcidevs_unlock(); } static int vpci_msi_enable(const struct pci_dev *pdev, unsigned int nr, @@ -778,15 +777,14 @@ int vpci_msi_arch_enable(struct vpci_msi *msi, const struct pci_dev *pdev, int rc; ASSERT(msi->arch.pirq == INVALID_PIRQ); + ASSERT(rw_is_locked(&pdev->domain->pci_lock)); rc = vpci_msi_enable(pdev, vectors, 0); if ( rc < 0 ) return rc; msi->arch.pirq = rc; - pcidevs_lock(); msi->arch.bound = !vpci_msi_update(pdev, msi->data, msi->address, vectors, msi->arch.pirq, msi->mask); - pcidevs_unlock(); return 0; } @@ -797,8 +795,8 @@ static void vpci_msi_disable(const struct pci_dev *pdev, int pirq, unsigned int i; ASSERT(pirq != INVALID_PIRQ); + ASSERT(rw_is_locked(&pdev->domain->pci_lock)); - pcidevs_lock(); for ( i = 0; i < nr && bound; i++ ) { struct xen_domctl_bind_pt_irq bind = { @@ -814,7 +812,6 @@ static void vpci_msi_disable(const struct pci_dev *pdev, int pirq, write_lock(&pdev->domain->event_lock); unmap_domain_pirq(pdev->domain, pirq); write_unlock(&pdev->domain->event_lock); - pcidevs_unlock(); } void vpci_msi_arch_disable(struct vpci_msi *msi, const struct pci_dev *pdev) @@ -854,6 +851,7 @@ int vpci_msix_arch_enable_entry(struct vpci_msix_entry *entry, int rc; ASSERT(entry->arch.pirq == INVALID_PIRQ); + ASSERT(rw_is_locked(&pdev->domain->pci_lock)); rc = vpci_msi_enable(pdev, vmsix_entry_nr(pdev->vpci->msix, entry), table_base); if ( rc < 0 ) @@ -861,7 +859,6 @@ int vpci_msix_arch_enable_entry(struct vpci_msix_entry *entry, entry->arch.pirq = rc; - pcidevs_lock(); rc = vpci_msi_update(pdev, entry->data, entry->addr, 1, entry->arch.pirq, entry->masked); if ( rc ) @@ -869,7 +866,6 @@ int vpci_msix_arch_enable_entry(struct vpci_msix_entry *entry, vpci_msi_disable(pdev, entry->arch.pirq, 1, false); entry->arch.pirq = INVALID_PIRQ; } - pcidevs_unlock(); return rc; } @@ -895,6 +891,8 @@ int vpci_msix_arch_print(const struct vpci_msix *msix) { unsigned int i; + ASSERT(rw_is_locked(&msix->pdev->domain->pci_lock)); + for ( i = 0; i < msix->max_entries; i++ ) { const struct vpci_msix_entry *entry = &msix->entries[i]; @@ -913,7 +911,9 @@ int vpci_msix_arch_print(const struct vpci_msix *msix) struct pci_dev *pdev = msix->pdev; spin_unlock(&msix->pdev->vpci->lock); + read_unlock(&pdev->domain->pci_lock); process_pending_softirqs(); + read_lock(&pdev->domain->pci_lock); /* NB: we assume that pdev cannot go away for an alive domain. */ if ( !pdev->vpci || !spin_trylock(&pdev->vpci->lock) ) return -EBUSY; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 8ff675883c2b..890faef48b82 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -413,7 +413,7 @@ static int cf_check vmx_pi_update_irte(const struct vcpu *v, spin_unlock_irq(&desc->lock); - ASSERT(pcidevs_locked()); + ASSERT(pcidevs_locked() || rw_is_locked(&msi_desc->dev->domain->pci_lock)); return iommu_update_ire_from_msi(msi_desc, &msi_desc->msg); diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c index 50e49e1a4b6f..4d89d9af99fe 100644 --- a/xen/arch/x86/irq.c +++ b/xen/arch/x86/irq.c @@ -2166,7 +2166,7 @@ int map_domain_pirq( struct pci_dev *pdev; unsigned int nr = 0; - ASSERT(pcidevs_locked()); + ASSERT(pcidevs_locked() || rw_is_locked(&d->pci_lock)); ret = -ENODEV; if ( !cpu_has_apic ) @@ -2323,7 +2323,7 @@ int unmap_domain_pirq(struct domain *d, int pirq) if ( (pirq < 0) || (pirq >= d->nr_pirqs) ) return -EINVAL; - ASSERT(pcidevs_locked()); + ASSERT(pcidevs_locked() || rw_is_locked(&d->pci_lock)); ASSERT(rw_is_write_locked(&d->event_lock)); info = pirq_info(d, pirq); @@ -2888,6 +2888,8 @@ int allocate_and_map_msi_pirq(struct domain *d, int index, int *pirq_p, { int irq, pirq, ret; + ASSERT(pcidevs_locked() || rw_is_locked(&d->pci_lock)); + switch ( type ) { case MAP_PIRQ_TYPE_MSI: @@ -2917,7 +2919,6 @@ int allocate_and_map_msi_pirq(struct domain *d, int index, int *pirq_p, msi->irq = irq; - pcidevs_lock(); /* Verify or get pirq. */ write_lock(&d->event_lock); pirq = allocate_pirq(d, index, *pirq_p, irq, type, &msi->entry_nr); @@ -2933,7 +2934,6 @@ int allocate_and_map_msi_pirq(struct domain *d, int index, int *pirq_p, done: write_unlock(&d->event_lock); - pcidevs_unlock(); if ( ret ) { switch ( type ) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index 335c0868a225..7da2affa2e82 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -602,7 +602,7 @@ static int msi_capability_init(struct pci_dev *dev, unsigned int i, mpos; uint16_t control; - ASSERT(pcidevs_locked()); + ASSERT(pcidevs_locked() || rw_is_locked(&dev->domain->pci_lock)); pos = pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSI); if ( !pos ) return -ENODEV; @@ -771,7 +771,7 @@ static int msix_capability_init(struct pci_dev *dev, if ( !pos ) return -ENODEV; - ASSERT(pcidevs_locked()); + ASSERT(pcidevs_locked() || rw_is_locked(&dev->domain->pci_lock)); control = pci_conf_read16(dev->sbdf, msix_control_reg(pos)); /* @@ -988,11 +988,11 @@ static int __pci_enable_msi(struct pci_dev *pdev, struct msi_info *msi, { struct msi_desc *old_desc; - ASSERT(pcidevs_locked()); - if ( !pdev ) return -ENODEV; + ASSERT(pcidevs_locked() || rw_is_locked(&pdev->domain->pci_lock)); + old_desc = find_msi_entry(pdev, msi->irq, PCI_CAP_ID_MSI); if ( old_desc ) { @@ -1043,11 +1043,11 @@ static int __pci_enable_msix(struct pci_dev *pdev, struct msi_info *msi, { struct msi_desc *old_desc; - ASSERT(pcidevs_locked()); - if ( !pdev || !pdev->msix ) return -ENODEV; + ASSERT(pcidevs_locked() || rw_is_locked(&pdev->domain->pci_lock)); + if ( msi->entry_nr >= pdev->msix->nr_entries ) return -EINVAL; @@ -1154,7 +1154,7 @@ int pci_prepare_msix(u16 seg, u8 bus, u8 devfn, bool off) int pci_enable_msi(struct pci_dev *pdev, struct msi_info *msi, struct msi_desc **desc) { - ASSERT(pcidevs_locked()); + ASSERT(pcidevs_locked() || rw_is_locked(&pdev->domain->pci_lock)); if ( !use_msi ) return -EPERM; diff --git a/xen/arch/x86/physdev.c b/xen/arch/x86/physdev.c index 47c4da0af7e1..369c9e788c1c 100644 --- a/xen/arch/x86/physdev.c +++ b/xen/arch/x86/physdev.c @@ -123,7 +123,9 @@ int physdev_map_pirq(domid_t domid, int type, int *index, int *pirq_p, case MAP_PIRQ_TYPE_MSI: case MAP_PIRQ_TYPE_MULTI_MSI: + pcidevs_lock(); ret = allocate_and_map_msi_pirq(d, *index, pirq_p, type, msi); + pcidevs_unlock(); break; default: diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 1439d1ef2b26..3a973324bca1 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -750,7 +750,6 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, pdev->domain = hardware_domain; write_lock(&hardware_domain->pci_lock); list_add(&pdev->domain_list, &hardware_domain->pdev_list); - write_unlock(&hardware_domain->pci_lock); /* * For devices not discovered by Xen during boot, add vPCI handlers @@ -759,18 +758,18 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, ret = vpci_add_handlers(pdev); if ( ret ) { - printk(XENLOG_ERR "Setup of vPCI failed: %d\n", ret); - write_lock(&hardware_domain->pci_lock); list_del(&pdev->domain_list); write_unlock(&hardware_domain->pci_lock); pdev->domain = NULL; + printk(XENLOG_ERR "Setup of vPCI failed: %d\n", ret); goto out; } + write_unlock(&hardware_domain->pci_lock); ret = iommu_add_device(pdev); if ( ret ) { - vpci_remove_device(pdev); write_lock(&hardware_domain->pci_lock); + vpci_remove_device(pdev); list_del(&pdev->domain_list); write_unlock(&hardware_domain->pci_lock); pdev->domain = NULL; @@ -1146,7 +1145,9 @@ static void __hwdom_init setup_one_hwdom_device(const struct setup_hwdom *ctxt, } while ( devfn != pdev->devfn && PCI_SLOT(devfn) == PCI_SLOT(pdev->devfn) ); + write_lock(&ctxt->d->pci_lock); err = vpci_add_handlers(pdev); + write_unlock(&ctxt->d->pci_lock); if ( err ) printk(XENLOG_ERR "setup of vPCI for d%d failed: %d\n", ctxt->d->domain_id, err); diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 58195549d50a..8f5850b8cf6d 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -173,6 +173,7 @@ bool vpci_process_pending(struct vcpu *v) if ( rc == -ERESTART ) return true; + write_lock(&v->domain->pci_lock); spin_lock(&v->vpci.pdev->vpci->lock); /* Disable memory decoding unconditionally on failure. */ modify_decoding(v->vpci.pdev, @@ -191,6 +192,7 @@ bool vpci_process_pending(struct vcpu *v) * failure. */ vpci_remove_device(v->vpci.pdev); + write_unlock(&v->domain->pci_lock); } return false; @@ -202,8 +204,20 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, struct map_data data = { .d = d, .map = true }; int rc; + ASSERT(rw_is_write_locked(&d->pci_lock)); + while ( (rc = rangeset_consume_ranges(mem, map_range, &data)) == -ERESTART ) + { + /* + * It's safe to drop and reacquire the lock in this context + * without risking pdev disappearing because devices cannot be + * removed until the initial domain has been started. + */ + write_unlock(&d->pci_lock); process_pending_softirqs(); + write_lock(&d->pci_lock); + } + rangeset_destroy(mem); if ( !rc ) modify_decoding(pdev, cmd, false); @@ -244,6 +258,8 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) unsigned int i; int rc; + ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); + if ( !mem ) return -ENOMEM; @@ -524,6 +540,8 @@ static int cf_check init_header(struct pci_dev *pdev) int rc; bool mask_cap_list = false; + ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); + switch ( pci_conf_read8(pdev->sbdf, PCI_HEADER_TYPE) & 0x7f ) { case PCI_HEADER_TYPE_NORMAL: diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index a253ccbd7db7..6ff71e5f9ab7 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -263,7 +263,7 @@ REGISTER_VPCI_INIT(init_msi, VPCI_PRIORITY_LOW); void vpci_dump_msi(void) { - const struct domain *d; + struct domain *d; rcu_read_lock(&domlist_read_lock); for_each_domain ( d ) @@ -275,6 +275,9 @@ void vpci_dump_msi(void) printk("vPCI MSI/MSI-X d%d\n", d->domain_id); + if ( !read_trylock(&d->pci_lock) ) + continue; + for_each_pdev ( d, pdev ) { const struct vpci_msi *msi; @@ -316,14 +319,33 @@ void vpci_dump_msi(void) * holding the lock. */ printk("unable to print all MSI-X entries: %d\n", rc); - process_pending_softirqs(); - continue; + goto pdev_done; } } spin_unlock(&pdev->vpci->lock); + pdev_done: + /* + * Unlock lock to process pending softirqs. This is + * potentially unsafe, as d->pdev_list can be changed in + * meantime. + */ + read_unlock(&d->pci_lock); process_pending_softirqs(); + if ( !read_trylock(&d->pci_lock) ) + { + printk("unable to access other devices for the domain\n"); + goto domain_done; + } } + read_unlock(&d->pci_lock); + domain_done: + /* + * We need this label at the end of the loop, but some + * compilers might not be happy about label at the end of the + * compound statement so we adding an empty statement here. + */ + ; } rcu_read_unlock(&domlist_read_lock); } diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index d1126a417da9..b6abab47efdd 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -147,6 +147,8 @@ static struct vpci_msix *msix_find(const struct domain *d, unsigned long addr) { struct vpci_msix *msix; + ASSERT(rw_is_locked(&d->pci_lock)); + list_for_each_entry ( msix, &d->arch.hvm.msix_tables, next ) { const struct vpci_bar *bars = msix->pdev->vpci->header.bars; @@ -163,7 +165,13 @@ static struct vpci_msix *msix_find(const struct domain *d, unsigned long addr) static int cf_check msix_accept(struct vcpu *v, unsigned long addr) { - return !!msix_find(v->domain, addr); + int rc; + + read_lock(&v->domain->pci_lock); + rc = !!msix_find(v->domain, addr); + read_unlock(&v->domain->pci_lock); + + return rc; } static bool access_allowed(const struct pci_dev *pdev, unsigned long addr, @@ -358,21 +366,35 @@ static int adjacent_read(const struct domain *d, const struct vpci_msix *msix, static int cf_check msix_read( struct vcpu *v, unsigned long addr, unsigned int len, unsigned long *data) { - const struct domain *d = v->domain; - struct vpci_msix *msix = msix_find(d, addr); + struct domain *d = v->domain; + struct vpci_msix *msix; const struct vpci_msix_entry *entry; unsigned int offset; *data = ~0UL; + read_lock(&d->pci_lock); + + msix = msix_find(d, addr); if ( !msix ) + { + read_unlock(&d->pci_lock); return X86EMUL_RETRY; + } if ( adjacent_handle(msix, addr) ) - return adjacent_read(d, msix, addr, len, data); + { + int rc = adjacent_read(d, msix, addr, len, data); + + read_unlock(&d->pci_lock); + return rc; + } if ( !access_allowed(msix->pdev, addr, len) ) + { + read_unlock(&d->pci_lock); return X86EMUL_OKAY; + } spin_lock(&msix->pdev->vpci->lock); entry = get_entry(msix, addr); @@ -404,6 +426,7 @@ static int cf_check msix_read( break; } spin_unlock(&msix->pdev->vpci->lock); + read_unlock(&d->pci_lock); return X86EMUL_OKAY; } @@ -491,19 +514,33 @@ static int adjacent_write(const struct domain *d, const struct vpci_msix *msix, static int cf_check msix_write( struct vcpu *v, unsigned long addr, unsigned int len, unsigned long data) { - const struct domain *d = v->domain; - struct vpci_msix *msix = msix_find(d, addr); + struct domain *d = v->domain; + struct vpci_msix *msix; struct vpci_msix_entry *entry; unsigned int offset; + read_lock(&d->pci_lock); + + msix = msix_find(d, addr); if ( !msix ) + { + read_unlock(&d->pci_lock); return X86EMUL_RETRY; + } if ( adjacent_handle(msix, addr) ) - return adjacent_write(d, msix, addr, len, data); + { + int rc = adjacent_write(d, msix, addr, len, data); + + read_unlock(&d->pci_lock); + return rc; + } if ( !access_allowed(msix->pdev, addr, len) ) + { + read_unlock(&d->pci_lock); return X86EMUL_OKAY; + } spin_lock(&msix->pdev->vpci->lock); entry = get_entry(msix, addr); @@ -579,6 +616,7 @@ static int cf_check msix_write( break; } spin_unlock(&msix->pdev->vpci->lock); + read_unlock(&d->pci_lock); return X86EMUL_OKAY; } diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 72ef277c4f8e..a1a004460491 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -42,6 +42,8 @@ extern vpci_register_init_t *const __end_vpci_array[]; void vpci_remove_device(struct pci_dev *pdev) { + ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); + if ( !has_vpci(pdev->domain) || !pdev->vpci ) return; @@ -77,6 +79,8 @@ int vpci_add_handlers(struct pci_dev *pdev) const unsigned long *ro_map; int rc = 0; + ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); + if ( !has_vpci(pdev->domain) ) return 0; @@ -361,7 +365,7 @@ static uint32_t merge_result(uint32_t data, uint32_t new, unsigned int size, uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size) { - const struct domain *d = current->domain; + struct domain *d = current->domain; const struct pci_dev *pdev; const struct vpci_register *r; unsigned int data_offset = 0; @@ -375,13 +379,19 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size) /* * Find the PCI dev matching the address, which for hwdom also requires - * consulting DomXEN. Passthrough everything that's not trapped. + * consulting DomXEN. Passthrough everything that's not trapped. + * If this is hwdom and the device is assigned to dom_xen, acquiring hwdom's + * pci_lock is sufficient. */ + read_lock(&d->pci_lock); pdev = pci_get_pdev(d, sbdf); if ( !pdev && is_hardware_domain(d) ) pdev = pci_get_pdev(dom_xen, sbdf); if ( !pdev || !pdev->vpci ) + { + read_unlock(&d->pci_lock); return vpci_read_hw(sbdf, reg, size); + } spin_lock(&pdev->vpci->lock); @@ -428,6 +438,7 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size) ASSERT(data_offset < size); } spin_unlock(&pdev->vpci->lock); + read_unlock(&d->pci_lock); if ( data_offset < size ) { @@ -470,7 +481,7 @@ static void vpci_write_helper(const struct pci_dev *pdev, void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, uint32_t data) { - const struct domain *d = current->domain; + struct domain *d = current->domain; const struct pci_dev *pdev; const struct vpci_register *r; unsigned int data_offset = 0; @@ -483,8 +494,14 @@ void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, /* * Find the PCI dev matching the address, which for hwdom also requires - * consulting DomXEN. Passthrough everything that's not trapped. + * consulting DomXEN. Passthrough everything that's not trapped. + * If this is hwdom and the device is assigned to dom_xen, acquiring hwdom's + * pci_lock is sufficient. + * + * TODO: We need to take pci_locks in exclusive mode only if we + * are modifying BARs, so there is a room for improvement. */ + write_lock(&d->pci_lock); pdev = pci_get_pdev(d, sbdf); if ( !pdev && is_hardware_domain(d) ) pdev = pci_get_pdev(dom_xen, sbdf); @@ -493,6 +510,8 @@ void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, /* Ignore writes to read-only devices, which have no ->vpci. */ const unsigned long *ro_map = pci_get_ro_map(sbdf.seg); + write_unlock(&d->pci_lock); + if ( !ro_map || !test_bit(sbdf.bdf, ro_map) ) vpci_write_hw(sbdf, reg, size, data); return; @@ -534,6 +553,7 @@ void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, ASSERT(data_offset < size); } spin_unlock(&pdev->vpci->lock); + write_unlock(&d->pci_lock); if ( data_offset < size ) /* Tailing gap, write the remaining. */ diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 9da91e0e6244..37f5922f3206 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -462,7 +462,8 @@ struct domain #ifdef CONFIG_HAS_PCI struct list_head pdev_list; /* - * pci_lock protects access to pdev_list. + * pci_lock protects access to pdev_list. pci_lock also protects pdev->vpci + * structure from being removed. * * Any user *reading* from pdev_list, or from devices stored in pdev_list, * should hold either pcidevs_lock() or pci_lock in read mode. Optionally, From patchwork Tue Jan 9 21:51:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05884C4707B for ; Tue, 9 Jan 2024 21:52:35 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665013.1035191 (Exim 4.92) (envelope-from ) id 1rNK1K-00087F-Jy; Tue, 09 Jan 2024 21:52:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665013.1035191; Tue, 09 Jan 2024 21:52:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1K-000878-HC; Tue, 09 Jan 2024 21:52:26 +0000 Received: by outflank-mailman (input) for mailman id 665013; Tue, 09 Jan 2024 21:52:25 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1J-0007gG-Ls for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:52:25 +0000 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on20601.outbound.protection.outlook.com [2a01:111:f403:2417::601]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 5ecfc8e2-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:52:23 +0100 (CET) Received: from SJ0PR05CA0083.namprd05.prod.outlook.com (2603:10b6:a03:332::28) by PH0PR12MB8049.namprd12.prod.outlook.com (2603:10b6:510:28f::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.21; Tue, 9 Jan 2024 21:52:20 +0000 Received: from SJ1PEPF00001CE4.namprd03.prod.outlook.com (2603:10b6:a03:332:cafe::4f) by SJ0PR05CA0083.outlook.office365.com (2603:10b6:a03:332::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.15 via Frontend Transport; Tue, 9 Jan 2024 21:52:19 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CE4.mail.protection.outlook.com (10.167.242.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:52:19 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:52:19 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:52:18 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:52:17 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5ecfc8e2-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Q9l3UghIyVCk+1hN3vH0tk526Pob2VuTeo94lsGNFBtDSSwSK7DFc5g9/ol4gtLiZOe1+VqOM18gQpm+4uU5XaljF03RXYzTJJBY8L8FUKo9ofq4duBDKZHA5cfEConNZbdeGD+i9LSjcdgjqVdSoYvrEIFsFqRzseWd579o0gpO/4II82TnU30oOjr9qunayZHXend9D5uKTg4mxbqk0VOIeyAQ9W+Cq9CjEiK7EFT9ANOZCjTlt++3vfpYPFa8r3WPBUUnnlKnfgLDZvKMoCGzkIvMaYpBTcLeTNlZC+JF6Q6bxJgtWt/gfiRINYqDi1MAdeWO6N1DUiHJXimvdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XB9PkT1l9t41YyMel2hU6TA5dMUGiXDLX5RX/vyOjHw=; b=VplYJ5P2tEeLBuOC12g+mizsei1kldMX4XbxIaYezuSKi45cJp6fGLlClfMZf03wY9tJ4crvD9Nhdj/pY08RooYp4e5lFDAzX+kxtplLB5WZZfZncLQnWF2UKRNiBwHVF+9vSylKcZ7r8n3b6GWu6fnESMQ9ymCmXzyGvJ29A0dgv0F/POcJPk8oBbl1Y3I2Ll2Q3i1yf5esdn3lOfc48ZSl8UVgJQeCSK5S36eCoCoOYCMURXQXtarfDlz8i0WI7Vq2ixhuAxTadCoAABVQahqhl/FIwzF7o5fIMUXHuLAbrsrFiX1RnGMiZ6ZDG/2ANYBtOCPAJvBAaJek+wtpGw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XB9PkT1l9t41YyMel2hU6TA5dMUGiXDLX5RX/vyOjHw=; b=AJxgA/DpUp5i2xH+4coEsrkxA9s2y2wPhbWPM5vqekBj9HT4LRhxHl03E5B2WLJjoATaW9qDUp4wp+eQ7cOqttz+V5t+Wp/HEhfxjTBwul2m+LDDPQIt2kLFqJyPljeqsULfr7gqErY3K51F02KoKUJlANgLJt6w2MRFC9lfP+4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , =?utf-8?q?Ro?= =?utf-8?q?ger_Pau_Monn=C3=A9?= , "Volodymyr Babchuk" , Stewart Hildebrand Subject: [PATCH v12 02/15] vpci: restrict unhandled read/write operations for guests Date: Tue, 9 Jan 2024 16:51:17 -0500 Message-ID: <20240109215145.430207-3-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE4:EE_|PH0PR12MB8049:EE_ X-MS-Office365-Filtering-Correlation-Id: ea1f000d-31b2-46cc-7f96-08dc115d40ec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TweVXBUv8JtOkDCyh0xJ7XapFlUQKNLX26/pESydd7yWJocdiF3Ca0vuU+NRApmXIjsXAPAYj1VW94zwwLdZEiZfg4R4x6n2d4gqbDNGom6exdLuKRt3pOkrPPKVh/l7nv/ePME1xYnCilo+PWjinCCzABcgH5koivVYAFiBgaBBm8B/95YOA3qCs+iZVhI/UrNavV5/YMs3Jok53NInh9lFzE1f1E86cbVkESeyjYWR7CiTThqYqJhLRI90gZY0wi1cgITdr8Xj6x8KcxDcZUIc6iYon1lpTyw5iuW5EriwbepEasNVOlAYkdkKqRHTIgOcjtb+XvRRtOEDnIRD49DTdB40JgojdnOh2NweuEm66dRK1P36AnKGYuPZAKBndWIPRnmjXhcFQZGzsb9i7/ms10u8Rbpy3oXyyI+KXtHZRZn8KTOut+132fzUtnSIZtyeuCD4IG+Ty6Gt+bmckWLbB8hUnqJC4SvHO9XWdbEttYvesHaFJNyroREhcyBIl2TrONIMCwmqcWt5A0vG1ockRkuFc/epOCgEYMqLxH1O+0bT2AFtKu/t4aYGTYL/yF5LqRnIL6FIhXCqhAL3/UidCNywjq/OKwQmrnQVmKjgO0pkuliZuTTBfzcMyqg/KJQQlM5UoYwQZ0Anvotf7c44ng+6BZ5OyQ8McqbZOv3QBrRKQ21VGn3Q6vwSbKjzf7Mp4p3AuyDQo45kfpzsTPX+ZSb9lti84rb9YXg4/HE5DIKQ3tsSgVZV5gWwGjcRtXBExqN3xnHwSMdE+OcFGQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(39860400002)(136003)(346002)(230922051799003)(451199024)(64100799003)(186009)(1800799012)(82310400011)(40470700004)(36840700001)(46966006)(36860700001)(478600001)(82740400003)(47076005)(40460700003)(40480700001)(81166007)(356005)(83380400001)(426003)(336012)(8676002)(26005)(2616005)(2906002)(316002)(5660300002)(44832011)(54906003)(8936002)(6916009)(36756003)(70206006)(86362001)(1076003)(4326008)(70586007)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:52:19.7545 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea1f000d-31b2-46cc-7f96-08dc115d40ec X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8049 From: Oleksandr Andrushchenko A guest would be able to read and write those registers which are not emulated and have no respective vPCI handlers, so it will be possible for it to access the hardware directly. In order to prevent a guest from reads and writes from/to the unhandled registers make sure only hardware domain can access the hardware directly and restrict guests from doing so. Suggested-by: Roger Pau Monné Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Reviewed-by: Roger Pau Monné Signed-off-by: Stewart Hildebrand --- Since v9: - removed stray formatting change - added Roger's R-b tag Since v6: - do not use is_hwdom parameter for vpci_{read|write}_hw and use current->domain internally - update commit message New in v6 --- xen/drivers/vpci/vpci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index a1a004460491..e98693e1dc3e 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -268,6 +268,10 @@ static uint32_t vpci_read_hw(pci_sbdf_t sbdf, unsigned int reg, { uint32_t data; + /* Guest domains are not allowed to read real hardware. */ + if ( !is_hardware_domain(current->domain) ) + return ~(uint32_t)0; + switch ( size ) { case 4: @@ -311,6 +315,10 @@ static uint32_t vpci_read_hw(pci_sbdf_t sbdf, unsigned int reg, static void vpci_write_hw(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, uint32_t data) { + /* Guest domains are not allowed to write real hardware. */ + if ( !is_hardware_domain(current->domain) ) + return; + switch ( size ) { case 4: From patchwork Tue Jan 9 21:51:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5C42C4706C for ; Tue, 9 Jan 2024 21:52:51 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665018.1035201 (Exim 4.92) (envelope-from ) id 1rNK1a-0000Kt-TW; Tue, 09 Jan 2024 21:52:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665018.1035201; Tue, 09 Jan 2024 21:52:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1a-0000Kk-Qj; Tue, 09 Jan 2024 21:52:42 +0000 Received: by outflank-mailman (input) for mailman id 665018; Tue, 09 Jan 2024 21:52:41 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1Z-0007gG-H2 for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:52:41 +0000 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2061d.outbound.protection.outlook.com [2a01:111:f400:7e88::61d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 67b647c9-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:52:39 +0100 (CET) Received: from BYAPR07CA0038.namprd07.prod.outlook.com (2603:10b6:a03:60::15) by IA1PR12MB8222.namprd12.prod.outlook.com (2603:10b6:208:3f2::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.21; Tue, 9 Jan 2024 21:52:32 +0000 Received: from SJ1PEPF00001CEB.namprd03.prod.outlook.com (2603:10b6:a03:60:cafe::76) by BYAPR07CA0038.outlook.office365.com (2603:10b6:a03:60::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23 via Frontend Transport; Tue, 9 Jan 2024 21:52:32 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CEB.mail.protection.outlook.com (10.167.242.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:52:31 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:52:31 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Tue, 9 Jan 2024 13:52:30 -0800 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:52:29 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 67b647c9-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fPbIe4AGfLg5H0PbZGcMsjYQlGEej/LE1fqXDyhwi7toYFEj7KYD49a0/IqrxKH60x4CuikZhw9PVCTs1F2Bg7lbqEyqy2UCfeHyx/6XX59RwmNXjNJZtS4am8G/UF2XBFCwc2JJ+KlqzsQ2begBdo38JuDQUzPPVPZ9WelEx3VQQIfVe0anhMwCANcwk5MEf+J2KrLpt/2Jo/slg7sZB3ENwLw5U+fyESTciZre4avZtpQS8+NHUDIIXgsvOlqwPSWhsMefADQwDlTzZOPIAM7/WnSUXb9kXE5zeoxA8g5LDkFU7orRTkEHI7WJj3G3BMGbCwxIpmAOzl3x1Amg/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=E94DHi+8iv4ojBdqEJ1iMS9iLwhVWhZwG3WSVolNNZs=; b=TJKuLxN/j36qbc5UEdXNe7W1jlepvl+EmE6BLK/Z9lhgJ1umW8m6pxtERrTmn3v6Xn6QxnzTUIP7x1DBplWedEc0/U2m8X/c8/orHCOxaa47pRr6gsy/8657rMvkbXjLVXmD5BqZCVSELb9LEiXwDY0/saRbjHB8wx2N2XKw5b0fAJXVJvAcOVp/tgs4RN6hnUtjYKHUnxFLMStCbLIdWqVXTyijAQyGZONGq9Qux/QEq+WCo5LVEk6MCjdubte0oWe7CSsUFyEtHJi8xuSrBLsPWxy7YMkmXSV1lKvHjXXZbFYQWOar+4KUgrMr8PLPb7tbNaa8N2J4HoyoueCwCw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=E94DHi+8iv4ojBdqEJ1iMS9iLwhVWhZwG3WSVolNNZs=; b=voZTB7MskqiJBx8TjC9BHBKzn/J+EeCWUYSlFtt9GULzDleqPMtPSD55PxNRdco7NaAGrN22wwHdeDPC9gplRFgMYi7llkBLLpqJnkX1oMUYNYLvcuXfxA5XzFWckesDRHwUGAo/YJ35DA4zT/2zRCM2FrGttKN1dWDn7Q+Oe7A= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , Jan Beulich , Paul Durrant , =?utf-8?q?Rog?= =?utf-8?q?er_Pau_Monn=C3=A9?= , "Volodymyr Babchuk" , Stewart Hildebrand Subject: [PATCH v12 03/15] vpci: add hooks for PCI device assign/de-assign Date: Tue, 9 Jan 2024 16:51:18 -0500 Message-ID: <20240109215145.430207-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|IA1PR12MB8222:EE_ X-MS-Office365-Filtering-Correlation-Id: c8a76ff7-9028-4648-a64c-08dc115d47fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7T229zm9TmGhKkB5r1olrQAAAYXaH9dfzplmQvd/w9VYONGVkJp9z3WF+JellbLR37bz/rOuXkqtcJ9OXMt0HwmqFoJaxLmW+g7AdIpAB3pKJ66SHWAJDEq0Y8MR0G5mbkzHattZFH4bvxj7T/gPmX430Bc6wDZ9lwTfycZodnSHnUsWbhdFEEeF+eXJUZ3YI8ngYANvtJ6H5Ybs+ZtQghrSnYcQCKnv7LTbX16iVN2V7GOseNXPqcUrYYQ4JX6aXK6xn2vVyv3Uk6E7Te37tTOM9LVeaDVUSNy/j7UDVzhM2RAlHA3FoAkjAckecRoyw/8ZVR/YkXDk5TnJ9RYVORjcqXOfcQ4aFEKe/X/Y35jLXpEbuD3yMqzxEslugV0kNeDTnMU7U9N9UANB+6ZpDJI9KNYwNmxaU2TKb+BoEQ0+z8Tpy5kj82aZz9NwMXJt7EPfiQe4LWqTX+64mbrSlxi2j9LPnihsxNg8IorqKri+GiSDBmltQOincMFOFjT8YDQuu6dBN/4tuR8yV+Leobvx7sfSx+gJvrKe/CqKfay96RHlEgYH8Mb9PdIimqw+3NnAhLSmwHxHMb2aepuJxx6Nds4w6Ykyzr9J0BpKXuTbjMv4cS5v4VEm67gA+Bp0BfvMFLM9gZq3YmZDGnHOjSS4OvrjdYTYRUfl6pzjLxZFEbVKNQgkhBpruaXtZNRKghGJHP5+XG5jPwyi8wvDe88PPVfZliayOE1t5Mt1fDAByNAzT72a3dOjf+0BLonUvlRxgSxSytDwyhZT3XB2iRp2OFlofmnAdeYj45CNYTPqx8JcYa9jXmqazGi7hRGa X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(136003)(376002)(396003)(230922051799003)(230273577357003)(230173577357003)(1800799012)(82310400011)(186009)(451199024)(64100799003)(36840700001)(46966006)(40470700004)(36860700001)(47076005)(2906002)(2616005)(70586007)(1076003)(70206006)(41300700001)(86362001)(40480700001)(26005)(40460700003)(36756003)(82740400003)(356005)(81166007)(5660300002)(54906003)(316002)(426003)(336012)(6666004)(4326008)(44832011)(6916009)(478600001)(83380400001)(8936002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:52:31.5822 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8a76ff7-9028-4648-a64c-08dc115d47fb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8222 From: Oleksandr Andrushchenko When a PCI device gets assigned/de-assigned we need to initialize/de-initialize vPCI state for the device. Also, rename vpci_add_handlers() to vpci_assign_device() and vpci_remove_device() to vpci_deassign_device() to better reflect role of the functions. Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Reviewed-by: Roger Pau Monné Signed-off-by: Stewart Hildebrand Acked-by: Jan Beulich --- In v12: - Add Roger's R-b - Clean up comment in xen/include/xen/vpci.h - Add comment in xen/drivers/passthrough/pci.c:deassign_device() to clarify vpci_assign_device() call In v11: - Call vpci_assign_device() in "deassign_device" if IOMMU call "reassign_device" was successful. In v10: - removed HAS_VPCI_GUEST_SUPPORT checks - HAS_VPCI_GUEST_SUPPORT config option (in Kconfig) as it is not used anywhere In v9: - removed previous vpci_[de]assign_device function and renamed existing handlers - dropped attempts to handle errors in assign_device() function - do not call vpci_assign_device for dom_io - use d instead of pdev->domain - use IS_ENABLED macro In v8: - removed vpci_deassign_device In v6: - do not pass struct domain to vpci_{assign|deassign}_device as pdev->domain can be used - do not leave the device assigned (pdev->domain == new domain) in case vpci_assign_device fails: try to de-assign and if this also fails, then crash the domain In v5: - do not split code into run_vpci_init - do not check for is_system_domain in vpci_{de}assign_device - do not use vpci_remove_device_handlers_locked and re-allocate pdev->vpci completely - make vpci_deassign_device void In v4: - de-assign vPCI from the previous domain on device assignment - do not remove handlers in vpci_assign_device as those must not exist at that point In v3: - remove toolstack roll-back description from the commit message as error are to be handled with proper cleanup in Xen itself - remove __must_check - remove redundant rc check while assigning devices - fix redundant CONFIG_HAS_VPCI check for CONFIG_HAS_VPCI_GUEST_SUPPORT - use REGISTER_VPCI_INIT machinery to run required steps on device init/assign: add run_vpci_init helper In v2: - define CONFIG_HAS_VPCI_GUEST_SUPPORT so dead code is not compiled for x86 In v1: - constify struct pci_dev where possible - do not open code is_system_domain() - extended the commit message --- xen/drivers/passthrough/pci.c | 25 +++++++++++++++++++++---- xen/drivers/vpci/header.c | 2 +- xen/drivers/vpci/vpci.c | 6 +++--- xen/include/xen/vpci.h | 10 +++++----- 4 files changed, 30 insertions(+), 13 deletions(-) diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 3a973324bca1..a902de6a8693 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -755,7 +755,7 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, * For devices not discovered by Xen during boot, add vPCI handlers * when Dom0 first informs Xen about such devices. */ - ret = vpci_add_handlers(pdev); + ret = vpci_assign_device(pdev); if ( ret ) { list_del(&pdev->domain_list); @@ -769,7 +769,7 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, if ( ret ) { write_lock(&hardware_domain->pci_lock); - vpci_remove_device(pdev); + vpci_deassign_device(pdev); list_del(&pdev->domain_list); write_unlock(&hardware_domain->pci_lock); pdev->domain = NULL; @@ -817,7 +817,7 @@ int pci_remove_device(u16 seg, u8 bus, u8 devfn) list_for_each_entry ( pdev, &pseg->alldevs_list, alldevs_list ) if ( pdev->bus == bus && pdev->devfn == devfn ) { - vpci_remove_device(pdev); + vpci_deassign_device(pdev); pci_cleanup_msi(pdev); ret = iommu_remove_device(pdev); if ( pdev->domain ) @@ -875,6 +875,10 @@ static int deassign_device(struct domain *d, uint16_t seg, uint8_t bus, goto out; } + write_lock(&d->pci_lock); + vpci_deassign_device(pdev); + write_unlock(&d->pci_lock); + devfn = pdev->devfn; ret = iommu_call(hd->platform_ops, reassign_device, d, target, devfn, pci_to_dev(pdev)); @@ -886,6 +890,11 @@ static int deassign_device(struct domain *d, uint16_t seg, uint8_t bus, pdev->fault.count = 0; + write_lock(&target->pci_lock); + /* Re-assign back to hardware_domain */ + ret = vpci_assign_device(pdev); + write_unlock(&target->pci_lock); + out: if ( ret ) printk(XENLOG_G_ERR "%pd: deassign (%pp) failed (%d)\n", @@ -1146,7 +1155,7 @@ static void __hwdom_init setup_one_hwdom_device(const struct setup_hwdom *ctxt, PCI_SLOT(devfn) == PCI_SLOT(pdev->devfn) ); write_lock(&ctxt->d->pci_lock); - err = vpci_add_handlers(pdev); + err = vpci_assign_device(pdev); write_unlock(&ctxt->d->pci_lock); if ( err ) printk(XENLOG_ERR "setup of vPCI for d%d failed: %d\n", @@ -1476,6 +1485,10 @@ static int assign_device(struct domain *d, u16 seg, u8 bus, u8 devfn, u32 flag) if ( pdev->broken && d != hardware_domain && d != dom_io ) goto done; + write_lock(&pdev->domain->pci_lock); + vpci_deassign_device(pdev); + write_unlock(&pdev->domain->pci_lock); + rc = pdev_msix_assign(d, pdev); if ( rc ) goto done; @@ -1502,6 +1515,10 @@ static int assign_device(struct domain *d, u16 seg, u8 bus, u8 devfn, u32 flag) pci_to_dev(pdev), flag); } + write_lock(&d->pci_lock); + rc = vpci_assign_device(pdev); + write_unlock(&d->pci_lock); + done: if ( rc ) printk(XENLOG_G_WARNING "%pd: assign (%pp) failed (%d)\n", diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 8f5850b8cf6d..2f2d98ada012 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -191,7 +191,7 @@ bool vpci_process_pending(struct vcpu *v) * killed in order to avoid leaking stale p2m mappings on * failure. */ - vpci_remove_device(v->vpci.pdev); + vpci_deassign_device(v->vpci.pdev); write_unlock(&v->domain->pci_lock); } diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index e98693e1dc3e..42eac85106a3 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -40,7 +40,7 @@ extern vpci_register_init_t *const __start_vpci_array[]; extern vpci_register_init_t *const __end_vpci_array[]; #define NUM_VPCI_INIT (__end_vpci_array - __start_vpci_array) -void vpci_remove_device(struct pci_dev *pdev) +void vpci_deassign_device(struct pci_dev *pdev) { ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); @@ -73,7 +73,7 @@ void vpci_remove_device(struct pci_dev *pdev) pdev->vpci = NULL; } -int vpci_add_handlers(struct pci_dev *pdev) +int vpci_assign_device(struct pci_dev *pdev) { unsigned int i; const unsigned long *ro_map; @@ -107,7 +107,7 @@ int vpci_add_handlers(struct pci_dev *pdev) } if ( rc ) - vpci_remove_device(pdev); + vpci_deassign_device(pdev); return rc; } diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index d20c301a3db3..99fe76f08ace 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -25,11 +25,11 @@ typedef int vpci_register_init_t(struct pci_dev *dev); static vpci_register_init_t *const x##_entry \ __used_section(".data.vpci." p) = x -/* Add vPCI handlers to device. */ -int __must_check vpci_add_handlers(struct pci_dev *pdev); +/* Assign vPCI to device by adding handlers. */ +int __must_check vpci_assign_device(struct pci_dev *pdev); /* Remove all handlers and free vpci related structures. */ -void vpci_remove_device(struct pci_dev *pdev); +void vpci_deassign_device(struct pci_dev *pdev); /* Add/remove a register handler. */ int __must_check vpci_add_register_mask(struct vpci *vpci, @@ -255,12 +255,12 @@ bool vpci_ecam_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int len, #else /* !CONFIG_HAS_VPCI */ struct vpci_vcpu {}; -static inline int vpci_add_handlers(struct pci_dev *pdev) +static inline int vpci_assign_device(struct pci_dev *pdev) { return 0; } -static inline void vpci_remove_device(struct pci_dev *pdev) { } +static inline void vpci_deassign_device(struct pci_dev *pdev) { } static inline void vpci_dump_msi(void) { } From patchwork Tue Jan 9 21:51:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6F9BC4707B for ; Tue, 9 Jan 2024 21:53:04 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665022.1035211 (Exim 4.92) (envelope-from ) id 1rNK1n-0000nO-6b; Tue, 09 Jan 2024 21:52:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665022.1035211; Tue, 09 Jan 2024 21:52:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1n-0000nC-2z; Tue, 09 Jan 2024 21:52:55 +0000 Received: by outflank-mailman (input) for mailman id 665022; Tue, 09 Jan 2024 21:52:53 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1l-0007gG-Q1 for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:52:53 +0000 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on20600.outbound.protection.outlook.com [2a01:111:f403:2009::600]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 6ef8d12a-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:52:51 +0100 (CET) Received: from BYAPR07CA0040.namprd07.prod.outlook.com (2603:10b6:a03:60::17) by CY5PR12MB6060.namprd12.prod.outlook.com (2603:10b6:930:2f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:52:48 +0000 Received: from SJ1PEPF00001CEB.namprd03.prod.outlook.com (2603:10b6:a03:60:cafe::35) by BYAPR07CA0040.outlook.office365.com (2603:10b6:a03:60::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23 via Frontend Transport; Tue, 9 Jan 2024 21:52:48 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CEB.mail.protection.outlook.com (10.167.242.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:52:48 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:52:47 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Tue, 9 Jan 2024 13:52:47 -0800 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:52:41 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6ef8d12a-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Y+5HlEFy3MHOeNhPCqMISwTSFG+joYrrsH3bAScNRWY2tK7knWBpdY85nUn5RKi/IxdYcIlE+uvcsRdoj0F3pFGYL30obtjwFlCFyI3zT5lgaUuFO7w9h3JNYcn1pNRclIP76BFMgQ/6jCIXqxecVpvniLC5iT6JYty5NQ2daI/cXllcDsm6CYgU2CUjg3HiYGUrWF/rHl0Zu4e7l67w7ZXdFApB0brBIz5Oq5ZkE/fnfnJLSngxgFE4pP6vqPItRX8ET9ZpMIHEaYphpBwVCKOy4niTJtINxm3sV2eVItyyXrKsZa9lY3RyWOhcuOpq8xyMYQFweid+3FNGyC0QpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xyiyI3xsKrX/cnHhNKfE69AhVBubvl5XKQMwzn7dWtQ=; b=oDqZs4HAfGnLUBIiU8+mlX3jy8LMVYynhTEqpfbNoJbfftZk0AIZLa2ypplgqxmBFXCzKbyedbjBfKy2xedPA28A4JxHn+DHDQZmbB+zj2IcONFZaxHKUp08difWJILrV1oa9aEGP1/e8i+HHdqKbUfVA4v313kTt/7oWW5FnERIi5Oz78tTFPiNlI9rN4eN/BhF7QbatOYnIf9r8D60OFcr9SO02D9XGKzEeTajr+7AbBm+LegfcvYUaOsO+Esurl7s6/8HQs+WJn60kXq1WpKX/DO3vvK6ZsRyMm9RlCtu1DXxXcNFxYKvm7UDLl2bWaWBRMv07ByZrUvyB2GFxg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xyiyI3xsKrX/cnHhNKfE69AhVBubvl5XKQMwzn7dWtQ=; b=u25+q2Rm6peMsIxRMQfyGhyvoinGKCFhRHvZsGRVcZkwhp0d2A4t5zx4+j8vBGBTUqsirq/OvH67ANWHR80sGT+JphmEKxLYpweVqIJr69VYluA0kJ8QR4Nv2T4+bpSIRyF+EWXd47ZCsBkJvUkiYgG1YiTBUlb/LBrC3BjMecQ= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Volodymyr Babchuk , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= , "Volodymyr Babchuk" , Stewart Hildebrand Subject: [PATCH v12 04/15] vpci/header: rework exit path in init_header() Date: Tue, 9 Jan 2024 16:51:19 -0500 Message-ID: <20240109215145.430207-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|CY5PR12MB6060:EE_ X-MS-Office365-Filtering-Correlation-Id: 2dade6b8-1008-45d0-2504-08dc115d5214 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VilKMBb0cRVOBScucQf2T6cJBYRyCR89ZC7Dhbn3mZK9wbyiVcfTZyX5whMr5aGUyrKUoVMYYEScDwUKgLv57Ivnw0U8HpOfdCAMEr+weooOF9IVxRlVISaWT7bnF+nPsgnry2DdLSlH5bRQtVuJ7PDEmLgjpQLoSlbC/gMqC+4jNyQCHDfI7wBGeA6Zep+8TllYkRiRl2ktsSze0N8SPElq3sBdiMWjqHzLiUEH1d6NaXicVxrb5J0GoFKOnyys0rf5MuAoW+Uf4YLQfsEFHaSIp7Vev4F1Hvvbrmu+T0rj3PWwM2MLbv+Qzq4FM5fWHnIhOyW464gQrvGPKoIUnEZjghJH5zZaJ+W6TpKRcDGtCgR5O9vwwBQSphAv4nyOwVOzz2G5tCKUNi80he49IP/qNaqEoRZmpc7aMIDFpwUiPv0aQGryVEY3agsJ2FFe7XjtpV1ylFqmdyx0aYpO0WLRejNW4/dSETAAzA11NMIWNm86tnbj1YVpqagOAI6v7Q6LmdUsYxJ1hm+Z4mGkJWipswtcKsU0J13BPpdRTkdPFC3atNJeenWQYOthTXWj5mzhDvvkEjrsekibmAKfkgO3cA570cS/yToOXauG8e6irlvnMvYBvxhqM0stHikPbU7xHmNCyYD48vPw6zF7PiaIBD0tNwEI+kZl52BpJj9jc+i5I+Y/m9SnuNAuK/0c+tE00QikhBVIT/88AnTuZusl0Hta6sp5GCOoyt/j2rfa1NR0EsQ2loISKIYnCPI9vjzTvDHI5QFVHq+8zIx7Ng== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(396003)(136003)(39860400002)(230922051799003)(82310400011)(64100799003)(186009)(451199024)(1800799012)(46966006)(36840700001)(40470700004)(40480700001)(40460700003)(2906002)(478600001)(36860700001)(5660300002)(6666004)(81166007)(4326008)(44832011)(356005)(41300700001)(8936002)(316002)(70206006)(70586007)(54906003)(36756003)(6916009)(8676002)(2616005)(86362001)(426003)(26005)(336012)(1076003)(83380400001)(47076005)(82740400003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:52:48.5200 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2dade6b8-1008-45d0-2504-08dc115d5214 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6060 From: Volodymyr Babchuk Introduce "fail" label in init_header() function to have the centralized error return path. This is the pre-requirement for the future changes in this function. This patch does not introduce functional changes. Suggested-by: Roger Pau Monné Signed-off-by: Volodymyr Babchuk Acked-by: Roger Pau Monné Signed-off-by: Stewart Hildebrand --- In v12: - s/init_bars/init_header/ - Re-order tags - Fixup scissors line In v11: - Do not remove empty line between "goto fail;" and "continue;" In v10: - Added Roger's A-b tag. In v9: - New in v9 --- xen/drivers/vpci/header.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 2f2d98ada012..803fe4bb99a6 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -656,10 +656,7 @@ static int cf_check init_header(struct pci_dev *pdev) rc = vpci_add_register(pdev->vpci, vpci_hw_read32, bar_write, reg, 4, &bars[i]); if ( rc ) - { - pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); - return rc; - } + goto fail; continue; } @@ -679,10 +676,7 @@ static int cf_check init_header(struct pci_dev *pdev) rc = pci_size_mem_bar(pdev->sbdf, reg, &addr, &size, (i == num_bars - 1) ? PCI_BAR_LAST : 0); if ( rc < 0 ) - { - pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); - return rc; - } + goto fail; if ( size == 0 ) { @@ -697,10 +691,7 @@ static int cf_check init_header(struct pci_dev *pdev) rc = vpci_add_register(pdev->vpci, vpci_hw_read32, bar_write, reg, 4, &bars[i]); if ( rc ) - { - pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); - return rc; - } + goto fail; } /* Check expansion ROM. */ @@ -722,6 +713,10 @@ static int cf_check init_header(struct pci_dev *pdev) } return (cmd & PCI_COMMAND_MEMORY) ? modify_bars(pdev, cmd, false) : 0; + + fail: + pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); + return rc; } REGISTER_VPCI_INIT(init_header, VPCI_PRIORITY_MIDDLE); From patchwork Tue Jan 9 21:51:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CC7CC4707B for ; Tue, 9 Jan 2024 21:53:14 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665026.1035221 (Exim 4.92) (envelope-from ) id 1rNK1x-0001M6-K4; Tue, 09 Jan 2024 21:53:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665026.1035221; Tue, 09 Jan 2024 21:53:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1x-0001Lu-Gs; Tue, 09 Jan 2024 21:53:05 +0000 Received: by outflank-mailman (input) for mailman id 665026; Tue, 09 Jan 2024 21:53:04 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK1w-0008W6-O8 for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:53:04 +0000 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on20607.outbound.protection.outlook.com [2a01:111:f400:fe5b::607]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 76bf668c-af39-11ee-98ef-6d05b1d4d9a1; Tue, 09 Jan 2024 22:53:03 +0100 (CET) Received: from MN2PR08CA0030.namprd08.prod.outlook.com (2603:10b6:208:239::35) by SJ0PR12MB5488.namprd12.prod.outlook.com (2603:10b6:a03:3ad::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:53:00 +0000 Received: from BL6PEPF0001AB50.namprd04.prod.outlook.com (2603:10b6:208:239:cafe::48) by MN2PR08CA0030.outlook.office365.com (2603:10b6:208:239::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.17 via Frontend Transport; Tue, 9 Jan 2024 21:52:59 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB50.mail.protection.outlook.com (10.167.242.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:52:59 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:52:58 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:52:58 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:52:57 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 76bf668c-af39-11ee-98ef-6d05b1d4d9a1 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=N5b5Fw/AzErrrlM6vfG/PLd918GfdvQeL+oaLT0/vPm8IhDcJG4LbnUMDhHilMmZUYwj6ufxEyF8EBmpJVXoq88Y//w/p3xYjCT7a9FkJRL2Gy60hpPbN7uoalPnoNlqlFM2AXVXrliybOApBMTl2slkIA+5rOVCX5DxFjhb9DdW24w/rPN/O72COydeGmpUf3kPQldKiue+Pox+69mipcvkYxRzlKAp2WYtzs8FmOyD9j8oEupg9+sTWMCMnDoYhLwcEGVCRRXVT8RBekL2KspuDaBe556qpBXbHiuiRWuTqcP2VXlI+Ruku+7fR/J7mQcx1OzLO6R/oZwIPK27GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3fv9DTE0P0KLmwQzPHqaJ/yxioeZbVVsJLRZmvugJrA=; b=MPvT46Ugv/DKPNl4xfpzhu7LPSsPFaMmkRfCXucOpNaNJaRaLQsPDuD4bWa5xXWFxRMJV3Y8rVxGOkjOHdJIew0gkR3bP/xjsmmHQ1ksy+r6hbzVnHjnQMwk4FstEEjgNmeGvrMWMWQQ1J78HmmrfPSlY3c5xI4TrjcYZzuzU6SA0OhiaUNEbYK/Hh7bak0An4gN7CJGQJY5whOCfZMFoPdpktXXgaL4ectGf2xMK86hEWAGA6zQAQf8vZe4k3+oUXOiw/PN8V+itzy8yqfaYgGKQDrcadw3VFpB9mEbPjMALW30ngwf3zVCL8bwOgUX44FOTrQdtthqS+CN3p4clQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3fv9DTE0P0KLmwQzPHqaJ/yxioeZbVVsJLRZmvugJrA=; b=GTebfnXm9F59ch75uYteM5zIK14PU1hQ1aJW/96Khljb5c2kC1T/QxqCdItMfB7KLSUBRyqXwZqLOu9UHNvJ4RHjiHTVWOa4iuZ0LhQ7bVf4e0/K48iYOwi/zX4vsrMdJ+ehUcU3YnsBOMi522F2FWpDLq6LNNRY23f4G3i+/Xg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , =?utf-8?q?Ro?= =?utf-8?q?ger_Pau_Monn=C3=A9?= , "Volodymyr Babchuk" , Stewart Hildebrand Subject: [PATCH v12 05/15] vpci/header: implement guest BAR register handlers Date: Tue, 9 Jan 2024 16:51:20 -0500 Message-ID: <20240109215145.430207-6-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB50:EE_|SJ0PR12MB5488:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c3fbd5e-ce19-4d4f-b775-08dc115d5879 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IcUbXmpu/TxDo7CJ/ZS/lEIhzs5pB8Y5pgmNQGKtJL0taHcLfSw1qRxaCP9EQP3YgWFonB3ECZhCAH5dGB1q8upiSfgHAYTe6DuVazXxej0SZULolVdcPQ60JtLWjiWZBSBsvTfNC5+fvTN6wpuZYyhhXEJ7cHXz6RtNh/An5CgfzkMMe3fKLy39DcNzGgX8T/ywkxEo95+TRaGbWk85pFn/rBVW+fRgUCRCTqtIZswIeNtUJ5JFQxgtzGtAAtx93HUTu4aTkmzLaQ/ufJx031Zo2UNa/JJ5eJln2vDUFtCDxbTXyHuDkHYrxLg9d5OFtZ57fFBdme1icsoT57X4vKVYWL0ALECJeH2pD2HqLM1rvUTZrmKC5slwwgQ5dfvQ1blqabOzEDXF/9g2+AKqS9z15dAyBrBUUXMYWtrZ14lIT0BoXIEc9MtP1xyvgO+7T8l9rqjuHs6mNcIW/raIszXVO7Sp70izK+wVk1NGmlInRdXgN+nNj61FSlce9R+XBkD6LzZ4MxFRpNGPTZ43QSvNqruBwtUAyftVtK7aZEVNqoxJAL3PluSbQ3Qm2tgfaoeDXB9D1p2hlCcpGxawtm19JQwJmSZW8PGrItASWVWabjW/lu9WPA58RXHyVlRwzIEjbIiF8VqKfkmzcg2zsyh3y9feM+E6wtlkPJumfWyUj409D0IMsse0t2VfCHCRvxoVJD7hL6SJ8KLwyZ2+N9UpABTOSrWDndmTVwowHHeCbZRRLHqrEhsJYrIhFcvkJcxAokuqQp0BsW6wp54vLWAAjqsR6TbOXpDFXLv9/SbG0RYxhft+S/K4yFHk1V16 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(136003)(39860400002)(346002)(230273577357003)(230173577357003)(230922051799003)(1800799012)(64100799003)(82310400011)(186009)(451199024)(40470700004)(36840700001)(46966006)(40480700001)(40460700003)(83380400001)(316002)(70586007)(41300700001)(356005)(81166007)(82740400003)(86362001)(36756003)(70206006)(36860700001)(47076005)(478600001)(5660300002)(336012)(426003)(1076003)(2616005)(26005)(6666004)(6916009)(2906002)(54906003)(8936002)(44832011)(4326008)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:52:59.3457 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c3fbd5e-ce19-4d4f-b775-08dc115d5879 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB50.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5488 From: Oleksandr Andrushchenko Add relevant vpci register handlers when assigning PCI device to a domain and remove those when de-assigning. This allows having different handlers for different domains, e.g. hwdom and other guests. Emulate guest BAR register values: this allows creating a guest view of the registers and emulates size and properties probe as it is done during PCI device enumeration by the guest. All empty, IO and ROM BARs for guests are emulated by returning 0 on reads and ignoring writes: this BARs are special with this respect as their lower bits have special meaning, so returning default ~0 on read may confuse guest OS. Introduce is_hwdom convenience variable and convert an existing is_hardware_domain() check. Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Reviewed-by: Roger Pau Monné Signed-off-by: Stewart Hildebrand --- In v12: - Add Roger's R-b - Get rid of empty_bar_read, use vpci_read_val instead - Convert an existing is_hardware_domain() check to is_hwdom - Re-indent usage of ternary operator - Use ternary operator to avoid re-indenting expansion ROM block In v11: - Access guest_addr after adjusting for MEM64_HI bar in guest_bar_write() - guest bar handlers renamed and now _mem_ part to denote that they are handling only memory BARs - refuse to update guest BAR address if BAR is enabled In v10: - ull -> ULL to be MISRA-compatbile - Use PAGE_OFFSET() instead of combining with ~PAGE_MASK - Set type of empty bars to VPCI_BAR_EMPTY In v9: - factored-out "fail" label introduction in init_bars() - replaced #ifdef CONFIG_X86 with IS_ENABLED() - do not pass bars[i] to empty_bar_read() handler - store guest's BAR address instead of guests BAR register view Since v6: - unify the writing of the PCI_COMMAND register on the error path into a label - do not introduce bar_ignore_access helper and open code - s/guest_bar_ignore_read/empty_bar_read - update error message in guest_bar_write - only setup empty_bar_read for IO if !x86 Since v5: - make sure that the guest set address has the same page offset as the physical address on the host - remove guest_rom_{read|write} as those just implement the default behaviour of the registers not being handled - adjusted comment for struct vpci.addr field - add guest handlers for BARs which are not handled and will otherwise return ~0 on read and ignore writes. The BARs are special with this respect as their lower bits have special meaning, so returning ~0 doesn't seem to be right Since v4: - updated commit message - s/guest_addr/guest_reg Since v3: - squashed two patches: dynamic add/remove handlers and guest BAR handler implementation - fix guest BAR read of the high part of a 64bit BAR (Roger) - add error handling to vpci_assign_device - s/dom%pd/%pd - blank line before return Since v2: - remove unneeded ifdefs for CONFIG_HAS_VPCI_GUEST_SUPPORT as more code has been eliminated from being built on x86 Since v1: - constify struct pci_dev where possible - do not open code is_system_domain() - simplify some code3. simplify - use gdprintk + error code instead of gprintk - gate vpci_bar_{add|remove}_handlers with CONFIG_HAS_VPCI_GUEST_SUPPORT, so these do not get compiled for x86 - removed unneeded is_system_domain check - re-work guest read/write to be much simpler and do more work on write than read which is expected to be called more frequently - removed one too obvious comment --- xen/drivers/vpci/header.c | 109 +++++++++++++++++++++++++++++++++++--- xen/include/xen/vpci.h | 3 ++ 2 files changed, 106 insertions(+), 6 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 803fe4bb99a6..39e11e141b38 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -478,6 +478,69 @@ static void cf_check bar_write( pci_conf_write32(pdev->sbdf, reg, val); } +static void cf_check guest_mem_bar_write(const struct pci_dev *pdev, + unsigned int reg, uint32_t val, + void *data) +{ + struct vpci_bar *bar = data; + bool hi = false; + uint64_t guest_addr; + + if ( bar->type == VPCI_BAR_MEM64_HI ) + { + ASSERT(reg > PCI_BASE_ADDRESS_0); + bar--; + hi = true; + } + else + { + val &= PCI_BASE_ADDRESS_MEM_MASK; + } + + guest_addr = bar->guest_addr; + guest_addr &= ~(0xffffffffULL << (hi ? 32 : 0)); + guest_addr |= (uint64_t)val << (hi ? 32 : 0); + + /* Allow guest to size BAR correctly */ + guest_addr &= ~(bar->size - 1); + + /* + * Xen only cares whether the BAR is mapped into the p2m, so allow BAR + * writes as long as the BAR is not mapped into the p2m. + */ + if ( bar->enabled ) + { + /* If the value written is the current one avoid printing a warning. */ + if ( guest_addr != bar->guest_addr ) + gprintk(XENLOG_WARNING, + "%pp: ignored guest BAR %zu write while mapped\n", + &pdev->sbdf, bar - pdev->vpci->header.bars + hi); + return; + } + bar->guest_addr = guest_addr; +} + +static uint32_t cf_check guest_mem_bar_read(const struct pci_dev *pdev, + unsigned int reg, void *data) +{ + const struct vpci_bar *bar = data; + uint32_t reg_val; + + if ( bar->type == VPCI_BAR_MEM64_HI ) + { + ASSERT(reg > PCI_BASE_ADDRESS_0); + bar--; + return bar->guest_addr >> 32; + } + + reg_val = bar->guest_addr; + reg_val |= bar->type == VPCI_BAR_MEM32 ? PCI_BASE_ADDRESS_MEM_TYPE_32 : + PCI_BASE_ADDRESS_MEM_TYPE_64; + reg_val |= bar->prefetchable ? PCI_BASE_ADDRESS_MEM_PREFETCH : 0; + + return reg_val; +} + static void cf_check rom_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { @@ -539,6 +602,7 @@ static int cf_check init_header(struct pci_dev *pdev) struct vpci_bar *bars = header->bars; int rc; bool mask_cap_list = false; + bool is_hwdom = is_hardware_domain(pdev->domain); ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); @@ -564,7 +628,7 @@ static int cf_check init_header(struct pci_dev *pdev) if ( rc ) return rc; - if ( !is_hardware_domain(pdev->domain) ) + if ( !is_hwdom ) { if ( pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST ) { @@ -653,8 +717,11 @@ static int cf_check init_header(struct pci_dev *pdev) if ( i && bars[i - 1].type == VPCI_BAR_MEM64_LO ) { bars[i].type = VPCI_BAR_MEM64_HI; - rc = vpci_add_register(pdev->vpci, vpci_hw_read32, bar_write, reg, - 4, &bars[i]); + rc = vpci_add_register(pdev->vpci, + is_hwdom ? vpci_hw_read32 + : guest_mem_bar_read, + is_hwdom ? bar_write : guest_mem_bar_write, + reg, 4, &bars[i]); if ( rc ) goto fail; @@ -665,6 +732,14 @@ static int cf_check init_header(struct pci_dev *pdev) if ( (val & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO ) { bars[i].type = VPCI_BAR_IO; + if ( !IS_ENABLED(CONFIG_X86) && !is_hwdom ) + { + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + reg, 4, (void *)0); + if ( rc ) + goto fail; + } + continue; } if ( (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == @@ -681,6 +756,15 @@ static int cf_check init_header(struct pci_dev *pdev) if ( size == 0 ) { bars[i].type = VPCI_BAR_EMPTY; + + if ( !is_hwdom ) + { + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + reg, 4, (void *)0); + if ( rc ) + goto fail; + } + continue; } @@ -688,14 +772,18 @@ static int cf_check init_header(struct pci_dev *pdev) bars[i].size = size; bars[i].prefetchable = val & PCI_BASE_ADDRESS_MEM_PREFETCH; - rc = vpci_add_register(pdev->vpci, vpci_hw_read32, bar_write, reg, 4, - &bars[i]); + rc = vpci_add_register(pdev->vpci, + is_hwdom ? vpci_hw_read32 : guest_mem_bar_read, + is_hwdom ? bar_write : guest_mem_bar_write, + reg, 4, &bars[i]); if ( rc ) goto fail; } /* Check expansion ROM. */ - rc = pci_size_mem_bar(pdev->sbdf, rom_reg, &addr, &size, PCI_BAR_ROM); + rc = is_hwdom ? pci_size_mem_bar(pdev->sbdf, rom_reg, &addr, &size, + PCI_BAR_ROM) + : 0; if ( rc > 0 && size ) { struct vpci_bar *rom = &header->bars[num_bars]; @@ -711,6 +799,15 @@ static int cf_check init_header(struct pci_dev *pdev) if ( rc ) rom->type = VPCI_BAR_EMPTY; } + else if ( !is_hwdom ) + { + /* TODO: Check expansion ROM, we do not handle ROM for guests for now */ + header->bars[num_bars].type = VPCI_BAR_EMPTY; + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + rom_reg, 4, (void *)0); + if ( rc ) + goto fail; + } return (cmd & PCI_COMMAND_MEMORY) ? modify_bars(pdev, cmd, false) : 0; diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 99fe76f08ace..b0e38a5a1acb 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -87,7 +87,10 @@ struct vpci { struct vpci_header { /* Information about the PCI BARs of this device. */ struct vpci_bar { + /* Physical (host) address. */ uint64_t addr; + /* Guest address. */ + uint64_t guest_addr; uint64_t size; enum { VPCI_BAR_EMPTY, From patchwork Tue Jan 9 21:51:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76F58C4707B for ; Tue, 9 Jan 2024 21:53:28 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665031.1035230 (Exim 4.92) (envelope-from ) id 1rNK2A-0001xg-TX; Tue, 09 Jan 2024 21:53:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665031.1035230; Tue, 09 Jan 2024 21:53:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK2A-0001xZ-Qp; Tue, 09 Jan 2024 21:53:18 +0000 Received: by outflank-mailman (input) for mailman id 665031; Tue, 09 Jan 2024 21:53:17 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK29-0008W6-6W for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:53:17 +0000 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on20600.outbound.protection.outlook.com [2a01:111:f403:2409::600]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 7e6b801e-af39-11ee-98ef-6d05b1d4d9a1; Tue, 09 Jan 2024 22:53:16 +0100 (CET) Received: from BY5PR03CA0025.namprd03.prod.outlook.com (2603:10b6:a03:1e0::35) by SJ0PR12MB7081.namprd12.prod.outlook.com (2603:10b6:a03:4ae::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:53:12 +0000 Received: from SJ1PEPF00001CE5.namprd03.prod.outlook.com (2603:10b6:a03:1e0:cafe::8e) by BY5PR03CA0025.outlook.office365.com (2603:10b6:a03:1e0::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.24 via Frontend Transport; Tue, 9 Jan 2024 21:53:12 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CE5.mail.protection.outlook.com (10.167.242.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:53:12 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:53:12 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:53:11 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:53:09 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7e6b801e-af39-11ee-98ef-6d05b1d4d9a1 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WXTz2Mpvj/QfnORkTyz17SzRJMmmPl9jXvRlwdSdk+v81jVDIsPnV9G234ofXWU6BSM79izfS6//ImHglgJs8rFMSmxJI/uY7kwVV3KI9l5uCCCqWOtk3HmHod57NZvjOdMPskqg9ecA5xoOkGVYVkPmbiNcXYHPsnhFgyu0QeJhH4LjihfcjjPGScgdcyTHMWBxG5M/6Uv7JnOu3nuClhXht25xHKWHm7wJgb6iV2OL3EENMa18ew+cdPO5OTWbOpZT/yopedhj9lax5NpO3iBKIFLr3N1TDuKejMM+z3u+cYJ5u7wcVka795AxiFWMG2LRJEJ0H5H7fVR8/F+3LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tIlYNCEQ+4nfk+sRGPCKjR3ey13meQvjdP5M2lt1W5E=; b=nCtMQHj6MfUf/M2KMlwQlA3qG8FH414UUpmqyV/fFQg+HakhC9qCjLEnDG/dfqVdRT9ZfWsKNzBhAxI9P9Io90TBTAPIvi3wZA3rWLvueFPI3SBWNmG8ZcTwZWHjUKOfA6LZI/uYRxEFZxUX8JOnJQT5YMEbn5CUiKxRtVeGS32OZcU0UIGS4MRIVscKpmj+If/ihdeJoPLnicIgnmgasN5qh/+aeQIX+iCNrG847is3Nh2JotUEJkDZCGQQIVEs/hcgd2qUNHixR2PGWSCp4UhxdCqBs1MHw5c8/UFb9CijpO/UIDw9QxlHhBGzC5Fux3enZGgXfqdSMMwbvp79NA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tIlYNCEQ+4nfk+sRGPCKjR3ey13meQvjdP5M2lt1W5E=; b=pgtpAF1ZosNJ3024LD7SEw7MXSUBKz5aeessqqpYdYVsdWKQn+zKBdIwhuUk/Qn/l5o0qYSq4Hqp7BKHSzVvYxXsj9YrVHQJMyVsJcRMRg+DezXL6/Aw4j4dPQhrh4nnXzl2GaLjslmYwiRL2+cihjI5QTOs9BGAJdpO2ZxLTPI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , Volodymyr Babchuk , Stewart Hildebrand Subject: [PATCH v12 06/15] rangeset: add RANGESETF_no_print flag Date: Tue, 9 Jan 2024 16:51:21 -0500 Message-ID: <20240109215145.430207-7-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE5:EE_|SJ0PR12MB7081:EE_ X-MS-Office365-Filtering-Correlation-Id: 75a7f3bf-8b1a-4200-87c0-08dc115d6077 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rUqNpyN1LLfmUKSPQX70rqqcylRCdeJ6msqMj/6uZlUk+udyT4kHmlWMV14X3qvNSW21UkormSg4qIAEhxGSwe58PE2VPF5xCT+5yvzrRktVawQzQOCwbAhJKWmiGRhJyNAlm6xP29Bei5Dn/QFggWE6OPySXjSCi2wK/CUFCsObM0YcOsQovI2UeRD9EJDEp8xnPib/wg3QOE5UuJG1HPtFf/bzwMDzhgt2nvf/zG4Uz7uBejtO6Xwt5XIYIolWW+Fq8WswmTKc3O3JUTNxgZxrgCf1iVGat1IEqIbUWmigHBSigxDXTJlgdbH02+ywpxWcG+RP4qcH+xkkxR41HsBx3C1Fbuzmw0JB/HS3Xi9YKG9KjTr7WLN6kUpWasNm0wx8r3cCBWqvLdB5ktQyrTw6lrOCnX5GXVnPS6i75klS4sNPkIwBJ+wZFXuslsXcKT35mnSBm749aiDtwWTguf12PnIh5tBFlkgjaA7lVeKuxbPfAHMLkxyeUO2BZ5IKxsKWy9da7P9Fjx7JccS1L59CdRKG1/g0mqDWpfRwYu+62TM8k0OioU12hxHNj0yTvRW8NB+8qJ7o/NvRkGCPAADU1Mxsz88LiDB+H8zp/c9XWtWkbwGszwKM//DMA7c2MRGg1Zv6poXtjn412KaPCdy8qJAd61lRzh/ks8nIktbTnpZ/Q9gl6zX+Mmne/EQEp9avRO0mnjKVIyHgNXJvgY6piNgW57sCv8I5TST0wrFZ9Wr7E1p6Qbb5Z45WrqEuQLcP7lN1r25vPj4KctumwA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(376002)(136003)(346002)(396003)(230922051799003)(1800799012)(186009)(64100799003)(82310400011)(451199024)(36840700001)(40470700004)(46966006)(40460700003)(40480700001)(356005)(41300700001)(36756003)(81166007)(86362001)(36860700001)(2906002)(82740400003)(47076005)(83380400001)(26005)(1076003)(426003)(2616005)(336012)(6666004)(478600001)(70206006)(6916009)(70586007)(316002)(54906003)(8936002)(4326008)(5660300002)(8676002)(44832011)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:53:12.6593 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75a7f3bf-8b1a-4200-87c0-08dc115d6077 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7081 From: Oleksandr Andrushchenko There are range sets which should not be printed, so introduce a flag which allows marking those as such. Implement relevant logic to skip such entries while printing. While at it also simplify the definition of the flags by directly defining those without helpers. Suggested-by: Jan Beulich Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Reviewed-by: Jan Beulich Signed-off-by: Stewart Hildebrand --- Since v5: - comment indentation (Jan) Since v1: - update BUG_ON with new flag - simplify the definition of the flags --- xen/common/rangeset.c | 5 ++++- xen/include/xen/rangeset.h | 5 +++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/xen/common/rangeset.c b/xen/common/rangeset.c index 16a4c3b842e6..0ccd53caac52 100644 --- a/xen/common/rangeset.c +++ b/xen/common/rangeset.c @@ -433,7 +433,7 @@ struct rangeset *rangeset_new( INIT_LIST_HEAD(&r->range_list); r->nr_ranges = -1; - BUG_ON(flags & ~RANGESETF_prettyprint_hex); + BUG_ON(flags & ~(RANGESETF_prettyprint_hex | RANGESETF_no_print)); r->flags = flags; safe_strcpy(r->name, name ?: "(no name)"); @@ -575,6 +575,9 @@ void rangeset_domain_printk( list_for_each_entry ( r, &d->rangesets, rangeset_list ) { + if ( r->flags & RANGESETF_no_print ) + continue; + printk(" "); rangeset_printk(r); printk("\n"); diff --git a/xen/include/xen/rangeset.h b/xen/include/xen/rangeset.h index 8be0722787ed..87bd956962b5 100644 --- a/xen/include/xen/rangeset.h +++ b/xen/include/xen/rangeset.h @@ -49,8 +49,9 @@ void rangeset_limit( /* Flags for passing to rangeset_new(). */ /* Pretty-print range limits in hexadecimal. */ -#define _RANGESETF_prettyprint_hex 0 -#define RANGESETF_prettyprint_hex (1U << _RANGESETF_prettyprint_hex) +#define RANGESETF_prettyprint_hex (1U << 0) + /* Do not print entries marked with this flag. */ +#define RANGESETF_no_print (1U << 1) bool __must_check rangeset_is_empty( const struct rangeset *r); From patchwork Tue Jan 9 21:51:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515416 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24155C4706C for ; Tue, 9 Jan 2024 21:53:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665038.1035240 (Exim 4.92) (envelope-from ) id 1rNK2T-0002e0-5w; Tue, 09 Jan 2024 21:53:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665038.1035240; Tue, 09 Jan 2024 21:53:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK2T-0002dt-3B; Tue, 09 Jan 2024 21:53:37 +0000 Received: by outflank-mailman (input) for mailman id 665038; Tue, 09 Jan 2024 21:53:35 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK2R-0007gG-KF for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:53:35 +0000 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2062c.outbound.protection.outlook.com [2a01:111:f400:7e88::62c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 88364cd0-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:53:33 +0100 (CET) Received: from BY5PR03CA0024.namprd03.prod.outlook.com (2603:10b6:a03:1e0::34) by BL0PR12MB4900.namprd12.prod.outlook.com (2603:10b6:208:1c1::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:53:29 +0000 Received: from SJ1PEPF00001CE5.namprd03.prod.outlook.com (2603:10b6:a03:1e0:cafe::d0) by BY5PR03CA0024.outlook.office365.com (2603:10b6:a03:1e0::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23 via Frontend Transport; Tue, 9 Jan 2024 21:53:29 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CE5.mail.protection.outlook.com (10.167.242.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:53:29 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:53:28 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:53:27 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:53:21 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 88364cd0-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aqAc6GkKdA6GodqTHVzOU9FGo71zLMXNd3B5l8OeO/weuDPdB08WgVusoETSjkC/AG2GMSZTKDml4xkT8Rt52PkAPUyDhDDNsXOnBnCqoTGzwyvrIsuIUMQnOVAr9eHCDkDVEhNOweeVY8zBaVsjNEkWSXi4YAa+U+8L5oomJxfAZF95Xumh8KsqER43p+lEoUUJc8YI0EToN+FizBg96fH0CjH2/eV3IeR84n+CWEQZxVCTDid1whp/mgvUcoAxsLv667uRaRYanNqS1EFnT/8juVITD2BpPqqrx2n9oO2H3pXfPgSORZy9OZ5wYkCdXd4De3t5lPFbZ0x2fgzAYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PqQc6f/gIUwm1XzrHE/xObpB2I0zC8wUwYomXWUX7YU=; b=UgJ/TYSOBt/AMeAlbs08A+/uJR6IB7qtNhTlGLMX+VYv6GbBcn/amZHBHGb9FkAnKiJtqTUG4R1b0niNQwQZY3mXPXI6FWLgzDx5+/SXqEH0MYSseg83ELe0LMSVJV0a82jpB0ikb9aSdU+hdZLYOc81mr0uUILuX2zKLeitsmgbF1dKsIwpp+b9VsPsKJU0ursUYpKbT8ZZo+J/GPQBc84+Kyewuob9P+GblytYCc+8AVkayvuWte0nvHuihriS+Me1maCFY378tvO+GASZLSv+BBEKTrF12vwniyA8NG5U8J1iR+3r7LwsXKtMlVLQd4CWgYSM76uB8UxHykNOAw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PqQc6f/gIUwm1XzrHE/xObpB2I0zC8wUwYomXWUX7YU=; b=XSPc1GoBid0FI/MPj7zulTa9Ah5xyopFnvsg/pCbESnXyfXU7HwGvoaufJFgbF57uOjTcXiRw101O0n269xFVrITlOjkM0eKXkF9WA+O1GYSi0teCQA6tXJNYdIiAC22ZU73zxkRrVTmE++N6RKz3yIwALlICJWFztqNWQnofyo= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Volodymyr Babchuk , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , Volodymyr Babchuk , Stewart Hildebrand Subject: [PATCH v12 07/15] rangeset: add rangeset_purge() function Date: Tue, 9 Jan 2024 16:51:22 -0500 Message-ID: <20240109215145.430207-8-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE5:EE_|BL0PR12MB4900:EE_ X-MS-Office365-Filtering-Correlation-Id: 469cb7ec-29f2-4343-69a9-08dc115d6a35 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q8oMiLfRnHbOKLCfZhqOIxxl8ht/vQuBxOjuWD5VvEKhBXMgmximr6mkE7ffa+TCLBGUu4qEPswvHu208VkUrzDBJwvXS8XogoOUzcMOYqmdbQ7hbtmXXWCIA2PzECyRGSQA93RSnu3C9NJMx45A1w7DXwq5gjOg9FzSgLjfwH1ITtp+0qhOAox/z2R9ERJ0lX13rsBwPqqoVs6BgbZe/0SFD1tn59rgogpyNCXJYwnwNYcl6H4OjsKFvhkoJvB0fZ36VIE/CmJWAJBKXr4XNyYMhqheo02f8zYWbPbIQxyEVRLPTpdiQ0cDu3HLW0vvoiagYOcx8Vum/w01Q3Cy9VQxXaAtM+WcujfR+iWZJcPxhSKGcOzAx3adovA+9nRT+HkH6umh5W+IX0MQXzw3ZeOENwO09E8UGTi3ESqhkkkMI9IlN7ZWbRFR3eBqYNcgdSW8Ep0ink2YQrNtEQo4lixQxozhVxIFbosGIOOo9x0nC0BiAf0hKE0uT/lTrEegQc+edrSfv2Fqph0TvsFM08SPk/7gmrzNLkbVjFhHLhApn16Z0lDdo4Wzp7bt1nVPaBtrPYYuVMJslm5fcxPmfWA2iUF3KCvuR3U6zI7vcu2EThz5hH10uQQRNjTjYgpCoiJKeof0psmbBr/o0RnbiaivLDuoKj/SEQTnoXbNN0dBhuqN6cyaD+9TS5S9vxKtD4JQWl6ohayvGqg+S1S5rSBozzsmKzdLbctShBTYnNcsely9IpeWKEaimayACV94Ui8gBcItggrAYd+V/pDT2A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(136003)(39860400002)(376002)(230922051799003)(451199024)(64100799003)(1800799012)(82310400011)(186009)(40470700004)(36840700001)(46966006)(2906002)(82740400003)(5660300002)(86362001)(41300700001)(81166007)(356005)(36756003)(36860700001)(316002)(54906003)(426003)(336012)(8936002)(8676002)(47076005)(2616005)(26005)(70206006)(40460700003)(70586007)(40480700001)(478600001)(1076003)(6916009)(83380400001)(4326008)(44832011)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:53:29.0033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 469cb7ec-29f2-4343-69a9-08dc115d6a35 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4900 From: Volodymyr Babchuk This function can be used when user wants to remove all rangeset entries but do not want to destroy rangeset itself. Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand Acked-by: Jan Beulich --- Changes in v12: - s/rangeset_empty/rangeset_purge/ Changes in v11: - Now the function only empties rangeset, without removing it from domain's list Changes in v10: - New in v10. The function is used in "vpci/header: handle p2m range sets per BAR" --- xen/common/rangeset.c | 16 ++++++++++++---- xen/include/xen/rangeset.h | 3 ++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/xen/common/rangeset.c b/xen/common/rangeset.c index 0ccd53caac52..b75590f90744 100644 --- a/xen/common/rangeset.c +++ b/xen/common/rangeset.c @@ -448,11 +448,20 @@ struct rangeset *rangeset_new( return r; } -void rangeset_destroy( - struct rangeset *r) +void rangeset_purge(struct rangeset *r) { struct range *x; + if ( r == NULL ) + return; + + while ( (x = first_range(r)) != NULL ) + destroy_range(r, x); +} + +void rangeset_destroy( + struct rangeset *r) +{ if ( r == NULL ) return; @@ -463,8 +472,7 @@ void rangeset_destroy( spin_unlock(&r->domain->rangesets_lock); } - while ( (x = first_range(r)) != NULL ) - destroy_range(r, x); + rangeset_purge(r); xfree(r); } diff --git a/xen/include/xen/rangeset.h b/xen/include/xen/rangeset.h index 87bd956962b5..96c918082501 100644 --- a/xen/include/xen/rangeset.h +++ b/xen/include/xen/rangeset.h @@ -56,7 +56,7 @@ void rangeset_limit( bool __must_check rangeset_is_empty( const struct rangeset *r); -/* Add/claim/remove/query a numeric range. */ +/* Add/claim/remove/query/purge a numeric range. */ int __must_check rangeset_add_range( struct rangeset *r, unsigned long s, unsigned long e); int __must_check rangeset_claim_range(struct rangeset *r, unsigned long size, @@ -70,6 +70,7 @@ bool __must_check rangeset_overlaps_range( int rangeset_report_ranges( struct rangeset *r, unsigned long s, unsigned long e, int (*cb)(unsigned long s, unsigned long e, void *data), void *ctxt); +void rangeset_purge(struct rangeset *r); /* * Note that the consume function can return an error value apart from From patchwork Tue Jan 9 21:51:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28F03C4706C for ; Tue, 9 Jan 2024 22:06:10 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665089.1035311 (Exim 4.92) (envelope-from ) id 1rNKER-00011y-ET; Tue, 09 Jan 2024 22:05:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665089.1035311; Tue, 09 Jan 2024 22:05:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNKER-00011r-Ar; Tue, 09 Jan 2024 22:05:59 +0000 Received: by outflank-mailman (input) for mailman id 665089; Tue, 09 Jan 2024 22:05:58 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK2d-0007gG-PN for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:53:47 +0000 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on20600.outbound.protection.outlook.com [2a01:111:f403:2009::600]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 8f52a3d3-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:53:45 +0100 (CET) Received: from SJ0PR03CA0254.namprd03.prod.outlook.com (2603:10b6:a03:3a0::19) by CH2PR12MB4311.namprd12.prod.outlook.com (2603:10b6:610:a8::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.25; Tue, 9 Jan 2024 21:53:41 +0000 Received: from SJ1PEPF00001CEA.namprd03.prod.outlook.com (2603:10b6:a03:3a0:cafe::d9) by SJ0PR03CA0254.outlook.office365.com (2603:10b6:a03:3a0::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23 via Frontend Transport; Tue, 9 Jan 2024 21:53:41 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CEA.mail.protection.outlook.com (10.167.242.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:53:40 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:53:40 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:53:39 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8f52a3d3-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bQ8LdFFdpPqsdBlAaEdalVN2W6q4/m9/OMZ2QX+60gsa+ukNv8mPs+fV/2QvsZ2Zdphujqkw6xGDJcGCzAIz+yu9hs2US8spVmIpx3BCBQo2KASqSE3IP3pSAD1L6ITuFN506mR6UqisMVZYg7K/R1Yb7BD+Epb/nUXnfxq99er8ZzPsgTHe833gg5uoP/YNJ32itB60umpqfBgTLpZwknITal9e2/eYpBKNCcpN15d57Y9MwadoAJLSguBfHx4t2bG3kssasxg9QuKabDNa6echG0WAS/cuqvRNqLPRep6fsyhROO/X5F+GSrp8XqPfKioIC1IAo+DuUU/3hSLF0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8rT/5Ji7hQyXs6rmimqQBYS2da8mep0A+0DZ9Q5ryDI=; b=VSjmurngnAIBEwvuPoq/p/ZMqXW+Z2nwHtUsX8hMZyvTk+infL5JkRlVDyNKon354Y4N7jv6D2yMknpMWAH2+/XiPpf8nlvjW8DADfnFrhb+QTAb6T+tFVvOKgANg6VJpAz4oGvtqvzqiNgW+/AkzAc2dXwwGjDvWe8vx00BWapp7IaDv1NxnxDNcls/PZzDFobfFY+9TMThtYNyUWDp9lfpByTIcos4sV4FoHp9G0CWHYAoIM0bXxiJQ2uwLQ6mFZcBqPp7/CKMzQuEkm4qGZLFMLwX+yPOZ2Ef59RsvBUKvige40RrmJCWod/FzuTjUzmF626A/HJ/CFfIqVPnuA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8rT/5Ji7hQyXs6rmimqQBYS2da8mep0A+0DZ9Q5ryDI=; b=OSNOQWIGMDBR+zQgnYwBdt1he+Pbv9qOfagol4HdFKGP5H65DIDzLxggn3nW2oC9eU+PsnDVmShfML7iGoNLNVo73AaNE75Ktaazr134kqy9nDZ+NbPIbUvFwA6ZmBIUKN1rA6mLtN8WKdsUUZ5+szYPYZrijeThrfEPpdWEhRY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , =?utf-8?q?Ro?= =?utf-8?q?ger_Pau_Monn=C3=A9?= , "Volodymyr Babchuk" , Stewart Hildebrand Subject: [PATCH v12 08/15] vpci/header: handle p2m range sets per BAR Date: Tue, 9 Jan 2024 16:51:23 -0500 Message-ID: <20240109215145.430207-9-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|CH2PR12MB4311:EE_ X-MS-Office365-Filtering-Correlation-Id: 525c7da1-a1dc-4416-5a0d-08dc115d7131 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kuzD1DFmS0pNCy//oT2WjRRl18sPlpGUY89DGtN2eBTZWojoVi+OaRHySzpLJOfxoWTpq3FwRxNyB5xhoAJsZ09Z2ElA2goL1jhx5QF4aT6etMwmFWSAeA5Y0r9iZ4tWl5hIiDelmximMLyAnKFlUXSnqrk1IuK1yei7a9pf3iXaFG10tgy2WF09spP10RvSvFNKP4/RefiVcMVRfL6A36stV5mTIo0Zw74kAgWkxPbX4HiwriVRgTWp8LYIpuIuUlGprJJif6s9H5dgqySc5a5J/P0t7R+7yz5PFo7cLcPZ0DR8RbIWZb/wuT4Di37AoGUtzoSvHl4T97TFS5SlJm0yC0lbcEIZ0tB7r0bsKZ+FlaMFEoXlqt3jR7vZVAhox3i0kpiKn+dDzxuzTBB5QPFbpJ1xdANNVMrTmv9i1ps2svhr5lng5hsQF1xulks9XGnw8ZK0yM8+Uos8VYju5IBF1ooCRjRni5AGK+sSQQbVlORc1EpU98qYGv2tXfgJkca+VKDI9ckWiB5HUfRfOwXNVpng3BkZ/ZSxl/bq5MAhq/Noxip+Chx1qxyB8epKOAFK63q28KYc4lIz95ZIQHvY4cA381tTv1/Fp0/eJC3Z095Qtg0d3PzrbHA0AQ/iKgizo8Rj8m/0B2qXxSXxoIdn5LvEbADJ0wXEnyoDQsuODTIjfijOxwIMvropkjqT6iNNov8Lx5aETmQUbfUeN0Rc0h9CXrsWdjKYP0kObBU66LS+YEIqv1HrLnSEPxfL6oWxOo+CfDKEJVFkf7uM1JF/GSLDpqWew1YDFzDyGT2FVbcMrdNDIATzehnucmdy X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(396003)(136003)(39860400002)(230173577357003)(230273577357003)(230922051799003)(82310400011)(64100799003)(186009)(451199024)(1800799012)(46966006)(36840700001)(40470700004)(40480700001)(40460700003)(2906002)(478600001)(36860700001)(30864003)(5660300002)(6666004)(81166007)(4326008)(44832011)(356005)(41300700001)(8936002)(316002)(70206006)(70586007)(54906003)(36756003)(6916009)(8676002)(2616005)(86362001)(426003)(26005)(336012)(1076003)(83380400001)(47076005)(82740400003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:53:40.7208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 525c7da1-a1dc-4416-5a0d-08dc115d7131 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4311 From: Oleksandr Andrushchenko Instead of handling a single range set, that contains all the memory regions of all the BARs and ROM, have them per BAR. As the range sets are now created when a PCI device is added and destroyed when it is removed so make them named and accounted. Note that rangesets were chosen here despite there being only up to 3 separate ranges in each set (typically just 1). But rangeset per BAR was chosen for the ease of implementation and existing code re-usability. Also note that error handling of vpci_process_pending() is slightly modified, and that vPCI handlers are no longer removed if the creation of the mappings in vpci_process_pending() fails, as that's unlikely to lead to a functional device in any case. This is in preparation of making non-identity mappings in p2m for the MMIOs. Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Reviewed-by: Roger Pau Monné Signed-off-by: Stewart Hildebrand --- In v12: - s/rangeset_empty/rangeset_purge/ - change i to num_bars for expansion ROM (purely cosmetic change) In v11: - Modified commit message to note changes in error handling in vpci_process_pending() - Removed redundant ASSERT() in defer_map. There is no reason to introduce it in this patch and there is no other patch where introducing that ASSERT() was appropriate. - Fixed formatting - vpci_process_pending() clears v->vpci.pdev if it failed checks at the beginning - Added Roger's R-B tag In v10: - Added additional checks to vpci_process_pending() - vpci_process_pending() now clears rangeset in case of failure - Fixed locks in vpci_process_pending() - Fixed coding style issues - Fixed error handling in init_bars In v9: - removed d->vpci.map_pending in favor of checking v->vpci.pdev != NULL - printk -> gprintk - renamed bar variable to fix shadowing - fixed bug with iterating on remote device's BARs - relaxed lock in vpci_process_pending - removed stale comment Since v6: - update according to the new locking scheme - remove odd fail label in modify_bars Since v5: - fix comments - move rangeset allocation to init_bars and only allocate for MAPPABLE BARs - check for overlap with the already setup BAR ranges Since v4: - use named range sets for BARs (Jan) - changes required by the new locking scheme - updated commit message (Jan) Since v3: - re-work vpci_cancel_pending accordingly to the per-BAR handling - s/num_mem_ranges/map_pending and s/uint8_t/bool - ASSERT(bar->mem) in modify_bars - create and destroy the rangesets on add/remove --- xen/drivers/vpci/header.c | 257 ++++++++++++++++++++++++++------------ xen/drivers/vpci/vpci.c | 6 + xen/include/xen/vpci.h | 2 +- 3 files changed, 185 insertions(+), 80 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 39e11e141b38..feccd070ddd0 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -162,63 +162,107 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, bool vpci_process_pending(struct vcpu *v) { - if ( v->vpci.mem ) + struct pci_dev *pdev = v->vpci.pdev; + struct map_data data = { + .d = v->domain, + .map = v->vpci.cmd & PCI_COMMAND_MEMORY, + }; + struct vpci_header *header = NULL; + unsigned int i; + + if ( !pdev ) + return false; + + read_lock(&v->domain->pci_lock); + + if ( !pdev->vpci || (v->domain != pdev->domain) ) { - struct map_data data = { - .d = v->domain, - .map = v->vpci.cmd & PCI_COMMAND_MEMORY, - }; - int rc = rangeset_consume_ranges(v->vpci.mem, map_range, &data); + v->vpci.pdev = NULL; + read_unlock(&v->domain->pci_lock); + return false; + } + + header = &pdev->vpci->header; + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) + { + struct vpci_bar *bar = &header->bars[i]; + int rc; + + if ( rangeset_is_empty(bar->mem) ) + continue; + + rc = rangeset_consume_ranges(bar->mem, map_range, &data); if ( rc == -ERESTART ) + { + read_unlock(&v->domain->pci_lock); return true; + } - write_lock(&v->domain->pci_lock); - spin_lock(&v->vpci.pdev->vpci->lock); - /* Disable memory decoding unconditionally on failure. */ - modify_decoding(v->vpci.pdev, - rc ? v->vpci.cmd & ~PCI_COMMAND_MEMORY : v->vpci.cmd, - !rc && v->vpci.rom_only); - spin_unlock(&v->vpci.pdev->vpci->lock); - - rangeset_destroy(v->vpci.mem); - v->vpci.mem = NULL; if ( rc ) - /* - * FIXME: in case of failure remove the device from the domain. - * Note that there might still be leftover mappings. While this is - * safe for Dom0, for DomUs the domain will likely need to be - * killed in order to avoid leaking stale p2m mappings on - * failure. - */ - vpci_deassign_device(v->vpci.pdev); - write_unlock(&v->domain->pci_lock); + { + spin_lock(&pdev->vpci->lock); + /* Disable memory decoding unconditionally on failure. */ + modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY, + false); + spin_unlock(&pdev->vpci->lock); + + /* Clean all the rangesets */ + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) + if ( !rangeset_is_empty(header->bars[i].mem) ) + rangeset_purge(header->bars[i].mem); + + v->vpci.pdev = NULL; + + read_unlock(&v->domain->pci_lock); + + if ( !is_hardware_domain(v->domain) ) + domain_crash(v->domain); + + return false; + } } + v->vpci.pdev = NULL; + + spin_lock(&pdev->vpci->lock); + modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only); + spin_unlock(&pdev->vpci->lock); + + read_unlock(&v->domain->pci_lock); return false; } static int __init apply_map(struct domain *d, const struct pci_dev *pdev, - struct rangeset *mem, uint16_t cmd) + uint16_t cmd) { struct map_data data = { .d = d, .map = true }; - int rc; + struct vpci_header *header = &pdev->vpci->header; + int rc = 0; + unsigned int i; ASSERT(rw_is_write_locked(&d->pci_lock)); - while ( (rc = rangeset_consume_ranges(mem, map_range, &data)) == -ERESTART ) + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { - /* - * It's safe to drop and reacquire the lock in this context - * without risking pdev disappearing because devices cannot be - * removed until the initial domain has been started. - */ - write_unlock(&d->pci_lock); - process_pending_softirqs(); - write_lock(&d->pci_lock); - } + struct vpci_bar *bar = &header->bars[i]; - rangeset_destroy(mem); + if ( rangeset_is_empty(bar->mem) ) + continue; + + while ( (rc = rangeset_consume_ranges(bar->mem, map_range, + &data)) == -ERESTART ) + { + /* + * It's safe to drop and reacquire the lock in this context + * without risking pdev disappearing because devices cannot be + * removed until the initial domain has been started. + */ + write_unlock(&d->pci_lock); + process_pending_softirqs(); + write_lock(&d->pci_lock); + } + } if ( !rc ) modify_decoding(pdev, cmd, false); @@ -226,7 +270,7 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, } static void defer_map(struct domain *d, struct pci_dev *pdev, - struct rangeset *mem, uint16_t cmd, bool rom_only) + uint16_t cmd, bool rom_only) { struct vcpu *curr = current; @@ -237,7 +281,6 @@ static void defer_map(struct domain *d, struct pci_dev *pdev, * started for the same device if the domain is not well-behaved. */ curr->vpci.pdev = pdev; - curr->vpci.mem = mem; curr->vpci.cmd = cmd; curr->vpci.rom_only = rom_only; /* @@ -251,33 +294,33 @@ static void defer_map(struct domain *d, struct pci_dev *pdev, static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) { struct vpci_header *header = &pdev->vpci->header; - struct rangeset *mem = rangeset_new(NULL, NULL, 0); struct pci_dev *tmp, *dev = NULL; const struct domain *d; const struct vpci_msix *msix = pdev->vpci->msix; - unsigned int i; + unsigned int i, j; int rc; ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); - if ( !mem ) - return -ENOMEM; - /* - * Create a rangeset that represents the current device BARs memory region - * and compare it against all the currently active BAR memory regions. If - * an overlap is found, subtract it from the region to be mapped/unmapped. + * Create a rangeset per BAR that represents the current device memory + * region and compare it against all the currently active BAR memory + * regions. If an overlap is found, subtract it from the region to be + * mapped/unmapped. * - * First fill the rangeset with all the BARs of this device or with the ROM + * First fill the rangesets with the BAR of this device or with the ROM * BAR only, depending on whether the guest is toggling the memory decode * bit of the command register, or the enable bit of the ROM BAR register. */ for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { - const struct vpci_bar *bar = &header->bars[i]; + struct vpci_bar *bar = &header->bars[i]; unsigned long start = PFN_DOWN(bar->addr); unsigned long end = PFN_DOWN(bar->addr + bar->size - 1); + if ( !bar->mem ) + continue; + if ( !MAPPABLE_BAR(bar) || (rom_only ? bar->type != VPCI_BAR_ROM : (bar->type == VPCI_BAR_ROM && !header->rom_enabled)) || @@ -293,14 +336,31 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) continue; } - rc = rangeset_add_range(mem, start, end); + rc = rangeset_add_range(bar->mem, start, end); if ( rc ) { printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", start, end, rc); - rangeset_destroy(mem); return rc; } + + /* Check for overlap with the already setup BAR ranges. */ + for ( j = 0; j < i; j++ ) + { + struct vpci_bar *prev_bar = &header->bars[j]; + + if ( rangeset_is_empty(prev_bar->mem) ) + continue; + + rc = rangeset_remove_range(prev_bar->mem, start, end); + if ( rc ) + { + gprintk(XENLOG_WARNING, + "%pp: failed to remove overlapping range [%lx, %lx]: %d\n", + &pdev->sbdf, start, end, rc); + return rc; + } + } } /* Remove any MSIX regions if present. */ @@ -310,14 +370,21 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) unsigned long end = PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + vmsix_table_size(pdev->vpci, i) - 1); - rc = rangeset_remove_range(mem, start, end); - if ( rc ) + for ( j = 0; j < ARRAY_SIZE(header->bars); j++ ) { - printk(XENLOG_G_WARNING - "Failed to remove MSIX table [%lx, %lx]: %d\n", - start, end, rc); - rangeset_destroy(mem); - return rc; + const struct vpci_bar *bar = &header->bars[j]; + + if ( rangeset_is_empty(bar->mem) ) + continue; + + rc = rangeset_remove_range(bar->mem, start, end); + if ( rc ) + { + gprintk(XENLOG_WARNING, + "%pp: failed to remove MSIX table [%lx, %lx]: %d\n", + &pdev->sbdf, start, end, rc); + return rc; + } } } @@ -357,27 +424,37 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) for ( i = 0; i < ARRAY_SIZE(tmp->vpci->header.bars); i++ ) { - const struct vpci_bar *bar = &tmp->vpci->header.bars[i]; - unsigned long start = PFN_DOWN(bar->addr); - unsigned long end = PFN_DOWN(bar->addr + bar->size - 1); - - if ( !bar->enabled || - !rangeset_overlaps_range(mem, start, end) || - /* - * If only the ROM enable bit is toggled check against - * other BARs in the same device for overlaps, but not - * against the same ROM BAR. - */ - (rom_only && tmp == pdev && bar->type == VPCI_BAR_ROM) ) + const struct vpci_bar *remote_bar = &tmp->vpci->header.bars[i]; + unsigned long start = PFN_DOWN(remote_bar->addr); + unsigned long end = PFN_DOWN(remote_bar->addr + + remote_bar->size - 1); + + if ( !remote_bar->enabled ) continue; - rc = rangeset_remove_range(mem, start, end); - if ( rc ) + for ( j = 0; j < ARRAY_SIZE(header->bars); j++) { - printk(XENLOG_G_WARNING "Failed to remove [%lx, %lx]: %d\n", - start, end, rc); - rangeset_destroy(mem); - return rc; + const struct vpci_bar *bar = &header->bars[j]; + + if ( !rangeset_overlaps_range(bar->mem, start, end) || + /* + * If only the ROM enable bit is toggled check against + * other BARs in the same device for overlaps, but not + * against the same ROM BAR. + */ + (rom_only && + tmp == pdev && + bar->type == VPCI_BAR_ROM) ) + continue; + + rc = rangeset_remove_range(bar->mem, start, end); + if ( rc ) + { + gprintk(XENLOG_WARNING, + "%pp: failed to remove [%lx, %lx]: %d\n", + &pdev->sbdf, start, end, rc); + return rc; + } } } } @@ -401,10 +478,10 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) * will always be to establish mappings and process all the BARs. */ ASSERT((cmd & PCI_COMMAND_MEMORY) && !rom_only); - return apply_map(pdev->domain, pdev, mem, cmd); + return apply_map(pdev->domain, pdev, cmd); } - defer_map(dev->domain, dev, mem, cmd, rom_only); + defer_map(dev->domain, dev, cmd, rom_only); return 0; } @@ -593,6 +670,18 @@ static void cf_check rom_write( rom->addr = val & PCI_ROM_ADDRESS_MASK; } +static int bar_add_rangeset(const struct pci_dev *pdev, struct vpci_bar *bar, + unsigned int i) +{ + char str[32]; + + snprintf(str, sizeof(str), "%pp:BAR%u", &pdev->sbdf, i); + + bar->mem = rangeset_new(pdev->domain, str, RANGESETF_no_print); + + return !bar->mem ? -ENOMEM : 0; +} + static int cf_check init_header(struct pci_dev *pdev) { uint16_t cmd; @@ -748,6 +837,10 @@ static int cf_check init_header(struct pci_dev *pdev) else bars[i].type = VPCI_BAR_MEM32; + rc = bar_add_rangeset(pdev, &bars[i], i); + if ( rc ) + goto fail; + rc = pci_size_mem_bar(pdev->sbdf, reg, &addr, &size, (i == num_bars - 1) ? PCI_BAR_LAST : 0); if ( rc < 0 ) @@ -798,6 +891,12 @@ static int cf_check init_header(struct pci_dev *pdev) 4, rom); if ( rc ) rom->type = VPCI_BAR_EMPTY; + else + { + rc = bar_add_rangeset(pdev, rom, num_bars); + if ( rc ) + goto fail; + } } else if ( !is_hwdom ) { diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 42eac85106a3..a0e8b1012509 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -42,6 +42,8 @@ extern vpci_register_init_t *const __end_vpci_array[]; void vpci_deassign_device(struct pci_dev *pdev) { + unsigned int i; + ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); if ( !has_vpci(pdev->domain) || !pdev->vpci ) @@ -67,6 +69,10 @@ void vpci_deassign_device(struct pci_dev *pdev) if ( pdev->vpci->msix->table[i] ) iounmap(pdev->vpci->msix->table[i]); } + + for ( i = 0; i < ARRAY_SIZE(pdev->vpci->header.bars); i++ ) + rangeset_destroy(pdev->vpci->header.bars[i].mem); + xfree(pdev->vpci->msix); xfree(pdev->vpci->msi); xfree(pdev->vpci); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index b0e38a5a1acb..817ee9ee7300 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -92,6 +92,7 @@ struct vpci { /* Guest address. */ uint64_t guest_addr; uint64_t size; + struct rangeset *mem; enum { VPCI_BAR_EMPTY, VPCI_BAR_IO, @@ -176,7 +177,6 @@ struct vpci { struct vpci_vcpu { /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ - struct rangeset *mem; struct pci_dev *pdev; uint16_t cmd; bool rom_only : 1; From patchwork Tue Jan 9 21:51:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96CE0C4707B for ; Tue, 9 Jan 2024 22:03:32 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665074.1035291 (Exim 4.92) (envelope-from ) id 1rNKBq-0007l2-Hy; Tue, 09 Jan 2024 22:03:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665074.1035291; Tue, 09 Jan 2024 22:03:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNKBq-0007kv-Et; Tue, 09 Jan 2024 22:03:18 +0000 Received: by outflank-mailman (input) for mailman id 665074; Tue, 09 Jan 2024 22:03:17 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK2t-0007gG-Li for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:54:03 +0000 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2061b.outbound.protection.outlook.com [2a01:111:f400:7e88::61b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 989366b6-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:54:01 +0100 (CET) Received: from MN2PR08CA0029.namprd08.prod.outlook.com (2603:10b6:208:239::34) by SJ2PR12MB7964.namprd12.prod.outlook.com (2603:10b6:a03:4cf::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:53:55 +0000 Received: from BL6PEPF0001AB50.namprd04.prod.outlook.com (2603:10b6:208:239:cafe::76) by MN2PR08CA0029.outlook.office365.com (2603:10b6:208:239::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23 via Frontend Transport; Tue, 9 Jan 2024 21:53:55 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB50.mail.protection.outlook.com (10.167.242.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:53:54 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:53:54 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:53:54 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:53:53 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 989366b6-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ItPSuv7suMx4U2wRojCyh4OZPpOdnIs1PHP0KJjI5QXrdWKCh8+8mRnCCeFOZSvKDbbiuHC60dBRxZixP+Jz56tzJEiv9K2Za9f1p33t6GFg2wNQ727oTMeiaNHfIPXIgkR9YXjJg/YUzjDE4dMstSdnutVBi7dxv8pMf+jRuX7FiNVNa/pY4W5tfChUhltntC850lHwsqJ4KWxrKxhNKNHPYLrrtekdXUzbRZFLsKedRb77g7/cysxU4C6D5f3hGGy3dR/cqTKjY3x+sWjQdIewLPifZ9cdCQjO89SSkVRWHKY0wKKi4eEfS11YOeahHTKM/Ezpo1jUsbPMGhKwqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3OVx++8ILg3L0aD2CuO8hPm8Z1yWpD5eQLVMw0q3dKw=; b=cfRamUJYRztRnorK2IuhKaWwIsviD0d/OMryuXz6XZFbvFT55DW6lvc1UyitGo21sCF8+Scveingl8avj/jw9UIIrXo9T0cyCrKnClHtZ1bqDFsDZLyPRnJ7LtoZBD56x3t4/kGVcGMRQLhxLtw004NKItzzof3U6b6rf5KQYX5NKfvTrjjjh7uQ5fAkmUiElip9PcE5bapNpeXCnLlbpKykBlBSmGC5rEwjo6XaQ+L00ZQtB25MoIyeuDTVezKeRXeRrLNAaJvdsxbBx2f129c0c7Okz/9PHJ+rFTkOynsTB7qyqQfdTiDxbGjfXq2hAd3EbU9V4AMG6S6S5ffVNg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3OVx++8ILg3L0aD2CuO8hPm8Z1yWpD5eQLVMw0q3dKw=; b=EeDOaNdZIk7gscAIQ/8XvB/3DIPZbluVbFmnIr6bucuHFjPBrxHur9VonjqZXII/GquICS0Uj3Hv0xAJph6usZjcWLaiJsFIytqoeQsCLxRTQqvHw1RNLh+CyYA+hYeed2yJCluHdXB5WwVDRvqwxVqHzws5mjvgkETSO7OrEds= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , =?utf-8?q?Ro?= =?utf-8?q?ger_Pau_Monn=C3=A9?= , "Daniel P. Smith" , Volodymyr Babchuk , Stewart Hildebrand Subject: [PATCH v12 09/15] vpci/header: program p2m with guest BAR view Date: Tue, 9 Jan 2024 16:51:24 -0500 Message-ID: <20240109215145.430207-10-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB50:EE_|SJ2PR12MB7964:EE_ X-MS-Office365-Filtering-Correlation-Id: c49a5374-5ab3-4d3a-c8c9-08dc115d79a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BLYCoHe7MEN0Nkcnd6GlnZeuXBXf+mCSSlB8pTGjB4mbvZFtQAUGK5Pa3rw3jLon5tDseua4khnJnS9FXzY/zcH157UCRk9aajV7yyY28EZLDGJNRdspNatG1VWJsEoVFC5WrqMDPQfNajLb0iXzFYRKp1yvFQAcwF+QC3HgkIqEkRw79Jd1d+uc0R5rzTfvGoNHIiXuIW0Idtw4SdMF4i9Ct8UwC+vBYKAyrV9LelUqvLt4uPkrmA2WzMrHOXjt9Y6nQ92h2AoA+NgnaoXh7BL86ChFFlS4oERVvYzt8RDnlVOsq41MeaPa+IKnAII6qREQP4BaxE5C1yG3hTLwhsykwJf4+057EKJgs3xURxkXMNWMRfUSAis6wAsJbu8f/vomIJfnx1PYuiOXh6W+3439adZfkhZAdC+kDZQ08oREIlCKmIFbjoDnr1Zll/mt37d13FKTFJgEzfmHOSjvQMrRwsaKxLvErkx/kjIOC7rSQtfM2Y753tRAh9yGCMNgcApjrd8TE3dQWubMzGq1/n3MRABCOTzMRTW5MD/GiFVbyE6BTSDCGnxhQWeAQ8ZlbHGSi8OAYVhA8ykhUiQ32OknCOnLYuOJ+hSaJ0nEJAuQjIYvFpi1xE52YaHwcg8Ppks9nU8cdVJi2Emi4UcudnaC5nGBQAa1826TsPfJCiDUtm5adYiibElZToH2mrSI0yprqANVM4HTgc1z0gGZtpDZJGyH9Melo23z/dvswPVqFwcLz3p1gkl+JokPhvMiw+8vIrVkOg88+TPNGBtYMt9hjDGlPhrSK37w9+TDW/zmSixLcTJCwlRC451MhWje X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(39860400002)(376002)(136003)(230173577357003)(230273577357003)(230922051799003)(82310400011)(186009)(451199024)(1800799012)(64100799003)(46966006)(36840700001)(40470700004)(336012)(83380400001)(2616005)(426003)(47076005)(40480700001)(1076003)(26005)(36860700001)(4326008)(44832011)(478600001)(6666004)(40460700003)(82740400003)(316002)(356005)(6916009)(70206006)(54906003)(70586007)(8936002)(8676002)(81166007)(41300700001)(86362001)(2906002)(36756003)(5660300002)(30864003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:53:54.9706 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c49a5374-5ab3-4d3a-c8c9-08dc115d79a3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB50.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7964 From: Oleksandr Andrushchenko Take into account guest's BAR view and program its p2m accordingly: gfn is guest's view of the BAR and mfn is the physical BAR value. This way hardware domain sees physical BAR values and guest sees emulated ones. Hardware domain continues getting the BARs identity mapped, while for domUs the BARs are mapped at the requested guest address without modifying the BAR address in the device PCI config space. Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand Reviewed-by: Roger Pau Monné --- In v12: - Update guest_addr in rom_write() - Use unsigned long for start_mfn and map_mfn to reduce mfn_x() calls - Use existing vmsix_table_*() functions - Change vmsix_table_base() to use .guest_addr In v11: - Add vmsix_guest_table_addr() and vmsix_guest_table_base() functions to access guest's view of the VMSIx tables. - Use MFN (not GFN) to check access permissions - Move page offset check to this patch - Call rangeset_remove_range() with correct parameters In v10: - Moved GFN variable definition outside the loop in map_range() - Updated printk error message in map_range() - Now BAR address is always stored in bar->guest_addr, even for HW dom, this removes bunch of ugly is_hwdom() checks in modify_bars() - vmsix_table_base() now uses .guest_addr instead of .addr In v9: - Extended the commit message - Use bar->guest_addr in modify_bars - Extended printk error message in map_range - Moved map_data initialization so .bar can be initialized during declaration Since v5: - remove debug print in map_range callback - remove "identity" from the debug print Since v4: - moved start_{gfn|mfn} calculation into map_range - pass vpci_bar in the map_data instead of start_{gfn|mfn} - s/guest_addr/guest_reg Since v3: - updated comment (Roger) - removed gfn_add(map->start_gfn, rc); which is wrong - use v->domain instead of v->vpci.pdev->domain - removed odd e.g. in comment - s/d%d/%pd in altered code - use gdprintk for map/unmap logs Since v2: - improve readability for data.start_gfn and restructure ?: construct Since v1: - s/MSI/MSI-X in comments --- xen/drivers/vpci/header.c | 81 +++++++++++++++++++++++++++++++-------- xen/include/xen/vpci.h | 3 +- 2 files changed, 66 insertions(+), 18 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index feccd070ddd0..f0b0b64b0929 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -34,6 +34,7 @@ struct map_data { struct domain *d; + const struct vpci_bar *bar; bool map; }; @@ -41,13 +42,24 @@ static int cf_check map_range( unsigned long s, unsigned long e, void *data, unsigned long *c) { const struct map_data *map = data; + /* Start address of the BAR as seen by the guest. */ + unsigned long start_gfn = PFN_DOWN(map->bar->guest_addr); + /* Physical start address of the BAR. */ + unsigned long start_mfn = PFN_DOWN(map->bar->addr); int rc; for ( ; ; ) { unsigned long size = e - s + 1; + /* + * Ranges to be mapped don't always start at the BAR start address, as + * there can be holes or partially consumed ranges. Account for the + * offset of the current address from the BAR start. + */ + unsigned long map_mfn = start_mfn + s - start_gfn; + unsigned long m_end = map_mfn + size - 1; - if ( !iomem_access_permitted(map->d, s, e) ) + if ( !iomem_access_permitted(map->d, map_mfn, m_end) ) { printk(XENLOG_G_WARNING "%pd denied access to MMIO range [%#lx, %#lx]\n", @@ -55,7 +67,8 @@ static int cf_check map_range( return -EPERM; } - rc = xsm_iomem_mapping(XSM_HOOK, map->d, s, e, map->map); + rc = xsm_iomem_mapping(XSM_HOOK, map->d, map_mfn, m_end, + map->map); if ( rc ) { printk(XENLOG_G_WARNING @@ -73,8 +86,8 @@ static int cf_check map_range( * - {un}map_mmio_regions doesn't support preemption. */ - rc = map->map ? map_mmio_regions(map->d, _gfn(s), size, _mfn(s)) - : unmap_mmio_regions(map->d, _gfn(s), size, _mfn(s)); + rc = map->map ? map_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn)) + : unmap_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn)); if ( rc == 0 ) { *c += size; @@ -83,8 +96,9 @@ static int cf_check map_range( if ( rc < 0 ) { printk(XENLOG_G_WARNING - "Failed to identity %smap [%lx, %lx] for d%d: %d\n", - map->map ? "" : "un", s, e, map->d->domain_id, rc); + "Failed to %smap [%lx %lx] -> [%lx %lx] for %pd: %d\n", + map->map ? "" : "un", s, e, map_mfn, + map_mfn + size, map->d, rc); break; } ASSERT(rc < size); @@ -163,10 +177,6 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, bool vpci_process_pending(struct vcpu *v) { struct pci_dev *pdev = v->vpci.pdev; - struct map_data data = { - .d = v->domain, - .map = v->vpci.cmd & PCI_COMMAND_MEMORY, - }; struct vpci_header *header = NULL; unsigned int i; @@ -186,6 +196,11 @@ bool vpci_process_pending(struct vcpu *v) for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar = &header->bars[i]; + struct map_data data = { + .d = v->domain, + .map = v->vpci.cmd & PCI_COMMAND_MEMORY, + .bar = bar, + }; int rc; if ( rangeset_is_empty(bar->mem) ) @@ -236,7 +251,6 @@ bool vpci_process_pending(struct vcpu *v) static int __init apply_map(struct domain *d, const struct pci_dev *pdev, uint16_t cmd) { - struct map_data data = { .d = d, .map = true }; struct vpci_header *header = &pdev->vpci->header; int rc = 0; unsigned int i; @@ -246,6 +260,7 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar = &header->bars[i]; + struct map_data data = { .d = d, .map = true, .bar = bar }; if ( rangeset_is_empty(bar->mem) ) continue; @@ -311,12 +326,16 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) * First fill the rangesets with the BAR of this device or with the ROM * BAR only, depending on whether the guest is toggling the memory decode * bit of the command register, or the enable bit of the ROM BAR register. + * + * For non-hardware domain we use guest physical addresses. */ for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar = &header->bars[i]; unsigned long start = PFN_DOWN(bar->addr); unsigned long end = PFN_DOWN(bar->addr + bar->size - 1); + unsigned long start_guest = PFN_DOWN(bar->guest_addr); + unsigned long end_guest = PFN_DOWN(bar->guest_addr + bar->size - 1); if ( !bar->mem ) continue; @@ -336,11 +355,25 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) continue; } - rc = rangeset_add_range(bar->mem, start, end); + /* + * Make sure that the guest set address has the same page offset + * as the physical address on the host or otherwise things won't work as + * expected. + */ + if ( PAGE_OFFSET(bar->guest_addr) != PAGE_OFFSET(bar->addr) ) + { + gprintk(XENLOG_G_WARNING, + "%pp: Can't map BAR%d because of page offset mismatch: %lx vs %lx\n", + &pdev->sbdf, i, PAGE_OFFSET(bar->guest_addr), + PAGE_OFFSET(bar->addr)); + return -EINVAL; + } + + rc = rangeset_add_range(bar->mem, start_guest, end_guest); if ( rc ) { printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", - start, end, rc); + start_guest, end_guest, rc); return rc; } @@ -352,12 +385,12 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) if ( rangeset_is_empty(prev_bar->mem) ) continue; - rc = rangeset_remove_range(prev_bar->mem, start, end); + rc = rangeset_remove_range(prev_bar->mem, start_guest, end_guest); if ( rc ) { gprintk(XENLOG_WARNING, "%pp: failed to remove overlapping range [%lx, %lx]: %d\n", - &pdev->sbdf, start, end, rc); + &pdev->sbdf, start_guest, end_guest, rc); return rc; } } @@ -425,8 +458,8 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) for ( i = 0; i < ARRAY_SIZE(tmp->vpci->header.bars); i++ ) { const struct vpci_bar *remote_bar = &tmp->vpci->header.bars[i]; - unsigned long start = PFN_DOWN(remote_bar->addr); - unsigned long end = PFN_DOWN(remote_bar->addr + + unsigned long start = PFN_DOWN(remote_bar->guest_addr); + unsigned long end = PFN_DOWN(remote_bar->guest_addr + remote_bar->size - 1); if ( !remote_bar->enabled ) @@ -513,6 +546,8 @@ static void cf_check bar_write( struct vpci_bar *bar = data; bool hi = false; + ASSERT(is_hardware_domain(pdev->domain)); + if ( bar->type == VPCI_BAR_MEM64_HI ) { ASSERT(reg > PCI_BASE_ADDRESS_0); @@ -543,6 +578,10 @@ static void cf_check bar_write( */ bar->addr &= ~(0xffffffffULL << (hi ? 32 : 0)); bar->addr |= (uint64_t)val << (hi ? 32 : 0); + /* + * Update guest address as well, so hardware domain sees BAR identity mapped + */ + bar->guest_addr = bar->addr; /* Make sure Xen writes back the same value for the BAR RO bits. */ if ( !hi ) @@ -639,11 +678,14 @@ static void cf_check rom_write( } if ( !rom->enabled ) + { /* * If the ROM BAR is not mapped update the address field so the * correct address is mapped into the p2m. */ rom->addr = val & PCI_ROM_ADDRESS_MASK; + rom->guest_addr = rom->addr; + } if ( !header->bars_mapped || rom->enabled == new_enabled ) { @@ -667,7 +709,10 @@ static void cf_check rom_write( return; if ( !new_enabled ) + { rom->addr = val & PCI_ROM_ADDRESS_MASK; + rom->guest_addr = rom->addr; + } } static int bar_add_rangeset(const struct pci_dev *pdev, struct vpci_bar *bar, @@ -862,6 +907,7 @@ static int cf_check init_header(struct pci_dev *pdev) } bars[i].addr = addr; + bars[i].guest_addr = addr; bars[i].size = size; bars[i].prefetchable = val & PCI_BASE_ADDRESS_MEM_PREFETCH; @@ -884,6 +930,7 @@ static int cf_check init_header(struct pci_dev *pdev) rom->type = VPCI_BAR_ROM; rom->size = size; rom->addr = addr; + rom->guest_addr = addr; header->rom_enabled = pci_conf_read32(pdev->sbdf, rom_reg) & PCI_ROM_ADDRESS_ENABLE; diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 817ee9ee7300..e89c571890b2 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -216,7 +216,8 @@ int vpci_msix_arch_print(const struct vpci_msix *msix); */ static inline paddr_t vmsix_table_base(const struct vpci *vpci, unsigned int nr) { - return vpci->header.bars[vpci->msix->tables[nr] & PCI_MSIX_BIRMASK].addr; + return vpci->header.bars[vpci->msix->tables[nr] & + PCI_MSIX_BIRMASK].guest_addr; } static inline paddr_t vmsix_table_addr(const struct vpci *vpci, unsigned int nr) From patchwork Tue Jan 9 21:51:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A89FC4706C for ; Tue, 9 Jan 2024 22:06:56 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665092.1035320 (Exim 4.92) (envelope-from ) id 1rNKFD-0001ws-O7; Tue, 09 Jan 2024 22:06:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665092.1035320; Tue, 09 Jan 2024 22:06:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNKFD-0001wl-LF; Tue, 09 Jan 2024 22:06:47 +0000 Received: by outflank-mailman (input) for mailman id 665092; Tue, 09 Jan 2024 22:06:45 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK34-0007gG-3i for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:54:14 +0000 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on20627.outbound.protection.outlook.com [2a01:111:f400:7e8c::627]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9f5ef59c-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:54:12 +0100 (CET) Received: from SJ0PR03CA0046.namprd03.prod.outlook.com (2603:10b6:a03:33e::21) by CH0PR12MB5283.namprd12.prod.outlook.com (2603:10b6:610:d6::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:54:07 +0000 Received: from SJ1PEPF00001CE8.namprd03.prod.outlook.com (2603:10b6:a03:33e:cafe::c6) by SJ0PR03CA0046.outlook.office365.com (2603:10b6:a03:33e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23 via Frontend Transport; Tue, 9 Jan 2024 21:54:07 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CE8.mail.protection.outlook.com (10.167.242.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:54:07 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:54:06 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:54:04 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9f5ef59c-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=n/jOB2IVHFoIb2RKQldmNTWHJY50uNdRs1wgRU2pMm0WcNKGI9r6fk0RrgKKAxr0E5naS3MeSfdXgDTvei9XE/OLs3mQjbDhxDnvJ7BGpSlRNLsWZwGj4YqLCvDCafbRIQvy8BSygo+1ouMk2fh4HDxHE52F1rAKNfIPlWhONVUK+hUrgPBuAgzswInE+Dkyfpvra1d0wmaCHaPOqiPOwyII0hYBURYuLNDevaKHRY3EHKH0Osg2U/k4HewPYGEk6Rn0OCrksBXIHh/KpQiN3WlZyzhEJO2xjemrJqScZ+WrdGzVrdrYPAxbO+sGtLNCmmpf6WeRX1j9JWO6U8IoHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3xDFu5KZSSDdncpc2mzzqE3hD5UQFFULxFo1QzgNY0Y=; b=au9aOPYYnfT7xgPmfgCOi83lHOmKU/18fCns6YLvy2sdFNBTJoWBSdL65ZMBHNKu3T9cYcwoLP/Q7ni5A+R7fz6jw+r0wmI+7ufGTJsRIJBULhWnMBOMgNq+MZXzTiD1IL9W1iqKxhyxbatKBsonnerRUobvQAUOv96/pxCytqnyHjksn0t4OOO1mpbclPlJcUVYMfmYd93iCpu9iiS0CWEG3BOZWWgOCOoZNdebCm1+ZqcmRGxm4jCqF5d5oBpxkLuc2Z0I3cXM5SDIkq4a/lSTTj1Q++Tvvss1S/kf+XGt5/k7jUNiOSC9xQq+nU6cSQagPE8N/3aVl65ZflkFmw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3xDFu5KZSSDdncpc2mzzqE3hD5UQFFULxFo1QzgNY0Y=; b=vXz9QO25TmODe1fbtOuuf/834KfbD4gemYFKdyQpIz8KP6Cg6ur0U/CxGjmPPtFO8lU/Qkyed268scxdyibZyWSh1AT3M0kFa/BVcW0m3NEs6CRzJTVJB/uY5IaHeRZ+TmpSCZpcisOYok14qq5sm9vPSrUul9gVmdIA1g0oe3Q= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , =?utf-8?q?Ro?= =?utf-8?q?ger_Pau_Monn=C3=A9?= , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , Volodymyr Babchuk , Stewart Hildebrand Subject: [PATCH v12 10/15] vpci/header: emulate PCI_COMMAND register for guests Date: Tue, 9 Jan 2024 16:51:25 -0500 Message-ID: <20240109215145.430207-11-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE8:EE_|CH0PR12MB5283:EE_ X-MS-Office365-Filtering-Correlation-Id: 72bf7f9d-e407-4aa4-1f37-08dc115d812b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UplPkD0BSlNmzrFH/GBY+acm9DEHZHSCB+famK1O433/KKF46MZTSxwK3b2x+Cf4tCfuD/yhwsKj8T7R217Wy4ljZ5HXAFzPygz2BWgrE7NIkzgdjP3lMGyE5BizYLsMprrl9eLTr2weH9RrSIdosX9tEcF/Etgr2eGT0u6uqMafg/T3fjslmzql5ruV7zIaSRiKRq6m1+Ho6TMvh/YW3YmdD3ZeWgx+r84UHThOaeDnmE2WPIAiijJAgL3QOtOe1rwoZBrdpb0OQTTErDezvuUp2L0qknGBiJd0bs1tPcqhFs0vqmWgaYoQqhByyjLmhbmFdiH4dgXNw7NGKWYZQQUwxV5dc/l4CiIlAw/aXU54/CaECrkZY0bU7vQ3wYDQTWc8f/jxgCRrgMHTFnqzXK+R5VKw2JkVyM9GB4zJeDu7dKpDOHMGrFRrcpAB1x0YExmrBa8gV7uRruw0g59H4QXAvMpwsiCidm0qGdg7u6c8UKtw9h/I9b3/2f0DecM6DoPQAP9Ck2L4w/wbnVX8hjxZS+G6Qklz4wVFGzXfXAMG/eoVZWSwGgNRF42/OMEK66bfNAe7Q7n0bCvGzxtah/7NzGWqIw615IX7Kde7lsHc1iYCp6OvHe1j8GziTCH3vn9JaK0TXkrCHt4F1p9tBaRvjnwZdfy7h+ZIdEeWdI9buRSjO02K0KLDhfUVc2byfLjgCtWpw0PNWlDhyq+td2KuB5dgfckBTn2kYxNvv5nm6YesESyl6VkzhSLAvB+zDC8+B05GxiDfB5dPQHnmOTMcO4cWuJLtEXlaUfcaYEU3whmnDpDTxlyNVXscHD1C X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(136003)(396003)(39860400002)(230173577357003)(230273577357003)(230922051799003)(64100799003)(1800799012)(451199024)(82310400011)(186009)(36840700001)(40470700004)(46966006)(2616005)(41300700001)(1076003)(478600001)(426003)(26005)(336012)(6666004)(36860700001)(81166007)(86362001)(36756003)(82740400003)(356005)(47076005)(83380400001)(70586007)(30864003)(2906002)(40460700003)(7416002)(8676002)(8936002)(70206006)(40480700001)(316002)(54906003)(5660300002)(44832011)(4326008)(6916009)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:54:07.5235 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72bf7f9d-e407-4aa4-1f37-08dc115d812b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5283 From: Oleksandr Andrushchenko Xen and/or Dom0 may have put values in PCI_COMMAND which they expect to remain unaltered. PCI_COMMAND_SERR bit is a good example: while the guest's (domU) view of this will want to be zero (for now), the host having set it to 1 should be preserved, or else we'd effectively be giving the domU control of the bit. Thus, PCI_COMMAND register needs proper emulation in order to honor host's settings. According to "PCI LOCAL BUS SPECIFICATION, REV. 3.0", section "6.2.2 Device Control" the reset state of the command register is typically 0, so when assigning a PCI device use 0 as the initial state for the guest's (domU) view of the command register. Here is the full list of command register bits with notes about PCI/PCIe specification, and how Xen handles the bit. QEMU's behavior is also documented here since that is our current reference implementation for PCI passthrough. PCI_COMMAND_IO (bit 0) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. QEMU sets this bit to 1 in hardware if an I/O BAR is exposed to the guest. Xen domU: (rsvdp_mask) We treat this bit as RsvdP for now since we don't yet support I/O BARs for domUs. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_MEMORY (bit 1) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. QEMU sets this bit to 1 in hardware if a Memory BAR is exposed to the guest. Xen domU/dom0: We handle writes to this bit by mapping/unmapping BAR regions. Xen domU: For devices assigned to DomUs, memory decoding will be disabled at the time of initialization. PCI_COMMAND_MASTER (bit 2) PCIe 6.1: RW PCI LB 3.0: RW QEMU: Pass through writes to hardware. Xen domU/dom0: Pass through writes to hardware. PCI_COMMAND_SPECIAL (bit 3) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: RW QEMU: Pass through writes to hardware. Xen domU/dom0: Pass through writes to hardware. PCI_COMMAND_INVALIDATE (bit 4) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: RW QEMU: Pass through writes to hardware. Xen domU/dom0: Pass through writes to hardware. PCI_COMMAND_VGA_PALETTE (bit 5) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: RW QEMU: Pass through writes to hardware. Xen domU/dom0: Pass through writes to hardware. PCI_COMMAND_PARITY (bit 6) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. Xen domU: (rsvdp_mask) We treat this bit as RsvdP. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_WAIT (bit 7) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: hardwire to 0 QEMU: res_mask Xen domU: (rsvdp_mask) We treat this bit as RsvdP. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_SERR (bit 8) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. Xen domU: (rsvdp_mask) We treat this bit as RsvdP. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_FAST_BACK (bit 9) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. Xen domU: (rsvdp_mask) We treat this bit as RsvdP. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_INTX_DISABLE (bit 10) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. QEMU checks if INTx was mapped for a device. If it is not, then guest can't control PCI_COMMAND_INTX_DISABLE bit. Xen domU: We prohibit a guest from enabling INTx if MSI(X) is enabled. Xen dom0: We allow dom0 to control this bit freely. Bits 11-15 PCIe 6.1: RsvdP PCI LB 3.0: Reserved QEMU: res_mask Xen domU/dom0: rsvdp_mask Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand --- In v12: - Rework patch using vpci_add_register_mask() - Add bitmask #define in pci_regs.h according to PCIe 6.1 spec, except don't add the RO bits because they were RW in PCI LB 3.0 spec. - Move and expand TODO comment about properly emulating bits - Update guest_cmd in msi.c/msix.c:control_write() - Simplify cmd_write(), thanks to rsvdp_mask - Update commit description In v11: - Fix copy-paste mistake: vpci->msi should be vpci->msix - Handle PCI_COMMAND_IO - Fix condition for disabling INTx in the MSI-X code - Show domU changes to only allowed bits - Show PCI_COMMAND_MEMORY write only after P2M was altered - Update comments in the code In v10: - Added cf_check attribute to guest_cmd_read - Removed warning about non-zero cmd - Updated comment MSI code regarding disabling INTX - Used ternary operator in vpci_add_register() call - Disable memory decoding for DomUs in init_bars() In v9: - Reworked guest_cmd_read - Added handling for more bits Since v6: - fold guest's logic into cmd_write - implement cmd_read, so we can report emulated INTx state to guests - introduce header->guest_cmd to hold the emulated state of the PCI_COMMAND register for guests Since v5: - add additional check for MSI-X enabled while altering INTX bit - make sure INTx disabled while guests enable MSI/MSI-X Since v3: - gate more code on CONFIG_HAS_MSI - removed logic for the case when MSI/MSI-X not enabled --- xen/drivers/vpci/header.c | 59 +++++++++++++++++++++++++++++++++++--- xen/drivers/vpci/msi.c | 9 ++++++ xen/drivers/vpci/msix.c | 7 +++++ xen/include/xen/pci_regs.h | 1 + xen/include/xen/vpci.h | 3 ++ 5 files changed, 75 insertions(+), 4 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index f0b0b64b0929..374e8e119231 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -168,6 +168,9 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, if ( !rom_only ) { pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); + /* Show DomU that we updated P2M */ + header->guest_cmd &= ~PCI_COMMAND_MEMORY; + header->guest_cmd |= cmd & PCI_COMMAND_MEMORY; header->bars_mapped = map; } else @@ -524,9 +527,26 @@ static void cf_check cmd_write( { struct vpci_header *header = data; + if ( !is_hardware_domain(pdev->domain) ) + { + const struct vpci *vpci = pdev->vpci; + + if ( (vpci->msi && vpci->msi->enabled) || + (vpci->msix && vpci->msix->enabled) ) + cmd |= PCI_COMMAND_INTX_DISABLE; + + /* + * Do not show change to PCI_COMMAND_MEMORY bit until we finish + * modifying P2M mappings. + */ + header->guest_cmd = (cmd & ~PCI_COMMAND_MEMORY) | + (header->guest_cmd & PCI_COMMAND_MEMORY); + } + /* * Let Dom0 play with all the bits directly except for the memory - * decoding one. + * decoding one. Bits that are not allowed for DomU are already + * handled above and by the rsvdp_mask. */ if ( header->bars_mapped != !!(cmd & PCI_COMMAND_MEMORY) ) /* @@ -540,6 +560,14 @@ static void cf_check cmd_write( pci_conf_write16(pdev->sbdf, reg, cmd); } +static uint32_t cf_check guest_cmd_read( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + const struct vpci_header *header = data; + + return header->guest_cmd; +} + static void cf_check bar_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { @@ -756,9 +784,23 @@ static int cf_check init_header(struct pci_dev *pdev) return -EOPNOTSUPP; } - /* Setup a handler for the command register. */ - rc = vpci_add_register(pdev->vpci, vpci_hw_read16, cmd_write, PCI_COMMAND, - 2, header); + /* + * Setup a handler for the command register. + * + * TODO: If support for emulated bits is added, re-visit how to handle + * PCI_COMMAND_PARITY, PCI_COMMAND_SERR, and PCI_COMMAND_FAST_BACK. + */ + rc = vpci_add_register_mask(pdev->vpci, + is_hwdom ? vpci_hw_read16 : guest_cmd_read, + cmd_write, PCI_COMMAND, 2, header, 0, 0, + PCI_COMMAND_RSVDP_MASK | + (is_hwdom ? 0 + : PCI_COMMAND_IO | + PCI_COMMAND_PARITY | + PCI_COMMAND_WAIT | + PCI_COMMAND_SERR | + PCI_COMMAND_FAST_BACK), + 0); if ( rc ) return rc; @@ -843,6 +885,15 @@ static int cf_check init_header(struct pci_dev *pdev) if ( cmd & PCI_COMMAND_MEMORY ) pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMORY); + /* + * Clear PCI_COMMAND_MEMORY and PCI_COMMAND_IO for DomUs, so they will + * always start with memory decoding disabled and to ensure that we will not + * call modify_bars() at the end of this function. + */ + if ( !is_hwdom ) + cmd &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + header->guest_cmd = cmd; + for ( i = 0; i < num_bars; i++ ) { uint8_t reg = PCI_BASE_ADDRESS_0 + i * 4; diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 6ff71e5f9ab7..aae8055ce92d 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -70,6 +70,15 @@ static void cf_check control_write( if ( vpci_msi_arch_enable(msi, pdev, vectors) ) return; + + /* + * Make sure domU doesn't enable INTx while enabling MSI. + */ + if ( !is_hardware_domain(pdev->domain) ) + { + pci_intx(pdev, false); + pdev->vpci->header.guest_cmd |= PCI_COMMAND_INTX_DISABLE; + } } else vpci_msi_arch_disable(msi, pdev); diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index b6abab47efdd..d4f756ce287a 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -135,6 +135,13 @@ static void cf_check control_write( } } + /* Make sure domU doesn't enable INTx while enabling MSI-X. */ + if ( new_enabled && !msix->enabled && !is_hardware_domain(pdev->domain) ) + { + pci_intx(pdev, false); + pdev->vpci->header.guest_cmd |= PCI_COMMAND_INTX_DISABLE; + } + msix->masked = new_masked; msix->enabled = new_enabled; diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index 9909b27425a5..b2f2e43e864d 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -48,6 +48,7 @@ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ +#define PCI_COMMAND_RSVDP_MASK 0xf800 #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index e89c571890b2..77320a667e55 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -107,6 +107,9 @@ struct vpci { } bars[PCI_HEADER_NORMAL_NR_BARS + 1]; /* At most 6 BARS + 1 expansion ROM BAR. */ + /* Guest (domU only) view of the PCI_COMMAND register. */ + uint16_t guest_cmd; + /* * Store whether the ROM enable bit is set (doesn't imply ROM BAR * is mapped into guest p2m) if there's a ROM BAR on the device. From patchwork Tue Jan 9 21:51:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515422 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25BFFC4706C for ; Tue, 9 Jan 2024 22:03:57 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665079.1035301 (Exim 4.92) (envelope-from ) id 1rNKCK-0008LS-UQ; Tue, 09 Jan 2024 22:03:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665079.1035301; Tue, 09 Jan 2024 22:03:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNKCK-0008LL-PH; Tue, 09 Jan 2024 22:03:48 +0000 Received: by outflank-mailman (input) for mailman id 665079; Tue, 09 Jan 2024 22:03:47 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK3E-0007gG-Am for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:54:24 +0000 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2062d.outbound.protection.outlook.com [2a01:111:f400:7eaa::62d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a5b93a9c-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:54:22 +0100 (CET) Received: from MN2PR12CA0022.namprd12.prod.outlook.com (2603:10b6:208:a8::35) by SA1PR12MB7039.namprd12.prod.outlook.com (2603:10b6:806:24e::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:54:19 +0000 Received: from BL6PEPF0001AB4E.namprd04.prod.outlook.com (2603:10b6:208:a8:cafe::10) by MN2PR12CA0022.outlook.office365.com (2603:10b6:208:a8::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.17 via Frontend Transport; Tue, 9 Jan 2024 21:54:18 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4E.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:54:18 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:54:18 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Tue, 9 Jan 2024 13:54:18 -0800 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:54:16 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a5b93a9c-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Q9BtIlizngkNSUc/TM76ErL6XdoEY2phrbSmdte7XhmX9iwS/cyDoqdaw4CCdwi/G64CFQG7TTdwHUzh1zbFFUhMqIIKGzQxO+QwEoCgkRTFuvLIIOUq5Gebui77UFOvUdQb6Rj4244dQV00WRAWnnbSoxRWI5KKJo9yBefT4P8kqJ8EojwsIVtVZnVRlnydtwm9cNr6Ht/XCUdDh/zpcsuPvZDFaZF++ofazneZMiAqCu1u4xXL9YZdG7KWNQYbrA/ObuQOdwxsDqxWoSozWqMwREOkotAw9OJFS99CYK2cOX7dRVjmAsqK1WmzWlsHFiOuabggA72zolb81i+bEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RzlfpTzl8irwryHRYk7h7olENGrZhukS2mcF6gt7c7w=; b=GCy/8CZ5YQHW21zvco9Bnfs76xEKP4oROxkZmxFFGLTL2zXzvoitHj9N/EX2hOzY01qKyjOQZwbYiZKN+2sdMAtkfUd1IqQhC45fcmt5c8FKlEnksG0hf1ypUTW8VmImJkLzTTufyNgpLveyG4/NJQNZXotpuNR9h/MmGVK3R9G6+nia8o7blDg+iYRrDAv9K2jPTmsPv09XCwrAQrpaIpDtq+dc+vA5Xsh44uPmW9i+uVWAVlRJBhJFhvJKiwmMElDxCf8uXo+3FuANHoX9BpxqgA3Dk0DNKCzQKXH5QcbQTmPPCl++VrzFhwpL0VYv4c7QmdPsnca4UVu8rEfgaw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RzlfpTzl8irwryHRYk7h7olENGrZhukS2mcF6gt7c7w=; b=mSXNX9wLyARp/+kLY6hWFsOC4A0AmrySPfADAoOfHMXloyMgAIPTbx0IQCss7hny8O5Prsq1/b7e3ifPc+8pHAuvjht/YwR790W5BjW4DeGOonATPaJq1XJcroD/asITlBShJbf+TyOFLrk9RQvqQggh3tzh1853C6ua/O93ib4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , "Volodymyr Babchuk" , Stewart Hildebrand Subject: [PATCH v12 11/15] vpci: add initial support for virtual PCI bus topology Date: Tue, 9 Jan 2024 16:51:26 -0500 Message-ID: <20240109215145.430207-12-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|SA1PR12MB7039:EE_ X-MS-Office365-Filtering-Correlation-Id: e25ff8bf-35b0-493b-c94f-08dc115d87c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1kY4rpoNWAyUo6LHB6bUj8h5SaQuz0mkr1VrTLi08ns8DVl71qwpd64jJaWCzwJ9l1tmx7EPN/Yw0v8rQweUFFHy/j5xuUa4ZPdUdCBFugDi7I/9z55/9APfjrRONGujtym29/6LcIADumQuqplWCL5AE1ksw9lUVLCSbGstLLUKbjUdq29kCC41U5Vaa6hWwGILHHk1MeBLmUABxFzD5pJ/RUeRBvmeBkNqAkgMe/1OFpCY9T2mPPk9dVPfxUwC2dpVgPvU1QHX6tbJkzuzI/QQUUlzzx/MaHPrkNS6QkaDzOp3MUEDygAyXjeIx0uYyYTMtOrSGN5eniUPCQxSqxLxWeG9/O+/MjKAqL9mM4j6XjltOJip775s73KNzZzY72SBgxuqs7ax9yM8u2/PnCKVfo0vAV7brrzK4tgCEVoshf59Pnm9n6XP/umEW2eNLlhQz/0CS+WWejioIu/ft5gBcn/4W5Wy4ggkw5xREXvIBe0V0vI/CiNlzkH8i9DHfkr0cT/kc5ARgwBQLq/UYcnatEr9n/u7BtUwRv+MEXepMdkmJdSQdpUcdyc7rntdN7SqB4/67BSovhwwp5j2lStTURBM6h/48rzWSs535j9YFMmwT2H4KnXd3elX7dYe88lZ3cM45VEe8r+i/E8JBvn0f/RN0PGNKbN3ajvcf/67kZ6kja9qKkQPgbPLsQiwCKqslYanXeJssniln+jjlJG2NFMXfqR2YqshDZstKdR2UD2NNOaQ3PllqkLFizpuEX1ODdHxviw/w3Cqewcr6Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(376002)(396003)(346002)(230922051799003)(186009)(82310400011)(64100799003)(1800799012)(451199024)(36840700001)(46966006)(40470700004)(83380400001)(426003)(1076003)(336012)(26005)(2616005)(36860700001)(82740400003)(47076005)(4326008)(8676002)(8936002)(7416002)(44832011)(6916009)(5660300002)(2906002)(6666004)(478600001)(316002)(70586007)(70206006)(86362001)(41300700001)(54906003)(356005)(36756003)(81166007)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:54:18.6790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e25ff8bf-35b0-493b-c94f-08dc115d87c7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7039 From: Oleksandr Andrushchenko Assign SBDF to the PCI devices being passed through with bus 0. The resulting topology is where PCIe devices reside on the bus 0 of the root complex itself (embedded endpoints). This implementation is limited to 32 devices which are allowed on a single PCI bus. Please note, that at the moment only function 0 of a multifunction device can be passed through. Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand --- In v11: - Fixed code formatting - Removed bogus write_unlock() call - Fixed type for new_dev_number In v10: - Removed ASSERT(pcidevs_locked()) - Removed redundant code (local sbdf variable, clearing sbdf during device removal, etc) - Added __maybe_unused attribute to "out:" label - Introduced HAS_VPCI_GUEST_SUPPORT Kconfig option, as this is the first patch where it is used (previously was in "vpci: add hooks for PCI device assign/de-assign") In v9: - Lock in add_virtual_device() replaced with ASSERT (thanks, Stewart) In v8: - Added write lock in add_virtual_device Since v6: - re-work wrt new locking scheme - OT: add ASSERT(pcidevs_write_locked()); to add_virtual_device() Since v5: - s/vpci_add_virtual_device/add_virtual_device and make it static - call add_virtual_device from vpci_assign_device and do not use REGISTER_VPCI_INIT machinery - add pcidevs_locked ASSERT - use DECLARE_BITMAP for vpci_dev_assigned_map Since v4: - moved and re-worked guest sbdf initializers - s/set_bit/__set_bit - s/clear_bit/__clear_bit - minor comment fix s/Virtual/Guest/ - added VPCI_MAX_VIRT_DEV constant (PCI_SLOT(~0) + 1) which will be used later for counting the number of MMIO handlers required for a guest (Julien) Since v3: - make use of VPCI_INIT - moved all new code to vpci.c which belongs to it - changed open-coded 31 to PCI_SLOT(~0) - added comments and code to reject multifunction devices with functions other than 0 - updated comment about vpci_dev_next and made it unsigned int - implement roll back in case of error while assigning/deassigning devices - s/dom%pd/%pd Since v2: - remove casts that are (a) malformed and (b) unnecessary - add new line for better readability - remove CONFIG_HAS_VPCI_GUEST_SUPPORT ifdef's as the relevant vPCI functions are now completely gated with this config - gate common code with CONFIG_HAS_VPCI_GUEST_SUPPORT New in v2 --- xen/drivers/Kconfig | 4 +++ xen/drivers/vpci/vpci.c | 57 +++++++++++++++++++++++++++++++++++++++++ xen/include/xen/sched.h | 8 ++++++ xen/include/xen/vpci.h | 11 ++++++++ 4 files changed, 80 insertions(+) diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig index db94393f47a6..780490cf8e39 100644 --- a/xen/drivers/Kconfig +++ b/xen/drivers/Kconfig @@ -15,4 +15,8 @@ source "drivers/video/Kconfig" config HAS_VPCI bool +config HAS_VPCI_GUEST_SUPPORT + bool + depends on HAS_VPCI + endmenu diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index a0e8b1012509..57cfabfd9ad3 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -40,6 +40,49 @@ extern vpci_register_init_t *const __start_vpci_array[]; extern vpci_register_init_t *const __end_vpci_array[]; #define NUM_VPCI_INIT (__end_vpci_array - __start_vpci_array) +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT +static int add_virtual_device(struct pci_dev *pdev) +{ + struct domain *d = pdev->domain; + unsigned int new_dev_number; + + if ( is_hardware_domain(d) ) + return 0; + + ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); + + /* + * Each PCI bus supports 32 devices/slots at max or up to 256 when + * there are multi-function ones which are not yet supported. + */ + if ( pdev->info.is_extfn && !pdev->info.is_virtfn ) + { + gdprintk(XENLOG_ERR, "%pp: only function 0 passthrough supported\n", + &pdev->sbdf); + return -EOPNOTSUPP; + } + new_dev_number = find_first_zero_bit(d->vpci_dev_assigned_map, + VPCI_MAX_VIRT_DEV); + if ( new_dev_number == VPCI_MAX_VIRT_DEV ) + return -ENOSPC; + + __set_bit(new_dev_number, &d->vpci_dev_assigned_map); + + /* + * Both segment and bus number are 0: + * - we emulate a single host bridge for the guest, e.g. segment 0 + * - with bus 0 the virtual devices are seen as embedded + * endpoints behind the root complex + * + * TODO: add support for multi-function devices. + */ + pdev->vpci->guest_sbdf = PCI_SBDF(0, 0, new_dev_number, 0); + + return 0; +} + +#endif /* CONFIG_HAS_VPCI_GUEST_SUPPORT */ + void vpci_deassign_device(struct pci_dev *pdev) { unsigned int i; @@ -49,6 +92,12 @@ void vpci_deassign_device(struct pci_dev *pdev) if ( !has_vpci(pdev->domain) || !pdev->vpci ) return; +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT + if ( pdev->vpci->guest_sbdf.sbdf != ~0 ) + __clear_bit(pdev->vpci->guest_sbdf.dev, + &pdev->domain->vpci_dev_assigned_map); +#endif + spin_lock(&pdev->vpci->lock); while ( !list_empty(&pdev->vpci->handlers) ) { @@ -105,6 +154,13 @@ int vpci_assign_device(struct pci_dev *pdev) INIT_LIST_HEAD(&pdev->vpci->handlers); spin_lock_init(&pdev->vpci->lock); +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT + pdev->vpci->guest_sbdf.sbdf = ~0; + rc = add_virtual_device(pdev); + if ( rc ) + goto out; +#endif + for ( i = 0; i < NUM_VPCI_INIT; i++ ) { rc = __start_vpci_array[i](pdev); @@ -112,6 +168,7 @@ int vpci_assign_device(struct pci_dev *pdev) break; } + out: __maybe_unused; if ( rc ) vpci_deassign_device(pdev); diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 37f5922f3206..b58a822847be 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -484,6 +484,14 @@ struct domain * 2. pdev->vpci->lock */ rwlock_t pci_lock; +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT + /* + * The bitmap which shows which device numbers are already used by the + * virtual PCI bus topology and is used to assign a unique SBDF to the + * next passed through virtual PCI device. + */ + DECLARE_BITMAP(vpci_dev_assigned_map, VPCI_MAX_VIRT_DEV); +#endif #endif #ifdef CONFIG_HAS_PASSTHROUGH diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 77320a667e55..053467f04982 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -21,6 +21,13 @@ typedef int vpci_register_init_t(struct pci_dev *dev); #define VPCI_ECAM_BDF(addr) (((addr) & 0x0ffff000) >> 12) +/* + * Maximum number of devices supported by the virtual bus topology: + * each PCI bus supports 32 devices/slots at max or up to 256 when + * there are multi-function ones which are not yet supported. + */ +#define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) + #define REGISTER_VPCI_INIT(x, p) \ static vpci_register_init_t *const x##_entry \ __used_section(".data.vpci." p) = x @@ -175,6 +182,10 @@ struct vpci { struct vpci_arch_msix_entry arch; } entries[]; } *msix; +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT + /* Guest SBDF of the device. */ + pci_sbdf_t guest_sbdf; +#endif #endif }; From patchwork Tue Jan 9 21:51:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4587C4706C for ; Tue, 9 Jan 2024 21:54:52 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665048.1035251 (Exim 4.92) (envelope-from ) id 1rNK3W-0003T9-MV; Tue, 09 Jan 2024 21:54:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665048.1035251; Tue, 09 Jan 2024 21:54:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK3W-0003T2-Jr; Tue, 09 Jan 2024 21:54:42 +0000 Received: by outflank-mailman (input) for mailman id 665048; Tue, 09 Jan 2024 21:54:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK3W-0003SZ-6e for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:54:42 +0000 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2062a.outbound.protection.outlook.com [2a01:111:f400:7e88::62a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b023d02b-af39-11ee-98ef-6d05b1d4d9a1; Tue, 09 Jan 2024 22:54:40 +0100 (CET) Received: from SJ0PR03CA0252.namprd03.prod.outlook.com (2603:10b6:a03:3a0::17) by SJ2PR12MB9190.namprd12.prod.outlook.com (2603:10b6:a03:554::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:54:34 +0000 Received: from SJ1PEPF00001CEA.namprd03.prod.outlook.com (2603:10b6:a03:3a0:cafe::ac) by SJ0PR03CA0252.outlook.office365.com (2603:10b6:a03:3a0::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.17 via Frontend Transport; Tue, 9 Jan 2024 21:54:34 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CEA.mail.protection.outlook.com (10.167.242.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:54:34 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:54:34 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:54:27 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b023d02b-af39-11ee-98ef-6d05b1d4d9a1 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Qc0BiCiCQS3BoatDQnZLjAwgeVo73gibk18ormyzrbMVHZESfBuByQwRULCkLskZIWw2kOVCGhLuL8sdFJCm1EcHkXPcwKS9HgeEIk1xuqpE+1CJ79Iq9wJQWMnjp2BVdOLHA5AlUDrlCjVfN2xbu9+icBg40CUC/cw4dDosWUXdDpeHMf6Pbv+g+k/pRKOtvZTncuG+/+iJxWEr4ZblfgfQv9LkfwKEWwg8HrHhC5fxhKYs9nD/LJ/snht6FX7JftNgxDoHpItEYFfGcbuRlQjjg+CrNT42oR+a4Mc5mWDm4TNbc9sAzwHk3fIUvPAz8hXVsY9olnmmaAjb+405ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xXxqm2R+KG+DNPuVmoVRc8P1hQTGMm+S12P871URecc=; b=frVQVoanV4MZOE+xUTMmzl9dbSacIETz6QfHNacws+yhfzrZr4MXANupHYDKn3jLDCv9LcqmsnCKqaGdxBOxKjY+MzhZpDDlWTOfXL8zRMCmKg/Wp8mFhRazEfuZe+LIuyDd2V1F3QYZoSIl1NZxT7YqugQpPBu0bx3CQPVVPMtVDQYK1IuW3/AgXWQ64FuVcW53qOrWf6QzpHhmsidcpalEJlxU+63hAiYOSrSlFGF7+YoTQqAN5YRcQIGvcdh/HrcB4icHc3MOdTPT9ZQW+Si9WiykuntKjnDyeIyO1xF1pFV2BBXhYgAycizMLioZTPmSL6xFmplmSLBtIgYMWw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xXxqm2R+KG+DNPuVmoVRc8P1hQTGMm+S12P871URecc=; b=3EmUpLLbKy4CDmYgkHTU5CgcnTfSWmJT0U98lN9s//5/vWrZAFJbG15vOeDM3s4SP1pZcFWMh5QwW6uUXg1lqjVgieKJ+bzGo/QQiZJm6ttdDhsv4ibRE+hLEm9ADXBus3rcVFQLRlNpgqm/bIRpwofu97fh4FDFF7Xd6CbSjqc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , "Stefano Stabellini" , Julien Grall , "Bertrand Marquis" , Michal Orzel , Volodymyr Babchuk , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= , "Volodymyr Babchuk" , Stewart Hildebrand Subject: [PATCH v12 12/15] xen/arm: translate virtual PCI bus topology for guests Date: Tue, 9 Jan 2024 16:51:27 -0500 Message-ID: <20240109215145.430207-13-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|SJ2PR12MB9190:EE_ X-MS-Office365-Filtering-Correlation-Id: d40471b3-af2f-4f68-767f-08dc115d916f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FoW/3jSMKiVHG0OLtejhEQLKvbkbVN5BcoHU/6kvYF14nS7GL1OjifUJil7VpSQGyr4tu5BUWB4rUzFEBZMXo06xw2k+8rn7WkzXaGjI2T42pHG9onvHZHGPhnA4rAYE8MuC7A3v5hEA/N0TPPUOWUUoqyFo2JTXVNhSQB23UnKP7hkFehYjw3e1Sc7e3so5DdmWq5rYDBlBE6cWCEllgYA/C5dntJoKEHRcrl8atCtvPjN9FLluOcFC9O/jEw56TteP2t9W8IL1Q7MJnbgWLnQKIuF+JMlJJoUl8nIgSvYURoAoSaDiRD7i89ExU2OFHLyKrfks4SXFQk07Oxi1JFkBX/igItNjIvxx2Am4wfykIeyZ2Fls5EolhhguW/ZoV4FlAkPDOm1fL4ipP/rIdlyP2tDm2Plb67xLpwRpDDO9tZzIcBAqMaHXl+BYkled4vKBjIB4KEm9XaqEp6NHNaIccrTsLbRzsLhJSUJl3JJQ57HjAh3aYBYOA6BqFoHRHCLBxQWqv2qkco0YWS97Lj0yOM8A6xmHHq35IhR7TkXExNSbv03W1ugZvwaSqK4Q90E81vJbJ704Tv0/tPIdnUtg3KJSn33W/DZUmXKMsFvYPQ1l8FbA9KwnMtwzMPHxlsmkBhqrIeWeOXL/l6esvpj0eaUrEzTOdAV9szMfS4Em1oJ5hR0QMcdsUleN6BlMGbyh9AFHqJlAxDMSZIOa8LvCCgVYpwLPUnDKdGhAbRQPcluK7b1k1/HD6ijDuNocORldzMmvBlBEwfLNhYvbfQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(136003)(376002)(346002)(230922051799003)(82310400011)(1800799012)(186009)(451199024)(64100799003)(46966006)(36840700001)(40470700004)(40480700001)(40460700003)(2906002)(478600001)(36860700001)(5660300002)(81166007)(4326008)(44832011)(356005)(41300700001)(8936002)(316002)(70206006)(70586007)(54906003)(36756003)(6916009)(2616005)(8676002)(86362001)(426003)(1076003)(26005)(336012)(83380400001)(47076005)(82740400003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:54:34.8149 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d40471b3-af2f-4f68-767f-08dc115d916f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9190 From: Oleksandr Andrushchenko There are three originators for the PCI configuration space access: 1. The domain that owns physical host bridge: MMIO handlers are there so we can update vPCI register handlers with the values written by the hardware domain, e.g. physical view of the registers vs guest's view on the configuration space. 2. Guest access to the passed through PCI devices: we need to properly map virtual bus topology to the physical one, e.g. pass the configuration space access to the corresponding physical devices. 3. Emulated host PCI bridge access. It doesn't exist in the physical topology, e.g. it can't be mapped to some physical host bridge. So, all access to the host bridge itself needs to be trapped and emulated. Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand --- In v11: - Fixed format issues - Added ASSERT_UNREACHABLE() to the dummy implementation of vpci_translate_virtual_device() - Moved variable in vpci_sbdf_from_gpa(), now it is easier to follow the logic in the function Since v9: - Commend about required lock replaced with ASSERT() - Style fixes - call to vpci_translate_virtual_device folded into vpci_sbdf_from_gpa Since v8: - locks moved out of vpci_translate_virtual_device() Since v6: - add pcidevs locking to vpci_translate_virtual_device - update wrt to the new locking scheme Since v5: - add vpci_translate_virtual_device for #ifndef CONFIG_HAS_VPCI_GUEST_SUPPORT case to simplify ifdefery - add ASSERT(!is_hardware_domain(d)); to vpci_translate_virtual_device - reset output register on failed virtual SBDF translation Since v4: - indentation fixes - constify struct domain - updated commit message - updates to the new locking scheme (pdev->vpci_lock) Since v3: - revisit locking - move code to vpci.c Since v2: - pass struct domain instead of struct vcpu - constify arguments where possible - gate relevant code with CONFIG_HAS_VPCI_GUEST_SUPPORT New in v2 --- xen/arch/arm/vpci.c | 47 +++++++++++++++++++++++++++++++---------- xen/drivers/vpci/vpci.c | 24 +++++++++++++++++++++ xen/include/xen/vpci.h | 12 +++++++++++ 3 files changed, 72 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index 3bc4bb55082a..7a6a0017d132 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -7,31 +7,51 @@ #include -static pci_sbdf_t vpci_sbdf_from_gpa(const struct pci_host_bridge *bridge, - paddr_t gpa) +static bool vpci_sbdf_from_gpa(struct domain *d, + const struct pci_host_bridge *bridge, + paddr_t gpa, pci_sbdf_t *sbdf) { - pci_sbdf_t sbdf; + bool translated = true; + + ASSERT(sbdf); if ( bridge ) { - sbdf.sbdf = VPCI_ECAM_BDF(gpa - bridge->cfg->phys_addr); - sbdf.seg = bridge->segment; - sbdf.bus += bridge->cfg->busn_start; + sbdf->sbdf = VPCI_ECAM_BDF(gpa - bridge->cfg->phys_addr); + sbdf->seg = bridge->segment; + sbdf->bus += bridge->cfg->busn_start; } else - sbdf.sbdf = VPCI_ECAM_BDF(gpa - GUEST_VPCI_ECAM_BASE); + { + /* + * For the passed through devices we need to map their virtual SBDF + * to the physical PCI device being passed through. + */ + sbdf->sbdf = VPCI_ECAM_BDF(gpa - GUEST_VPCI_ECAM_BASE); + read_lock(&d->pci_lock); + translated = vpci_translate_virtual_device(d, sbdf); + read_unlock(&d->pci_lock); + } - return sbdf; + return translated; } static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, register_t *r, void *p) { struct pci_host_bridge *bridge = p; - pci_sbdf_t sbdf = vpci_sbdf_from_gpa(bridge, info->gpa); + pci_sbdf_t sbdf; /* data is needed to prevent a pointer cast on 32bit */ unsigned long data; + ASSERT(!bridge == !is_hardware_domain(v->domain)); + + if ( !vpci_sbdf_from_gpa(v->domain, bridge, info->gpa, &sbdf) ) + { + *r = ~0UL; + return 1; + } + if ( vpci_ecam_read(sbdf, ECAM_REG_OFFSET(info->gpa), 1U << info->dabt.size, &data) ) { @@ -39,7 +59,7 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, return 1; } - *r = ~0ul; + *r = ~0UL; return 0; } @@ -48,7 +68,12 @@ static int vpci_mmio_write(struct vcpu *v, mmio_info_t *info, register_t r, void *p) { struct pci_host_bridge *bridge = p; - pci_sbdf_t sbdf = vpci_sbdf_from_gpa(bridge, info->gpa); + pci_sbdf_t sbdf; + + ASSERT(!bridge == !is_hardware_domain(v->domain)); + + if ( !vpci_sbdf_from_gpa(v->domain, bridge, info->gpa, &sbdf) ) + return 1; return vpci_ecam_write(sbdf, ECAM_REG_OFFSET(info->gpa), 1U << info->dabt.size, r); diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 57cfabfd9ad3..6e2d428d691b 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -81,6 +81,30 @@ static int add_virtual_device(struct pci_dev *pdev) return 0; } +/* + * Find the physical device which is mapped to the virtual device + * and translate virtual SBDF to the physical one. + */ +bool vpci_translate_virtual_device(const struct domain *d, pci_sbdf_t *sbdf) +{ + const struct pci_dev *pdev; + + ASSERT(!is_hardware_domain(d)); + ASSERT(rw_is_locked(&d->pci_lock)); + + for_each_pdev ( d, pdev ) + { + if ( pdev->vpci && (pdev->vpci->guest_sbdf.sbdf == sbdf->sbdf) ) + { + /* Replace guest SBDF with the physical one. */ + *sbdf = pdev->sbdf; + return true; + } + } + + return false; +} + #endif /* CONFIG_HAS_VPCI_GUEST_SUPPORT */ void vpci_deassign_device(struct pci_dev *pdev) diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 053467f04982..3cfd9a401178 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -302,6 +302,18 @@ static inline bool __must_check vpci_process_pending(struct vcpu *v) } #endif +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT +bool vpci_translate_virtual_device(const struct domain *d, pci_sbdf_t *sbdf); +#else +static inline bool vpci_translate_virtual_device(const struct domain *d, + pci_sbdf_t *sbdf) +{ + ASSERT_UNREACHABLE(); + + return false; +} +#endif + #endif /* From patchwork Tue Jan 9 21:51:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 842BEC4706C for ; Tue, 9 Jan 2024 21:55:11 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665050.1035261 (Exim 4.92) (envelope-from ) id 1rNK3q-0003tn-2T; Tue, 09 Jan 2024 21:55:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665050.1035261; Tue, 09 Jan 2024 21:55:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK3p-0003tg-Tx; Tue, 09 Jan 2024 21:55:01 +0000 Received: by outflank-mailman (input) for mailman id 665050; Tue, 09 Jan 2024 21:55:00 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK3o-0003SZ-Qy for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:55:00 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2062c.outbound.protection.outlook.com [2a01:111:f400:fe5a::62c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id bb6fe35c-af39-11ee-98ef-6d05b1d4d9a1; Tue, 09 Jan 2024 22:55:00 +0100 (CET) Received: from SJ0PR05CA0188.namprd05.prod.outlook.com (2603:10b6:a03:330::13) by PH0PR12MB7888.namprd12.prod.outlook.com (2603:10b6:510:28b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:54:54 +0000 Received: from SJ1PEPF00001CEB.namprd03.prod.outlook.com (2603:10b6:a03:330:cafe::cb) by SJ0PR05CA0188.outlook.office365.com (2603:10b6:a03:330::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.17 via Frontend Transport; Tue, 9 Jan 2024 21:54:53 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CEB.mail.protection.outlook.com (10.167.242.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:54:53 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:54:50 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:54:44 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bb6fe35c-af39-11ee-98ef-6d05b1d4d9a1 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IiBl8ClfkYnTxi/Xyj8Ga5UXNGV/baEq5apBTm36tQiOpxa1C8ohnoDpWyWlT62vrmiwsUa566Idg4vDHl8MWq2Tujf60V4D5QGdFSz19gHGQxiTyp6n+Jxzz7M3UoTcfi9kMesPtoiRIcvWSFVvr/Zn8XgPuHGT2KB5SRpezY8zpCRNYvsGp7bB2ESJT2kJTt3kanRjqp5UwBqcoYuuvQoaXZpxeGV03PA5gWBPPCMRUf2hIOmtifBG/IxCwYlvJtYDUEUodVooMBWDE1yvtP+EZ1BV3O9Dsx5uWtcdjiRzga5bU8DxMVMbXotNWAmnK7seszn4sEEHmQJhmV/6Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PsoOL/G8DIgXV37+ao0tajW6v6ZQDcdP8FQCKLy06D4=; b=S1ytKzBBBuRm/e9Ea9bFI4XiicMcIx/YHQFCKg8tw4gaH+KErmHoIxJQWM0RPreYG3FI7FUk3h9IrWI6AiwIC3kWLH1SpFGjPzmo9EKiAe8iohKLo7TCCfBKvuO9KvfgAeHYy6iUOvNc1wZtgvELtxjUL0YZaPs/hAsPHlhdwuAmy714ePS5egRFCm9wkg1lg0wblzOAIRgBpfYBL2m0JqXnZtWw+qW6iO1S/H7E7Hz2thGfB9gLgOpeyhpw7da+2PwzMhl8Lzi+XUp5cz2xy5s4scJ558/wboqVspBwvarkEy1sCNxo2+k9KCsiOobRo55RIieUUpUZSxkZZ0YJuQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PsoOL/G8DIgXV37+ao0tajW6v6ZQDcdP8FQCKLy06D4=; b=EMUPFIapm7SX2CZwngMiuUbU8sSFWQO/3WmL/bkEpCucvt1HdA3ISwSAi3Nbh2QDlc5OEOnFV6KzrSGG5dUs8WZKLdtlgtlYgu/3GIC7q7L+Mxi55csLeZOY5FLCCt3LqJv4XdIzBwUpMNRrxb+31/W9YQ+7GGG1J2HlBP91nfQ= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , "Stefano Stabellini" , Julien Grall , "Bertrand Marquis" , Michal Orzel , Volodymyr Babchuk , Julien Grall , Volodymyr Babchuk , "Stewart Hildebrand" Subject: [PATCH v12 13/15] xen/arm: account IO handlers for emulated PCI MSI-X Date: Tue, 9 Jan 2024 16:51:28 -0500 Message-ID: <20240109215145.430207-14-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|PH0PR12MB7888:EE_ X-MS-Office365-Filtering-Correlation-Id: 670b2910-6897-4576-99ce-08dc115d9c87 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xbttFXelL7degQf26Jl6Kd01+Kx1dejBkgh0Rnlei0Q1P0CrFRAytzXQmoAeWWFcuKE2uNxATcJ8dHPD/GiMYdXi+8x9V5e8+XRFIX+2GkDIBYQao4JQ8/n4pxnUkBpK+a+r0eYQJwQVg41tMOm6qn1JFfdEWzIKiD/I/BsQVONnpG+RZW/AnZOm4rO6LYxBQc23Q1n+ueOUopNUNzVdmAlUQ52V1MP7N7/UKLX2D2J/TpXfOHSX5Gxoq/qVnyXt+lEkrGCac8iJCwE2hM6uwbLs6irWtiOqdRscMBA3F4m1rXh4g5My57iBu2YXKZfn5qw8Tr9a2tdec0UaMNxsCL3MGNiyekZSrK53yagI35tW50q2+/XmyMUhmPwhij5fRQkRos0IMZlAQZaGnF0gPlSVLKwvNeI2lf3XAyurlU+T00wpTAYPnBrwkKQOAVSimnmVnNy2EmSk++o5THw6iSzeL9uRKbaif2yn2rbRUl5xwqn7ATdgW1wwBPquVf0m+VfHu8pm2OE3i8QPr8mc1mQCXPjiEcOwA57+5I1IC7Owm3prObNh1VRqj16XUbEyr8svWSP/FJS1okPBFu5O7PJyJa241BtoYfxV+gq2mOV+Sa89zRYvohoagmEmWsh2N8SDNSKMVRZNBgwEOEKmw+FzaVxwUWf67/6XWkE+LBjHqfRa87eVETm4mKDwIP1f39V9WCdf4dpIPlS9ERGBsKmj6a0tn94QgKJYh/SFOP6mK/qpvoJC0iTy2URJx+n+Y0stmlWDZ6Zjqt2MboB/Ow== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(376002)(396003)(346002)(230922051799003)(186009)(82310400011)(64100799003)(1800799012)(451199024)(36840700001)(46966006)(40470700004)(83380400001)(426003)(1076003)(336012)(26005)(2616005)(36860700001)(82740400003)(47076005)(4326008)(8676002)(8936002)(44832011)(15650500001)(6916009)(5660300002)(2906002)(6666004)(478600001)(316002)(70586007)(70206006)(86362001)(41300700001)(54906003)(356005)(36756003)(81166007)(40480700001)(66899024)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:54:53.4280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 670b2910-6897-4576-99ce-08dc115d9c87 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7888 From: Oleksandr Andrushchenko At the moment, we always allocate an extra 16 slots for IO handlers (see MAX_IO_HANDLER). So while adding IO trap handlers for the emulated MSI-X registers we need to explicitly tell that we have additional IO handlers, so those are accounted. Signed-off-by: Oleksandr Andrushchenko Acked-by: Julien Grall Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand --- This actually moved here from the part 2 of the prep work for PCI passthrough on Arm as it seems to be the proper place for it. Since v5: - optimize with IS_ENABLED(CONFIG_HAS_PCI_MSI) since VPCI_MAX_VIRT_DEV is defined unconditionally New in v5 --- xen/arch/arm/vpci.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index 7a6a0017d132..348ba0fbc860 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -130,6 +130,8 @@ static int vpci_get_num_handlers_cb(struct domain *d, unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d) { + unsigned int count; + if ( !has_vpci(d) ) return 0; @@ -150,7 +152,17 @@ unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d) * For guests each host bridge requires one region to cover the * configuration space. At the moment, we only expose a single host bridge. */ - return 1; + count = 1; + + /* + * There's a single MSI-X MMIO handler that deals with both PBA + * and MSI-X tables per each PCI device being passed through. + * Maximum number of emulated virtual devices is VPCI_MAX_VIRT_DEV. + */ + if ( IS_ENABLED(CONFIG_HAS_PCI_MSI) ) + count += VPCI_MAX_VIRT_DEV; + + return count; } /* From patchwork Tue Jan 9 21:51:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F220C4706C for ; Tue, 9 Jan 2024 21:55:22 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665052.1035271 (Exim 4.92) (envelope-from ) id 1rNK42-0004IP-A7; Tue, 09 Jan 2024 21:55:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665052.1035271; Tue, 09 Jan 2024 21:55:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK42-0004II-6V; Tue, 09 Jan 2024 21:55:14 +0000 Received: by outflank-mailman (input) for mailman id 665052; Tue, 09 Jan 2024 21:55:12 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK40-0003ql-D2 for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:55:12 +0000 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on20601.outbound.protection.outlook.com [2a01:111:f403:2412::601]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c276fa03-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:55:10 +0100 (CET) Received: from BLAP220CA0012.NAMP220.PROD.OUTLOOK.COM (2603:10b6:208:32c::17) by MW4PR12MB7262.namprd12.prod.outlook.com (2603:10b6:303:228::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23; Tue, 9 Jan 2024 21:55:05 +0000 Received: from BL6PEPF0001AB4F.namprd04.prod.outlook.com (2603:10b6:208:32c:cafe::6b) by BLAP220CA0012.outlook.office365.com (2603:10b6:208:32c::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.23 via Frontend Transport; Tue, 9 Jan 2024 21:55:05 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4F.mail.protection.outlook.com (10.167.242.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:55:04 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:55:04 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:55:04 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:55:02 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c276fa03-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=W1kmXkcivhmxB0LSnjBAQftoBe1GsxXGF9sILGmhe6yshJBV7toPL6Rolc+2sUGUOb3Vt1XHlXvIHHb3gR9w2ZG8TFpx2uBDJs7hpi7/VZD4DV60Nx3MCq64zx5xNzxbX6DwcsfhBFbVxmoQ83HNE4Qn3j04MRowsT1mClxqyCZcsN+HvzAZEgaJ26kP1Z4tpYbw16hAQrK4nJRQGuoITgM9rh5G2QhDEq2HEdzD3bKAwbFfuaDGhLdXvebdOhh4VV1M+bGt6T70SnI2K37xOQZCHVYlYCTRXhKnoz377JXeJKBRRQNbSG8FPuml3dl5F8W7JGqjyJv7UllgIBC0Eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Sds9Y/npwbMXFe2dWuz/kb6byGvdHn8OQgeszTqP9BU=; b=Mg2/Fu1E0TwcnYFP8X4bUxgJtad9udpaZgNKaOj0Magq70PZDsPYvRkoMnDwzsAwVfYQX5hEsqTHigryRC1bQFvaMnu+wGE8wxOLkT/9WxnjbXrAPUu0ytWOz9BBTYoouRjP3yZM2kwBv6cP+L9TE5p+R8iYL8dDy9pI8IyrQRqZdy6Dg5qd078Mg45CbBDnE3byRyBHdQrNbEgK9/LkkJOQ53F4Xe02J/0sHC2LZmRUaS84hoWWEc4n7Ttz6Ks0nuWrLH5wD0QDAOFr+jR68/jNwly49++umzY9Wv5Os3QLcbAPp+Fwdee0hukyjxpVtp9IFJuYOWAgZH0Cp8St8w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Sds9Y/npwbMXFe2dWuz/kb6byGvdHn8OQgeszTqP9BU=; b=TYhbABS3gl/hk/31rMNUv0zLynkV37MBk7U663m1YfWgvvW8CpdnZOLsiaLYz+zxlQDbUOcIx540fZu7UQPuHlrezol4MBxWFCjs3obrMrzeHb2ZSzSWp8vCtdAvz6FVpymM2MCArePlK4x9umc+MuQ7UPRAVS7y7udBUQHzOlw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Andrew Cooper , George Dunlap , "Jan Beulich" , Wei Liu Subject: [PATCH v12 14/15] xen/arm: vpci: permit access to guest vpci space Date: Tue, 9 Jan 2024 16:51:29 -0500 Message-ID: <20240109215145.430207-15-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4F:EE_|MW4PR12MB7262:EE_ X-MS-Office365-Filtering-Correlation-Id: fbe115e6-b59a-4f06-1915-08dc115da358 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ns4bMm7h8Eig2xdrhP0Uc2Cnw8FSxIEf3jPMOhRDi5z7lfczCnfiIFs3gmB5lQA5lNmoAPsU1XyXQuYQyXSqfF+YdTvQHpbAT8uTFh9WK7QSI5t9SinL3Q49dSu7Fk+G/wyU4bRDpydxCoanr2gVmwG9msbclY+Jzcy8vCGqvOIhTwYwJMpoAsaCET6nzu+5V/UTTQ5LrbOlt5NiuS8Ej5GnaL+D/DkUxaR4gLiVY5MvQD0naSyQEQ3JHL3bWHMTDheGyRV8haC0jmtItwEeRLzGsZJchtH5ZOyJED4YZnc8ap/z0RkeLPRFAN0qhdQqBIA1D2dSMNVX1EBig2X3ChYzd0C33C4BG/cGtGkuFmI05ilV17B2aWtIhzpAB9nHqn1VOwk/oOHFcrYPZO0fqR0D8ViHbP4owVfsMdZ2ugSYudYdm4ANvykzTjZUDN2rdujt4jY0g3m0upeCyXgL/lqRqWIPnUUWYjgmiwZgFxU7W/JHJlJeEBkKOMuP0RJspKdqahwRwQOPVaLdI9nUDhbesI753vCunDQ0dWrXFKaFPW+w2telVNHLTAJqk7n+hYQ8kWit1KxJLBxLsFPmVRqZ9SXN7eT8LLHMoA/hdp2eQ73FlX6rJIvv2Z3Bu8QCOF/d8ZmmQ2bqZppCwpEffwWHeg3uHnurUtf0KQEh83McQfAFh+igsjlBViLYy3XbnUHc8Z4yySDdCBuKvBAJ5mTQklpuHk8ZngieI/OGQTjS+5PNF+v69uDG87KqZSJLUoit+uncEHJMw/gEscS62Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(39860400002)(376002)(346002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(82310400011)(36840700001)(40470700004)(46966006)(83380400001)(26005)(426003)(1076003)(336012)(2616005)(36860700001)(47076005)(82740400003)(4326008)(8936002)(8676002)(5660300002)(44832011)(2906002)(6916009)(6666004)(478600001)(54906003)(316002)(41300700001)(70586007)(70206006)(356005)(81166007)(36756003)(86362001)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:55:04.8452 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbe115e6-b59a-4f06-1915-08dc115da358 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7262 Move iomem_caps initialization earlier (before arch_domain_create()). Signed-off-by: Stewart Hildebrand --- Changes in v11: * move both iomem_caps and irq_caps initializations earlier, along with NULL check Changes in v10: * fix off-by-one * also permit access to GUEST_VPCI_PREFETCH_MEM_ADDR Changes in v9: * new patch This is sort of a follow-up to: baa6ea700386 ("vpci: add permission checks to map_range()") I don't believe we need a fixes tag since this depends on the vPCI p2m BAR patches. --- xen/arch/arm/vpci.c | 9 +++++++++ xen/common/domain.c | 12 ++++++------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index 348ba0fbc860..b6ef440f17b0 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -2,6 +2,7 @@ /* * xen/arch/arm/vpci.c */ +#include #include #include @@ -115,8 +116,16 @@ int domain_vpci_init(struct domain *d) return ret; } else + { register_mmio_handler(d, &vpci_mmio_handler, GUEST_VPCI_ECAM_BASE, GUEST_VPCI_ECAM_SIZE, NULL); + iomem_permit_access(d, paddr_to_pfn(GUEST_VPCI_MEM_ADDR), + paddr_to_pfn(GUEST_VPCI_MEM_ADDR + + GUEST_VPCI_MEM_SIZE - 1)); + iomem_permit_access(d, paddr_to_pfn(GUEST_VPCI_PREFETCH_MEM_ADDR), + paddr_to_pfn(GUEST_VPCI_PREFETCH_MEM_ADDR + + GUEST_VPCI_PREFETCH_MEM_SIZE - 1)); + } return 0; } diff --git a/xen/common/domain.c b/xen/common/domain.c index f6f557499660..8078d1ade690 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -693,6 +693,12 @@ struct domain *domain_create(domid_t domid, d->nr_pirqs = min(d->nr_pirqs, nr_irqs); radix_tree_init(&d->pirq_tree); + + err = -ENOMEM; + d->iomem_caps = rangeset_new(d, "I/O Memory", RANGESETF_prettyprint_hex); + d->irq_caps = rangeset_new(d, "Interrupts", 0); + if ( !d->iomem_caps || !d->irq_caps ) + goto fail; } if ( (err = arch_domain_create(d, config, flags)) != 0 ) @@ -711,12 +717,6 @@ struct domain *domain_create(domid_t domid, watchdog_domain_init(d); init_status |= INIT_watchdog; - err = -ENOMEM; - d->iomem_caps = rangeset_new(d, "I/O Memory", RANGESETF_prettyprint_hex); - d->irq_caps = rangeset_new(d, "Interrupts", 0); - if ( !d->iomem_caps || !d->irq_caps ) - goto fail; - if ( (err = xsm_domain_create(XSM_HOOK, d, config->ssidref)) != 0 ) goto fail; From patchwork Tue Jan 9 21:51:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13515420 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9BF5C4706C for ; Tue, 9 Jan 2024 21:55:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.665053.1035281 (Exim 4.92) (envelope-from ) id 1rNK4E-0004mx-PM; Tue, 09 Jan 2024 21:55:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 665053.1035281; Tue, 09 Jan 2024 21:55:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK4E-0004mO-KJ; Tue, 09 Jan 2024 21:55:26 +0000 Received: by outflank-mailman (input) for mailman id 665053; Tue, 09 Jan 2024 21:55:25 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rNK4D-0003ql-7E for xen-devel@lists.xenproject.org; Tue, 09 Jan 2024 21:55:25 +0000 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on20600.outbound.protection.outlook.com [2a01:111:f403:2009::600]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c9adeb7b-af39-11ee-9b0f-b553b5be7939; Tue, 09 Jan 2024 22:55:23 +0100 (CET) Received: from SJ0PR03CA0195.namprd03.prod.outlook.com (2603:10b6:a03:2ef::20) by CH2PR12MB4326.namprd12.prod.outlook.com (2603:10b6:610:af::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.17; Tue, 9 Jan 2024 21:55:20 +0000 Received: from SJ1PEPF00001CE6.namprd03.prod.outlook.com (2603:10b6:a03:2ef:cafe::ce) by SJ0PR03CA0195.outlook.office365.com (2603:10b6:a03:2ef::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7159.25 via Frontend Transport; Tue, 9 Jan 2024 21:55:20 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00001CE6.mail.protection.outlook.com (10.167.242.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Tue, 9 Jan 2024 21:55:20 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 9 Jan 2024 15:55:19 -0600 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 9 Jan 2024 15:55:13 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c9adeb7b-af39-11ee-9b0f-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bd5HjMCqvBekugTEjrpyaS6ANo2q8gssnhqrzxYZxmFlWRCEHJBc7FfqAoGQouZS+8YGbe+udzCB/Efj80Z5XWap3xN8eswlPxV7YQL79HOMTIdcyVSDBRKifs3Ru9sbNJlipjqqsbeP4ZfVAN3X6MW6d+1ams1yTYyxDEWmDiyvSV8hkW4e8nbYFgm3uongglvJmqInL66P8ukH1nZgn/DrO3eZzI5/vo/VqG0zRtd4MjISlnTjOIdljmzhb7ih0G/0DQ2x9pA6D75MXK9OGfvi33Bm53o0E3Rx4PjDegjdMO5FRoEKFqh4WG7xU/6QS0GxCMrCodnu9+WEJ90CbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UMvnpYtMsr+XyhV7s4jn4yVI4a71Jl58SaqRvfzmz4E=; b=hRWeCL1gZ0UXku6fhKw/+XUNShm+4f7ma7DxypjnuBXoOCeMc1yLMu+73qcWlXRYyPWU6l0QPmUyjhki4fWnBg/DiUsGrHTjd7CojEotcuu4a0onAZS3+spp7hY/6VZPK9UBHLxtS0vcpjRr2UYcw4ktmVtN5x53qkRquOl3JS1Hgf2+e7NFM0UapX+zFv4tFKe3VwZrwSGcR6z+vHnwfqHV/tTm6PQbdeuNYf/vli5eETPi2C8HScSi9JWWq98FWkiCRUbiKMxmWJFUUO8nemOPATiBt/TBD1mZCEWQ2NbHwDzG9I0RYMjh9uNHFaI5SvPg8fpiVnkiDuLDlnO26w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UMvnpYtMsr+XyhV7s4jn4yVI4a71Jl58SaqRvfzmz4E=; b=v5XnFYjeP+bT2ni0jm4sbqjzfwhLRYm5aIZr4KP4XhlfsLhqil6i9mneoy+QTHl8IMhMrim9qMg0ojSvHgBsagQxPJE+wgoN0O177rCxNJ2gkLWbRi/indb0PBFCIXXSVnlBxlZ2awPIbgEcOswAoehtutY7b9fOYkbGpqQZzyY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Stewart Hildebrand Subject: [PATCH v12 15/15] arm/vpci: honor access size when returning an error Date: Tue, 9 Jan 2024 16:51:30 -0500 Message-ID: <20240109215145.430207-16-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109215145.430207-1-stewart.hildebrand@amd.com> References: <20240109215145.430207-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE6:EE_|CH2PR12MB4326:EE_ X-MS-Office365-Filtering-Correlation-Id: c3589657-cb2f-479a-79fd-08dc115daca5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uTbryQmsQTZ2QgQasnldQSiBljJxmtfvG+q11RceWgGOjMTONsZZ39mm3ZL7uxXO8A319HprVvDtYB34R6Bgcg1f0YcFTBs+p+RCuVKfHuZ/hvBFOeIPv4pdKQqkvNdiv4OuSBqsoz3+DoQs+Sg91cRMOTw+K1P6XbFt5GENXbt53QEdLOyvl8SYYqnTgORiPqW9MJqbm9gq1+cs8k/z//ufVtB96icdJ2VWQRVqDJyOpE2OR9kih5NQuC4CEAOObZ2ivvncVbrH6kJ2KiAgsRWKC64Iluwr8Fo5ozPfWq0G2blQuWW8/6Ohj2d3uQlKnMRd4hievrFVmn593sdcfz0fgdkWiy8sOPdelXDujBUiVwdxans2a5iY+A+jnWiR+qf/P4GUmq8XKptYj/c599vIShHBWR05YiKWF8kj0bvq5ftYvDODJN23vC58RCiASx6fB05q5wrDZ5sA4W3xv1gJWnXopreocob4nXfXyzjKVVml2lMukWW2DpVqy+ozMZ2up3G8H100VPocofpu1Arb1X33lS1TgmnWMeZe++9gKdRuwSzvqGEUDF/eF7vO0TtvqlXvtD//8HLGICJGkF7IzNa9KrBpQ1oFNdM4VwbkQeODAVgTbsxbYN8g4t3nuBSUOxfrL+itVE8WkCVmMsaIw/oK0kFPDSJgwLxgeOwz/QhJBohbdZ0rK2GOZmfbBtgLFM3OweVo7Kk2dbu/EP2SHmFO4USPeYl1RtKY6CZWxm+4L5kBpTYcTjf9sY3NnKXizJEc7I1RQEa5cBbqVQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(396003)(376002)(346002)(230922051799003)(451199024)(64100799003)(82310400011)(186009)(1800799012)(40470700004)(46966006)(36840700001)(36860700001)(6666004)(5660300002)(478600001)(70206006)(2616005)(86362001)(41300700001)(8676002)(8936002)(54906003)(426003)(70586007)(316002)(6916009)(47076005)(82740400003)(83380400001)(1076003)(26005)(336012)(81166007)(356005)(4326008)(36756003)(44832011)(40480700001)(2906002)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 21:55:20.4674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3589657-cb2f-479a-79fd-08dc115daca5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4326 From: Volodymyr Babchuk Guest can try to read config space using different access sizes: 8, 16, 32, 64 bits. We need to take this into account when we are returning an error back to MMIO handler, otherwise it is possible to provide more data than requested: i.e. guest issues LDRB instruction to read one byte, but we are writing 0xFFFFFFFFFFFFFFFF in the target register. Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand --- xen/arch/arm/vpci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index b6ef440f17b0..05a479096ef7 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -42,6 +42,8 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, { struct pci_host_bridge *bridge = p; pci_sbdf_t sbdf; + const uint8_t access_size = (1 << info->dabt.size) * 8; + const uint64_t access_mask = GENMASK_ULL(access_size - 1, 0); /* data is needed to prevent a pointer cast on 32bit */ unsigned long data; @@ -49,7 +51,7 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, if ( !vpci_sbdf_from_gpa(v->domain, bridge, info->gpa, &sbdf) ) { - *r = ~0UL; + *r = access_mask; return 1; } @@ -60,7 +62,7 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, return 1; } - *r = ~0UL; + *r = access_mask; return 0; }