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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:09 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/13] spi: add core support for controllers with offload capabilities Date: Wed, 10 Jan 2024 13:49:42 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-1-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds a feature for specialized SPI controllers that can record a series of SPI transfers, including tx data, cs assertions, delays, etc. and then play them back using a hardware trigger without CPU intervention. The intended use case for this is with the AXI SPI Engine to capture data from ADCs at high rates (MSPS) with a stable sample period. Most of the implementation is controller-specific and will be handled by drivers that implement the offload_ops callbacks. The API follows a prepare/enable pattern that should be familiar to users of the clk subsystem. Consumers of this API will make calls similar to this: /* in probe() */ offload = spi_offload_get(spi, 0); ... /* in some setup function */ ret = spi_offload_prepare(offload, xfers, ARRAY_SIZE(xfers)); ... /* in some enable function */ ret = spi_offload_enable(offload); ... /* in corresponding disable function */ spi_offload_disable(offload); ... /* in corresponding teardown function */ spi_offload_unprepare(offload); ... Signed-off-by: David Lechner --- drivers/spi/spi.c | 39 +++++++++++++++ include/linux/spi/spi.h | 123 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 162 insertions(+) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index a4b8c07c5951..f1d66b5d5491 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -3057,6 +3057,13 @@ static int spi_controller_check_ops(struct spi_controller *ctlr) } } + if (ctlr->offload_ops && !(ctlr->offload_ops->get && + ctlr->offload_ops->prepare && + ctlr->offload_ops->unprepare && + ctlr->offload_ops->enable && + ctlr->offload_ops->disable)) + return -EINVAL; + return 0; } @@ -4448,6 +4455,38 @@ int spi_write_then_read(struct spi_device *spi, } EXPORT_SYMBOL_GPL(spi_write_then_read); +/** + * spi_offload_prepare - prepare offload hardware for a transfer + * @offload: The offload instance. + * @spi: The spi device to use for the transfers. + * @xfers: The transfers to be executed. + * @num_xfers: The number of transfers. + * + * Records a series of transfers to be executed later by the offload hardware + * trigger. + * + * Return: 0 on success, else a negative error code. + */ +int spi_offload_prepare(struct spi_offload *offload, struct spi_device *spi, + struct spi_transfer *xfers, unsigned int num_xfers) +{ + struct spi_controller *ctlr = offload->controller; + struct spi_message msg; + int ret; + + spi_message_init_with_transfers(&msg, xfers, num_xfers); + + ret = __spi_validate(spi, &msg); + if (ret) + return ret; + + msg.spi = spi; + ret = ctlr->offload_ops->prepare(offload, &msg); + + return ret; +} +EXPORT_SYMBOL_GPL(spi_offload_prepare); + /*-------------------------------------------------------------------------*/ #if IS_ENABLED(CONFIG_OF_DYNAMIC) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 5d65a6273dcf..f116dfc1d52c 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -28,6 +28,8 @@ struct spi_transfer; struct spi_controller_mem_ops; struct spi_controller_mem_caps; struct spi_message; +struct spi_controller_offload_ops; +struct spi_offload; /* * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, @@ -713,6 +715,9 @@ struct spi_controller { const struct spi_controller_mem_ops *mem_ops; const struct spi_controller_mem_caps *mem_caps; + /* Operations for controllers with offload support. */ + const struct spi_controller_offload_ops *offload_ops; + /* GPIO chip select */ struct gpio_desc **cs_gpiods; bool use_gpio_descriptors; @@ -1505,6 +1510,124 @@ static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) /*---------------------------------------------------------------------------*/ +/* + * Offloading support. + * + * Some SPI controllers support offloading of SPI transfers. Essentially, + * this allows the SPI controller to record SPI transfers and then play them + * back later via a hardware trigger. + */ + +/** + * SPI_OFFLOAD_RX - placeholder for indicating read transfers for offloads + * + * Assign xfer->rx_buf to this value for any read transfer passed to + * spi_offload_prepare(). This will act as a flag to indicate to the offload + * that it should do something with the data read during this transfer. What + * that something can be is determined by the specific hardware, e.g. it could + * be piped to DMA or a DSP, etc. + */ +#define SPI_OFFLOAD_RX_SENTINEL ((void *)1) + +/** + * struct spi_controller_offload_ops - callbacks for offload support + * + * Drivers for hardware with offload support need to implement all of these + * callbacks. + */ +struct spi_controller_offload_ops { + /** + * @get: Callback to get the offload assigned to the given SPI device. + * Index is an index in the offloads array fwnode property of the device. + * Implementations must return the pointer to the device or a negative + * error code (return -ENODEV rather than NULL if no matching device). + */ + struct spi_offload *(*get)(struct spi_device *spi, unsigned int index); + /** + * @prepare: Callback to prepare the offload for the given SPI message. + * @msg and any of its members (including any xfer->tx_buf) is not + * guaranteed to be valid beyond the lifetime of this call. + */ + int (*prepare)(struct spi_offload *offload, struct spi_message *msg); + /** + * @unprepare: Callback to release any resources used by prepare(). + */ + void (*unprepare)(struct spi_offload *offload); + /** + * @enable: Callback to enable the offload. + */ + int (*enable)(struct spi_offload *offload); + /** + * @disable: Callback to disable the offload. + */ + void (*disable)(struct spi_offload *offload); +}; + +/** struct spi_offload - offload handle */ +struct spi_offload { + /** @controller: The associated SPI controller. */ + struct spi_controller *controller; + /** @dev: The device associated with the offload instance. */ + struct device *dev; + /** @priv: Private instance data used by the SPI controller. */ + void *priv; +}; + +/** + * spi_offload_get - gets an offload assigned to the given SPI device + * @spi: SPI device. + * @index: Index of the offload in the SPI device's fwnode int array. + * + * The lifetime of the returned offload is tied to the struct spi_controller + * instance. Since @spi owns a reference to the controller, most consumers + * should not have to do anything extra. But if the offload is passed somewhere + * outside of the control of the SPI device driver, then an additional reference + * to the controller must be made. + * + * Return: Pointer to the offload handle or negative error code. + */ +static inline struct spi_offload *spi_offload_get(struct spi_device *spi, + unsigned int index) +{ + if (!spi->controller->offload_ops) + return ERR_PTR(-EOPNOTSUPP); + + return spi->controller->offload_ops->get(spi, index); +} + +int spi_offload_prepare(struct spi_offload *offload, struct spi_device *spi, + struct spi_transfer *xfers, unsigned int num_xfers); + +/** + * spi_offload_unprepare - releases any resources used by spi_offload_prepare() + * @offload: The offload instance. + */ +static inline void spi_offload_unprepare(struct spi_offload *offload) +{ + offload->controller->offload_ops->unprepare(offload); +} + +/** + * spi_offload_enable - enables the offload + * @offload: The offload instance. + * Return: 0 on success or negative error code. + */ +static inline int spi_offload_enable(struct spi_offload *offload) +{ + return offload->controller->offload_ops->enable(offload); +} + +/** + * spi_offload_disable - disables the offload + * @offload: The offload instance. + */ +static inline void spi_offload_disable(struct spi_offload *offload) +{ + offload->controller->offload_ops->disable(offload); +} + +/*---------------------------------------------------------------------------*/ + /* * INTERFACE between board init code and SPI infrastructure. * From patchwork Wed Jan 10 19:49:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516424 Received: from mail-oo1-f48.google.com (mail-oo1-f48.google.com [209.85.161.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C68A94EB23 for ; Wed, 10 Jan 2024 19:51:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="yKV/+Qfr" Received: by mail-oo1-f48.google.com with SMTP id 006d021491bc7-58e256505f7so2394548eaf.3 for ; Wed, 10 Jan 2024 11:51:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1704916271; x=1705521071; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8tQFXGB0UBE3yQVmYcImKXXjk/ehD/gF98AYs7jrXzE=; b=yKV/+Qfriqeu0qBj16IXEt1rSLw90lnlhjOy+tyC7v7TdhP6uGBuPEMCUXuy1c4O7t avMDDkMYaHi7r3eppgI2HoVRyNAxiTYvpiisrGng2hZn609pSm9uAgau+o0nDORZYyRF S7wrVb3HuSBn9M4f41ZLCyXDvAMNwS/bZz7rkfhFi0cBecwBe8GMG+PnCG4yV7bUUbDc Ao0Mz4cbNDXxNtB/sp/GBvFVqhBqNVJEX+E4dAwSxlI3qJwx9X2jbEroAcAGoVgsP7xa yaP2LVm/b9zkPJ9n/zYrm6TZ2OUzZBl1jPuIKCYquxUU5+taZlpjjC3jlL72wx4FYUiz 1mCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704916271; x=1705521071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8tQFXGB0UBE3yQVmYcImKXXjk/ehD/gF98AYs7jrXzE=; b=MxbFs4e6iuQieYF+DYWMNhbCPxYgYS/QlMXScQzXB1PxUCntJWzM0Vh+sk4FxYZE94 yUKcgsLTnqsReYFMB2yvafbfagxO95TVNDMVFmgZjLtpqVKeSc+H5Le2JhzGbrbLR9dQ cJ0W1y6FjCpmT3tqEYYwfNfhUM40U0bR4EfJ/OPGlfmp/1mqJ1njB1jLo/YtN67T7RYC cpgIqLTfLCySa9einlv4wVixXDiAiEKgrpOgFF53igK5IGjoRRDf91bC/kh4S/uDxJ5Y JOkK3kBYCUGN6fvSA0eGTBS/iAQ7Dprwb+sjksBhfpToa8YSnkKISOex96HX17YmaH66 CQjg== X-Gm-Message-State: AOJu0YxQHCNLSuq982qzp/83amEoprNWEnRmX8AsrgoSy0mplpFxOmQc 6XGqNdMIlvcFypfG9tWXDGyMLJuZ1OkDgA== X-Google-Smtp-Source: AGHT+IGLTZ7rbIwDjuwU/b4aEWgy3uOE14zbEekH51p0401rK+4z9X/59v8/8YDpPt2l2qc30H7TDg== X-Received: by 2002:a05:6820:2382:b0:591:acf8:d08f with SMTP id co2-20020a056820238200b00591acf8d08fmr140554oob.11.1704916270980; Wed, 10 Jan 2024 11:51:10 -0800 (PST) Received: from freyr.lechnology.com (ip98-183-112-25.ok.ok.cox.net. [98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:10 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/13] scripts: dtc: checks: don't warn on SPI non-peripheral child nodes Date: Wed, 10 Jan 2024 13:49:43 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-2-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 According to the spi-controller.yaml bindings, SPI peripheral child nodes match the pattern "^.*@[0-9a-f]+$". A SPI controller binding may require a child object node that is not a peripheral. For example, the adi,axi-spi-engine binding requires an "offloads" child node that is not a peripheral but rather a part of the controller itself. By checking for '@' in the node name, we can avoids a warnings like: Warning (spi_bus_reg): /example-0/spi@44a00000/offloads: missing or empty reg property for a binding like: spi { ... offloads { offload@0 { ... }; ... }; peripheral@0 { ... }; }; Signed-off-by: David Lechner --- scripts/dtc/checks.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c index 9f31d2607182..5af68642f231 100644 --- a/scripts/dtc/checks.c +++ b/scripts/dtc/checks.c @@ -1144,6 +1144,10 @@ static void check_spi_bus_reg(struct check *c, struct dt_info *dti, struct node if (!node->parent || (node->parent->bus != &spi_bus)) return; + /* only nodes with '@' in name are SPI devices */ + if (!strchr(unitname, '@')) + return; + if (get_property(node->parent, "spi-slave")) return; From patchwork Wed Jan 10 19:49:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516425 Received: from mail-oo1-f45.google.com (mail-oo1-f45.google.com [209.85.161.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA5BB4EB3B for ; Wed, 10 Jan 2024 19:51:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="YdUX1Pq7" Received: by mail-oo1-f45.google.com with SMTP id 006d021491bc7-59898a3db56so599540eaf.1 for ; Wed, 10 Jan 2024 11:51:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1704916272; x=1705521072; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QGJNLPLyI0esp3kiyP6ekV4MJE/CQ1txcBdZozy1qY4=; b=YdUX1Pq76By7xCBv/J0TNuqf+K4DeKMAjdxNFoln4YpV3JPYDimyHzZ9OKy0jWvPnv I9g5aFG2jnjg+0Ieg7J7KYEi77+9tGnr2EPFGJGj+ywmm0YYVDUeYUZCWOPErIzQOiCp ZXPcya2G/X44xaT0h8x4CSnCaryhgiO3diTTJJb3qcVenWhDiHySWTVb9ngvTmEkrnYT X8bsHNWnEie8hosmA2b0pmo4cLhPpkAquYaHubQu5kWkHYQyQDvGFDV1Cm9TE2Z6h4th GtP1YCNc2pZCZNMsWVH4QuLdJ88MvzSEEhda/L7k4sZKX180Ajiwm5VeOBTYa8tXLmsP iCkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704916272; x=1705521072; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QGJNLPLyI0esp3kiyP6ekV4MJE/CQ1txcBdZozy1qY4=; b=pOByUU0Gt6gngJYeKyoX3Fj8oWeNwmT25QpIT+Xhwmj4hqz4OOGu2/+lOTLMqkvOUN s7P/iJ6uKfrtbzpdlp+zmSl7yKcvRttoH0dhKnqvmKVGZZno2s3zVZn61v36Mqeir9cR R/QuInukF+qyDlMe7VbdedpaqcECYq5sT6MK8q0HyYQ9ZVsQCV+EaHeRsd8TTidN3A1f AW7tzgLV01XvOMFdkf5nUoAYH97B5YKo4zTQasympdMTs+cHAac7qvncESHzYS1LXXZA j1hiekRlYRLoO1d7GD0UOLgPANVo8PQ5rBdqgDv+AZRCWLDBiVzQcXg9jRbqanwEalHb jjgw== X-Gm-Message-State: AOJu0Yy4m2SwjB5VyRcUMlfLrVA9bvVYeVnE1WK2wHU9NoXZ8Fhz+Jp0 +FVBIPugNXNnw7/c8OYLz0xzNqGf2KRNCg== X-Google-Smtp-Source: AGHT+IFqQsQrIOCFpE4RsIKPQ3gHKMPk+6t2PPhDGvVXODesiyE6VwJfYeEefY+r+svD2MqX1koi+g== X-Received: by 2002:a05:6820:2406:b0:598:6fb0:ba36 with SMTP id cp6-20020a056820240600b005986fb0ba36mr130528oob.1.1704916271980; Wed, 10 Jan 2024 11:51:11 -0800 (PST) Received: from freyr.lechnology.com (ip98-183-112-25.ok.ok.cox.net. [98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:11 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/13] spi: do not attempt to register DT nodes without @ in name Date: Wed, 10 Jan 2024 13:49:44 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-3-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 In the DT bindings for SPI devices, it is specified that peripheral nodes have the @ character in the node name. A SPI controller may need to create bindings with child nodes that are not peripherals. For example, the AXI SPI Engine bindings will use an "offloads" child node to describe what is connected to the offload interfaces of the SPI controller. Without this change, the SPI controller would attempt to register all child nodes as SPI devices. After this change, only nodes with '@' in the name will be registered as SPI devices. Signed-off-by: David Lechner --- drivers/spi/spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index f1d66b5d5491..5be5e654284c 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2379,7 +2379,9 @@ static void of_register_spi_devices(struct spi_controller *ctlr) struct device_node *nc; for_each_available_child_of_node(ctlr->dev.of_node, nc) { - if (of_node_test_and_set_flag(nc, OF_POPULATED)) + /* Only nodes with '@' in the name are peripheral nodes. */ + if (of_node_test_and_set_flag(nc, OF_POPULATED) || + !strchr(kbasename(nc->full_name), '@')) continue; spi = of_register_spi_device(ctlr, nc); if (IS_ERR(spi)) { From patchwork Wed Jan 10 19:49:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516426 Received: from mail-oo1-f42.google.com (mail-oo1-f42.google.com [209.85.161.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4B2A4EB44 for ; Wed, 10 Jan 2024 19:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="nooHw6Bw" Received: by mail-oo1-f42.google.com with SMTP id 006d021491bc7-5989add5511so500083eaf.3 for ; Wed, 10 Jan 2024 11:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1704916273; x=1705521073; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BxwuK84w923F+g+Vt8AcwM39UH7HsN98gaGyRuSrYT0=; b=nooHw6Bw+oo7gGwZ0e+OXaV63hLdzwuhAFVPwdLJ+J6Q7hO2B6OEDEt1WlHPKM1U0v STcz4y+lFqp0rfW8QkiW2ec+ijvVt2YP49GnGz9RyICdZ05pz9KS9Um+aCIbgaAwZGEp JwJx0qEJoAwnF2V8R7tQQ21+ta/+br44wDRgaW1m6k7vLtsYRZVps+g1Fp62GcyX5wl8 wFi5bQWiYHk4CPJcoLaUJeny9f1LT5H7F1vqFEqjkG3xAgov6eOX0RVSy0zKtAWoR1R1 ckqo8+920CM3FJsGMk6rfqzPhMxBhuhgUmH9mOWNJJI08RqAZ9OnPe+OKL4Ly48z4/XJ 7odQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704916273; x=1705521073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BxwuK84w923F+g+Vt8AcwM39UH7HsN98gaGyRuSrYT0=; b=A2kr19xMa7KXE39REB9G0A1VkIoVtVuUMkxz5OK3bnVFa4JBVqsi3wYEnsa+esr1P8 Jc9n5StNWxTkeM4bYDmEmn35GDtz0uvktMLW5C6kmBwwTmAHah/DEmSw4GAgrcOQNmxN vSXpk0pQk5Y6pWTicU2QJXhQ9/HFc82wpl/f9hPbyL6tw9/bMtEmEtf4sXT+ZQT+FtGb jiWMJGy5crEFrTzhbYELuHZgXGytgVry1DpOuMlXU09sOVf3Jheqq3Sbjk28bNZ7IaJ9 w2/sxUI5Adu7cgHig4caSD9m4ozn81H66Pl4GNEBtEl9lDo0laZOMZgt9eibUhHYgtUS ufSg== X-Gm-Message-State: AOJu0YxiMppiSaLZJWez50BfP4TiJsWu8iK3SbSTHgQ8txPodA2JhD0/ WwwKwolyCAYriYfXHkYhw+AV8GAH8xm+QQ== X-Google-Smtp-Source: AGHT+IGJ+O/PYxjqHIL/1LHHTnKjU7G2qVmk8BAvyUKQ/5nDAwbS6rdUFjjZNIceJMm0d4HdbWXbjQ== X-Received: by 2002:a4a:5888:0:b0:598:8f50:d37e with SMTP id f130-20020a4a5888000000b005988f50d37emr94684oob.16.1704916272986; Wed, 10 Jan 2024 11:51:12 -0800 (PST) Received: from freyr.lechnology.com (ip98-183-112-25.ok.ok.cox.net. [98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:12 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/13] spi: dt-bindings: adi,axi-spi-engine: add offload bindings Date: Wed, 10 Jan 2024 13:49:45 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-4-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 The ADI AXI SPI Engine driver supports offloading SPI transfers to hardware. This is essentially a feature that allows recording an arbitrary sequence of SPI transfers and then playing them back with no CPU intervention via a hardware trigger. This adds the bindings for this feature. Each SPI Engine instance can have from 0 to 32 offload instances. Each offload instance has a trigger input and a data stream output. As an example, this could be used with an ADC SPI peripheral. In this case the trigger is connected to a PWM/clock to determine the sampling rate for the ADC and the output stream is connected to a DMA channel to pipe the sample data to memory. SPI peripherals act as consumers of the offload instances. Typically, one SPI peripheral will be connected to one offload instance. But to make the bindings future-proof, the property is an array. Signed-off-by: David Lechner --- .../spi/adi,axi-spi-engine-peripheral-props.yaml | 24 +++++++++++ .../bindings/spi/adi,axi-spi-engine.yaml | 49 +++++++++++++++++++++- .../bindings/spi/spi-peripheral-props.yaml | 1 + 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine-peripheral-props.yaml new file mode 100644 index 000000000000..19b685fc3b39 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine-peripheral-props.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/adi,axi-spi-engine-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral properties for Analog Devices AXI SPI Engine Controller + +maintainers: + - Michael Hennerich + - Nuno Sá + +properties: + adi,offloads: + description: + List of AXI SPI Engine offload instances assigned to this peripheral. + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 32 + items: + items: + - minimum: 0 + maximum: 31 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index d48faa42d025..69f3261bab47 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -21,6 +21,23 @@ maintainers: allOf: - $ref: /schemas/spi/spi-controller.yaml# +$defs: + offload: + description: + Describes the connections of the trigger input and the data output stream + of one or more offload instances. + + properties: + reg: + description: + Index of the offload instance. + items: + - minimum: 0 + maximum: 31 + + required: + - reg + properties: compatible: const: adi,axi-spi-engine-1.00.a @@ -41,6 +58,22 @@ properties: - const: s_axi_aclk - const: spi_clk + offloads: + type: object + description: Zero or more offloads supported by the controller. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^offload@[0-8a-f]+$": + type: object + $ref: '#/$defs/offload' + required: - compatible - reg @@ -62,5 +95,19 @@ examples: #address-cells = <1>; #size-cells = <0>; - /* SPI devices */ + offloads { + #address-cells = <1>; + #size-cells = <0>; + + offload@0 { + compatible = "adi,example-offload"; + reg = <0>; + }; + }; + + adc@0 { + compatible = "adi,example-adc"; + reg = <0>; + adi,offloads = <0>; + }; }; diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 1c8e71c18234..7beb5a3798a5 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -132,6 +132,7 @@ properties: # The controller specific properties go here. allOf: + - $ref: adi,axi-spi-engine-peripheral-props.yaml# - $ref: arm,pl022-peripheral-props.yaml# - $ref: cdns,qspi-nor-peripheral-props.yaml# - $ref: samsung,spi-peripheral-props.yaml# From patchwork Wed Jan 10 19:49:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516427 Received: from mail-oo1-f54.google.com (mail-oo1-f54.google.com [209.85.161.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9AD94F1EA for ; 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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:13 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Lars-Peter Clausen Subject: [PATCH 05/13] spi: axi-spi-engine: add SPI offload support Date: Wed, 10 Jan 2024 13:49:46 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-5-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds an implementation of the SPI offload_ops to the AXI SPI Engine driver to provide offload support. Offload lookup is done by device property lookup. SPI Engine commands and tx data are recorded by writing to offload-specific FIFOs in the SPI Engine hardware. Co-developed-by: Lars-Peter Clausen Signed-off-by: Lars-Peter Clausen Signed-off-by: David Lechner --- drivers/spi/spi-axi-spi-engine.c | 270 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 270 insertions(+) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-engine.c index 58280dd1c901..1d7ddc867b50 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -2,9 +2,11 @@ /* * SPI-Engine SPI controller driver * Copyright 2015 Analog Devices Inc. + * Copyright 2023 BayLibre, SAS * Author: Lars-Peter Clausen */ +#include #include #include #include @@ -38,11 +40,22 @@ #define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8 #define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec +#define SPI_ENGINE_MAX_NUM_OFFLOADS 32 + +#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + (SPI_ENGINE_MAX_NUM_OFFLOADS * x)) +#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + (SPI_ENGINE_MAX_NUM_OFFLOADS * x)) +#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + (SPI_ENGINE_MAX_NUM_OFFLOADS * x)) +#define SPI_ENGINE_REG_OFFLOAD_CMD_FIFO(x) (0x110 + (SPI_ENGINE_MAX_NUM_OFFLOADS * x)) +#define SPI_ENGINE_REG_OFFLOAD_SDO_FIFO(x) (0x114 + (SPI_ENGINE_MAX_NUM_OFFLOADS * x)) + #define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0) #define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1) #define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2) #define SPI_ENGINE_INT_SYNC BIT(3) +#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE BIT(0) +#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED BIT(0) + #define SPI_ENGINE_CONFIG_CPHA BIT(0) #define SPI_ENGINE_CONFIG_CPOL BIT(1) #define SPI_ENGINE_CONFIG_3WIRE BIT(2) @@ -76,6 +89,10 @@ #define SPI_ENGINE_CMD_SYNC(id) \ SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id)) +/* default sizes - can be changed when SPI Engine firmware is compiled */ +#define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16 +#define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16 + struct spi_engine_program { unsigned int length; uint16_t instructions[]; @@ -107,6 +124,10 @@ struct spi_engine_message_state { u8 sync_id; }; +struct spi_engine_offload { + unsigned int index; +}; + struct spi_engine { struct clk *clk; struct clk *ref_clk; @@ -119,6 +140,9 @@ struct spi_engine { struct spi_controller *controller; unsigned int int_enable; + + struct spi_offload offloads[SPI_ENGINE_MAX_NUM_OFFLOADS]; + struct spi_engine_offload offload_priv[SPI_ENGINE_MAX_NUM_OFFLOADS]; }; static void spi_engine_program_add_cmd(struct spi_engine_program *p, @@ -603,6 +627,239 @@ static int spi_engine_transfer_one_message(struct spi_controller *host, return 0; } +static struct spi_offload *spi_engine_offload_get(struct spi_device *spi, + unsigned int index) +{ + struct spi_controller *host = spi->controller; + struct spi_engine *spi_engine = spi_controller_get_devdata(host); + struct spi_offload *offload; + u32 vals[SPI_ENGINE_MAX_NUM_OFFLOADS]; + int ret; + + /* Use the adi,offloads array to find the offload at index. */ + + if (index >= ARRAY_SIZE(vals)) + return ERR_PTR(-EINVAL); + + ret = device_property_read_u32_array(&spi->dev, "adi,offloads", vals, + index + 1); + if (ret < 0) + return ERR_PTR(ret); + + if (vals[index] >= SPI_ENGINE_MAX_NUM_OFFLOADS) + return ERR_PTR(-EINVAL); + + offload = &spi_engine->offloads[vals[index]]; + + return offload; +} + +static int spi_engine_offload_prepare(struct spi_offload *offload, + struct spi_message *msg) +{ + struct spi_controller *host = offload->controller; + struct spi_engine_offload *priv = offload->priv; + struct spi_engine *spi_engine = spi_controller_get_devdata(host); + struct spi_engine_program p_dry, *p __free(kfree) = NULL; + struct spi_transfer *xfer; + void __iomem *cmd_addr; + void __iomem *sdo_addr; + size_t tx_word_count = 0; + unsigned int i; + + /* count total number of tx words in message */ + list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (!xfer->tx_buf) + continue; + + if (xfer->bits_per_word <= 8) + tx_word_count += xfer->len; + else if (xfer->bits_per_word <= 16) + tx_word_count += xfer->len / 2; + else + tx_word_count += xfer->len / 4; + } + + /* REVISIT: could get actual size from devicetree if needed */ + if (tx_word_count > SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE) + return -EINVAL; + + spi_engine_precompile_message(msg); + + /* dry run to get length */ + p_dry.length = 0; + spi_engine_compile_message(msg, true, &p_dry); + + /* REVISIT: could get actual size from devicetree if needed */ + if (p_dry.length > SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE) + return -EINVAL; + + p = kzalloc(sizeof(*p) + sizeof(*p->instructions) * p_dry.length, GFP_KERNEL); + if (!p) + return -ENOMEM; + + spi_engine_compile_message(msg, false, p); + + cmd_addr = spi_engine->base + SPI_ENGINE_REG_OFFLOAD_CMD_FIFO(priv->index); + sdo_addr = spi_engine->base + SPI_ENGINE_REG_OFFLOAD_SDO_FIFO(priv->index); + + list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (!xfer->tx_buf) + continue; + + if (xfer->bits_per_word <= 8) { + const u8 *buf = xfer->tx_buf; + + for (i = 0; i < xfer->len; i++) + writel_relaxed(buf[i], sdo_addr); + } else if (xfer->bits_per_word <= 16) { + const u16 *buf = xfer->tx_buf; + + for (i = 0; i < xfer->len / 2; i++) + writel_relaxed(buf[i], sdo_addr); + } else { + const u32 *buf = xfer->tx_buf; + + for (i = 0; i < xfer->len / 4; i++) + writel_relaxed(buf[i], sdo_addr); + } + } + + for (i = 0; i < p->length; i++) + writel_relaxed(p->instructions[i], cmd_addr); + + return 0; +} + +static void spi_engine_offload_unprepare(struct spi_offload *offload) +{ + struct spi_controller *host = offload->controller; + struct spi_engine_offload *priv = offload->priv; + struct spi_engine *spi_engine = spi_controller_get_devdata(host); + + writel_relaxed(1, spi_engine->base + + SPI_ENGINE_REG_OFFLOAD_RESET(priv->index)); + writel_relaxed(0, spi_engine->base + + SPI_ENGINE_REG_OFFLOAD_RESET(priv->index)); +} + +static int spi_engine_offload_enable(struct spi_offload *offload) +{ + struct spi_controller *host = offload->controller; + struct spi_engine_offload *priv = offload->priv; + struct spi_engine *spi_engine = spi_controller_get_devdata(host); + unsigned int reg; + + reg = readl_relaxed(spi_engine->base + + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->index)); + reg |= SPI_ENGINE_OFFLOAD_CTRL_ENABLE; + writel_relaxed(reg, spi_engine->base + + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->index)); + + return 0; +} + +static void spi_engine_offload_disable(struct spi_offload *offload) +{ + struct spi_controller *host = offload->controller; + struct spi_engine_offload *priv = offload->priv; + struct spi_engine *spi_engine = spi_controller_get_devdata(host); + unsigned int reg; + + reg = readl_relaxed(spi_engine->base + + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->index)); + reg &= ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE; + writel_relaxed(reg, spi_engine->base + + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->index)); +} + +static const struct spi_controller_offload_ops spi_engine_offload_ops = { + .get = spi_engine_offload_get, + .prepare = spi_engine_offload_prepare, + .unprepare = spi_engine_offload_unprepare, + .enable = spi_engine_offload_enable, + .disable = spi_engine_offload_disable, +}; + +static void spi_engine_offload_release(void *p) +{ + struct spi_offload *offload = p; + struct platform_device *pdev = container_of(offload->dev, + struct platform_device, dev); + + offload->dev = NULL; + platform_device_unregister(pdev); +} + +/** + * devm_spi_engine_register_offload() - Registers platform device for offload. + * + * @dev: The parent platform device node. + * @offload: The offload firmware node. + * + * Return: 0 on success, negative error code otherwise. + */ +static int devm_spi_engine_register_offload(struct device *dev, + struct spi_engine *spi_engine, + struct fwnode_handle *fwnode) +{ + struct platform_device_info pdevinfo = { + .parent = dev, + .name = "offload", + .fwnode = fwnode, + }; + struct platform_device *pdev; + struct spi_offload *offload; + u32 index; + int ret; + + ret = fwnode_property_read_u32(fwnode, "reg", &index); + if (ret) + return ret; + + if (index >= SPI_ENGINE_MAX_NUM_OFFLOADS) + return -EINVAL; + + pdevinfo.id = index; + + pdev = platform_device_register_full(&pdevinfo); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + offload = &spi_engine->offloads[index]; + offload->dev = &pdev->dev; + + return devm_add_action_or_reset(dev, spi_engine_offload_release, offload); +} + +/** + * spi_engine_offload_populate() - Registers platform device for each offload instance. + * @host: The SPI controller. + * @spi_engine: The SPI engine. + * @dev: The parent platform device. + */ +static void spi_engine_offload_populate(struct spi_controller *host, + struct spi_engine *spi_engine, + struct device *dev) +{ + struct fwnode_handle *offloads; + struct fwnode_handle *child; + int ret; + + /* offloads are optional */ + offloads = device_get_named_child_node(dev, "offloads"); + if (!offloads) + return; + + fwnode_for_each_available_child_node(offloads, child) { + ret = devm_spi_engine_register_offload(dev, spi_engine, child); + if (ret) + dev_warn(dev, "failed to register offload: %d\n", ret); + } + + fwnode_handle_put(offloads); +} + static void spi_engine_timeout(struct timer_list *timer) { struct spi_engine *spi_engine = from_timer(spi_engine, timer, watchdog_timer); @@ -633,6 +890,7 @@ static int spi_engine_probe(struct platform_device *pdev) unsigned int version; int irq; int ret; + int i; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -670,6 +928,15 @@ static int spi_engine_probe(struct platform_device *pdev) return -ENODEV; } + for (i = 0; i < SPI_ENGINE_MAX_NUM_OFFLOADS; i++) { + struct spi_engine_offload *priv = &spi_engine->offload_priv[i]; + struct spi_offload *offload = &spi_engine->offloads[i]; + + priv->index = i; + offload->controller = host; + offload->priv = priv; + } + writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET); writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING); writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); @@ -692,6 +959,7 @@ static int spi_engine_probe(struct platform_device *pdev) host->prepare_message = spi_engine_prepare_message; host->unprepare_message = spi_engine_unprepare_message; host->num_chipselect = 8; + host->offload_ops = &spi_engine_offload_ops; if (host->max_speed_hz == 0) return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0"); @@ -702,6 +970,8 @@ static int spi_engine_probe(struct platform_device *pdev) platform_set_drvdata(pdev, host); + spi_engine_offload_populate(host, spi_engine, &pdev->dev); + return 0; } From patchwork Wed Jan 10 19:49:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516428 Received: from mail-oo1-f49.google.com (mail-oo1-f49.google.com [209.85.161.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B63E24EB23 for ; Wed, 10 Jan 2024 19:51:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Y3XOe08z" Received: by mail-oo1-f49.google.com with SMTP id 006d021491bc7-598a0063134so424866eaf.0 for ; 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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:14 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/13] iio: buffer: add hardware triggered buffer support Date: Wed, 10 Jan 2024 13:49:47 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-6-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds a new mode INDIO_HW_BUFFER_TRIGGERED to the IIO subsystem. This mode is essentially the hardware version of INDIO_BUFFER_TRIGGERED where the trigger has the semantics of INDIO_HARDWARE_TRIGGERED and the buffer has the semantics of INDIO_BUFFER_HARDWARE. So basically INDIO_HW_BUFFER_TRIGGERED is the same as INDIO_BUFFER_HARDWARE except that it also enables the trigger when the buffer is enabled. Signed-off-by: David Lechner --- drivers/iio/industrialio-buffer.c | 43 ++++++++++++++++++++++++++++++++++++--- include/linux/iio/iio.h | 16 ++++++++++++--- 2 files changed, 53 insertions(+), 6 deletions(-) diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c index 176d31d9f9d8..ffee3043c65a 100644 --- a/drivers/iio/industrialio-buffer.c +++ b/drivers/iio/industrialio-buffer.c @@ -27,6 +27,7 @@ #include #include #include +#include static const char * const iio_endian_prefix[] = { [IIO_BE] = "be", @@ -867,8 +868,17 @@ static int iio_verify_update(struct iio_dev *indio_dev, insert_buffer->watermark); } - /* Definitely possible for devices to support both of these. */ - if ((modes & INDIO_BUFFER_TRIGGERED) && indio_dev->trig) { + /* Definitely possible for devices to support all of these. */ + if (modes & INDIO_HW_BUFFER_TRIGGERED) { + /* + * Keep things simple for now and only allow a single buffer to + * be connected in hardware mode. + */ + if (insert_buffer && !list_empty(&iio_dev_opaque->buffer_list)) + return -EINVAL; + config->mode = INDIO_HW_BUFFER_TRIGGERED; + strict_scanmask = true; + } else if ((modes & INDIO_BUFFER_TRIGGERED) && indio_dev->trig) { config->mode = INDIO_BUFFER_TRIGGERED; } else if (modes & INDIO_BUFFER_HARDWARE) { /* @@ -1107,11 +1117,21 @@ static int iio_enable_buffers(struct iio_dev *indio_dev, } } + if (iio_dev_opaque->currentmode == INDIO_HW_BUFFER_TRIGGERED) { + struct iio_trigger *trig = indio_dev->trig; + + if (trig->ops && trig->ops->set_trigger_state) { + ret = trig->ops->set_trigger_state(trig, true); + if (ret) + goto err_disable_buffers; + } + } + if (iio_dev_opaque->currentmode == INDIO_BUFFER_TRIGGERED) { ret = iio_trigger_attach_poll_func(indio_dev->trig, indio_dev->pollfunc); if (ret) - goto err_disable_buffers; + goto err_disable_hw_trigger; } if (indio_dev->setup_ops->postenable) { @@ -1130,6 +1150,16 @@ static int iio_enable_buffers(struct iio_dev *indio_dev, iio_trigger_detach_poll_func(indio_dev->trig, indio_dev->pollfunc); } +err_disable_hw_trigger: + if (iio_dev_opaque->currentmode == INDIO_HW_BUFFER_TRIGGERED) { + struct iio_trigger *trig = indio_dev->trig; + + if (trig->ops && trig->ops->set_trigger_state) { + ret = trig->ops->set_trigger_state(trig, false); + if (ret) + return ret; + } + } err_disable_buffers: buffer = list_prepare_entry(tmp, &iio_dev_opaque->buffer_list, buffer_list); list_for_each_entry_continue_reverse(buffer, &iio_dev_opaque->buffer_list, @@ -1174,6 +1204,13 @@ static int iio_disable_buffers(struct iio_dev *indio_dev) indio_dev->pollfunc); } + if (iio_dev_opaque->currentmode == INDIO_HW_BUFFER_TRIGGERED) { + struct iio_trigger *trig = indio_dev->trig; + + if (trig->ops && trig->ops->set_trigger_state) + trig->ops->set_trigger_state(trig, false); + } + list_for_each_entry(buffer, &iio_dev_opaque->buffer_list, buffer_list) { ret2 = iio_buffer_disable(buffer, indio_dev); if (ret2 && !ret) diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index d0ce3b71106a..16f62bd38041 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -366,6 +366,11 @@ s64 iio_get_time_ns(const struct iio_dev *indio_dev); * they must be managed by the core, but without the entire interrupts/poll * functions burden. Interrupts are irrelevant as the data flow is hardware * mediated and distributed. + * @INDIO_HW_BUFFER_TRIGGERED: Very unusual mode. + * This is similar to INDIO_BUFFER_TRIGGERED but everything is done in hardware + * therefore there are no poll functions attached. It also implies the semantics + * of both INDIO_HARDWARE_TRIGGERED for the trigger and INDIO_BUFFER_HARDWARE + * for the buffer. */ #define INDIO_DIRECT_MODE 0x01 #define INDIO_BUFFER_TRIGGERED 0x02 @@ -373,14 +378,19 @@ s64 iio_get_time_ns(const struct iio_dev *indio_dev); #define INDIO_BUFFER_HARDWARE 0x08 #define INDIO_EVENT_TRIGGERED 0x10 #define INDIO_HARDWARE_TRIGGERED 0x20 +#define INDIO_HW_BUFFER_TRIGGERED 0x40 -#define INDIO_ALL_BUFFER_MODES \ - (INDIO_BUFFER_TRIGGERED | INDIO_BUFFER_HARDWARE | INDIO_BUFFER_SOFTWARE) +#define INDIO_ALL_BUFFER_MODES \ + (INDIO_BUFFER_TRIGGERED \ + | INDIO_BUFFER_HARDWARE \ + | INDIO_BUFFER_SOFTWARE \ + | INDIO_HW_BUFFER_TRIGGERED) #define INDIO_ALL_TRIGGERED_MODES \ (INDIO_BUFFER_TRIGGERED \ | INDIO_EVENT_TRIGGERED \ - | INDIO_HARDWARE_TRIGGERED) + | INDIO_HARDWARE_TRIGGERED \ + | INDIO_HW_BUFFER_TRIGGERED) #define INDIO_MAX_RAW_ELEMENTS 4 From patchwork Wed Jan 10 19:49:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516429 Received: from mail-oo1-f44.google.com (mail-oo1-f44.google.com [209.85.161.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 719234F213 for ; Wed, 10 Jan 2024 19:51:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="O9k1ATy+" Received: by mail-oo1-f44.google.com with SMTP id 006d021491bc7-59827210160so1975444eaf.1 for ; Wed, 10 Jan 2024 11:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1704916275; x=1705521075; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jqqZ1xFBo82n6w1dVaiJcbo432Ln6B24n8maUrb2mjE=; b=O9k1ATy+T89/CZvFYID+81bz5WDTQh/+XvcBDMsj8tdNpV1z0rqQu57uYQRlIO6wJK YXDzg37ZwMMbC9fEudVU27qkgDQ5oRJw/hrGEyqafUT//j1eTc7MjCPjFafmSqYjbJGN 8taVXuHsKE5BCwPqydf2bLmxnAy7kgSgADSCKAjCcvOMZNoAbeWz7adTbYIzLxtxnOjd BT+nA0QK+2x1wyWvxwKgudoEHwQ7hIZk+aY/I+snjpSWb+XvzyTBHICU4qsCpPD+EPEf u2PJ2N+00gE9sZ9MTbY8wY43bR3oTzgkpxajp7Q7t8y2vxb0Rjx6JsWC966MaQsLmHmu qBoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704916275; x=1705521075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jqqZ1xFBo82n6w1dVaiJcbo432Ln6B24n8maUrb2mjE=; b=aUQ/0wJdiyNtvjXE1IhZxQNubBmH5hdvNPPl9Ty3GFw6cjYFhfPaQoTAhPFWUtRNmW KpqjmXRcOD7CBPgjhhzwWV0OjcwYSip7x0GcZNHJBBeWutYyfl6mS67v62WtRzTH9OWd DdZ8cLuBUZTaguIVx7QvBqUxPBREkrFbM+TFXFbL97ZJn60OI4Xfuh/2riIlEMFDHz8t SBOZQ4NLQ5JuO76ZaCYc69XMm8270iW34ENA34A81oNRGPwu1FeQjgfJ5qc7vPdaauTv fZ7MC+I8qME8Z9ed3H/LrnfHSE3qiKJJBAQDn6Issdd/hJCThAzM6prBKZQy5DGx+6hm duXg== X-Gm-Message-State: AOJu0Yyurztj7+KzEYhzbIOcS9B5teW1VAgDrg0MuiQ3iXjjNmIslqIg o25DDttiaJ24qHLxQwq6u4Kt2OZYJQt6dg== X-Google-Smtp-Source: AGHT+IGpvpbNrgicdFH6SZalFJARifgnOCGpguDFxh622L8t3QzMdc8P1+4NLpt69DdVpeiIu3LAlA== X-Received: by 2002:a4a:c385:0:b0:598:9871:2800 with SMTP id u5-20020a4ac385000000b0059898712800mr400192oop.3.1704916275707; Wed, 10 Jan 2024 11:51:15 -0800 (PST) Received: from freyr.lechnology.com (ip98-183-112-25.ok.ok.cox.net. [98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:15 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/13] iio: buffer: dmaengine: add INDIO_HW_BUFFER_TRIGGERED flag Date: Wed, 10 Jan 2024 13:49:48 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-7-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds the new INDIO_HW_BUFFER_TRIGGERED flag to the available modes of the dmaengine buffer. This allows it to be used as the buffer of devices that use the INDIO_HW_BUFFER_TRIGGERED flag. Signed-off-by: David Lechner --- drivers/iio/buffer/industrialio-buffer-dmaengine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/buffer/industrialio-buffer-dmaengine.c b/drivers/iio/buffer/industrialio-buffer-dmaengine.c index 5f85ba38e6f6..c67ddf963bfb 100644 --- a/drivers/iio/buffer/industrialio-buffer-dmaengine.c +++ b/drivers/iio/buffer/industrialio-buffer-dmaengine.c @@ -120,7 +120,7 @@ static const struct iio_buffer_access_funcs iio_dmaengine_buffer_ops = { .data_available = iio_dma_buffer_data_available, .release = iio_dmaengine_buffer_release, - .modes = INDIO_BUFFER_HARDWARE, + .modes = INDIO_BUFFER_HARDWARE | INDIO_HW_BUFFER_TRIGGERED, .flags = INDIO_BUFFER_FLAG_FIXED_WATERMARK, }; From patchwork Wed Jan 10 19:49:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516431 Received: from mail-oo1-f45.google.com (mail-oo1-f45.google.com [209.85.161.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C491F4F5FA for ; Wed, 10 Jan 2024 19:51:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="t5cFwVVr" Received: by mail-oo1-f45.google.com with SMTP id 006d021491bc7-598a3a5bd36so280752eaf.0 for ; Wed, 10 Jan 2024 11:51:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1704916277; x=1705521077; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y7PWqKKUmIJfOHhEo7bhsOSHT+T28MHjs59pcUd3qYA=; b=t5cFwVVrDBIe40U3IAx7Z1O+47Lx54RlcTqA3y0fMFCB64JCJhuuZpRxk00nUy1m7h KfKCp9HBFNuikxuFJ4nyxFfQEZNvZn+V8lsornUMDLTtrxya/FWDNToWAt55IcK3w4AF WBI+oMOCWY7OKRuKaRecyMQONOop4mfIenpX34EUFWprGnUrml0Gw3x42DtrDjy0wvGE zLuvtEiWo3ctyWLpkMd4zwjnBaO9TuxBTKRXbDPnMgyfVcCXJ4LLd+664kIGTKYxcsfc in/BI5UiCACx+64qcV4ID97rqUzxl3BBFR1E/DuO6xQTeX7xU9nzOH5pmekUBjxZ/f5b Izpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704916277; x=1705521077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y7PWqKKUmIJfOHhEo7bhsOSHT+T28MHjs59pcUd3qYA=; b=xKAfqFD/YRO/OtWBItvzrAEGIvHEAZP992RhyeYHQxZJbpnSJ1BcfbhkHTjNDbxSCG OqZ0SlZpiGrpdfDZId8/hfKPL3+gjrO/LC9L8/zqsztXs5mZBVhQ76MHi4C+PQjqeiRl 2sIOZOyLfsnbwhPv63ONeXq1U3mRrWrvgfZ0M962IxRZ6JXdeiAPSDXt+C43qfn2/Chn 5pQcFxgcNtgnbP/JYadWck0NJKJRCAvwpBr7eUNt+WEouD2MyIC0pxkCqiM6EqC8alqw v0bO1Cn9++dq2kOK4hiFib6am9BSL5UrTMQQNCObuixXiPLz8oe4Sek9LShgEu6STfD0 xC0Q== X-Gm-Message-State: AOJu0YzhF+43hpkGbPf1FOhpNtDFbA966okAsWzk9eX3RihnDEb0k1Lu le/jTCDehXRS+HmyoJAD+u04Z07HLoaCCXGCB7jQ3t8f6vc= X-Google-Smtp-Source: AGHT+IG/pQstA269+Q9le7ThaVf0owpqSI3RhN8sLNCjdHTp/Q1xvhsyx76vcyZGXAyczFLDe5FZbA== X-Received: by 2002:a4a:9b17:0:b0:591:c16b:eb29 with SMTP id a23-20020a4a9b17000000b00591c16beb29mr92673ook.13.1704916276715; Wed, 10 Jan 2024 11:51:16 -0800 (PST) Received: from freyr.lechnology.com (ip98-183-112-25.ok.ok.cox.net. [98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:16 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/13] iio: buffer: add new hardware triggered buffer driver Date: Wed, 10 Jan 2024 13:49:49 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-8-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds a new hardware triggered buffer driver for the IIO subsystem. This driver is intended to be used by IIO device drivers that have a hardware buffer that is triggered by a hardware signal. It is expected that components such as those providing a backend via the IIO backend framework will provide the actual implementation of this functionality by registering a matching device on the auxiliary bus. The auxiliary bus was chosen since it allows us to make use of existing kernel infrastructure instead of implementing our own registration and lookup system. Signed-off-by: David Lechner --- Documentation/driver-api/driver-model/devres.rst | 1 + drivers/iio/buffer/Kconfig | 7 ++ drivers/iio/buffer/Makefile | 1 + .../iio/buffer/industrialio-hw-triggered-buffer.c | 104 +++++++++++++++++++++ include/linux/iio/hw_triggered_buffer.h | 14 +++ include/linux/iio/hw_triggered_buffer_impl.h | 16 ++++ 6 files changed, 143 insertions(+) diff --git a/Documentation/driver-api/driver-model/devres.rst b/Documentation/driver-api/driver-model/devres.rst index c5f99d834ec5..b23d4a2b68a6 100644 --- a/Documentation/driver-api/driver-model/devres.rst +++ b/Documentation/driver-api/driver-model/devres.rst @@ -296,6 +296,7 @@ IIO devm_iio_channel_get() devm_iio_channel_get_all() devm_iio_hw_consumer_alloc() + devm_iio_hw_triggered_buffer_setup() devm_fwnode_iio_channel_get_by_name() INPUT diff --git a/drivers/iio/buffer/Kconfig b/drivers/iio/buffer/Kconfig index 047b931591a9..925c5bf074bc 100644 --- a/drivers/iio/buffer/Kconfig +++ b/drivers/iio/buffer/Kconfig @@ -53,3 +53,10 @@ config IIO_TRIGGERED_BUFFER select IIO_KFIFO_BUF help Provides helper functions for setting up triggered buffers. + +config IIO_HW_TRIGGERED_BUFFER + tristate "Industrial I/O hardware triggered buffer support" + select AUXILIARY_BUS + select IIO_TRIGGER + help + Provides helper functions for setting up hardware triggered buffers. diff --git a/drivers/iio/buffer/Makefile b/drivers/iio/buffer/Makefile index 1403eb2f9409..d1142bb20f61 100644 --- a/drivers/iio/buffer/Makefile +++ b/drivers/iio/buffer/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_IIO_BUFFER_DMA) += industrialio-buffer-dma.o obj-$(CONFIG_IIO_BUFFER_DMAENGINE) += industrialio-buffer-dmaengine.o obj-$(CONFIG_IIO_BUFFER_HW_CONSUMER) += industrialio-hw-consumer.o obj-$(CONFIG_IIO_TRIGGERED_BUFFER) += industrialio-triggered-buffer.o +obj-$(CONFIG_IIO_HW_TRIGGERED_BUFFER) += industrialio-hw-triggered-buffer.o obj-$(CONFIG_IIO_KFIFO_BUF) += kfifo_buf.o diff --git a/drivers/iio/buffer/industrialio-hw-triggered-buffer.c b/drivers/iio/buffer/industrialio-hw-triggered-buffer.c new file mode 100644 index 000000000000..7a8a71066b0e --- /dev/null +++ b/drivers/iio/buffer/industrialio-hw-triggered-buffer.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Analog Devices, Inc. + * Copyright (c) 2024 BayLibre, SAS + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int iio_hw_triggered_buffer_match(struct device *dev, const void *match) +{ + return dev->parent == match; +} + +static struct iio_hw_triggered_buffer_device +*iio_hw_trigger_buffer_get(struct device *match) +{ + struct auxiliary_device *adev; + + adev = auxiliary_find_device(NULL, match, iio_hw_triggered_buffer_match); + if (!adev) + return ERR_PTR(-ENOENT); + + return container_of(adev, struct iio_hw_triggered_buffer_device, adev); +} + +static void iio_hw_trigger_buffer_put(void *dev) +{ + put_device(dev); +} + +/** + * devm_iio_hw_triggered_buffer_setup - Setup a hardware triggered buffer + * @dev: Device for devm management + * @indio_dev: An unconfigured/partially configured IIO device struct + * @match: Device for matching the auxiliary bus device that provides the + * interface to the hardware triggered buffer + * @ops: Buffer setup functions to use for this IIO device + * + * Return: 0 on success, negative error code on failure. + * + * This function will search all registered hardware triggered buffers for one + * that matches the given indio_dev. If found, it will be used to setup both + * the trigger and the buffer on the indio_dev. + */ +int devm_iio_hw_triggered_buffer_setup(struct device *dev, + struct iio_dev *indio_dev, + struct device *match, + const struct iio_buffer_setup_ops *ops) +{ + struct iio_hw_triggered_buffer_device *hw; + int ret; + + hw = iio_hw_trigger_buffer_get(match); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + ret = devm_add_action_or_reset(dev, iio_hw_trigger_buffer_put, &hw->adev.dev); + if (ret) + return ret; + + indio_dev->modes |= INDIO_HW_BUFFER_TRIGGERED; + indio_dev->trig = iio_trigger_get(hw->trig); + indio_dev->setup_ops = ops; + + return iio_device_attach_buffer(indio_dev, hw->buffer); +} +EXPORT_SYMBOL_GPL(devm_iio_hw_triggered_buffer_setup); + +static int iio_hw_trigger_buffer_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct iio_hw_triggered_buffer_device *hw = + container_of(adev, struct iio_hw_triggered_buffer_device, adev); + + if (!hw->buffer || !hw->trig) + return -EINVAL; + + return 0; +} + +static const struct auxiliary_device_id iio_hw_trigger_buffer_id_table[] = { + { } +}; +MODULE_DEVICE_TABLE(auxiliary, iio_hw_trigger_buffer_id_table); + +static struct auxiliary_driver iio_hw_trigger_buffer_driver = { + .driver = { + .name = "iio-hw-triggered-buffer", + }, + .probe = iio_hw_trigger_buffer_probe, + .id_table = iio_hw_trigger_buffer_id_table, +}; +module_auxiliary_driver(iio_hw_trigger_buffer_driver); + +MODULE_AUTHOR("David Lechner "); +MODULE_DESCRIPTION("IIO helper functions for setting up hardware triggered buffers"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/iio/hw_triggered_buffer.h b/include/linux/iio/hw_triggered_buffer.h new file mode 100644 index 000000000000..6bd8035f1b92 --- /dev/null +++ b/include/linux/iio/hw_triggered_buffer.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_IIO_HW_TRIGGEREDED_BUFFER_H_ +#define _LINUX_IIO_HW_TRIGGEREDED_BUFFER_H_ + +struct device; +struct iio_dev; +struct iio_buffer_setup_ops; + +int devm_iio_hw_triggered_buffer_setup(struct device *dev, + struct iio_dev *indio_dev, + struct device *match, + const struct iio_buffer_setup_ops *ops); + +#endif /* _LINUX_IIO_HW_TRIGGEREDED_BUFFER_H_ */ diff --git a/include/linux/iio/hw_triggered_buffer_impl.h b/include/linux/iio/hw_triggered_buffer_impl.h new file mode 100644 index 000000000000..d9a3ad2c8c24 --- /dev/null +++ b/include/linux/iio/hw_triggered_buffer_impl.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_IIO_HW_TRIGGEREDED_BUFFER_IMPL_H_ +#define _LINUX_IIO_HW_TRIGGEREDED_BUFFER_IMPL_H_ + +#include + +struct iio_buffer; +struct iio_trigger; + +struct iio_hw_triggered_buffer_device { + struct auxiliary_device adev; + struct iio_buffer *buffer; + struct iio_trigger *trig; +}; + +#endif /* _LINUX_IIO_HW_TRIGGEREDED_BUFFER_IMPL_H_ */ From patchwork Wed Jan 10 19:49:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516430 Received: from mail-oo1-f45.google.com (mail-oo1-f45.google.com [209.85.161.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 571A84F60F for ; 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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:17 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/13] bus: auxiliary: increase AUXILIARY_NAME_SIZE Date: Wed, 10 Jan 2024 13:49:50 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-9-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 The auxiliary bus uses names in the form of "module_name.device_name" for matching devices to drivers. Since the module name is the actual module name, it can be quite long which doesn't leave enough room for the device name. This patch increases the size AUXILIARY_NAME_SIZE to 64 to allow for both a ~32 character module name and a ~32 character device name. Signed-off-by: David Lechner --- include/linux/mod_devicetable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index f458469c5ce5..4bd2d20067b6 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -861,7 +861,7 @@ struct mhi_device_id { kernel_ulong_t driver_data; }; -#define AUXILIARY_NAME_SIZE 32 +#define AUXILIARY_NAME_SIZE 64 #define AUXILIARY_MODULE_PREFIX "auxiliary:" struct auxiliary_device_id { From patchwork Wed Jan 10 19:49:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516433 Received: from mail-oo1-f45.google.com (mail-oo1-f45.google.com [209.85.161.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A5C14F897 for ; Wed, 10 Jan 2024 19:51:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="DYtCGZ85" Received: by mail-oo1-f45.google.com with SMTP id 006d021491bc7-58e256505f7so2394602eaf.3 for ; Wed, 10 Jan 2024 11:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1704916278; x=1705521078; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WoFvxKWdDooo1qSzC88EM9Nr4w+h9Vd46EFkbYPsSPw=; b=DYtCGZ85pbfryJGNqhUF4Mwq/s2IJBCLYdbVXcZLOQTTMhJS86QolB3UIl1+Emd3nB P6ckUQiZlcgKwajSzt4FjkrPaY87p8sqQWrhlaIclD27u9YQLMHhY1Fw+l/lU4d0lejW ubUKXLJgEZ8pRnHY0PT5osdpTQDm3alUwirTkAbcpz6EFjJcGt6hI+kwYpkxx8PYImOJ oTyfdO73QCXeXWx1hl9OHm6IvpZmEovhyGlhSvzb8fxNsQq+ckrJk8f2MSywULRb0aF+ +wscSNVNacPlJS89FFH+DcLyrhP5gyhytLFKeL8R5/EWqDtXyeopuhGVbeqURHNH4+3f 6HGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704916278; x=1705521078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WoFvxKWdDooo1qSzC88EM9Nr4w+h9Vd46EFkbYPsSPw=; b=sdn2WPNrv8IdfKvRkQn/wpTwVBxqKWHnNSZDpdN8WYz9HBMkFTZF43ksZ1H59FkSrj OyDaA5U1LCO9GCe3oGy+lQK18weKuQoEvJGZO8CsuccISZGprhTlCCSMydnS2XVlt6IB +HqD2P6VczjWTHg1dh8WFPlroKmxRkDkd8IzoYpx8/Wtn3ZTRxUqQGc/8D6N4mTt1daR 20W62EGNa2/n5W4ru/ctYZbOokC/hNPdgd6YD7gf0ADB+7r91YGt3jaztLuW1jj19xvX s+KkpbokWqLoizwBSQfigx7o+K4vvnZazYNXa35R+P2wiE/edPiQFJIC/e1LdqZ3n4KG TzaA== X-Gm-Message-State: AOJu0YyiQZngmgZhXdmJ7ABoPpLGHqdBrswPcdukuPCNLKjlY8B7H/x2 RT6NRFGoYtG+IDT6CC38JAwsimFOp3Oe8w== X-Google-Smtp-Source: AGHT+IHrT/0uM2BhirfFIgGw42yzsFECk08FhInWXcIqOlIBJJbxXE41ntQmPNJUuiNBiHuZt4yDqw== X-Received: by 2002:a05:6820:1ca2:b0:594:3789:1aaf with SMTP id ct34-20020a0568201ca200b0059437891aafmr100073oob.15.1704916278503; Wed, 10 Jan 2024 11:51:18 -0800 (PST) Received: from freyr.lechnology.com (ip98-183-112-25.ok.ok.cox.net. [98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:18 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/13] iio: buffer: dmaengine: export devm_iio_dmaengine_buffer_alloc() Date: Wed, 10 Jan 2024 13:49:51 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-10-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This changes devm_iio_dmaengine_buffer_alloc() to an exported symbol. This will be used by drivers that need to allocate a DMA buffer without attaching it to an IIO device. Signed-off-by: David Lechner --- Documentation/driver-api/driver-model/devres.rst | 1 + drivers/iio/buffer/Kconfig | 14 +++++++------- drivers/iio/buffer/industrialio-buffer-dmaengine.c | 3 ++- include/linux/iio/buffer-dmaengine.h | 2 ++ 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/Documentation/driver-api/driver-model/devres.rst b/Documentation/driver-api/driver-model/devres.rst index b23d4a2b68a6..60e4b7ba38e5 100644 --- a/Documentation/driver-api/driver-model/devres.rst +++ b/Documentation/driver-api/driver-model/devres.rst @@ -285,6 +285,7 @@ I2C IIO devm_iio_device_alloc() devm_iio_device_register() + devm_iio_dmaengine_buffer_alloc() devm_iio_dmaengine_buffer_setup() devm_iio_kfifo_buffer_setup() devm_iio_kfifo_buffer_setup_ext() diff --git a/drivers/iio/buffer/Kconfig b/drivers/iio/buffer/Kconfig index 925c5bf074bc..27d82fb4bc4d 100644 --- a/drivers/iio/buffer/Kconfig +++ b/drivers/iio/buffer/Kconfig @@ -40,6 +40,13 @@ config IIO_BUFFER_HW_CONSUMER Should be selected by drivers that want to use the generic Hw consumer interface. +config IIO_HW_TRIGGERED_BUFFER + tristate "Industrial I/O hardware triggered buffer support" + select AUXILIARY_BUS + select IIO_TRIGGER + help + Provides helper functions for setting up hardware triggered buffers. + config IIO_KFIFO_BUF tristate "Industrial I/O buffering based on kfifo" help @@ -53,10 +60,3 @@ config IIO_TRIGGERED_BUFFER select IIO_KFIFO_BUF help Provides helper functions for setting up triggered buffers. - -config IIO_HW_TRIGGERED_BUFFER - tristate "Industrial I/O hardware triggered buffer support" - select AUXILIARY_BUS - select IIO_TRIGGER - help - Provides helper functions for setting up hardware triggered buffers. diff --git a/drivers/iio/buffer/industrialio-buffer-dmaengine.c b/drivers/iio/buffer/industrialio-buffer-dmaengine.c index c67ddf963bfb..03225939f223 100644 --- a/drivers/iio/buffer/industrialio-buffer-dmaengine.c +++ b/drivers/iio/buffer/industrialio-buffer-dmaengine.c @@ -244,7 +244,7 @@ static void __devm_iio_dmaengine_buffer_free(void *buffer) * * The buffer will be automatically de-allocated once the device gets destroyed. */ -static struct iio_buffer *devm_iio_dmaengine_buffer_alloc(struct device *dev, +struct iio_buffer *devm_iio_dmaengine_buffer_alloc(struct device *dev, const char *channel) { struct iio_buffer *buffer; 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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:19 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/13] dt-bindings: iio: offload: add binding for PWM/DMA triggered buffer Date: Wed, 10 Jan 2024 13:49:52 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-11-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds a new binding for a PWM trigger and DMA data output connected to an SPI controller offload instance. Signed-off-by: David Lechner --- .../adi,spi-offload-pwm-trigger-dma-buffer.yaml | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/offload/adi,spi-offload-pwm-trigger-dma-buffer.yaml b/Documentation/devicetree/bindings/iio/offload/adi,spi-offload-pwm-trigger-dma-buffer.yaml new file mode 100644 index 000000000000..748cfab19eff --- /dev/null +++ b/Documentation/devicetree/bindings/iio/offload/adi,spi-offload-pwm-trigger-dma-buffer.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/offload/adi,spi-offload-pwm-trigger-dma-buffer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI Offload with PWM Trigger and DMA Buffer Data Output + +maintainers: + - Michael Hennerich + - Nuno Sá + +description: | + This binding describes the connection of a PWM device to the trigger input + and a DMA channel to the output data stream of a SPI Offload instance. + + https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload + https://wiki.analog.com/resources/fpga/peripherals/spi_engine/tutorial + +$ref: /schemas/spi/adi,axi-spi-engine.yaml#/$defs/offload + +properties: + compatible: + const: adi,spi-offload-pwm-trigger-dma-buffer + + reg: + maxItems: 1 + + pwms: + maxItems: 1 + + dmas: + maxItems: 1 + +required: + - compatible + - pwms + - dmas + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + offloads { + #address-cells = <1>; + #size-cells = <0>; + + offload@0 { + compatible = "adi,spi-offload-pwm-trigger-dma-buffer"; + reg = <0>; + pwms = <&pwm 0>; + dmas = <&dma 0>; + }; + }; + }; From patchwork Wed Jan 10 19:49:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516434 Received: from mail-oo1-f41.google.com (mail-oo1-f41.google.com [209.85.161.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43B6D50256 for ; Wed, 10 Jan 2024 19:51:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="cbfW3zrC" Received: by mail-oo1-f41.google.com with SMTP id 006d021491bc7-5989add5511so500148eaf.3 for ; Wed, 10 Jan 2024 11:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1704916280; x=1705521080; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EAfisbraTIzPK5DNS+hXkieTeMFvO6LSXMmUPvgA/Yc=; b=cbfW3zrCzDrC2BsJDrvGh2OelkTFByfUxrTt4miiSoq3fT2DmiaOTNftPRWZpCoOMx d2gRMxkafALFBhuUMrgpW94onVz/j6zq9twsooZAcfDJjKfKEzZgraYwAbGXhD6Zghsq jJx0T8rDjFrVaUrO+t8X0MvaVxOgQ1xgAUgJ7fvEBYdarHT4UnehFRbSfLRMMDBJXRTn K9GOLzBYfxx6vyu/gIx8rYr65+rrnCasMncpBEp/1+vTM69O9WL8Au56+V2Lkx0qVqFO oWYSHYXHlXnI4J7I5KebEWMiw2meBOD2gser2+Kfzy+h/VdaDE9HkkEk7D0wSLUYyIdz MmRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704916280; x=1705521080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EAfisbraTIzPK5DNS+hXkieTeMFvO6LSXMmUPvgA/Yc=; b=ajkewWVcKmWIfjkjiPRjnavv8icuU3sS5pD6ZYyjAgTFZQ1vKBuN2SqBJqbCHP9QhI BSAAPGW5Ejjq9UCUV7QCKb4AGapxs4atA6a1h+ULQ7z1xKqAhW1rLIMF3ce1s3VHuUfU eb4/Xic2SEnzfWZbjtPlCdNnxDRr1YuEGGJX6QjjNovpJ41R7chc5NY7syAutJXgYS6U okgZLSZE/EcCjILNAftwcM82V6ilFAhhAmbVXewLWyXL/i5Ka8i3qAjJDmrdpXfOMIiA /MgXXgQVw8rRjuVVIf/n9+WJlzBAUTtM0gnghgWcDwsEOnZl2xGCT8IyphOTgphzs58U /Vxg== X-Gm-Message-State: AOJu0YyfmmBHGp9eBZ4utwZzrmDi9U5yOXlD1vlO6IKvOGIn6HrAht85 y0qo2ks1UkWIrMZ2FLY2UoO13tvs5oIhTQ== X-Google-Smtp-Source: AGHT+IHTumG0RvNmGteYGaGu6Rft2bQuoGUvLiP+GdymDcLixB0l11q6v2G9HH89HiPnDLtdCilfmg== X-Received: by 2002:a4a:3503:0:b0:590:2b6d:a862 with SMTP id l3-20020a4a3503000000b005902b6da862mr94634ooa.15.1704916280323; Wed, 10 Jan 2024 11:51:20 -0800 (PST) Received: from freyr.lechnology.com (ip98-183-112-25.ok.ok.cox.net. [98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:20 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/13] iio: offload: add new PWM triggered DMA buffer driver Date: Wed, 10 Jan 2024 13:49:53 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-12-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This adds a new driver for handling SPI offloading using a PWM as the trigger and DMA for the received data. This will be used by ADCs in conjunction with SPI controllers with offloading support to be able to sample at high rates without CPU intervention. Signed-off-by: David Lechner --- drivers/iio/Kconfig | 1 + drivers/iio/Makefile | 1 + .../iio/buffer/industrialio-hw-triggered-buffer.c | 1 + drivers/iio/offload/Kconfig | 21 ++ drivers/iio/offload/Makefile | 2 + drivers/iio/offload/iio-pwm-triggered-dma-buffer.c | 212 +++++++++++++++++++++ 6 files changed, 238 insertions(+) diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig index 52eb46ef84c1..56738282d82f 100644 --- a/drivers/iio/Kconfig +++ b/drivers/iio/Kconfig @@ -90,6 +90,7 @@ source "drivers/iio/imu/Kconfig" source "drivers/iio/light/Kconfig" source "drivers/iio/magnetometer/Kconfig" source "drivers/iio/multiplexer/Kconfig" +source "drivers/iio/offload/Kconfig" source "drivers/iio/orientation/Kconfig" source "drivers/iio/test/Kconfig" if IIO_TRIGGER diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile index 9622347a1c1b..20acf5e1a4a7 100644 --- a/drivers/iio/Makefile +++ b/drivers/iio/Makefile @@ -34,6 +34,7 @@ obj-y += imu/ obj-y += light/ obj-y += magnetometer/ obj-y += multiplexer/ +obj-y += offload/ obj-y += orientation/ obj-y += position/ obj-y += potentiometer/ diff --git a/drivers/iio/buffer/industrialio-hw-triggered-buffer.c b/drivers/iio/buffer/industrialio-hw-triggered-buffer.c index 7a8a71066b0e..a2fae6059616 100644 --- a/drivers/iio/buffer/industrialio-hw-triggered-buffer.c +++ b/drivers/iio/buffer/industrialio-hw-triggered-buffer.c @@ -86,6 +86,7 @@ static int iio_hw_trigger_buffer_probe(struct auxiliary_device *adev, } static const struct auxiliary_device_id iio_hw_trigger_buffer_id_table[] = { + { .name = "pwm-triggered-dma-buffer.triggered-buffer" }, { } }; MODULE_DEVICE_TABLE(auxiliary, iio_hw_trigger_buffer_id_table); diff --git a/drivers/iio/offload/Kconfig b/drivers/iio/offload/Kconfig new file mode 100644 index 000000000000..760c0cfe0e9c --- /dev/null +++ b/drivers/iio/offload/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# SPI offload handlers for Industrial I/O +# +# When adding new entries keep the list in alphabetical order + +menu "SPI offload handlers" + +config IIO_PWM_TRIGGERED_DMA_BUFFER + tristate "PWM trigger and DMA buffer connected to SPI offload" + select AUXILIARY_BUS + select IIO_BUFFER_DMAENGINE + help + Provides a periodic hardware trigger via a PWM connected to the + trigger input of a SPI offload and a hardware buffer implemented + via DMA connected to the data output stream the a SPI offload. + + To compile this driver as a module, choose M here: the + module will be called "iio-pwm-triggered-dma-buffer". + +endmenu diff --git a/drivers/iio/offload/Makefile b/drivers/iio/offload/Makefile new file mode 100644 index 000000000000..7300ce82f066 --- /dev/null +++ b/drivers/iio/offload/Makefile @@ -0,0 +1,2 @@ + +obj-$(CONFIG_IIO_PWM_TRIGGERED_DMA_BUFFER) := iio-pwm-triggered-dma-buffer.o diff --git a/drivers/iio/offload/iio-pwm-triggered-dma-buffer.c b/drivers/iio/offload/iio-pwm-triggered-dma-buffer.c new file mode 100644 index 000000000000..970ea82316f6 --- /dev/null +++ b/drivers/iio/offload/iio-pwm-triggered-dma-buffer.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Platform driver for a PWM trigger and DMA buffer connected to a SPI + * controller offload instance implementing the iio-hw-triggered-buffer + * interface. + * + * Copyright (C) 2023 Analog Devices, Inc. + * Copyright (C) 2023 BayLibre, SAS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct iio_pwm_triggered_dma_buffer { + struct iio_hw_triggered_buffer_device hw; + struct pwm_device *pwm; +}; + +static const struct iio_trigger_ops iio_pwm_triggered_dma_buffer_ops; + +static int iio_pwm_triggered_dma_buffer_set_state(struct iio_trigger *trig, bool state) +{ + struct iio_pwm_triggered_dma_buffer *st = iio_trigger_get_drvdata(trig); + + if (state) + return pwm_enable(st->pwm); + + pwm_disable(st->pwm); + + return 0; +} + +static int iio_pwm_triggered_dma_buffer_validate_device(struct iio_trigger *trig, + struct iio_dev *indio_dev) +{ + /* Don't allow assigning trigger via sysfs. */ + return -EINVAL; +} + +static const struct iio_trigger_ops iio_pwm_triggered_dma_buffer_ops = { + .set_trigger_state = iio_pwm_triggered_dma_buffer_set_state, + .validate_device = iio_pwm_triggered_dma_buffer_validate_device, +}; + +static u32 axi_spi_engine_offload_pwm_trigger_get_rate(struct iio_trigger *trig) +{ + struct iio_pwm_triggered_dma_buffer *st = iio_trigger_get_drvdata(trig); + u64 period_ns = pwm_get_period(st->pwm); + + if (period_ns) + return DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, period_ns); + + return 0; +} + +static int +axi_spi_engine_offload_set_samp_freq(struct iio_pwm_triggered_dma_buffer *st, + u32 requested_hz) +{ + int period_ns; + + if (requested_hz == 0) + return -EINVAL; + + period_ns = DIV_ROUND_UP(NSEC_PER_SEC, requested_hz); + + /* + * FIXME: We really just need a clock, not a PWM. The current duty cycle + * value is a hack to work around the edge vs. level offload trigger + * issue in the ADI AXI SPI Engine firmware. + */ + return pwm_config(st->pwm, 10, period_ns); +} + +static ssize_t sampling_frequency_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct iio_trigger *trig = to_iio_trigger(dev); + + return sysfs_emit(buf, "%u\n", + axi_spi_engine_offload_pwm_trigger_get_rate(trig)); +} + +static ssize_t sampling_frequency_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_trigger *trig = to_iio_trigger(dev); + struct iio_pwm_triggered_dma_buffer *st = iio_trigger_get_drvdata(trig); + int ret; + u32 val; + + ret = kstrtou32(buf, 10, &val); + if (ret) + return ret; + + ret = axi_spi_engine_offload_set_samp_freq(st, val); + if (ret) + return ret; + + return len; +} + +static DEVICE_ATTR_RW(sampling_frequency); + +static struct attribute *iio_pwm_triggered_dma_buffer_attrs[] = { + &dev_attr_sampling_frequency.attr, + NULL +}; + +ATTRIBUTE_GROUPS(iio_pwm_triggered_dma_buffer); + +static void iio_pwm_triggered_dma_buffer_adev_release(struct device *dev) +{ +} + +static void iio_pwm_triggered_dma_buffer_unregister_adev(void *adev) +{ + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int iio_pwm_triggered_dma_buffer_probe(struct platform_device *pdev) +{ + struct iio_pwm_triggered_dma_buffer *st; + struct auxiliary_device *adev; + int ret; + + st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); + if (!st) + return -ENOMEM; + + st->pwm = devm_pwm_get(&pdev->dev, NULL); + if (IS_ERR(st->pwm)) + return dev_err_probe(&pdev->dev, PTR_ERR(st->pwm), + "failed to get PWM\n"); + + st->hw.buffer = devm_iio_dmaengine_buffer_alloc(&pdev->dev, "rx"); + if (IS_ERR(st->hw.buffer)) + return dev_err_probe(&pdev->dev, PTR_ERR(st->hw.buffer), + "failed to allocate buffer\n"); + + st->hw.trig = devm_iio_trigger_alloc(&pdev->dev, "%s-%s-pwm-trigger", + dev_name(pdev->dev.parent), + dev_name(&pdev->dev)); + if (!st->hw.trig) + return -ENOMEM; + + st->hw.trig->ops = &iio_pwm_triggered_dma_buffer_ops; + st->hw.trig->dev.parent = &pdev->dev; + st->hw.trig->dev.groups = iio_pwm_triggered_dma_buffer_groups; + iio_trigger_set_drvdata(st->hw.trig, st); + + /* start with a reasonable default value */ + ret = axi_spi_engine_offload_set_samp_freq(st, 1000); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to set sampling frequency\n"); + + ret = devm_iio_trigger_register(&pdev->dev, st->hw.trig); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to register trigger\n"); + + adev = &st->hw.adev; + adev->name = "triggered-buffer"; + adev->dev.parent = &pdev->dev; + adev->dev.release = iio_pwm_triggered_dma_buffer_adev_release; + adev->id = 0; + + ret = auxiliary_device_init(adev); + if (ret) + return ret; + + ret = auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(&pdev->dev, + iio_pwm_triggered_dma_buffer_unregister_adev, adev); +} + +static const struct of_device_id iio_pwm_triggered_dma_buffer_match_table[] = { + { .compatible = "adi,spi-offload-pwm-trigger-dma-buffer" }, + { } +}; +MODULE_DEVICE_TABLE(of, iio_pwm_triggered_dma_buffer_match_table); + +static struct platform_driver iio_pwm_triggered_dma_buffer_driver = { + .probe = iio_pwm_triggered_dma_buffer_probe, + .driver = { + .name = "iio-pwm-triggered-dma-buffer", + .of_match_table = iio_pwm_triggered_dma_buffer_match_table, + }, +}; +module_platform_driver(iio_pwm_triggered_dma_buffer_driver); + +MODULE_AUTHOR("David Lechner "); +MODULE_DESCRIPTION("AXI SPI Engine Offload PWM Trigger"); +MODULE_LICENSE("GPL"); From patchwork Wed Jan 10 19:49:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 13516435 Received: from mail-oo1-f47.google.com (mail-oo1-f47.google.com [209.85.161.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E57C50274 for ; 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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 187-20020a4a0dc4000000b00595b35927a3sm938513oob.39.2024.01.10.11.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 11:51:20 -0800 (PST) From: David Lechner To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Frank Rowand Cc: David Lechner , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Corbet , linux-spi@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/13] iio: adc: ad7380: add SPI offload support Date: Wed, 10 Jan 2024 13:49:54 -0600 Message-ID: <20240109-axi-spi-engine-series-3-v1-13-e42c6a986580@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> References: <20240109-axi-spi-engine-series-3-v1-0-e42c6a986580@baylibre.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mailer: b4 0.12.4 This extends the ad7380 ADC driver to use the offload capabilities of capable SPI controllers. When offload support is available, a hardware triggered buffer is used to allow sampling a high rates without CPU intervention. To keep things simple, when this feature is present in hardware we disable the usual IIO triggered buffer and software timestamp rather than trying to support multiple buffers. Signed-off-by: David Lechner --- drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad7380.c | 84 +++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 80 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index cbfd626712e3..da44b585ea46 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -128,6 +128,7 @@ config AD7380 select IIO_BUFFER select IIO_TRIGGER select IIO_TRIGGERED_BUFFER + select IIO_HW_TRIGGERED_BUFFER help AD7380 is a family of simultaneous sampling ADCs that share the same SPI register map and have similar pinouts. diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 80712aaa9548..a71e8b81950b 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -133,6 +134,7 @@ struct ad7380_state { struct spi_device *spi; struct regulator *vref; struct regmap *regmap; + struct spi_offload *spi_offload; /* * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. @@ -335,6 +337,50 @@ static const struct iio_info ad7380_info = { .debugfs_reg_access = &ad7380_debugfs_reg_access, }; +static int ad7380_buffer_preenable(struct iio_dev *indio_dev) +{ + struct ad7380_state *st = iio_priv(indio_dev); + struct spi_transfer xfer = { + .bits_per_word = st->chip_info->channels[0].scan_type.realbits, + .len = 4, + .rx_buf = SPI_OFFLOAD_RX_SENTINEL, + }; + + return spi_offload_prepare(st->spi_offload, st->spi, &xfer, 1); +} + +static int ad7380_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad7380_state *st = iio_priv(indio_dev); + + return spi_offload_enable(st->spi_offload); +} + +static int ad7380_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad7380_state *st = iio_priv(indio_dev); + + spi_offload_disable(st->spi_offload); + + return 0; +} + +static int ad7380_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad7380_state *st = iio_priv(indio_dev); + + spi_offload_unprepare(st->spi_offload); + + return 0; +} + +static const struct iio_buffer_setup_ops ad7380_buffer_ops = { + .preenable = &ad7380_buffer_preenable, + .postenable = &ad7380_buffer_postenable, + .predisable = &ad7380_buffer_predisable, + .postdisable = &ad7380_buffer_postdisable, +}; + static int ad7380_init(struct ad7380_state *st) { int ret; @@ -417,11 +463,39 @@ static int ad7380_probe(struct spi_device *spi) indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->available_scan_masks = ad7380_2_channel_scan_masks; - ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, - iio_pollfunc_store_time, - ad7380_trigger_handler, NULL); - if (ret) - return ret; + st->spi_offload = spi_offload_get(spi, 0); + if (IS_ERR(st->spi_offload)) { + ret = PTR_ERR(st->spi_offload); + + if (ret == -EOPNOTSUPP) + st->spi_offload = NULL; + else + return dev_err_probe(&spi->dev, ret, + "failed to get SPI offload\n"); + } + + if (st->spi_offload) { + /* + * We can't have a soft timestamp (always last channel) when + * using a hardware triggered buffer. + */ + indio_dev->num_channels -= 1; + + ret = devm_iio_hw_triggered_buffer_setup(&spi->dev, + indio_dev, + st->spi_offload->dev, + &ad7380_buffer_ops); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to setup offload\n"); + } else { + ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, + iio_pollfunc_store_time, + ad7380_trigger_handler, + NULL); + if (ret) + return ret; + } ret = ad7380_init(st); if (ret)