From patchwork Thu Jan 11 11:04:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46E97C4707B for ; Thu, 11 Jan 2024 11:08:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNss7-0001Kv-NH; Thu, 11 Jan 2024 06:05:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss4-0001Jw-S1 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:12 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss1-0004N3-Qg for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:12 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3374eb61cbcso4674105f8f.0 for ; Thu, 11 Jan 2024 03:05:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971107; x=1705575907; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MdZwmTLITE8hM1960RQmf+O/Y15HZKpOylRTPJryBDk=; b=qkVW2vZ3aU/PhGkaOGoao9R6aq68PcAuA+uIwBW36uN/8L+TCHNZIYf4VTYHgguGks bFz6rrv4Fy0fbW4bjzoLwua+C6va4a+n0Iuc8Ch3qeLcpYOb0Rc4pMACX6wQCqCjF6Jp wroJCR6fXJwUNYctoID4y+UiTEGnPjpkVflNVHA4dbUa2asQwjkvA6/P23/AvLBisbAM oWORuMg/+frXngB5hYnRU2rMvpWK+CVDURMvXkrZyON+bP6lfCgxeOk5ZmbOHEQgdnVc KbXX+HOD37r1DzSnq0JhxwSp2GEK5NI/xEvJNCAlmfNMzv9S/Q6Wt/BoZkugTu+SnOoY cTTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971107; x=1705575907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MdZwmTLITE8hM1960RQmf+O/Y15HZKpOylRTPJryBDk=; b=kTDNPWoYDnehaJy/Bm6H1Ptr6OQOIse9HZ19Q+BVXeAu5ut94zEgw1DcKHAvAXLewi QTR/KEX7zQt1k1Qr5kiJ0Nk2eQKaTWj9+OJAudBy9XtVbhvCB4XGCu8KaQL+4XV27LVS tl0YWpxPZWh/XXxk4CRTqN6fu3eLLttUCrrIOR7smYwALsfSnhhO/YW6r0j+Vw4PD/WS NfW9Q+KZfSVvEGTs4QjCIzRZ2EWHSXfSIDpkmVu8JBN6GFCFEZjNZ0S2nSCZYcFltzqi G5hap32y6RUaWlSkjM6uFVXCXQz4viICjiHj6+XiHKw+exnGb/YF0Nmq/VAj+fGtwbL5 lT+Q== X-Gm-Message-State: AOJu0YxzGbg7iafPyZljP1PSdhSsPI3K/trRq6g7SiP1pVg5tBVusF7/ VuM7AKVhxYOVfoBHnBcEyw3+ZTDdEL+Osx6omv3nxYXmfqY= X-Google-Smtp-Source: AGHT+IGu89YwMtdCi41Bi0dSZSvqIkhmyDo8aKEvejO8MfjcrCZBhCwU+Uc3GpctDOE6oDyn1Kj1rQ== X-Received: by 2002:adf:ce83:0:b0:336:7790:6a36 with SMTP id r3-20020adfce83000000b0033677906a36mr542240wrn.129.1704971107649; Thu, 11 Jan 2024 03:05:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/41] hw/arm: add cache controller for Freescale i.MX6 Date: Thu, 11 Jan 2024 11:04:25 +0000 Message-Id: <20240111110505.1563291-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Nikita Ostrenkov Signed-off-by: Nikita Ostrenkov Reviewed-by: Philippe Mathieu-Daudé Message-id: 20231219105510.4907-1-n.ostrenkov@gmail.com [PMM: fixed stray whitespace] Signed-off-by: Peter Maydell --- hw/arm/fsl-imx6.c | 3 +++ hw/arm/Kconfig | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index b2153022c04..af2e982b052 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -154,6 +154,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); } + /* L2 cache controller */ + sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { return; } diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 660f49db498..b853577e725 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -537,6 +537,7 @@ config FSL_IMX6 select IMX_I2C select IMX_USBPHY select WDT_IMX2 + select PL310 # cache controller select SDHCI config ASPEED_SOC From patchwork Thu Jan 11 11:04:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 981F9C4707B for ; Thu, 11 Jan 2024 11:14:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssR-0001RV-HV; Thu, 11 Jan 2024 06:05:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss5-0001Jz-21 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss1-0004N8-Lz for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:12 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3374e332124so4018764f8f.2 for ; Thu, 11 Jan 2024 03:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971108; x=1705575908; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bt6pFgMxYQrPt6S3CAwmSz7UkOhzZR/7nCH1KuyRR1Q=; b=Tm6HM7zzVDgxu0te0xLm5Q+fhlO4mI4hCETi4ZSKQ3Xlq2m+jfSIIKvVS+DsIUwirT RzxzqyjEIUYc/4Xa7VKglXwfEVcqmY5J1WdGt64OumQuvnjy7E6YwBRoF99zFCmiKxrg JiMJA9ftTO0cD30s7CG0ezF54SknOf3jTEfxEUt4Sfc8N11/8i9gLXEqu85s8F4Lbc4E obU4gkEaD9Lgdhy6yVn9RfoxLJE1YnD11OI7ZKidPn8mD/WdpjZN/W9zPJSp/rckDlyW levXERBfofZWu2JxRK/95ARnKv5xGHIsfGgPhIwYjSvHYnZQirJPsyyOFHTtVsm6PyOm vmYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971108; x=1705575908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bt6pFgMxYQrPt6S3CAwmSz7UkOhzZR/7nCH1KuyRR1Q=; b=Ks5sgto+7nC1/HuGG5k9Ri3nYusxNY/ieVGYMNEOVeta7ilvUtAC4lyRcUwMHXnT0C 97vO1xWRz2e3ELpvFcTj/bkmCbG1HcQRlpdp8KtMbO1FSg1NWDrO69BIvr96wWqbg08f SEMYNetK2YY82+GZvtsiVtBmBbDTz/Fd0+P37ELQfGL8I9kGojIvW4ZpITUGxBsYRJ4Z G0CGlpnwk5wP8ngGs/mwVKmQLv9U1tOr33+qRnTqxpP4xeAfsTsApg/+noLWxa++KPJr ml0AWZSlgeC5Sh1GKiulEIJ0QR7cbiA+H36EAkH2hJI916aKTTG8WnocGwUzDvROIjyt jBcA== X-Gm-Message-State: AOJu0YxDv4KfId2Zy0gQ1OIwDX8chrnbNRJjXmq81bzOyGMQTqo5/dZb eno7E4KYaOAybkm4s98xMIQiQElFhPYc8UOzETLmU1gHDbA= X-Google-Smtp-Source: AGHT+IEICNRpVtWoJ6Hk7d2V75MaRSmQv3xYSpGtrLXEJMlFNgdFZ3tcObb9BYJz/5/Ugkhdp+l/3g== X-Received: by 2002:a05:6000:504:b0:336:6c0d:b79f with SMTP id a4-20020a056000050400b003366c0db79fmr507785wrf.39.1704971108139; Thu, 11 Jan 2024 03:05:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/41] hw/arm: Add minimal support for the STM32L4x5 SoC Date: Thu, 11 Jan 2024 11:04:26 +0000 Message-Id: <20240111110505.1563291-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Inès Varhol This patch adds a new STM32L4x5 SoC, it is necessary to add support for the B-L475E-IOT01A board. The implementation is derived from the STM32F405 SoC. The implementation contains no peripherals, only memory regions are implemented. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Message-id: 20240108135849.351719-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- MAINTAINERS | 8 + include/hw/arm/stm32l4x5_soc.h | 57 +++++++ hw/arm/stm32l4x5_soc.c | 265 +++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 5 + hw/arm/meson.build | 1 + 5 files changed, 336 insertions(+) create mode 100644 include/hw/arm/stm32l4x5_soc.h create mode 100644 hw/arm/stm32l4x5_soc.c diff --git a/MAINTAINERS b/MAINTAINERS index 00ec1f7ecaf..da29dcc16ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1122,6 +1122,14 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/olimex-stm32-h405.c +STM32L4x5 SoC Family +M: Arnaud Minier +M: Inès Varhol +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/stm32l4x5_soc.c +F: include/hw/arm/stm32l4x5_soc.h + SmartFusion2 M: Subbaraya Sundeep M: Peter Maydell diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h new file mode 100644 index 00000000000..2fd44a36a9d --- /dev/null +++ b/include/hw/arm/stm32l4x5_soc.h @@ -0,0 +1,57 @@ +/* + * STM32L4x5 SoC family + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * This work is heavily inspired by the stm32f405_soc by Alistair Francis. + * Original code is licensed under the MIT License: + * + * Copyright (c) 2014 Alistair Francis + */ + +/* + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html + */ + +#ifndef HW_ARM_STM32L4x5_SOC_H +#define HW_ARM_STM32L4x5_SOC_H + +#include "exec/memory.h" +#include "hw/arm/armv7m.h" +#include "qom/object.h" + +#define TYPE_STM32L4X5_SOC "stm32l4x5-soc" +#define TYPE_STM32L4X5XC_SOC "stm32l4x5xc-soc" +#define TYPE_STM32L4X5XE_SOC "stm32l4x5xe-soc" +#define TYPE_STM32L4X5XG_SOC "stm32l4x5xg-soc" +OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC) + +struct Stm32l4x5SocState { + SysBusDevice parent_obj; + + ARMv7MState armv7m; + + MemoryRegion sram1; + MemoryRegion sram2; + MemoryRegion flash; + MemoryRegion flash_alias; + + Clock *sysclk; + Clock *refclk; +}; + +struct Stm32l4x5SocClass { + SysBusDeviceClass parent_class; + + size_t flash_size; +}; + +#endif diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c new file mode 100644 index 00000000000..70609a6dac4 --- /dev/null +++ b/hw/arm/stm32l4x5_soc.c @@ -0,0 +1,265 @@ +/* + * STM32L4x5 SoC family + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * This work is heavily inspired by the stm32f405_soc by Alistair Francis. + * Original code is licensed under the MIT License: + * + * Copyright (c) 2014 Alistair Francis + */ + +/* + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "hw/arm/stm32l4x5_soc.h" +#include "hw/qdev-clock.h" +#include "hw/misc/unimp.h" + +#define FLASH_BASE_ADDRESS 0x08000000 +#define SRAM1_BASE_ADDRESS 0x20000000 +#define SRAM1_SIZE (96 * KiB) +#define SRAM2_BASE_ADDRESS 0x10000000 +#define SRAM2_SIZE (32 * KiB) + +static void stm32l4x5_soc_initfn(Object *obj) +{ + Stm32l4x5SocState *s = STM32L4X5_SOC(obj); + + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); + s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); +} + +static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) +{ + ERRP_GUARD(); + Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc); + const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc); + MemoryRegion *system_memory = get_system_memory(); + DeviceState *armv7m; + + /* + * We use s->refclk internally and only define it with qdev_init_clock_in() + * so it is correctly parented and not leaked on an init/deinit; it is not + * intended as an externally exposed clock. + */ + if (clock_has_source(s->refclk)) { + error_setg(errp, "refclk clock must not be wired up by the board code"); + return; + } + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"); + return; + } + + /* + * TODO: ideally we should model the SoC RCC and its ability to + * change the sysclk frequency and define different sysclk sources. + */ + + /* The refclk always runs at frequency HCLK / 8 */ + clock_set_mul_div(s->refclk, 8, 1); + clock_set_source(s->refclk, s->sysclk); + + if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash", + sc->flash_size, errp)) { + return; + } + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), + "flash_boot_alias", &s->flash, 0, + sc->flash_size); + + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); + memory_region_add_subregion(system_memory, 0, &s->flash_alias); + + if (!memory_region_init_ram(&s->sram1, OBJECT(dev_soc), "SRAM1", SRAM1_SIZE, + errp)) { + return; + } + memory_region_add_subregion(system_memory, SRAM1_BASE_ADDRESS, &s->sram1); + + if (!memory_region_init_ram(&s->sram2, OBJECT(dev_soc), "SRAM2", SRAM2_SIZE, + errp)) { + return; + } + memory_region_add_subregion(system_memory, SRAM2_BASE_ADDRESS, &s->sram2); + + object_initialize_child(OBJECT(dev_soc), "armv7m", &s->armv7m, TYPE_ARMV7M); + armv7m = DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + qdev_connect_clock_in(armv7m, "refclk", s->refclk); + object_property_set_link(OBJECT(&s->armv7m), "memory", + OBJECT(system_memory), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { + return; + } + + /* APB1 BUS */ + create_unimplemented_device("TIM2", 0x40000000, 0x400); + create_unimplemented_device("TIM3", 0x40000400, 0x400); + create_unimplemented_device("TIM4", 0x40000800, 0x400); + create_unimplemented_device("TIM5", 0x40000C00, 0x400); + create_unimplemented_device("TIM6", 0x40001000, 0x400); + create_unimplemented_device("TIM7", 0x40001400, 0x400); + /* RESERVED: 0x40001800, 0x1000 */ + create_unimplemented_device("RTC", 0x40002800, 0x400); + create_unimplemented_device("WWDG", 0x40002C00, 0x400); + create_unimplemented_device("IWDG", 0x40003000, 0x400); + /* RESERVED: 0x40001800, 0x400 */ + create_unimplemented_device("SPI2", 0x40003800, 0x400); + create_unimplemented_device("SPI3", 0x40003C00, 0x400); + /* RESERVED: 0x40004000, 0x400 */ + create_unimplemented_device("USART2", 0x40004400, 0x400); + create_unimplemented_device("USART3", 0x40004800, 0x400); + create_unimplemented_device("UART4", 0x40004C00, 0x400); + create_unimplemented_device("UART5", 0x40005000, 0x400); + create_unimplemented_device("I2C1", 0x40005400, 0x400); + create_unimplemented_device("I2C2", 0x40005800, 0x400); + create_unimplemented_device("I2C3", 0x40005C00, 0x400); + /* RESERVED: 0x40006000, 0x400 */ + create_unimplemented_device("CAN1", 0x40006400, 0x400); + /* RESERVED: 0x40006800, 0x400 */ + create_unimplemented_device("PWR", 0x40007000, 0x400); + create_unimplemented_device("DAC1", 0x40007400, 0x400); + create_unimplemented_device("OPAMP", 0x40007800, 0x400); + create_unimplemented_device("LPTIM1", 0x40007C00, 0x400); + create_unimplemented_device("LPUART1", 0x40008000, 0x400); + /* RESERVED: 0x40008400, 0x400 */ + create_unimplemented_device("SWPMI1", 0x40008800, 0x400); + /* RESERVED: 0x40008C00, 0x800 */ + create_unimplemented_device("LPTIM2", 0x40009400, 0x400); + /* RESERVED: 0x40009800, 0x6800 */ + + /* APB2 BUS */ + create_unimplemented_device("SYSCFG", 0x40010000, 0x30); + create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0); + create_unimplemented_device("COMP", 0x40010200, 0x200); + create_unimplemented_device("EXTI", 0x40010400, 0x400); + /* RESERVED: 0x40010800, 0x1400 */ + create_unimplemented_device("FIREWALL", 0x40011C00, 0x400); + /* RESERVED: 0x40012000, 0x800 */ + create_unimplemented_device("SDMMC1", 0x40012800, 0x400); + create_unimplemented_device("TIM1", 0x40012C00, 0x400); + create_unimplemented_device("SPI1", 0x40013000, 0x400); + create_unimplemented_device("TIM8", 0x40013400, 0x400); + create_unimplemented_device("USART1", 0x40013800, 0x400); + /* RESERVED: 0x40013C00, 0x400 */ + create_unimplemented_device("TIM15", 0x40014000, 0x400); + create_unimplemented_device("TIM16", 0x40014400, 0x400); + create_unimplemented_device("TIM17", 0x40014800, 0x400); + /* RESERVED: 0x40014C00, 0x800 */ + create_unimplemented_device("SAI1", 0x40015400, 0x400); + create_unimplemented_device("SAI2", 0x40015800, 0x400); + /* RESERVED: 0x40015C00, 0x400 */ + create_unimplemented_device("DFSDM1", 0x40016000, 0x400); + /* RESERVED: 0x40016400, 0x9C00 */ + + /* AHB1 BUS */ + create_unimplemented_device("DMA1", 0x40020000, 0x400); + create_unimplemented_device("DMA2", 0x40020400, 0x400); + /* RESERVED: 0x40020800, 0x800 */ + create_unimplemented_device("RCC", 0x40021000, 0x400); + /* RESERVED: 0x40021400, 0xC00 */ + create_unimplemented_device("FLASH", 0x40022000, 0x400); + /* RESERVED: 0x40022400, 0xC00 */ + create_unimplemented_device("CRC", 0x40023000, 0x400); + /* RESERVED: 0x40023400, 0x400 */ + create_unimplemented_device("TSC", 0x40024000, 0x400); + + /* RESERVED: 0x40024400, 0x7FDBC00 */ + + /* AHB2 BUS */ + create_unimplemented_device("GPIOA", 0x48000000, 0x400); + create_unimplemented_device("GPIOB", 0x48000400, 0x400); + create_unimplemented_device("GPIOC", 0x48000800, 0x400); + create_unimplemented_device("GPIOD", 0x48000C00, 0x400); + create_unimplemented_device("GPIOE", 0x48001000, 0x400); + create_unimplemented_device("GPIOF", 0x48001400, 0x400); + create_unimplemented_device("GPIOG", 0x48001800, 0x400); + create_unimplemented_device("GPIOH", 0x48001C00, 0x400); + /* RESERVED: 0x48002000, 0x7FDBC00 */ + create_unimplemented_device("OTG_FS", 0x50000000, 0x40000); + create_unimplemented_device("ADC", 0x50040000, 0x400); + /* RESERVED: 0x50040400, 0x20400 */ + create_unimplemented_device("RNG", 0x50060800, 0x400); + + /* AHB3 BUS */ + create_unimplemented_device("FMC", 0xA0000000, 0x1000); + create_unimplemented_device("QUADSPI", 0xA0001000, 0x400); +} + +static void stm32l4x5_soc_class_init(ObjectClass *klass, void *data) +{ + + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = stm32l4x5_soc_realize; + /* Reason: Mapped at fixed location on the system bus */ + dc->user_creatable = false; + /* No vmstate or reset required: device has no internal state */ +} + +static void stm32l4x5xc_soc_class_init(ObjectClass *oc, void *data) +{ + Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); + + ssc->flash_size = 256 * KiB; +} + +static void stm32l4x5xe_soc_class_init(ObjectClass *oc, void *data) +{ + Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); + + ssc->flash_size = 512 * KiB; +} + +static void stm32l4x5xg_soc_class_init(ObjectClass *oc, void *data) +{ + Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); + + ssc->flash_size = 1 * MiB; +} + +static const TypeInfo stm32l4x5_soc_types[] = { + { + .name = TYPE_STM32L4X5XC_SOC, + .parent = TYPE_STM32L4X5_SOC, + .class_init = stm32l4x5xc_soc_class_init, + }, { + .name = TYPE_STM32L4X5XE_SOC, + .parent = TYPE_STM32L4X5_SOC, + .class_init = stm32l4x5xe_soc_class_init, + }, { + .name = TYPE_STM32L4X5XG_SOC, + .parent = TYPE_STM32L4X5_SOC, + .class_init = stm32l4x5xg_soc_class_init, + }, { + .name = TYPE_STM32L4X5_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Stm32l4x5SocState), + .instance_init = stm32l4x5_soc_initfn, + .class_size = sizeof(Stm32l4x5SocClass), + .class_init = stm32l4x5_soc_class_init, + .abstract = true, + } +}; + +DEFINE_TYPES(stm32l4x5_soc_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index b853577e725..5f9780bbceb 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -449,6 +449,11 @@ config STM32F405_SOC select STM32F4XX_SYSCFG select STM32F4XX_EXTI +config STM32L4X5_SOC + bool + select ARM_V7M + select OR_IRQ + config XLNX_ZYNQMP_ARM bool default y if PIXMAN diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 68245d3ad10..9766da10c48 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -42,6 +42,7 @@ arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) +arm_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_soc.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) From patchwork Thu Jan 11 11:04:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44FFCC4707B for ; Thu, 11 Jan 2024 11:05:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssB-0001Ni-So; Thu, 11 Jan 2024 06:05:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss5-0001KO-NT for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss2-0004NI-EF for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-33761e291c1so3050938f8f.0 for ; Thu, 11 Jan 2024 03:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971108; x=1705575908; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4J8JnVbLxHPqG7/7Gj6ee0tGyPz56E2QBmSZoyA8w7A=; b=p3vFm7U4TsGRskbjoq5rwGgL7GgucIajNgBGdepY0PcGT/QXfpbHWDeu5sDK+0kYh5 emJ9F6zK8oSlulZCbAJ5YYGMdigi9tWL0slFYMMsn3pPLYiGrOxUnmudaAkAZ1HYvKeQ 4Tin7lMm/p1xZShUjx+a2Gene56ZHWqhk9qw3FdDGSzA2VhfuWGT/t6NyOaVuv+enENe y1iSpv60Pf4g6Vt3oXMD25YxKTeMBdBg6qF8jONkZtixwAqufYFAoIH648i2n8U33QIW Vp39YNL6KGQ6ixAI1tBFiH+lv1ehpca6/ldKJTl8bGosYOCclaObeKbu8kJaNtSQ3PSL bTRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971108; x=1705575908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4J8JnVbLxHPqG7/7Gj6ee0tGyPz56E2QBmSZoyA8w7A=; b=bYdGzCvxFPuLlqmayjQ9JsyfDediB/+8OlVlB30HOG+IqtHJ3MQG1+Xx0em6Cqp2dU tQncNqICxKGkxHCvS4KbXpkqh6qI9ZkpgjwpBeV6mVRsBzKl2nVQ9XllvunA59NZF/U2 gO6Vz9oQRVrV2JxQpI97GY2y467s/U+H00JqGohl/C9ogRpUg0PNN5c6QwrhFwCa67ha jWxzYoI8TaMz5E54BsoK2wM9WgdiyOnam7OpBjc+uCnJCVPs8uoP0nk5mGTPu0EFHXE1 bL2SZVyUqcvDjSdJlRbQd1hko/15Fu1a9T0F7BqPH0l2ju3pUgehNFujHQk0r7jVhMJZ nzfA== X-Gm-Message-State: AOJu0YwyOXlfKwkX64AkDqoY1pGQNdTyPxDHokbB0DUPAeAxD+2AfL44 YONNnJ/NfWc/mocLXFAPtg10MVPIhq/PIwUl+V7N7Ma7n1I= X-Google-Smtp-Source: AGHT+IGLxKTpQPiCgEE4tOofQorMkOglYLKFFwc4hUVwwWWWvEr2AGKKcpjqirsnDqm6amZ5fsSTlA== X-Received: by 2002:a5d:64e6:0:b0:337:507a:5c59 with SMTP id g6-20020a5d64e6000000b00337507a5c59mr473309wri.12.1704971108576; Thu, 11 Jan 2024 03:05:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/41] hw/arm: Add minimal support for the B-L475E-IOT01A board Date: Thu, 11 Jan 2024 11:04:27 +0000 Message-Id: <20240111110505.1563291-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Inès Varhol This commit adds a new B-L475E-IOT01A board using the STM32L475VG SoC as well as a dedicated documentation file. The implementation is derived from the Netduino Plus 2 machine. There are no peripherals implemented yet, only memory regions. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Message-id: 20240108135849.351719-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- MAINTAINERS | 7 +++ docs/system/arm/b-l475e-iot01a.rst | 46 ++++++++++++++++ docs/system/arm/stm32.rst | 6 ++- docs/system/target-arm.rst | 1 + configs/devices/arm-softmmu/default.mak | 1 + hw/arm/b-l475e-iot01a.c | 72 +++++++++++++++++++++++++ hw/arm/Kconfig | 6 +++ hw/arm/meson.build | 1 + 8 files changed, 138 insertions(+), 2 deletions(-) create mode 100644 docs/system/arm/b-l475e-iot01a.rst create mode 100644 hw/arm/b-l475e-iot01a.c diff --git a/MAINTAINERS b/MAINTAINERS index da29dcc16ec..b406fb20c05 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1130,6 +1130,13 @@ S: Maintained F: hw/arm/stm32l4x5_soc.c F: include/hw/arm/stm32l4x5_soc.h +B-L475E-IOT01A IoT Node +M: Arnaud Minier +M: Inès Varhol +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/b-l475e-iot01a.c + SmartFusion2 M: Subbaraya Sundeep M: Peter Maydell diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst new file mode 100644 index 00000000000..2b128e6b847 --- /dev/null +++ b/docs/system/arm/b-l475e-iot01a.rst @@ -0,0 +1,46 @@ +B-L475E-IOT01A IoT Node (``b-l475e-iot01a``) +============================================ + +The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on +ARM Cortex-M4F core. It is part of STMicroelectronics +:doc:`STM32 boards ` and more specifically the STM32L4 +ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and +integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A board +namely features 64 Mibit QSPI Flash, BT, WiFi and RF connectivity, +USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors. + +Supported devices +""""""""""""""""" + +Currently, B-L475E-IOT01A machine's implementation is minimal, +it only supports the following device: + +- Cortex-M4F based STM32L4x5 SoC + +Missing devices +""""""""""""""" + +The B-L475E-IOT01A does *not* support the following devices: + +- Extended interrupts and events controller (EXTI) +- Reset and clock control (RCC) +- Serial ports (UART) +- System configuration controller (SYSCFG) +- General-purpose I/Os (GPIO) +- Analog to Digital Converter (ADC) +- SPI controller +- Timer controller (TIMER) + +See the complete list of unimplemented peripheral devices +in the STM32L4x5 module : ``./hw/arm/stm32l4x5_soc.c`` + +Boot options +"""""""""""" + +The B-L475E-IOT01A machine can be started using the ``-kernel`` +option to load a firmware. Example: + +.. code-block:: bash + + $ qemu-system-arm -M b-l475e-iot01a -kernel firmware.bin + diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst index d7265b763d4..3b640f3ee07 100644 --- a/docs/system/arm/stm32.rst +++ b/docs/system/arm/stm32.rst @@ -16,11 +16,13 @@ based on this chip : - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller -The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin -compatible with STM32F2 series. The following machines are based on this chip : +The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4 +ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series. +The following machines are based on this ARM Cortex-M4F chip : - ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller - ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microcontroller +- ``b-l475e-iot01a`` :doc:`B-L475E-IOT01A IoT Node ` board with STM32L475VG microcontroller There are many other STM32 series that are currently not supported by QEMU. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 790ac1b8a2b..c9d7c0dda7e 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -84,6 +84,7 @@ undocumented; you can get a complete list by running arm/vexpress arm/aspeed arm/bananapi_m2u.rst + arm/b-l475e-iot01a.rst arm/sabrelite arm/digic arm/cubieboard diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak index 980c48a7d99..023faa2f750 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -19,6 +19,7 @@ CONFIG_ARM_VIRT=y # CONFIG_NSERIES=n # CONFIG_STELLARIS=n # CONFIG_STM32VLDISCOVERY=n +# CONFIG_B_L475E_IOT01A=n # CONFIG_REALVIEW=n # CONFIG_VERSATILE=n # CONFIG_VEXPRESS=n diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c new file mode 100644 index 00000000000..6ecde2db15c --- /dev/null +++ b/hw/arm/b-l475e-iot01a.c @@ -0,0 +1,72 @@ +/* + * B-L475E-IOT01A Discovery Kit machine + * (B-L475E-IOT01A IoT Node) + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * This work is heavily inspired by the netduinoplus2 by Alistair Francis. + * Original code is licensed under the MIT License: + * + * Copyright (c) 2014 Alistair Francis + */ + +/* + * The reference used is the STMicroElectronics UM2153 User manual + * Discovery kit for IoT node, multi-channel communication with STM32L4. + * https://www.st.com/en/evaluation-tools/b-l475e-iot01a.html#documentation + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32l4x5_soc.h" +#include "hw/arm/boot.h" + +/* Main SYSCLK frequency in Hz (80MHz) */ +#define MAIN_SYSCLK_FREQ_HZ 80000000ULL + +static void b_l475e_iot01a_init(MachineState *machine) +{ + const Stm32l4x5SocClass *sc; + DeviceState *dev; + Clock *sysclk; + + /* This clock doesn't need migration because it is fixed-frequency */ + sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, MAIN_SYSCLK_FREQ_HZ); + + dev = qdev_new(TYPE_STM32L4X5XG_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); + qdev_connect_clock_in(dev, "sysclk", sysclk); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + sc = STM32L4X5_SOC_GET_CLASS(dev); + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + 0, sc->flash_size); +} + +static void b_l475e_iot01a_machine_init(MachineClass *mc) +{ + static const char *machine_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)"; + mc->init = b_l475e_iot01a_init; + mc->valid_cpu_types = machine_valid_cpu_types; + + /* SRAM pre-allocated as part of the SoC instantiation */ + mc->default_ram_size = 0; +} + +DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 5f9780bbceb..39d255425b1 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -449,6 +449,12 @@ config STM32F405_SOC select STM32F4XX_SYSCFG select STM32F4XX_EXTI +config B_L475E_IOT01A + bool + default y + depends on TCG && ARM + select STM32L4X5_SOC + config STM32L4X5_SOC bool select ARM_V7M diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 9766da10c48..bb92b27db3e 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -42,6 +42,7 @@ arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) +arm_ss.add(when: 'CONFIG_B_L475E_IOT01A', if_true: files('b-l475e-iot01a.c')) arm_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_soc.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) From patchwork Thu Jan 11 11:04:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46FBCC47077 for ; Thu, 11 Jan 2024 11:05:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNss9-0001MA-O9; Thu, 11 Jan 2024 06:05:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss5-0001KC-CN for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss2-0004NP-Qs for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40e60e13762so3186585e9.2 for ; Thu, 11 Jan 2024 03:05:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971109; x=1705575909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CaJ0lo5TmAF8BFZ0QGqs81rse4aATjl1O9jO7ww+ztg=; b=cRCaNUQntyq4UDLQnlhaDdISitRxAwTafcAcikJzadIrgofqFIt+YcuTo6tOUJf/la JqCCuUbuLMeKisjZzxi0dwo/1EMCwImV50yqvh1bnXrqfjCsjECb8ziECiwxMqlLXdfr aiLQvNWIv7ucyLAK1hRg8/B2COMcWJoVUvt4d3UPL0vO/304tKnWkd47rT1TbK59pAdS 488Y+06F+aag8Juz0bQ/QEKig/OEbyZr1AmTiOcL6lcnSTgPiRPLXBfs1O10jgZY7qRr VFtMSyiMd2PUnCyPHlz/M/iX5sL9tdn5IPg/3UuWn6Hd/FyNBokYNqP0+wv1Col7/78Q slow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971109; x=1705575909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CaJ0lo5TmAF8BFZ0QGqs81rse4aATjl1O9jO7ww+ztg=; b=Y5bUMBjo9STw9GEnWsclR1uVimjv7qsmSDJenOX3ldXRzaKf5qp3hbERidhzft7fW6 nJlHlvODG1+z37irsbUFgHkconHyU6xf52KbuV978dN5dX6CjZ9nxT4bcbYL7Y3cTdRX eOPaziVb9Qu+0c+UL0Qx1Eiv7lnYxiSkhpeetdyz5lmyoB43iyWhkQ3j/VJZZbFsBc1S zZqRZ3pAxOvi02Lr8fZz8ZTCkl7TDq43UbDIUsFkKSFhaUzYDb/+AVCBiBYp6N8URI4Z lRxwdUDM3ElGB3iuAEi93BBuieiFceKd5LH14pcBJ+jJN0tQZq1vlsGb1RB2BEVU8M3r 8YjA== X-Gm-Message-State: AOJu0YxrUK7aOmvvVgr7EulpTXfhnBUCF5agFAQEahTnIYqZT97KW2sz UAJMPiWqYRoHg6mAf58Mpcy39uzx3J70/dmGDHLc4tF6p2g= X-Google-Smtp-Source: AGHT+IEWBrVmbE+GqWUDdgIY8khKd3OdTWIQd9GvBvjowGWGokz6WBY0Ig8BzCrXvCl/HIKn+RlSew== X-Received: by 2002:a05:600c:2158:b0:40e:526f:a110 with SMTP id v24-20020a05600c215800b0040e526fa110mr142562wml.107.1704971108972; Thu, 11 Jan 2024 03:05:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/41] hw/intc/armv7m_nvic: add "num-prio-bits" property Date: Thu, 11 Jan 2024 11:04:28 +0000 Message-Id: <20240111110505.1563291-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Samuel Tardieu Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up must use 3 or more bits. This adds a "num-prio-bits" property which will get sensible default values if unset (2 or 8 depending on the device). Unless a SOC specifies the number of bits to use, the previous behavior is maintained for backward compatibility. Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell Message-id: 20240106181503.1746200-2-sam@rfc1149.net Suggested-by: Anton Kochkov Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 50f9a973a2e..404a445138a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2572,6 +2572,11 @@ static const VMStateDescription vmstate_nvic = { static Property props_nvic[] = { /* Number of external IRQ lines (so excluding the 16 internal exceptions) */ DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), + /* + * Number of the maximum priority bits that can be used. 0 means + * to use a reasonable default. + */ + DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 0), DEFINE_PROP_END_OF_LIST() }; @@ -2685,7 +2690,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) /* include space for internal exception vectors */ s->num_irq += NVIC_FIRST_IRQ; - s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; + if (s->num_prio_bits == 0) { + /* + * If left unspecified, use 2 bits by default on Cortex-M0/M0+/M1 + * and 8 bits otherwise. + */ + s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; + } else { + uint8_t min_prio_bits = + arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 3 : 2; + if (s->num_prio_bits < min_prio_bits || s->num_prio_bits > 8) { + error_setg(errp, + "num-prio-bits %d is outside " + "NVIC acceptable range [%d-8]", + s->num_prio_bits, min_prio_bits); + return; + } + } /* * This device provides a single memory region which covers the From patchwork Thu Jan 11 11:04:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63145C4707B for ; Thu, 11 Jan 2024 11:14:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssR-0001RC-An; Thu, 11 Jan 2024 06:05:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss6-0001Kr-Tm for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:15 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss3-0004NS-Ci for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:14 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-33770772136so2385590f8f.3 for ; Thu, 11 Jan 2024 03:05:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971109; x=1705575909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=g2GtSaJUPBG1REo0r/4JXTUdrbWAUpzKuEobonnT25Y=; b=qYaM8sqNLWi8H2MFqYYUhDiScUhuE//McLJoxPbjJNCqJphldMUfJZ1CY2ZB4I0FVC c5CR2X+XOxTytwRS3srGOvxKsUsvVfxJFzPXmlskipLW2gstKo57dzX5TfgstLtmvHor O9IkaLzfNSG40shtM94Z0VszUDLoi64G89h+JTz5De4OxZiWJhhnmp19wLpPm6s4gXP/ QIa0doB/1M6keWxC1nwo2gB/5KCfk6CslQZZOpCYDHWv5iY0w4ld6jPVohvTZWiiM7/Q Pkq8at9AlAw4CiyiEWn/sSJPKFOpSPNOYtyTLVEyVi4psgMKxqAES2StkPkgbTWWsqBS WKfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971109; x=1705575909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g2GtSaJUPBG1REo0r/4JXTUdrbWAUpzKuEobonnT25Y=; b=AP82yo8t77/NDu34QF7jUEHTy3s0y+cOVugPmdH4ZoEHvjYGMGUEWE8Z80GVCO5ITD tIN5DuB6KzB83Z10afP156wBMyRlKltbyFLWIP9cwG/2UPuzd2vLMKvpV764X4KQ5ypG 60FbWoFduHcrCt5bQyHW4YYfUxifzmlFrOIVQlqQ5lIE95+YiAb66sIKZbJatk8NTXOu jRWSTGX8P22YZw7lBkG8UdY/7Hxng4F9Nn4PlllvGf0NjLLnxoGyYRBDBxKWqR5rXL83 1EMAHkAI6EYo3KY4Rh02qekd8+9OF4ABuhkG2taoB+OGnVzksU154/7PEoKNBRD5mLfC DYcw== X-Gm-Message-State: AOJu0Yx6WAM7oNpeYy8AbyQKRbWVHq+sK44v7OrchrYn2PFwjufvv6qq ztnUxas6DQJYnS9xXovXmHXctzlbBFPBvl66I5tRAWrqUx4= X-Google-Smtp-Source: AGHT+IGMaCLXrbm5ykW3ggtsPTpGy4r/th2CNp5naCekEa95oE86U/Pif2f1TV4VYMBy+FMWYQqQCQ== X-Received: by 2002:a5d:62c8:0:b0:336:62f7:2304 with SMTP id o8-20020a5d62c8000000b0033662f72304mr503943wrv.49.1704971109374; Thu, 11 Jan 2024 03:05:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/41] hw/arm/armv7m: alias the NVIC "num-prio-bits" property Date: Thu, 11 Jan 2024 11:04:29 +0000 Message-Id: <20240111110505.1563291-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Samuel Tardieu A SoC will not have a direct access to the NVIC embedded in its ARM core. By aliasing the "num-prio-bits" property similarly to what is done for the "num-irq" one, a SoC can easily configure it on its armv7m instance. Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240106181503.1746200-3-sam@rfc1149.net Signed-off-by: Peter Maydell --- include/hw/arm/armv7m.h | 1 + hw/arm/armv7m.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index e2cebbd15c0..5c057ab2ec9 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -43,6 +43,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET). * + Property "cpu-type": CPU type to instantiate * + Property "num-irq": number of external IRQ lines + * + Property "num-prio-bits": number of priority bits in the NVIC * + Property "memory": MemoryRegion defining the physical address space * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal * devices will be automatically layered on top of this view.) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index e39b61bc1af..1f218277734 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -256,6 +256,8 @@ static void armv7m_instance_init(Object *obj) object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC); object_property_add_alias(obj, "num-irq", OBJECT(&s->nvic), "num-irq"); + object_property_add_alias(obj, "num-prio-bits", + OBJECT(&s->nvic), "num-prio-bits"); object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS], TYPE_SYSTICK); From patchwork Thu Jan 11 11:04:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 407F0C4707B for ; Thu, 11 Jan 2024 11:07:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssT-0001Rg-K4; Thu, 11 Jan 2024 06:05:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss5-0001KF-GL for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss3-0004NU-BN for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-33674f60184so4942742f8f.1 for ; Thu, 11 Jan 2024 03:05:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971109; x=1705575909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xdmkDsShtK90/D77OytZy2H9fVO4LlCAzfF++RrV4Lw=; b=wwPMqyIyy5DtPCMcuazwHP/tCqc0wmR3f34LtZKCB/hcfreFRN6gP5I2jVvRaqUeT7 Vs2B5YehvGFkhKY6hbr+13eGxoK9Q63+9tKnt5rRhIPzGuIt8+ChaUhnfX0w/iIURj+r WtwGGWc++eGIJybG8FrATC/mlMREbYo7OLaPQ9dKGjmkeMMoifu+GPAeYLnV34+mGyI9 FEbJjiVcO+Vtpf6xiJKQIsihfRwhEPA4WZ91wn9EbCss8+KkdTbrnW04MYRanHwC+wmS ROM4PwTRxmEoBmcv/agGl8iXfNKGx1vwB/JjnD72/oHkm8APBBX9qscuyz5WX7GaLDQp B2TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971109; x=1705575909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xdmkDsShtK90/D77OytZy2H9fVO4LlCAzfF++RrV4Lw=; b=aYTc9hcjTSCtXOEG8JACokgVZv/I6RyDRT9fJGyvDHjE9Iw/jButQphCRCkY4PVMeS 6Sz4zVnyQ8vdscvqk72jTkofyRIUPVcx9CZLqsJ03KqkI3vH77Tb2ko1dKcgU/cPu3dD zeC17rS7PQFCR5iHOoOhhFYwixdtDsgRlzvyLmTO/6edG+Vcxe6oaJHs7FisIjSamzER EiTY7Q4exDZjLnyR248TUmmeyiI1ST22kXUqfnud9CKhzqs3L5RLUL9QqWGCCCqro6fR plIC4QIo5DupbaZ6Grvof06IinomTwzuTNpLphjpOdPWp0u1hXcDPq2KmeJUyJyvY5lR wdaA== X-Gm-Message-State: AOJu0Yz9+WPZ6Q2PZjnwMsmgKX9t4z6r+M71I8m/jcNTfBGgiOaKAcJM R8yyNGx5Zrvlb0aJFVAMPoo/a6HVcE2J686A8ImMrX/fobI= X-Google-Smtp-Source: AGHT+IFMZQ7WJj1FPZLsB13YobS1pNGynQBZJyXhH9dELj0hQKxGqNHzkSuV1TwPO6gMWNEtenQ3uA== X-Received: by 2002:a5d:4d82:0:b0:337:2ff5:f523 with SMTP id b2-20020a5d4d82000000b003372ff5f523mr362559wru.0.1704971109782; Thu, 11 Jan 2024 03:05:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/41] hw/arm/socs: configure priority bits for existing SOCs Date: Thu, 11 Jan 2024 11:04:30 +0000 Message-Id: <20240111110505.1563291-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Samuel Tardieu Update the number of priority bits for a number of existing SoCs according to their technical documentation: - STM32F100/F205/F405/L4x5: 4 bits - Stellaris (Sandstorm/Fury): 3 bits Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell Message-id: 20240106181503.1746200-4-sam@rfc1149.net Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 2 ++ hw/arm/stm32f100_soc.c | 1 + hw/arm/stm32f205_soc.c | 1 + hw/arm/stm32f405_soc.c | 1 + hw/arm/stm32l4x5_soc.c | 1 + 5 files changed, 6 insertions(+) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 729a8bf5695..d18b1144af5 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -47,6 +47,7 @@ #define BP_GAMEPAD 0x04 #define NUM_IRQ_LINES 64 +#define NUM_PRIO_BITS 3 typedef const struct { const char *name; @@ -1067,6 +1068,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) nvic = qdev_new(TYPE_ARMV7M); qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); + qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); qdev_prop_set_bit(nvic, "enable-bitband", true); qdev_connect_clock_in(nvic, "cpuclk", diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index b90d440d7aa..808b783515d 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -115,6 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) /* Init ARMv7m */ armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 61); + qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 1a548646f6e..a451e21f59c 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -127,6 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index a65bbe298d2..2ad5b79a069 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -149,6 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 70609a6dac4..159d5315c99 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -102,6 +102,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) object_initialize_child(OBJECT(dev_soc), "armv7m", &s->armv7m, TYPE_ARMV7M); armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_uint32(armv7m, "num-prio-bits", 4); qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); From patchwork Thu Jan 11 11:04:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31208C47077 for ; Thu, 11 Jan 2024 11:07:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssB-0001Ma-Di; Thu, 11 Jan 2024 06:05:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss6-0001Kq-TR for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:15 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss4-0004Nk-2C for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:14 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3375a236525so4180580f8f.0 for ; Thu, 11 Jan 2024 03:05:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971110; x=1705575910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0GNFtYvCPWXBGX6d6WliU7kR2DeEivpmW78851S/hGQ=; b=LgwdZO7UKoofP5hQV533+Ut4VZGR9YwI25eryAgcyGtIzYFZlZk4D1Zzs14jIAUOjD 7ZgexFrzliwlgnr1Xr69r4rT6G1WbPNqBToIG2r1D6RcSZ/Fu2apUiYrtvrbdu47Lwpg HFLBLy5cK17nfeToSt4DYJDB8NI/hjPMgZrtFXxInpMJChJH1mVxijymeCCecnufvvQX dseH/RX9WLQlBK7Ro2g62xVF2G6FPQuQUvHli59GI0IGNDM9lmKrzXVmtUf+bGkd9Gxa F3/YEtmz6v28LuUPbvQ3IqkjyLxt9MIMDDMToFe0Kq3xmiocKrANtMSopKBMuGhrQlLZ byCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971110; x=1705575910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0GNFtYvCPWXBGX6d6WliU7kR2DeEivpmW78851S/hGQ=; b=opKO16yDHEc8kts8hLmSiA1A1bl0eVWYKEPTiXsUSsKCh1I5TukWlkNV64Vqp2H7WJ 84mqOoMbFi8/oQW9a4oQ+d9m+wi9w8E2SgXejY7NdoxwWb5WWRRMyPJqs+Sm9NLYzlbj HC6FT0J332FK2GCN8NBtuNmBH3zQrPYeK0Dkwg0+/aekQ18Fz5zsRZ2wBGjZMzIiwlQV z9qs0EwW2wv/ezRngbG3fGl4OaHxD+UVsmVIy6ovV0zmVcJxvklmNi7wZMQTgz4AzABZ 98LL6Jq/pVVPaZQMPGp2od2ywO7EHnntB5kdW3XQCJX8WUag8pPAJjN7weMz8u7xqT75 3uIQ== X-Gm-Message-State: AOJu0YwaiOaWPTAkV4stzJ3V5cv2zZtUa8MOeJsDZ4qprmGbrJhXmr0H TPEHUdgC2cAIFejzO8IWKfa/ARIWYRfUPG9UGg+dVHGcBXk= X-Google-Smtp-Source: AGHT+IHesHXzBIncFz28Ysb9BB5AwK7rMTkqunGD04l1O7X1Y7BgjLf9Ftb3jP/XpvEB/3tIXd2Vng== X-Received: by 2002:a5d:6a46:0:b0:337:476f:9966 with SMTP id t6-20020a5d6a46000000b00337476f9966mr502493wrw.104.1704971110158; Thu, 11 Jan 2024 03:05:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/41] hw/arm: Add missing QOM parent for v7-M SoCs Date: Thu, 11 Jan 2024 11:04:31 +0000 Message-Id: <20240111110505.1563291-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20240104141159.53883-1-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/msf2-som.c | 1 + hw/arm/netduino2.c | 1 + hw/arm/netduinoplus2.c | 1 + hw/arm/olimex-stm32-h405.c | 1 + hw/arm/stm32vldiscovery.c | 1 + 5 files changed, 5 insertions(+) diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index eb74b23797c..a269cf044b9 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -60,6 +60,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); dev = qdev_new(TYPE_MSF2_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); qdev_prop_set_string(dev, "part-name", "M2S010"); qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type); diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 501f63a77f9..8b1a9a24379 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -44,6 +44,7 @@ static void netduino2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F205_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 2e589849478..bccd1003549 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -44,6 +44,7 @@ static void netduinoplus2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index d793de7c97f..4ad7b043be0 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -47,6 +47,7 @@ static void olimex_stm32_h405_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 190db6118b9..cc419351605 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -47,6 +47,7 @@ static void stm32vldiscovery_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F100_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); From patchwork Thu Jan 11 11:04:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517200 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4958FC4707B for ; Thu, 11 Jan 2024 11:12:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssj-0001fx-3I; Thu, 11 Jan 2024 06:05:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss6-0001Ku-V1 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:15 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss4-0004P0-IE for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:14 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3376555b756so3010278f8f.0 for ; Thu, 11 Jan 2024 03:05:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971110; x=1705575910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yscuAN2+W6F+E5GdpmQyLDg77dRJm7PXwcNzo7tUEdc=; b=PGa+d2ENAu+hfpA/yLS4+K6lpMvx491mlQ0r22T64WeQdY8apOzbrGKDg3nImZpWru h24mbNXspVkRflkTLRala0NUGV0N49CDhT/KBUw67tbxolu2iQVRjwU2IHkhOgfawUgy iFDH0CPAqY732B5Azvom9/0+DECcvHBI82aSZYbpx8IUkc8Xv2y6HlAg4ysO8Mz24+M2 wnERQAZVo3nf5qNKKfY2tpa0j9oMNmBSqBwzapjou/G0Ik2xv44XmfW/Xbdm3aCcLlBz BbglE7/Qmln5KnnHkbs3jn4E5V171R9AVYvZCIWXpNdzgLl3bXT4M4PRNlBR9JAr3iXb ruRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971110; x=1705575910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yscuAN2+W6F+E5GdpmQyLDg77dRJm7PXwcNzo7tUEdc=; b=JSm7lbed8mnwABULrgcbLI2VsEwonrnQqhTi8gLzgQhzqfEjcI31iYYuP03PzYOQqj dDq15UP0KCQhKbHtwBvMiDUUixXI4kN4PkZ705Uvjic4Uk1MPgV+RKzwhXpxDAjXOjIO Dz2Fl8GiSFB4uqd+3U3hCiDjfoT/+sI5VO2KK93D2bGK/gZ8UgcjkwP+vfnMMvQvoWwb EDWX4Rr+nmHSN6tE5ibApMfYjbA9peuUOSGf1XZXr3MAoNtW9LTmu/jEZ1Rsdrz7E2bH LNvxKCRoKpIYGOMynqP6tQNl3N7qpnBjk4u1p+hgVXnyjSsILiV5LEJCxveItnAKWPUy dKhg== X-Gm-Message-State: AOJu0YwMGigxt94wHBPkCXLVz26yT5fqmnDWcixl1ew6kJfrMb76atDU ThXzntlsTIhB2acba1W4TB/z9cBVstAb8pF97ccLKvxF5mU= X-Google-Smtp-Source: AGHT+IEzeVr7AsJQFCTYxbAjWqPQybHomtJI7ETWz/juZox6lFz3CGmo3jIptZo/x+RG7X2DJoVqpQ== X-Received: by 2002:adf:a183:0:b0:336:7608:d0f4 with SMTP id u3-20020adfa183000000b003367608d0f4mr421626wru.17.1704971110593; Thu, 11 Jan 2024 03:05:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/41] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU Date: Thu, 11 Jan 2024 11:04:32 +0000 Message-Id: <20240111110505.1563291-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The CTR_EL0 register has some bits which allow the implementation to tell the guest that it does not need to do cache maintenance for data-to-instruction coherence and instruction-to-data coherence. QEMU doesn't emulate caches and so our cache maintenance insns are all NOPs. We already have some models of specific CPUs where we set these bits (e.g. the Neoverse V1), but the 'max' CPU still uses the settings it inherits from Cortex-A57. Set the bits for 'max' as well, so the guest doesn't need to do unnecessary work. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/tcg/cpu64.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index fcda99e1583..40e7a45166f 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1105,6 +1105,16 @@ void aarch64_max_tcg_initfn(Object *obj) u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); cpu->clidr = u; + /* + * Set CTR_EL0.DIC and IDC to tell the guest it doesnt' need to + * do any cache maintenance for data-to-instruction or + * instruction-to-guest coherence. (Our cache ops are nops.) + */ + t = cpu->ctr; + t = FIELD_DP64(t, CTR_EL0, IDC, 1); + t = FIELD_DP64(t, CTR_EL0, DIC, 1); + cpu->ctr = t; + t = cpu->isar.id_aa64isar0; t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ From patchwork Thu Jan 11 11:04:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DD48C47077 for ; Thu, 11 Jan 2024 11:10:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssh-0001c8-2Z; Thu, 11 Jan 2024 06:05:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss6-0001Kt-UW for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:15 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss5-0004PC-2H for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:14 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3366e78d872so5439888f8f.3 for ; Thu, 11 Jan 2024 03:05:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971111; x=1705575911; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oeCuiQBz7GI2Tnh0N3wKJtjrrHPQdjyFY69+nM/wilI=; b=xYUDu7ttRpqKdcq3zGrKmP3Uno/mykpbIc3M67Bwig0pquz6wgR/w9VX/XE5s9XGBQ 3YaDoM2Yvuz0U3hygb5g7NVQIkD0FUB9mc5NFesVvwaObrn++mEJCrx/EJCo+6O55GHb VjZAt+JSZuihNHw+EfI8kztMpOhJgDX4dBQysBkVPTkGDFohbmzDmsbZnNy/TDMvBm8b is28vHsuJRVtu75nREjl5gQugHaUKOzwqiiGp2Ve6O5+4qv9jz2DWTHLpzF4q+uJHFux 1+iYHaRz5C9NAU8n3COXcYDQ5iKuKDwWjzrXbJUwGl00y+AuvTBIO9cYbyjU7gFGmLcO l2mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971111; x=1705575911; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oeCuiQBz7GI2Tnh0N3wKJtjrrHPQdjyFY69+nM/wilI=; b=Adx8WIh7MF+6hvGPPQqTDKp+4S7GbDSX8tn4+FD7sDLwJ63bpWklxPz+gQbQnIs1E7 G4widuNj/gjc2Q2KOrBNdnN69QhUX0rXls5aDI81KYw6Nv3lHYwM5nVbfZPAjJU0brW+ eEIHTcExfeaZP5J3RrRvfG3GzPfcfOaSnPEF2CaDTytuKKbkmBx+/9z0iv7zkWC1vdwI obDgwlnnqXen7u/fMlzv7KoZjiOgC+B3b7sS41A6/e1m7YwWJFrY2DtRV6vPuHtOf32Z m+TgdwatdY8CpcnVtrt/bHO32DfUbMAZxcG1PlXnW8vQDd3hVH6yUoUxPhU/94OMOqfW qPLA== X-Gm-Message-State: AOJu0YzOW+HYPVHwgGVpOJnWMSDAQzdDNBvXY7bJknaH+J2Z2yadY1G6 qggM+KKBgiDVeb9WtWXBSXyyO8eg0FzEsTZbbfuMpsJxiD4= X-Google-Smtp-Source: AGHT+IHl/SsxfsJrGNLgH/rRuGDPWhDEul4vFYdpFGsHCAr/cyB3MZmyFulbnukQwn5M8/bMjzVX/g== X-Received: by 2002:adf:e3c7:0:b0:337:427f:e993 with SMTP id k7-20020adfe3c7000000b00337427fe993mr309982wrm.85.1704971111005; Thu, 11 Jan 2024 03:05:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/41] hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers Date: Thu, 11 Jan 2024 11:04:33 +0000 Message-Id: <20240111110505.1563291-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The hypervisor can deliver (virtual) LPIs to a guest by setting up a list register to have an intid which is an LPI. The GIC has to treat these a little differently to standard interrupt IDs, because LPIs have no Active state, and so the guest will only EOI them, it will not also deactivate them. So icv_eoir_write() must do two things: * if the LPI ID is not in any list register, we drop the priority but do not increment the EOI count * if the LPI ID is in a list register, we immediately deactivate it, regardless of the split-drop-and-deactivate control This can be seen in the VirtualWriteEOIR0() and VirtualWriteEOIR1() pseudocode in the GICv3 architecture specification. Without this fix, potentially a hypervisor guest might stall because LPIs get stuck in a bogus Active+Pending state. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- hw/intc/arm_gicv3_cpuif.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 77c2a6dd3b6..6ac90536402 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1434,16 +1434,25 @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, idx = icv_find_active(cs, irq); if (idx < 0) { - /* No valid list register corresponding to EOI ID */ - icv_increment_eoicount(cs); + /* + * No valid list register corresponding to EOI ID; if this is a vLPI + * not in the list regs then do nothing; otherwise increment EOI count + */ + if (irq < GICV3_LPI_INTID_START) { + icv_increment_eoicount(cs); + } } else { uint64_t lr = cs->ich_lr_el2[idx]; int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp); if (thisgrp == grp && lr_gprio == dropprio) { - if (!icv_eoi_split(env, cs)) { - /* Priority drop and deactivate not split: deactivate irq now */ + if (!icv_eoi_split(env, cs) || irq >= GICV3_LPI_INTID_START) { + /* + * Priority drop and deactivate not split: deactivate irq now. + * LPIs always get their active state cleared immediately + * because no separate deactivate is expected. + */ icv_deactivate_irq(cs, idx); } } From patchwork Thu Jan 11 11:04:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 884C6C4707B for ; Thu, 11 Jan 2024 11:08:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssU-0001Rj-Dy; Thu, 11 Jan 2024 06:05:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss7-0001LR-UN for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:16 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss5-0004PD-2c for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:14 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-336990fb8fbso4247960f8f.1 for ; Thu, 11 Jan 2024 03:05:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971111; x=1705575911; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=K1vEHP8jltuQvEGl4ENo7Bv8xIOD4gLXh77ifsMSwb4=; b=C/s/jOrROYR6YAXmXOVc/jezFwwA7UWADeJYwc/6ZwwVlE49nnLFh5+3B+uAZOZ7sO ZVyBs/8jw3QRebSxylxvoqwvimx0A8BzcfHdcpcQeIBunht8afbmc2UZUJKZuW6xWR/G zifAEs3JQmRt1NcqpERCguVcntcc0Zso1qbDSfUZzfiN36bOBKVJezQQxVXHIu8LpSZr vcdf9ojSRZ3GGQ8U7RVarLF1YhgSy3Z2YfaZc0JQ8hsBhZkJMi7MrPtawvVcvO1KRbuA tKazIxdH2cv76y2vuNwTioUPwkHkPYdvKZXsv0ncmcV4OXKp3P85glxDzobgd/pi75up Nx+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971111; x=1705575911; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K1vEHP8jltuQvEGl4ENo7Bv8xIOD4gLXh77ifsMSwb4=; b=L0DqsBC71sQAJtp8KqPeOFRg1FT0WN4HYjnW60/Nc2LM8B3n+s98q1QIgOBFQfNfhh qjn9Wa5JJUspOkaMTgP3A79nECH5F6zHIbym9FjftoersmCXveP03nxXUylbRfxOAqcq LbRtceUPVVx822wNFY3cZL7FVB6RGBOUA5o5vvWgULmPLKqaA++NrXTbKjyFbYXNHppj EFBIKoj3jSpyc//tAkSrUbqC6PhEj0extKhlYSZ5t9Y2AKHA5hcCmx0ie+dGlMCHozj3 VqKKe5N3O5QjKLIyeO2xkPg7uECjOS2NffuWMoJUgrmOZkI8jc3QOZDXHlzL6gcGnjYH xiCw== X-Gm-Message-State: AOJu0YzftBJZH2mXuzaxABt1XlOZdUejsnBZFm+FEh14tR+1QhpJV+Zy 5/xsh3JkGbq9ZpgYfSC/ziFhcUsF2TnS9l9/8xoMYaW1FkM= X-Google-Smtp-Source: AGHT+IHd9pPeYYNaHaEtDHf0a64Q+e1O43jTZoAq7gBqFi7GrOUiXf6gbDZEvtGMBoFqHcpMKg2/rw== X-Received: by 2002:a5d:4146:0:b0:336:6778:6220 with SMTP id c6-20020a5d4146000000b0033667786220mr560548wrq.48.1704971111373; Thu, 11 Jan 2024 03:05:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/41] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV Date: Thu, 11 Jan 2024 11:04:34 +0000 Message-Id: <20240111110505.1563291-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org FEAT_NV defines three new bits in HCR_EL2: NV, NV1 and AT. When the feature is enabled, allow these bits to be written, and flush the TLBs for the bits which affect page table interpretation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpu-features.h | 5 +++++ target/arm/helper.c | 6 +++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 954d3582685..3a43c328d9e 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -839,6 +839,11 @@ static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; } +static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && diff --git a/target/arm/helper.c b/target/arm/helper.c index 7889fd45d67..4e5fd25199c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5815,6 +5815,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) if (cpu_isar_feature(aa64_rme, cpu)) { valid_mask |= HCR_GPF; } + if (cpu_isar_feature(aa64_nv, cpu)) { + valid_mask |= HCR_NV | HCR_NV1 | HCR_AT; + } } if (cpu_isar_feature(any_evt, cpu)) { @@ -5833,9 +5836,10 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) * HCR_DC disables stage1 and enables stage2 translation * HCR_DCT enables tagging on (disabled) stage1 translation * HCR_FWB changes the interpretation of stage2 descriptor bits + * HCR_NV and HCR_NV1 affect interpretation of descriptor bits */ if ((env->cp15.hcr_el2 ^ value) & - (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) { + (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB | HCR_NV | HCR_NV1)) { tlb_flush(CPU(cpu)); } env->cp15.hcr_el2 = value; From patchwork Thu Jan 11 11:04:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A806C47077 for ; Thu, 11 Jan 2024 11:06:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssh-0001dB-DH; Thu, 11 Jan 2024 06:05:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss7-0001LQ-UW for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:16 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss5-0004PL-BX for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:15 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-336746c7b6dso4417063f8f.0 for ; Thu, 11 Jan 2024 03:05:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971111; x=1705575911; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MggGO+NPAbBJmsyAFGskbOZEUDcciWvWwdLwaUXekp4=; b=k0fUZ55OnwPMRbZdtr9VeijGOF4Ni+eQP/QtBskG2QKY50YQ7IXU3Woa23gaW+IV4A cebyHUGIl8oVbgfkoYh0v/9/G8B4q0J/58nfAiOF3Mxv/Teb+f5ojOs3cscoCszJ9pmn KmPp4WD48+ar3Ae/xkKCyxJnlqSksFuU/UW5h8ciW1AyAkBxqSlIDDBrRGGlRFDNFsQc rjx5PBjq5H41kVZxjWlzaorqP/nABci2n0xaIBR9XhrcQUCGxm9WWINYondTWu+oJSK5 p6lCLDFCUl4zPWcC5VMYpb1BiAyy2BWsrnetOPrACqzWRFbs6h3S0RvQwyaOsgpp02Qa IEkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971111; x=1705575911; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MggGO+NPAbBJmsyAFGskbOZEUDcciWvWwdLwaUXekp4=; b=HG3eRKn3uU+PKAdBNqjTAMZg8HUQKaJo0cK6rKfDFl+s8jv9v+a8K7Ufsa/zCF0xO4 BPEhlHx6/Zje0NSkWBORTFhJyOxsDjCB4whFHLYAjFv5tGshkLS4YdtoqGRZP8E6mDd0 Ask2JF9lIbiySv2wyjmK/bj1ksRSWuya+64ziYbXSTyOnRsnICQZNx+Qf/iS2/i6UP2v 1C30UCH8ONkenyRuOKjF5kjFErICEPjXgFlFHNZM4STNfraftvdm6+bCXsT8QIoi3roB 5WSlxZhTQObg+s8m7EUJl1dpOcgXko2V8kcte+T4iNgsBfeZb9jAxhmwFtPm4V8qFV5v v1Sg== X-Gm-Message-State: AOJu0Yy7QrcMSdMWA8azRWvCZdvhvBNlEHDmXSgXaxVjYtH8i2vjLgdT ONXCoLzeQje5wqIXTZL0+M4ZOD3p6ZQyyIUnwcs749n2H/Y= X-Google-Smtp-Source: AGHT+IGGiBc3aZZZA5aurfolZP5L5u2bbef1yv0+fPOJp3vJEMFZHifDUVa9r7947LiLkpiyT25ceg== X-Received: by 2002:adf:e989:0:b0:336:d299:ada5 with SMTP id h9-20020adfe989000000b00336d299ada5mr482341wrm.112.1704971111723; Thu, 11 Jan 2024 03:05:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/41] target/arm: Implement HCR_EL2.AT handling Date: Thu, 11 Jan 2024 11:04:35 +0000 Message-Id: <20240111110505.1563291-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The FEAT_NV HCR_EL2.AT bit enables trapping of some address translation instructions from EL1 to EL2. Implement this behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4e5fd25199c..dc4b4123e00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3703,6 +3703,15 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, return at_e012_access(env, ri, isread); } +static CPAccessResult at_s1e01_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_AT)) { + return CP_ACCESS_TRAP_EL2; + } + return at_e012_access(env, ri, isread); +} + static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5568,22 +5577,22 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1R, - .accessfn = at_e012_access, .writefn = ats_write64 }, + .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1W, - .accessfn = at_e012_access, .writefn = ats_write64 }, + .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E0R, - .accessfn = at_e012_access, .writefn = ats_write64 }, + .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E0W, - .accessfn = at_e012_access, .writefn = ats_write64 }, + .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, @@ -8168,12 +8177,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] = { .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1RP, - .accessfn = at_e012_access, .writefn = ats_write64 }, + .accessfn = at_s1e01_access, .writefn = ats_write64 }, { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt = FGT_ATS1E1WP, - .accessfn = at_e012_access, .writefn = ats_write64 }, + .accessfn = at_s1e01_access, .writefn = ats_write64 }, }; static const ARMCPRegInfo ats1cp_reginfo[] = { From patchwork Thu Jan 11 11:04:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6CA2C4707B for ; Thu, 11 Jan 2024 11:08:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssS-0001RZ-0d; Thu, 11 Jan 2024 06:05:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss8-0001LS-1S for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:16 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss5-0004PV-Oe for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:15 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-40e6275e9beso161175e9.1 for ; Thu, 11 Jan 2024 03:05:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971112; x=1705575912; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UXRcXu0KHC3KDr0EhA03orQJ3pMJ3fXxZkZHJokxdik=; b=dRBZzVMB+9dNxeAO2D3vJC6zdAMOnaI2673gYwFxehWyznFenB8XUBqyCY0nVSTXgZ st4L/Ivv6L5wU/M3Q9rN7TcJ9CmvwZYgwPA8rnUg6+XjYx2vwZnIaLgH84+kRaFj6FZP MKthQIOtYw+LKcs9lYie0B48tLI82yOAvjHKqRPfOXUO2iOv5EHkBZE5pGSgjSp4SdMe 8TyYUjhf7by6pn/oFg1Qc90pmw9LEHIsKpFi23wpFk014NX4pyflWOqYw+N9UdUXswnD ghBWp/MAim0W+rBYbYm0hze2cwW9pO/Y0BJswa1/M1ck5uzr9lIB3AshwsZ9zfnnFMHM eRog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971112; x=1705575912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UXRcXu0KHC3KDr0EhA03orQJ3pMJ3fXxZkZHJokxdik=; b=IRugoXmcsosxJZme8O8nPNF2cyFGu/oxFwBqN4NbOFIl61EOT/SDN3URDZ3TD3pBnB m/hpqCetV80+N6Z6n+JAczM5F5Wkm70Q0d04xuA0sA7kXo6dWnH0HydA9hzAzV+q27XD itHWQk/8JUyTHw1LMlB4XkmazLrJJEXNv5xA5+Ew/R9dxbYU0gjPlY6PBdCgUxRqTaz0 /3zNwbE7V5lpzHXVvXk0x8AwP1g11N8NuBpRLwfJI+6KtuABkRv7wmqrZh45umDyesO+ IOZAwt0ns0zxDdqhYdcuI2n8blajhpChmKhqI79m5pTocTaruywpvJbY1QfOHwHjBjfD X4TA== X-Gm-Message-State: AOJu0YyK553gzmWNuquLreVvFScWH87+/jQ1GrEeezAUI268tT6wS+8V nPfE+M2P3dg2D5vGSK2nsUp6y0PCw+ampLkMLYO7Iql37ng= X-Google-Smtp-Source: AGHT+IGhLeZ85eX7BmK7/YcJoQrCUIwxLBYXdFQtyj5TzunLUqfEmcc6Hyvef/A5Z/xoZSHcGTL1DA== X-Received: by 2002:a05:600c:4f16:b0:40c:2394:1796 with SMTP id l22-20020a05600c4f1600b0040c23941796mr331979wmq.174.1704971112098; Thu, 11 Jan 2024 03:05:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/41] target/arm: Enable trapping of ERET for FEAT_NV Date: Thu, 11 Jan 2024 11:04:36 +0000 Message-Id: <20240111110505.1563291-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When FEAT_NV is turned on via the HCR_EL2.NV bit, ERET instructions are trapped, with the same syndrome information as for the existing FEAT_FGT fine-grained trap (in the pseudocode this is handled in AArch64.CheckForEretTrap()). Rename the DisasContext and tbflag bits to reflect that they are no longer exclusively for FGT traps, and set the tbflag bit when FEAT_NV is enabled as well as when the FGT is enabled. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpu.h | 2 +- target/arm/tcg/translate.h | 4 ++-- target/arm/tcg/hflags.c | 11 ++++++++++- target/arm/tcg/translate-a64.c | 6 +++--- 4 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8c3ca2e2319..8da6bfda228 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3232,7 +3232,7 @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) FIELD(TBFLAG_A64, SVL, 24, 4) /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) -FIELD(TBFLAG_A64, FGT_ERET, 29, 1) +FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) FIELD(TBFLAG_A64, NAA, 30, 1) FIELD(TBFLAG_A64, ATA0, 31, 1) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3c3bb3431ad..8c84377003c 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -138,10 +138,10 @@ typedef struct DisasContext { bool mve_no_pred; /* True if fine-grained traps are active */ bool fgt_active; - /* True if fine-grained trap on ERET is enabled */ - bool fgt_eret; /* True if fine-grained trap on SVC is enabled */ bool fgt_svc; + /* True if a trap on ERET is enabled (FGT or NV) */ + bool trap_eret; /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ bool naa; /* diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index a6ebd7571a3..560fb7964ab 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -169,6 +169,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, CPUARMTBFlags flags = {}; ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); uint64_t tcr = regime_tcr(env, mmu_idx); + uint64_t hcr = arm_hcr_el2_eff(env); uint64_t sctlr; int tbii, tbid; @@ -285,13 +286,21 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, if (arm_fgt_active(env, el)) { DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { - DP_TBFLAG_A64(flags, FGT_ERET, 1); + DP_TBFLAG_A64(flags, TRAP_ERET, 1); } if (fgt_svc(env, el)) { DP_TBFLAG_ANY(flags, FGT_SVC, 1); } } + /* + * ERET can also be trapped for FEAT_NV. arm_hcr_el2_eff() takes care + * of "is EL2 enabled" and the NV bit can only be set if FEAT_NV is present. + */ + if (el == 1 && (hcr & HCR_NV)) { + DP_TBFLAG_A64(flags, TRAP_ERET, 1); + } + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { /* * Set MTE_ACTIVE if any access may be Checked, and leave clear diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f3b5b9124d0..0f30e71f9bd 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1606,7 +1606,7 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) if (s->current_el == 0) { return false; } - if (s->fgt_eret) { + if (s->trap_eret) { gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(0), 2); return true; } @@ -1633,7 +1633,7 @@ static bool trans_ERETA(DisasContext *s, arg_reta *a) return false; } /* The FGT trap takes precedence over an auth trap. */ - if (s->fgt_eret) { + if (s->trap_eret) { gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(a->m ? 3 : 2), 2); return true; } @@ -13980,7 +13980,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC); - dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET); + dc->trap_eret = EX_TBFLAG_A64(tb_flags, TRAP_ERET); dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; From patchwork Thu Jan 11 11:04:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BBB63C47077 for ; Thu, 11 Jan 2024 11:05:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssV-0001Rm-JM; Thu, 11 Jan 2024 06:05:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss8-0001LT-3r for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:16 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss5-0004Pq-Sh for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:15 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-33674f60184so4942779f8f.1 for ; Thu, 11 Jan 2024 03:05:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971112; x=1705575912; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6ycUm1aTQ8P1D0oHh26lik8xW1H5/8FvjoM1bUhF2Zc=; b=wDgrbvmhbWSIzdiR2fx44GKIzie6iOpWq55sKHgYZPQTxVeFSCRFioRMZ2dPCuufC1 H36cKJJAll5pdlRyObvvBCRj1d5lkAnekXJ2XYxs0Z4Ha78RetPf3JyPM50Wt1d29Fjc n1ZPYuAKzPEIYSib5e+AtlTBbWOdfhFNeLswZCTfhWQsJQgUtyodbjW43vMh+QSRVnKy 11ggjtgnnNmagDKvg8WGpyKHYR59IyR7NLPS3yN6fHNNLoCRQ22oMOGCRpRE9/gXf+bO tmZIlYjKolHM1rgz2oj/Uf7m5Zbf6Wirbi1dYOM6IRDIH4ZWtrCQySokM+UNmb42efWU F0fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971112; x=1705575912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6ycUm1aTQ8P1D0oHh26lik8xW1H5/8FvjoM1bUhF2Zc=; b=hME/ssCH2FYeAzz7eOKj+dwDUtszM0DwES7PpyXMmu4gRi+ZgZIclU8OGJN10GWfIt RnZZTecsFHAOZsGCBn2QF+lXrQzoIEsq2fwSuLuuIZxxArgYA/M6NmY7/o0eNSQ60hg0 y53fth876DZz5CpSzUeKNmIJVzej1bnRqijXvdKva73jidmWCIZ7HxXwZiisF+JOP+ya FGTJqtqs87vlIShNl8blTSnVWhCRMArxEGNQLh7qJJ0Rzn75xCcolFrL4H6tvs8hAfmi kgcVhYFpyZYCrZumn3B32tNsVudY/jUkVE5XSTSIiYe8LmJ+xKBW5Cb5vnzzMDyilO/k sF7w== X-Gm-Message-State: AOJu0YyHWqAy/gLOFtmPnakYOipSk7ia96lbaDfx6Lpf0xJxW7R3J8Ch 6o4inl6/hmuyqhMIRgj7bnxPl53RPE2H+O9V/7gQNIaCLcc= X-Google-Smtp-Source: AGHT+IHYwHP/k/R565XeAOTItZeuq+BXFtiJiwgKDgg/JZddU7Ox/D72WPWiMooohxuW/ZBm5jkorg== X-Received: by 2002:adf:e9c2:0:b0:333:39d4:ff80 with SMTP id l2-20020adfe9c2000000b0033339d4ff80mr494842wrn.90.1704971112529; Thu, 11 Jan 2024 03:05:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/41] target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set Date: Thu, 11 Jan 2024 11:04:37 +0000 Message-Id: <20240111110505.1563291-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The HCR_EL2.TSC trap for trapping EL1 execution of SMC instructions has a behaviour change for FEAT_NV when EL3 is not implemented: * in older architecture versions TSC was required to have no effect (i.e. the SMC insn UNDEFs) * with FEAT_NV, when HCR_EL2.NV == 1 the trap must apply (i.e. SMC traps to EL2, as it already does in all cases when EL3 is implemented) * in newer architecture versions, the behaviour either without FEAT_NV or with FEAT_NV and HCR_EL2.NV == 0 is relaxed to an IMPDEF choice between UNDEF and trap-to-EL2 (i.e. it is permitted to always honour HCR_EL2.TSC) for AArch64 only Add the condition to honour the trap bit when HCR_EL2.NV == 1. We leave the HCR_EL2.NV == 0 case with the existing (UNDEF) behaviour, as our IMPDEF choice (both because it avoids a behaviour change for older CPU models and because we'd have to distinguish AArch32 from AArch64 if we opted to trap to EL2). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/tcg/op_helper.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 105ab63ed75..b5ac26061c7 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -985,7 +985,14 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) * * Conduit SMC, valid call Trap to EL2 PSCI Call * Conduit SMC, inval call Trap to EL2 Undef insn - * Conduit not SMC Undef insn Undef insn + * Conduit not SMC Undef or trap[1] Undef insn + * + * [1] In this case: + * - if HCR_EL2.NV == 1 we must trap to EL2 + * - if HCR_EL2.NV == 0 then newer architecture revisions permit + * AArch64 (but not AArch32) to trap to EL2 as an IMPDEF choice + * - otherwise we must UNDEF + * We take the IMPDEF choice to always UNDEF if HCR_EL2.NV == 0. */ /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state. @@ -999,9 +1006,12 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) : smd_flag && !secure; if (!arm_feature(env, ARM_FEATURE_EL3) && + !(arm_hcr_el2_eff(env) & HCR_NV) && cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { - /* If we have no EL3 then SMC always UNDEFs and can't be - * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3 + /* + * If we have no EL3 then traditionally SMC always UNDEFs and can't be + * trapped to EL2. For nested virtualization, SMC can be trapped to + * the outer hypervisor. PSCI-via-SMC is a sort of ersatz EL3 * firmware within QEMU, and we want an EL2 guest to be able * to forbid its EL1 from making PSCI calls into QEMU's * "firmware" via HCR.TSC, so for these purposes treat From patchwork Thu Jan 11 11:04:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1135C47077 for ; Thu, 11 Jan 2024 11:11:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssU-0001Rh-7q; Thu, 11 Jan 2024 06:05:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss8-0001M0-VR for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:17 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss6-0004Q1-Lu for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:16 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-336c9acec03so4519277f8f.2 for ; Thu, 11 Jan 2024 03:05:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971113; x=1705575913; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=H2twb/r8sx0w6+zjm6Opwu2RcD6Eydz3aISuZWYaH3g=; b=D7MtU716tFInI84HEdAxtdbTgM6gYEurt7lzh9pbY8t3ULctBtg//U3oqvpPIYE7Pc OLH5cNghkjzNbihKsb8bOU3eGUNJo9Qiq+aGWtIXpGYFN2b6ppAXAG6Tukn8G6kEuscS bNxNWZKm2TQ5ORwzK1dAdB+qArZAN6Y/XKmA2K/k3JPB4nwkdaJjhhyzc4xslh7yeZXt DW9o60MqtodYimr+jEXraW4rvkY/kb7R15hWbnK25GnEktlA/XpgPSBv2T7WRcOD7wJq hCz5wFa80yhnTOLtmuqjpjmd/FWJASEicyGIt5rSoUI3RHYuby0cmpCyJFiP1rTjFi5K Lh4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971113; x=1705575913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H2twb/r8sx0w6+zjm6Opwu2RcD6Eydz3aISuZWYaH3g=; b=CyMGJpzlBZPM7GA4CoQteygZ0psaKfQJiSX4B6uA6p0hUbFdLq9El5nQPVH38UIE1n iXovQbEdFEJ+lBcaW/rzmfZ9n01x5t06AhAszWomxGePasdeWESZuq0GstU2ZHgBxao6 BISLDxYy8XGYdeuRVvnMLagv1EKsoeTjOdWdfP2LComzNGTE7imeZF0jnK7LbLjRDimD iMvITfWaxqirPARLP7Hry1cW+FZuxeZs5rLCOayffBezjOm8cZgLF6zThOsR9v0Xav7F QhyX9PtRY4zoY8MYnBI5JBM+T0W6oWQo4FyOu89HbHoS8ZqW6BSQYdGq3r9flRNVGOv+ +76g== X-Gm-Message-State: AOJu0Yw5ZpeAAtcVYeM1mvPh/H4MifZU5HDGI3s/M2RcmBRTr6bC99C0 +Wm2zFO/VX7kJxmHFua4T5yTaTcNmn0Y4DQ3PKMeOGON39k= X-Google-Smtp-Source: AGHT+IFKd72UjlpGOCsGlU8ilmyif90aca6m0G3AhrLlv3m68TAtt5O+Xoh/uFouhbTupr8Gmta52Q== X-Received: by 2002:a5d:690f:0:b0:337:62c6:cd1c with SMTP id t15-20020a5d690f000000b0033762c6cd1cmr635279wru.80.1704971112946; Thu, 11 Jan 2024 03:05:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/41] target/arm: Allow use of upper 32 bits of TBFLAG_A64 Date: Thu, 11 Jan 2024 11:04:38 +0000 Message-Id: <20240111110505.1563291-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The TBFLAG_A64 TB flag bits go in flags2, which for AArch64 guests we know is 64 bits. However at the moment we use FIELD_EX32() and FIELD_DP32() to read and write these bits, which only works for bits 0 to 31. Since we're about to add a flag that uses bit 32, switch to FIELD_EX64() and FIELD_DP64() so that this will work. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpu.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8da6bfda228..6dd0f642581 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3237,12 +3237,14 @@ FIELD(TBFLAG_A64, NAA, 30, 1) FIELD(TBFLAG_A64, ATA0, 31, 1) /* - * Helpers for using the above. + * Helpers for using the above. Note that only the A64 accessors use + * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags + * word either is or might be 32 bits only. */ #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) #define DP_TBFLAG_A64(DST, WHICH, VAL) \ - (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) + (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) #define DP_TBFLAG_A32(DST, WHICH, VAL) \ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) #define DP_TBFLAG_M32(DST, WHICH, VAL) \ @@ -3251,7 +3253,7 @@ FIELD(TBFLAG_A64, ATA0, 31, 1) (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) -#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) From patchwork Thu Jan 11 11:04:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 665E5C47077 for ; Thu, 11 Jan 2024 11:12:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssn-0001lO-8q; Thu, 11 Jan 2024 06:05:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssD-0001O1-1z for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:25 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss7-0004QJ-DE for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:20 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-33694bf8835so4197722f8f.3 for ; Thu, 11 Jan 2024 03:05:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971113; x=1705575913; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xMUaXwQGKRqjkeLfl66MTj+REoCxCyxmGFuF/1PCBbc=; b=OYiwWlPOmmBQTPu6U9PbWzCyviu4GdD7aclJQFTMcqxf8qlBCShB8yknaRIXb/dEcx 6DQOgfLlxy9erqewaVO0ipwFJUv7miOqEeirGyjhkmwANZYfPK4/cUtDuOR+wtOKN6N+ 6ptjNQnxwsaxD2Vlvz9amdh8g7IC7LRQQSNL/D1AsEVue7wMzSas2RvEeFIB7+l14B33 gCX7AiWSN4ImbzTnmy4vPhZLt0pq5xlJZpHWWBAueJYsOd0a5LJ12z+AFNur7aONQEgO GgN1wJOsXNsAFORGRDpFsemjktyI2GiVSD4T50EK1+x8vX5NnR6NcqpP8jV82UEe8ZCi sxXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971113; x=1705575913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xMUaXwQGKRqjkeLfl66MTj+REoCxCyxmGFuF/1PCBbc=; b=HXkNUAsGc5XRyIVIhmy7hFlDXzFROuJkv17E11FreOqMIRYzb1U1e6v2Pqn2oPRYOC 0akVwPcaR+31DZ5vk4JBQRFYpFdn48MxKcNSPhF1JNDjHQ0WV9YupcS6AsH4jKm/od1U AbsdE15ycXjSaTEZ2rXetyNuEF7Vi4YYAopIm53JtSsqH1yyEfPjER12FLvfkRORpsMU AxCPgU1XbKbCcRL2DvIDVIs2b3mGcOV7uQNlrzPQvt16pAcSUJsAhWN8bdp2asAX4VW3 DO0aR4xKhrGuVRB6fC15eFKPuDU5EyoU+dLokvOHJ58pCHUgvxmOz2O53DJxYZ+qWFKF CYYg== X-Gm-Message-State: AOJu0YzkjWmrd6jpyrUiA3kjzGN1+H5lG24McfNcpNhguGrJ6AY9gHhB k6wBqUBov5nRHuVb2Ckkb3OaDy8zD3q4WYzVjNO6IcHQli8= X-Google-Smtp-Source: AGHT+IFWWd2dxib2awPoRmSiBK+KfV1YC8PFywCBhv2b3BBPDBm2SPcowTgw5JhCcZJWL75nRFOfnw== X-Received: by 2002:adf:f443:0:b0:336:8462:37f1 with SMTP id f3-20020adff443000000b00336846237f1mr486450wrp.51.1704971113330; Thu, 11 Jan 2024 03:05:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/41] target/arm: Record correct opcode fields in cpreg for E2H aliases Date: Thu, 11 Jan 2024 11:04:39 +0000 Message-Id: <20240111110505.1563291-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For FEAT_VHE, we define a set of register aliases, so that for instance: * the SCTLR_EL1 either accesses the real SCTLR_EL1, or (if E2H is 1) SCTLR_EL2 * a new SCTLR_EL12 register accesses SCTLR_EL1 if E2H is 1 However when we create the 'new_reg' cpreg struct for the SCTLR_EL12 register, we duplicate the information in the SCTLR_EL1 cpreg, which means the opcode fields are those of SCTLR_EL1, not SCTLR_EL12. This is a problem for code which looks at the cpreg opcode fields to determine behaviour (e.g. in access_check_cp_reg()). In practice the current checks we do there don't intersect with the *_EL12 registers, but for FEAT_NV this will become a problem. Write the correct values from the encoding into the new_reg struct. This restores the invariant that the cpreg that you get back from the hashtable has opcode fields that match the key you used to retrieve it. When we call the readfn or writefn for the target register, we pass it the cpreg struct for that target register, not the one for the alias, in case the readfn/writefn want to look at the opcode fields to determine behaviour. This means we need to interpose custom read/writefns for the e12 aliases. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index dc4b4123e00..dc2471eda7e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6522,6 +6522,19 @@ static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, writefn(env, ri, value); } +static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ + return ri->orig_readfn(env, ri->opaque); +} + +static void el2_e2h_e12_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ + return ri->orig_writefn(env, ri->opaque, value); +} + static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) { struct E2HAlias { @@ -6621,6 +6634,28 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) new_reg->type |= ARM_CP_ALIAS; /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ new_reg->access &= PL2_RW | PL3_RW; + /* The new_reg op fields are as per new_key, not the target reg */ + new_reg->crn = (a->new_key & CP_REG_ARM64_SYSREG_CRN_MASK) + >> CP_REG_ARM64_SYSREG_CRN_SHIFT; + new_reg->crm = (a->new_key & CP_REG_ARM64_SYSREG_CRM_MASK) + >> CP_REG_ARM64_SYSREG_CRM_SHIFT; + new_reg->opc0 = (a->new_key & CP_REG_ARM64_SYSREG_OP0_MASK) + >> CP_REG_ARM64_SYSREG_OP0_SHIFT; + new_reg->opc1 = (a->new_key & CP_REG_ARM64_SYSREG_OP1_MASK) + >> CP_REG_ARM64_SYSREG_OP1_SHIFT; + new_reg->opc2 = (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) + >> CP_REG_ARM64_SYSREG_OP2_SHIFT; + new_reg->opaque = src_reg; + new_reg->orig_readfn = src_reg->readfn ?: raw_read; + new_reg->orig_writefn = src_reg->writefn ?: raw_write; + if (!new_reg->raw_readfn) { + new_reg->raw_readfn = raw_read; + } + if (!new_reg->raw_writefn) { + new_reg->raw_writefn = raw_write; + } + new_reg->readfn = el2_e2h_e12_read; + new_reg->writefn = el2_e2h_e12_write; ok = g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)a->new_key, new_reg); From patchwork Thu Jan 11 11:04:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0774C47077 for ; Thu, 11 Jan 2024 11:08:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssX-0001Rs-Fl; Thu, 11 Jan 2024 06:05:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss9-0001M2-HT for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:17 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss7-0004QY-LE for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:17 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-337874b8164so359055f8f.2 for ; Thu, 11 Jan 2024 03:05:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971113; x=1705575913; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=w7B/8lPK1MV7k06ckol/zGTOa+v925bmxBrmmGd2s5s=; b=lMdQ6KlH9D1xcB4PL4MD0/UD6UOgg5PwYhQ3RgCoea8T/btwxvcAirG3xHsVFBPX/p JoNMiZYzJ1TfRSXExVTdQtURkgPMycDTVfmOh72Doi51G0Pc195YiXv796ygH3BrpMLk OGZbY8uoSSXsx3L6OqgSd3q1KWAz8604MXA0IWqzjNVzKsnn3L/OmhqoCZvPH0h+i/R+ A65aurv/0UMvfjC5smMSsmmNpQTYWCqx4iNNKPG+4wQeUuMKBlcnE+G31GmFuCsGngoC HlbuS6Fu+5S7PHtp1UrrCjtOJYFr4xsYIEHyECBIWRfE10W/L7vKsQfKMfqnYVzxl8uF tONA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971113; x=1705575913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w7B/8lPK1MV7k06ckol/zGTOa+v925bmxBrmmGd2s5s=; b=fKV92kXtbekHf/VfhZquDaunlQPemNQzUjrESQdJOxuhQUXCEw9awHLeVpdjVo0MBT 7VjY7QTHHCgN3oh1UFyp4h9mlR3ROTQDaB9WOwuLk5EI6JbTa4jBI0JxrXKYPdDWkYxB 1rrTmLxDUciN5hYVZ0TaAGEdKaPufs1xy+xQHsjX3YDZ5qUmKPmeAIY/9g/3Q7s1R5rJ Ue9Unb5b6ooFp7PW+whyY8duT22J/b9sJtBHbcQVKy4mgl41IYF2ojlzH06ZHPvqi2uF hm6vFFPjxl5HuCctKB7r2aBTpjkYsDNJ/iRGoR1nrn/or34qqUCMRy8JTOHRYEhJy+25 57Hg== X-Gm-Message-State: AOJu0YyqvcCI7uBq3f52vzLx3AZeh5etW/DOyWwiFlsnKBmTxV2AOput XXRN8mepBYnpHrVYP5zEuFrX0p3dMo1MtTH/ZhQDPTPX4kw= X-Google-Smtp-Source: AGHT+IEbPVU9UaxIQF/4tPfqHZVn3GBAkkclkZ8a7CbX0aj2A58gDlJtYylo1GVJwpBxrPF3zFBKqg== X-Received: by 2002:adf:ce83:0:b0:336:7790:6a36 with SMTP id r3-20020adfce83000000b0033677906a36mr542344wrn.129.1704971113683; Thu, 11 Jan 2024 03:05:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/41] target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0 Date: Thu, 11 Jan 2024 11:04:40 +0000 Message-Id: <20240111110505.1563291-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The alias registers like SCTLR_EL12 only exist when HCR_EL2.E2H is 1; they should UNDEF otherwise. We weren't implementing this. Add an intercept of the accessfn for these aliases, and implement the UNDEF check. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpregs.h | 3 ++- target/arm/helper.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index f1293d16c07..e748d184cb6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -937,7 +937,7 @@ struct ARMCPRegInfo { CPResetFn *resetfn; /* - * "Original" writefn and readfn. + * "Original" readfn, writefn, accessfn. * For ARMv8.1-VHE register aliases, we overwrite the read/write * accessor functions of various EL1/EL0 to perform the runtime * check for which sysreg should actually be modified, and then @@ -948,6 +948,7 @@ struct ARMCPRegInfo { */ CPReadFn *orig_readfn; CPWriteFn *orig_writefn; + CPAccessFn *orig_accessfn; }; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index dc2471eda7e..797b7518f61 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6535,6 +6535,20 @@ static void el2_e2h_e12_write(CPUARMState *env, const ARMCPRegInfo *ri, return ri->orig_writefn(env, ri->opaque, value); } +static CPAccessResult el2_e2h_e12_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */ + if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + if (ri->orig_accessfn) { + return ri->orig_accessfn(env, ri->opaque, isread); + } + return CP_ACCESS_OK; +} + static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) { struct E2HAlias { @@ -6648,6 +6662,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) new_reg->opaque = src_reg; new_reg->orig_readfn = src_reg->readfn ?: raw_read; new_reg->orig_writefn = src_reg->writefn ?: raw_write; + new_reg->orig_accessfn = src_reg->accessfn; if (!new_reg->raw_readfn) { new_reg->raw_readfn = raw_read; } @@ -6656,6 +6671,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) } new_reg->readfn = el2_e2h_e12_read; new_reg->writefn = el2_e2h_e12_write; + new_reg->accessfn = el2_e2h_e12_access; ok = g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)a->new_key, new_reg); From patchwork Thu Jan 11 11:04:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91300C47077 for ; Thu, 11 Jan 2024 11:12:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssj-0001gm-T4; Thu, 11 Jan 2024 06:05:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss9-0001MZ-Rs for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:18 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss7-0004Qj-Lt for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:17 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-336990fb8fbso4247977f8f.1 for ; Thu, 11 Jan 2024 03:05:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971114; x=1705575914; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=p08aMxgI1IXtfa2vzBRi+z+GrjTOXr7+5t5A30IuGRM=; b=Flk69zezy2jJwOxNLyABRoxIOzMLmVuuwgLbsF0h5OPoGIVJQnh211wy/SiYemt/uB YDescplGwvKkM/GIaOuvlHg3HCgbpideoFIKwbciz+JOmUAGD78sPmVZeG6G3D6SMJbD aUmnpd91kScvCnqDbdAxJ7x8UTO8JL6TBxGyqvBIu/cMWoy8fWPC5iO8/rHeACMVPJ75 LVyG8x57o1alZFWgK0yOg+REP/kfx9SOWdh3Gc160agGInokKpGg2U+J3z+KkBc/zimj A9ITYO6sLLzI+6+vvklBCOuHZjdEcJezbjzIWnrJmKWUtyUe6Qe7si5n6Y9mpkh8Gn1O N3UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971114; x=1705575914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p08aMxgI1IXtfa2vzBRi+z+GrjTOXr7+5t5A30IuGRM=; b=Fy/G0yvw+bM9LhiksJ84X/lVBl/hw74rpPtPtIHaiZE06ldb0QqYLVi3no6s8gorow 2LSpAZoIRkDh6CEHXElRTe0dbRbvyUbXajaXQygPchaIV6zdilzz7DT2CWkxR4ToGefC JVheBCoOoyzYa/tCiw/qJVAftxMrXwQEymm0Beb0veDRT6l+shQ5TRuW4KmTVQnoqXZb E1kjbRT9I1xtj4/n0/5l0wO8LGn0Vx1Dgw0Wjrx/+BqCjkkGs1ep72ZvG1f1Jpsbb/h6 o2Ui56iZWNKRdbU8d7oFdcyQkPl40NNTxu7/HWDsUbCOgJ+aIHuWTct1BOIQs63VIIQ8 2KeA== X-Gm-Message-State: AOJu0YyxjVAHplsR6qxaOkfOnUC+DMeNf0UApA7u2PatB+s10f5wWEGg VvdGE+N02oIutHS5TfJSCyd1I2HEcMy0PB/vR8co/lxmRjw= X-Google-Smtp-Source: AGHT+IFPkPP5pbgpwfzOT9B/y1CgsfCZsMNICw4/YiYTDAbTHY2Hqz2XTRSaNpW8QOVUFX2gyODCfw== X-Received: by 2002:a5d:4652:0:b0:337:2994:15b1 with SMTP id j18-20020a5d4652000000b00337299415b1mr584244wrs.135.1704971114117; Thu, 11 Jan 2024 03:05:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/41] target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses Date: Thu, 11 Jan 2024 11:04:41 +0000 Message-Id: <20240111110505.1563291-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org FEAT_NV and FEAT_NV2 will allow EL1 to attempt to access cpregs that only exist at EL2. This means we're going to want to run their accessfns when the CPU is at EL1. In almost all cases, the behaviour we want is "the accessfn returns OK if at EL1". Mostly the accessfn already does the right thing; in a few cases we need to explicitly check that the EL is not 1 before applying various trap controls, or split out an accessfn used both for an _EL1 and an _EL2 register into two so we can handle the FEAT_NV case correctly for the _EL2 register. There are two registers where we want the accessfn to trap for a FEAT_NV EL1 access: VSTTBR_EL2 and VSTCR_EL2 should UNDEF an access from NonSecure EL1, not trap to EL2 under FEAT_NV. The way we have written sel2_access() already results in this behaviour. We can identify the registers we care about here because they all have opc1 == 4 or 5. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/debug_helper.c | 12 +++++++- target/arm/helper.c | 65 ++++++++++++++++++++++++++++++++++----- 2 files changed, 69 insertions(+), 8 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 83d2619080f..b39144d5b93 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -844,6 +844,16 @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static CPAccessResult access_dbgvcr32(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + /* MCDR_EL3.TDMA doesn't apply for FEAT_NV traps */ + if (arm_current_el(env) == 2 && (env->cp15.mdcr_el3 & MDCR_TDA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + /* * Check for traps to Debug Comms Channel registers. If FEAT_FGT * is implemented then these are controlled by MDCR_EL2.TDCC for @@ -1062,7 +1072,7 @@ static const ARMCPRegInfo debug_aa32_el1_reginfo[] = { */ { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, - .access = PL2_RW, .accessfn = access_tda, + .access = PL2_RW, .accessfn = access_dbgvcr32, .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, }; diff --git a/target/arm/helper.c b/target/arm/helper.c index 797b7518f61..7c7f92c16de 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3324,6 +3324,11 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { + if (arm_current_el(env) == 1) { + /* This must be a FEAT_NV access */ + /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */ + return CP_ACCESS_OK; + } if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { return CP_ACCESS_TRAP; } @@ -6014,7 +6019,7 @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if (arm_current_el(env) < 3 + if (arm_current_el(env) == 2 && arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) { return CP_ACCESS_TRAP_EL3; @@ -6539,6 +6544,15 @@ static CPAccessResult el2_e2h_e12_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { + if (arm_current_el(env) == 1) { + /* + * This must be a FEAT_NV access (will either trap or redirect + * to memory). None of the registers with _EL12 aliases want to + * apply their trap controls for this kind of access, so don't + * call the orig_accessfn or do the "UNDEF when E2H is 0" check. + */ + return CP_ACCESS_OK; + } /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */ if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { return CP_ACCESS_TRAP_UNCATEGORIZED; @@ -7015,10 +7029,21 @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } -static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) +static CPAccessResult access_smprimap(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + /* If EL1 this is a FEAT_NV access and CPTR_EL3.ESM doesn't apply */ + if (arm_current_el(env) == 2 + && arm_feature(env, ARM_FEATURE_EL3) + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_smpri(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) { - /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */ if (arm_current_el(env) < 3 && arm_feature(env, ARM_FEATURE_EL3) && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { @@ -7137,12 +7162,12 @@ static const ARMCPRegInfo sme_reginfo[] = { */ { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4, - .access = PL1_RW, .accessfn = access_esm, + .access = PL1_RW, .accessfn = access_smpri, .fgt = FGT_NSMPRI_EL1, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5, - .access = PL2_RW, .accessfn = access_esm, + .access = PL2_RW, .accessfn = access_smprimap, .type = ARM_CP_CONST, .resetvalue = 0 }, }; @@ -7792,7 +7817,33 @@ static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { int el = arm_current_el(env); + if (el < 2 && arm_is_el2_enabled(env)) { + uint64_t hcr = arm_hcr_el2_eff(env); + if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { + return CP_ACCESS_TRAP_EL2; + } + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_ATA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} +static CPAccessResult access_tfsr_el2(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + /* + * TFSR_EL2: similar to generic access_mte(), but we need to + * account for FEAT_NV. At EL1 this must be a FEAT_NV access; + * we will trap to EL2 and the HCR/SCR traps do not apply. + */ + int el = arm_current_el(env); + + if (el == 1) { + return CP_ACCESS_OK; + } if (el < 2 && arm_is_el2_enabled(env)) { uint64_t hcr = arm_hcr_el2_eff(env); if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { @@ -7828,7 +7879,7 @@ static const ARMCPRegInfo mte_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, - .access = PL2_RW, .accessfn = access_mte, + .access = PL2_RW, .accessfn = access_tfsr_el2, .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, From patchwork Thu Jan 11 11:04:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A008AC47077 for ; Thu, 11 Jan 2024 11:11:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssY-0001Rz-DP; Thu, 11 Jan 2024 06:05:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssA-0001Mc-5J for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:19 -0500 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss8-0004RB-7H for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:17 -0500 Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2cd5c55d6b8so44181831fa.3 for ; Thu, 11 Jan 2024 03:05:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971114; x=1705575914; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ht2SfbwBAKAnjagPGJMRAPfEfW3fn0agSes/TIkhhrw=; b=HWfkWD4mfsJUYpz6KUZkuVHWtrWVKB9lzW68dUFhWMsjOvtwmf6UZg4iknN7LRZsNL NUtJCFYmq0YZqbYBlTmu11ognZV5JVw+AulQcEZtUQOTOpL1LG72o5k2EyjMrUxUy198 S1KDfdrHFx42up5Ifh72gSGalye7DBlhqJ+Jx/XJHVUhMisLI3EoJBd95nzvfV4QpUXN 3X+4nlJZV3JG+HLkjMKUnHjmyZMbSZBLhN4peZi+JL3CYhx4qMiK2WhGY5PJmnG9hB92 d99cUKzJoD8jBkSvmUd/l/ngXIcY+TWHLxmdTeaCg8kb2B4JTP4jEGDGjdCLsMxbii3Y BMvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971114; x=1705575914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ht2SfbwBAKAnjagPGJMRAPfEfW3fn0agSes/TIkhhrw=; b=ljftqOFM7bFrmnbUFm4pCeDHRhHFTx3hfzzXQLsv42MlEJhbUgc1Nz19a5SyzMjnvX bpnKQLO8L6vdu8ReRO2nLF3MYz6XiIIdZCAW+Bw0/I7g25zpjUGnxwA6V/HGYNRMI25r Et3A56Ypz5+8tnc7XI7FPrKk/Awz8P29/ulG3d4UFtT9w+RzhP47xrde3oTVl3rmg5pO yNr+2HpAwhv5mSHID2LIaA6RNjYJCxZiwg6A8DxmsE5cAi4Qn4ZQ8SKmxEeZZCDvAhOw A8fmrh9dcuC01FgeRoDw910wpru/dQygmsJUe1FQWobaJWdR/cA1Plb7mnKY7gwV6SuL ynPQ== X-Gm-Message-State: AOJu0YzkGuId86u/amd29i9AdGXUcFAs6yTP70Z1eCow7vTv4sA4WiT1 wFT27u73JeNjzarx/cGDzVP0rpINd8BTlr7ctETYIuqD/c4= X-Google-Smtp-Source: AGHT+IHja9/ptcLModQXlPT0+ZYdJ/ZP0AEnzq6buFaH19vyX5RtEavC7/8/OLABGZ+WanvljMkhwA== X-Received: by 2002:a05:651c:317:b0:2cc:72e9:520 with SMTP id a23-20020a05651c031700b002cc72e90520mr189311ljp.44.1704971114574; Thu, 11 Jan 2024 03:05:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/41] target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check Date: Thu, 11 Jan 2024 11:04:42 +0000 Message-Id: <20240111110505.1563291-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In handle_sys() we don't do the check for whether the register is marked as needing an FPU/SVE/SME access check until after we've handled the special cases covered by ARM_CP_SPECIAL_MASK. This is conceptually the wrong way around, because if for example we happen to implement an FPU-access-checked register as ARM_CP_NOP, we should do the access check first. Move the access checks up so they are with all the other access checks, not sandwiched between the special-case read/write handling and the normal-case read/write handling. This doesn't change behaviour at the moment, because we happen not to define any cpregs with both ARM_CPU_{FPU,SVE,SME} and one of the cases dealt with by ARM_CP_SPECIAL_MASK. Moving this code also means we have the correct place to put the FEAT_NV/FEAT_NV2 access handling, which should come after the access checks and before we try to do any read/write action. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/tcg/translate-a64.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0f30e71f9bd..5975fc47930 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2190,6 +2190,14 @@ static void handle_sys(DisasContext *s, bool isread, gen_a64_update_pc(s, 0); } + if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { + return; + } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { + return; + } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) { + return; + } + /* Handle special cases first */ switch (ri->type & ARM_CP_SPECIAL_MASK) { case 0: @@ -2268,13 +2276,6 @@ static void handle_sys(DisasContext *s, bool isread, default: g_assert_not_reached(); } - if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { - return; - } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { - return; - } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) { - return; - } if (ri->type & ARM_CP_IO) { /* I/O operations must end the TB here (whether read or write) */ From patchwork Thu Jan 11 11:04:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E181EC4707B for ; Thu, 11 Jan 2024 11:08:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssU-0001Ri-An; Thu, 11 Jan 2024 06:05:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssB-0001Ms-5V for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:19 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss8-0004RI-Kf for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:18 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-40e490c2115so24158575e9.0 for ; Thu, 11 Jan 2024 03:05:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971115; x=1705575915; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6RsxSjIcUD58WUOvXsMPtdbR5ZpZEnA1hGh8Q+e0BqA=; b=QL+xBxFVlqJr/5OX74AnruaCNI6/RnFHREfzzwQQhhaQVcmmtipG5vjdX16bZnBw8x 8BTFW4PSFcZGBtk+afvRhS6+ktRzjBTLhUOo/zN/f3cvg3rFAZQwZ3YFkeWTos4Oln16 t0kg2zTq6yn/+QY3zUBWNicuy0NARpJoknNBay6c2mSiGAFX3STNMt2hRZ50z6rkSqfN I7dliTONOJ5vJppwtx31lSQ2eGh4fpx9mSGC/4g9AMFmtUnsqFGLk9InUObb9b6SlX9g 93qpbPIq7fgjapB+LHVQ4HGGbv3wnmMY7Bcb8V6k27cm91MzALjnDyVMemRWJVQUxRIw nWbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971115; x=1705575915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6RsxSjIcUD58WUOvXsMPtdbR5ZpZEnA1hGh8Q+e0BqA=; b=AxWkub4UisVF/PtN5Iy9Hpn4qKUuMGJqB6BB/iQ9rtWRdS0jZwgmqAZcg1yLMAnP7S SPZvp4g0OwY7jF4Y5rqSdO4hPyidtpWh0s5hE4oGzJ/fOupWVvU1HHanUSVKOjs89Wik keidghdHL3sRK4v1+nXB4sHv5tb+LUyPGy1mpccuPVaicd+rRKejH+mTVEZ5OXg+6TQq Hkxw8oMHSY6VdZGItQM+HWFeNR9U/J5zE2e06iIMQ6W07CzmjS/9unxg4Eyd+p0p+0gG XHMRSXNT4hKLV9+se9AQ18AhAATjkbp8B3QgB5TbW2y5Eu9JsN9siTGpqsbmkK2Vqrs0 txUQ== X-Gm-Message-State: AOJu0YxWN1yEox30tdy0WnfHmXUNIANx6HMB98XIQ9RDudmSHBz1QT6K xuFgeh00HNr06WXwHcl6+zOZdeXgDGU7bT4h4eSe9HF/SW4= X-Google-Smtp-Source: AGHT+IG79IACIsPFIwnWABakgWy4Tl67Vi06UXHoKQO/RCkYFjK31aIOTHYh5XLayCb9axiGTbkKxQ== X-Received: by 2002:a05:600c:4f12:b0:40d:8850:a988 with SMTP id l18-20020a05600c4f1200b0040d8850a988mr386238wmq.5.1704971114990; Thu, 11 Jan 2024 03:05:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/41] target/arm: Trap sysreg accesses for FEAT_NV Date: Thu, 11 Jan 2024 11:04:43 +0000 Message-Id: <20240111110505.1563291-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For FEAT_NV, accesses to system registers and instructions from EL1 which would normally UNDEF there but which work in EL2 need to instead be trapped to EL2. Detect this both for "we know this will UNDEF at translate time" and "we found this UNDEFs at runtime", and make the affected registers trap to EL2 instead. The Arm ARM defines the set of registers that should trap in terms of their names; for our implementation this would be both awkward and inefficent as a test, so we instead trap based on the opc1 field of the sysreg. The regularity of the architectural choice of encodings for sysregs means that in practice this captures exactly the correct set of registers. Regardless of how we try to define the registers this trapping applies to, there's going to be a certain possibility of breakage if new architectural features introduce new registers that don't follow the current rules (FEAT_MEC is one example already visible in the released sysreg XML, though not yet in the Arm ARM). This approach seems to me to be straightforward and likely to require a minimum of manual overrides. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpregs.h | 34 +++++++++++++++++++++++ target/arm/cpu.h | 1 + target/arm/tcg/translate.h | 2 ++ target/arm/tcg/hflags.c | 1 + target/arm/tcg/translate-a64.c | 49 +++++++++++++++++++++++++++------- 5 files changed, 77 insertions(+), 10 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index e748d184cb6..3c5f1b48879 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1080,4 +1080,38 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); +/** + * arm_cpreg_trap_in_nv: Return true if cpreg traps in nested virtualization + * + * Return true if this cpreg is one which should be trapped to EL2 if + * it is executed at EL1 when nested virtualization is enabled via HCR_EL2.NV. + */ +static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri) +{ + /* + * The Arm ARM defines the registers to be trapped in terms of + * their names (I_TZTZL). However the underlying principle is "if + * it would UNDEF at EL1 but work at EL2 then it should trap", and + * the way the encoding of sysregs and system instructions is done + * means that the right set of registers is exactly those where + * the opc1 field is 4 or 5. (You can see this also in the assert + * we do that the opc1 field and the permissions mask line up in + * define_one_arm_cp_reg_with_opaque().) + * Checking the opc1 field is easier for us and avoids the problem + * that we do not consistently use the right architectural names + * for all sysregs, since we treat the name field as largely for debug. + * + * However we do this check, it is going to be at least potentially + * fragile to future new sysregs, but this seems the least likely + * to break. + * + * In particular, note that the released sysreg XML defines that + * the FEAT_MEC sysregs and instructions do not follow this FEAT_NV + * trapping rule, so we will need to add an ARM_CP_* flag to indicate + * "register does not trap on NV" to handle those if/when we implement + * FEAT_MEC. + */ + return ri->opc1 == 4 || ri->opc1 == 5; +} + #endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6dd0f642581..d7a10fb4b61 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3235,6 +3235,7 @@ FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) FIELD(TBFLAG_A64, NAA, 30, 1) FIELD(TBFLAG_A64, ATA0, 31, 1) +FIELD(TBFLAG_A64, NV, 32, 1) /* * Helpers for using the above. Note that only the A64 accessors use diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 8c84377003c..63e075bce3a 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -144,6 +144,8 @@ typedef struct DisasContext { bool trap_eret; /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ bool naa; + /* True if FEAT_NV HCR_EL2.NV is enabled */ + bool nv; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 560fb7964ab..f33c0a12741 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -299,6 +299,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, */ if (el == 1 && (hcr & HCR_NV)) { DP_TBFLAG_A64(flags, TRAP_ERET, 1); + DP_TBFLAG_A64(flags, NV, 1); } if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5975fc47930..f5377dbaf2d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2132,16 +2132,17 @@ static void handle_sys(DisasContext *s, bool isread, crn, crm, op0, op1, op2); const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key); bool need_exit_tb = false; + bool nv_trap_to_el2 = false; + bool skip_fp_access_checks = false; TCGv_ptr tcg_ri = NULL; TCGv_i64 tcg_rt; - uint32_t syndrome; + uint32_t syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); if (crn == 11 || crn == 15) { /* * Check for TIDCP trap, which must take precedence over * the UNDEF for "no such register" etc. */ - syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); switch (s->current_el) { case 0: if (dc_isar_feature(aa64_tidcp1, s)) { @@ -2167,15 +2168,35 @@ static void handle_sys(DisasContext *s, bool isread, /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { - gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt); - return; + /* + * FEAT_NV/NV2 handling does not do the usual FP access checks + * for registers only accessible at EL2 (though it *does* do them + * for registers accessible at EL1). + */ + skip_fp_access_checks = true; + if (s->nv && arm_cpreg_traps_in_nv(ri)) { + /* + * This register / instruction exists and is an EL2 register, so + * we must trap to EL2 if accessed in nested virtualization EL1 + * instead of UNDEFing. We'll do that after the usual access checks. + * (This makes a difference only for a couple of registers like + * VSTTBR_EL2 where the "UNDEF if NonSecure" should take priority + * over the trap-to-EL2. Most trapped-by-FEAT_NV registers have + * an accessfn which does nothing when called from EL1, because + * the trap-to-EL3 controls which would apply to that register + * at EL2 don't take priority over the FEAT_NV trap-to-EL2.) + */ + nv_trap_to_el2 = true; + } else { + gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt); + return; + } } if (ri->accessfn || (ri->fgt && s->fgt_active)) { /* Emit code to perform further access permissions checks at * runtime; this may result in an exception. */ - syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); gen_a64_update_pc(s, 0); tcg_ri = tcg_temp_new_ptr(); gen_helper_access_check_cp_reg(tcg_ri, tcg_env, @@ -2190,11 +2211,18 @@ static void handle_sys(DisasContext *s, bool isread, gen_a64_update_pc(s, 0); } - if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { - return; - } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { - return; - } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) { + if (!skip_fp_access_checks) { + if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { + return; + } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { + return; + } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) { + return; + } + } + + if (nv_trap_to_el2) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); return; } @@ -13998,6 +14026,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING); dc->naa = EX_TBFLAG_A64(tb_flags, NAA); + dc->nv = EX_TBFLAG_A64(tb_flags, NV); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Thu Jan 11 11:04:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7C80C47077 for ; Thu, 11 Jan 2024 11:10:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssl-0001j4-8h; Thu, 11 Jan 2024 06:05:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssB-0001Mr-51 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:19 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss8-0004RV-Nh for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:18 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-33678156e27so4461010f8f.1 for ; Thu, 11 Jan 2024 03:05:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971115; x=1705575915; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7DGlJd8zO7MQUcG5o1SU1odAfTI4o+ayPUZ+8rGfmO8=; b=q6f5r0sXYkCzmf3EvFlix7bfhI7CA5YpuM+73fI6MmhRBm2wmNm3gUHvFiU7TGdLaD pvxv5dxZYdGe++I8GuZ4Egx/k1Cx+cfbnc3VFJLU/FEB9Q14so8kIRK/ThXlCmy1bCLF zunMQtd8/lsU+LGYlh22AnkEBx/SR5uB3PIJdsfeY1q+fDUrHe3A7sRkKOOpQilwRkdl GhyITkDYhoBaovnCz124Gh8Dy+MFDqIXaA5w/c76n5LCbu/vwkiubRQ9lsi2wT+bo1+M P1XhdFOBj/ueliNQwG3KH+ZNEqmeOr84YXXfYP0IR3k5JGvWynlrokOaU6SPWxgOBo9B ruZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971115; x=1705575915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7DGlJd8zO7MQUcG5o1SU1odAfTI4o+ayPUZ+8rGfmO8=; b=pjH6s8WylfcqedzFu0WrTI6wHl8tgX47kWcntzys5lgzU1VbdfKSnn+pzqAvJb0XiT N7eEOFnkOmRAjZnh7SsWvvi2FrI9gPr5sE7mkWEW8AwPFKYPNns/dtMIKB13YCzEM+i3 wWgmAHKvglOzIrXItZNVoar+l2s79XMGGw/7QLSlMzK0MmN90NeHf+M4Ng7G5KIZbLhR lCsETCaAgLo9UWDw6mecAy7ohii1Sz8O+IwQOorMcvbwSAaCDozkJ/Y8MQhycdaxkQR1 Lz/2JzhRZTQaR0OmFQ9eKjBUmSwh6Opqvt83gQwD2MydMHDzpBVYqxhJqMVe9CPvARtm D0sQ== X-Gm-Message-State: AOJu0Yw4OdR98r4Db9sV8c0498rDBQZGPCDhEQG8BeFN0q+Qu6L7uEKe ViAo13a+IhfeCExtzrj059G3A0y7351sDHUZ+W9Hk5XGSq8= X-Google-Smtp-Source: AGHT+IFIPjQTHTYdINqO6e7MjuR2/6ZLOGs12aUtLM2Re26Rpzlutp+uIO3nUcZQYG6eD8EavH79UA== X-Received: by 2002:a5d:6091:0:b0:336:70ed:4cc with SMTP id w17-20020a5d6091000000b0033670ed04ccmr567863wrt.95.1704971115391; Thu, 11 Jan 2024 03:05:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/41] target/arm: Make NV reads of CurrentEL return EL2 Date: Thu, 11 Jan 2024 11:04:44 +0000 Message-Id: <20240111110505.1563291-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org FEAT_NV requires that when HCR_EL2.NV is set reads of the CurrentEL register from EL1 always report EL2 rather than the real EL. Implement this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/tcg/translate-a64.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f5377dbaf2d..ed1cc019a4c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2241,12 +2241,17 @@ static void handle_sys(DisasContext *s, bool isread, } return; case ARM_CP_CURRENTEL: - /* Reads as current EL value from pstate, which is + { + /* + * Reads as current EL value from pstate, which is * guaranteed to be constant by the tb flags. + * For nested virt we should report EL2. */ + int el = s->nv ? 2 : s->current_el; tcg_rt = cpu_reg(s, rt); - tcg_gen_movi_i64(tcg_rt, s->current_el << 2); + tcg_gen_movi_i64(tcg_rt, el << 2); return; + } case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. */ if (s->mte_active[0]) { From patchwork Thu Jan 11 11:04:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3A97C4707B for ; Thu, 11 Jan 2024 11:09:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssk-0001ha-HO; Thu, 11 Jan 2024 06:05:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssB-0001Mt-BL for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:19 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss9-0004Ro-28 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:19 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-337874b8164so359078f8f.2 for ; Thu, 11 Jan 2024 03:05:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971116; x=1705575916; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JW8YIe50LT4PZiM8mDHqQtLIGx6RzO+LKTb370XSXVc=; b=OhRz9XnMtL5LtnZ/EvexsRcx6g632WblfUwxHRXkDMdQ01bZSznU5dS3mjEKu1BmiZ xokdVl4cICVxSdtTq9IaGFL8wkU0UfZfjEkl2T0VcN+Rdq2B5rBIQAVObrBTFntChpak mjoUGcS4nUi6yF6Q34vJV2083YVITyDutytOg1v9iPbAtxJp7UwvKhoQgzjKHaVH4LeA /I75L9bWznEH8ugckVObt9aFOzFIoVtpbiOjM3fAEPw28NfTCmEyR8YvljVCQo5yBhqz rU/0BHaBMmzjJmgJC2uksCh96wAoyC9UeTpIocevA7CvciqAEq2gZkq3ciFRpl+buzn8 OYow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971116; x=1705575916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JW8YIe50LT4PZiM8mDHqQtLIGx6RzO+LKTb370XSXVc=; b=sNJXDPxJHF7MGN0Hh74BSlBTpV3KZDK8KCUcs6rfMhUFofPgpiQKZdFxPUbsGawARZ dXhBfxYb35RUz1u8HCadAP+vVnt6uqFsCX8MPfPRIi/byCyHhq+RD/g+Bng8NxtYKmQK C7JC5ftVCywBBydWqfImYOJnjrdgsIMEX/rMh+2DHpkvVUCmtkYx3FoH/gLzNNFlRgNs hDorDhPhpPnKNUZTo1Eca09x8dlaK5ZLfxRRSclCRlgMf6ZO/AQGGciG9GFh+OKzNHbS hnJ56sL1Vxjms3kHrWROOBZZrwvVUzYBN+3hZ2KaolgzUTSJoSPu1HG+ipmPStFWactF JWzw== X-Gm-Message-State: AOJu0YzyCRhw033As6K9d+3bEpMWxAKBfSC/y49N5Firyx6uomeVskd1 W2luM6kc5gZGIsd0uankMV9RLZVq60RA0yhWEVG5KcxhYQ0= X-Google-Smtp-Source: AGHT+IFe4Uzeb3za8wxAvmRvBBt47ndGNkeHEDvETTGYDlajp/HZzE3/sxpEH6B8Mj7ECVcEwT9daQ== X-Received: by 2002:adf:e812:0:b0:337:2e5d:4ac9 with SMTP id o18-20020adfe812000000b003372e5d4ac9mr534530wrm.81.1704971115813; Thu, 11 Jan 2024 03:05:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/41] target/arm: Set SPSR_EL1.M correctly when nested virt is enabled Date: Thu, 11 Jan 2024 11:04:45 +0000 Message-Id: <20240111110505.1563291-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,0} and an exception is taken from EL1 to EL1 then the reported EL in SPSR_EL1.M should be EL2, not EL1. Implement this behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7c7f92c16de..e48b03ba1d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11249,6 +11249,12 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) old_mode = pstate_read(env); aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] = env->pc; + + if (cur_el == 1 && new_el == 1 && + ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == HCR_NV)) { + /* I_ZJRNN: report EL2 in the SPSR by setting M[3:2] to 0b10 */ + old_mode = deposit32(old_mode, 2, 2, 2); + } } else { old_mode = cpsr_read_for_spsr_elx(env); env->elr_el[new_el] = env->regs[15]; From patchwork Thu Jan 11 11:04:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D40CCC47077 for ; Thu, 11 Jan 2024 11:13:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssZ-0001S0-T0; Thu, 11 Jan 2024 06:05:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssC-0001Ny-9p for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:25 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss9-0004Rz-Sf for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:20 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40e5f615a32so4439355e9.1 for ; Thu, 11 Jan 2024 03:05:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971116; x=1705575916; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Hav1ye9+RT9H+505sGqV2d7rdaD4VVDbqLiiWOv4ZlA=; b=GCP0+sbLxysF6xQs8XHY8LwKIx+C0dCVuQ/7qKd1wWuZuhqGz0gNLNrCGaUVIcwbXD 5aTSczvYLyHvGYGfGD1fsEOz0Q80VPEqZNLX1RW6qwopIgLewxFSbILyVRsKrJ1nC0Fs FBcY6+rP/+JNGGO6OtnJc0WA05Xx/jjINUuEiKLzOsBzK2xRvozO+D0OHPlrA9bmFb8D /UzNh4XeiRz3+IPSNzD6Y0h/Tu5qCRLLTXklzCZv8vA6lnSJnuax4twD21LddIRIz3i1 9p3R36zRTZStA/TE6hRi0pgVO/cKBWLwpQQqZ4mi4J/P5633QXpfMqP6SXx+5RPTuup9 46bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971116; x=1705575916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hav1ye9+RT9H+505sGqV2d7rdaD4VVDbqLiiWOv4ZlA=; b=sbtCkQ9S0GvDgLwOkJn0ftDbcEJ0VpvHhB3kEhbyI7rRgJiTx4H3uwqSNwVzfsao0C RBus1PLtaI+B7l/Do+vNUnoLzZ0/AsoETJ4Sb3m8yeDKnf9AYgm/JyR8FfcTVK8FzsdH H76T9yKnB0y4JchrO8YOCnTRCPMvhSj/Z7kT96aM1mRIJhrMmZsYTUQenyRXG7frxhzg PpgEs22bm6r/vj09Ih0mOYKYKY98wPYFXEKgqGzopFphcs5PelKy3zw6VBDRZtl4CNW/ Qgps62FqtpYAv5ylt5sj17Eg35Zt1WOHf+0D9w3VdWxmtPXEgw9EJmsgVEM+mG9aAZkr FCRw== X-Gm-Message-State: AOJu0YyG9smpha+NaBRVjVGeg3dmnQGk7ER8FX9Touv8c5fTfNY7xgKa 4ihjGIss83v571Q4hRxrnQYifbuWSI0LZNabYa6ewLPWDwE= X-Google-Smtp-Source: AGHT+IE0+vgsmyub1t2Xoiq11SmEUmFBVTMDzQfP2L0sUZV0N2lkm1auGMWiCkDDcTPHKg8ZhGkEuA== X-Received: by 2002:a05:600c:a082:b0:40e:5f54:816a with SMTP id jh2-20020a05600ca08200b0040e5f54816amr166206wmb.16.1704971116194; Thu, 11 Jan 2024 03:05:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/41] target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1} Date: Thu, 11 Jan 2024 11:04:46 +0000 Message-Id: <20240111110505.1563291-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When HCR_EL2.{NV,NV1} is {1,1} we must trap five extra registers to EL2: VBAR_EL1, ELR_EL1, SPSR_EL1, SCXTNUM_EL1 and TFSR_EL1. Implement these traps. This trap does not apply when FEAT_NV2 is implemented and enabled; include the check that HCR_EL2.NV2 is 0 here, to save us having to come back and add it later. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 45 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e48b03ba1d0..c8296a9c191 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5355,6 +5355,19 @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +static CPAccessResult access_nv1(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1) { + uint64_t hcr_nv = arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1 | HCR_NV2); + + if (hcr_nv == (HCR_NV | HCR_NV1)) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + #ifdef CONFIG_USER_ONLY /* * `IC IVAU` is handled to improve compatibility with JITs that dual-map their @@ -5703,12 +5716,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, - .access = PL1_RW, + .access = PL1_RW, .accessfn = access_nv1, .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, - .access = PL1_RW, + .access = PL1_RW, .accessfn = access_nv1, .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, /* * We rely on the access checks not allowing the guest to write to the @@ -7831,6 +7844,17 @@ static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static CPAccessResult access_tfsr_el1(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + CPAccessResult nv1 = access_nv1(env, ri, isread); + + if (nv1 != CP_ACCESS_OK) { + return nv1; + } + return access_mte(env, ri, isread); +} + static CPAccessResult access_tfsr_el2(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -7875,7 +7899,7 @@ static const ARMCPRegInfo mte_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, - .access = PL1_RW, .accessfn = access_mte, + .access = PL1_RW, .accessfn = access_tfsr_el1, .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, @@ -8027,6 +8051,18 @@ static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static CPAccessResult access_scxtnum_el1(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + CPAccessResult nv1 = access_nv1(env, ri, isread); + + if (nv1 != CP_ACCESS_OK) { + return nv1; + } + return access_scxtnum(env, ri, isread); +} + static const ARMCPRegInfo scxtnum_reginfo[] = { { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, @@ -8035,7 +8071,7 @@ static const ARMCPRegInfo scxtnum_reginfo[] = { .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, - .access = PL1_RW, .accessfn = access_scxtnum, + .access = PL1_RW, .accessfn = access_scxtnum_el1, .fgt = FGT_SCXTNUM_EL1, .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, @@ -9417,6 +9453,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write, + .accessfn = access_nv1, .fgt = FGT_VBAR_EL1, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, From patchwork Thu Jan 11 11:04:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64BAEC4707B for ; Thu, 11 Jan 2024 11:06:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssm-0001je-E1; Thu, 11 Jan 2024 06:05:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssD-0001O5-I7 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:25 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssA-0004T1-Vp for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:21 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3368abe1093so4130651f8f.2 for ; Thu, 11 Jan 2024 03:05:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971116; x=1705575916; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LwWUwjczvpD7+ZI2C4YQSC3wj+TJRP3iZxPLtk74qzM=; b=cCHT2MY7W/xubnO9TL6BFAHPQgP3d4TQqL5/LBKaOqUcPagUCVvTefBDzELSfQkcRm HVyTD8lm7/9Kqhx/zcyKpii/VjCS5Hdp1NstxyM4Fsnpa/6z++b/fzfvNQsXr1oktig8 OchVVT6U+dO0ACVdH3uzUAfpbwNR3Ah4mF4qwXQJ+Rqq3TzrmTbV0R5b9DmGQF6zK/I1 yaKe9wabhmJnZnlh/Ii4wOzIgwH4Bghen/Ds4Kgk67KEPd0lSy0JGmuWE6OMAqybddv2 wsA1iJor2Gw6zluvxBtBnXHrrAVfeUXXWk9BwZOfe12X6loKVURiP+NK1Srl54sytSwP 6c/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971116; x=1705575916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LwWUwjczvpD7+ZI2C4YQSC3wj+TJRP3iZxPLtk74qzM=; b=uksNk8Obsz/h2XqFQ2AMcrlRfSZP0/WBhuN7YR38idx9v2kcITaOwRRHFXStXa6Da3 3GIyNJeefre7Qd7lZsbb6egJq9KCh/ZfyOLUMbG/cdPLbjfncgn17gWkuTdZDCx3ZL5Q rxa8NVAyYoEneMQ35iTeqy4v806/umbCwkGR6AOqZrZhh8U+OVv3ZvmfqeaH7vzn8kde cZoqGf+em6+Me8OasMsYjxW3S9chudhRKOz1rIU/hOuApLeEi4NbnO0sA3XvasfLAnBt ju8T5ISyvVxndjR+WX3B2L5fIluhloqYuRuJFzF6tmpSbnvLiH7n7ns/06uEW0/qSZiJ b9XA== X-Gm-Message-State: AOJu0YzVEyRGfVXbyVLkbh2QvMhAKTAc5ZAzGx03RtoayTMsALMjyVPm XliXI1Es09He5QGBWvtXezQbwzqjBH5+Ps46x5PPydeyn0g= X-Google-Smtp-Source: AGHT+IFAic/FXrM4cE189FTlZNAIUWtMLxvJ/+hN+q/KtbithMLjwSSp+wH0Kr6Hy/QaplimjasoqA== X-Received: by 2002:adf:eb0d:0:b0:337:7c78:a4d5 with SMTP id s13-20020adfeb0d000000b003377c78a4d5mr461125wrn.73.1704971116636; Thu, 11 Jan 2024 03:05:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/41] target/arm: Always use arm_pan_enabled() when checking if PAN is enabled Date: Thu, 11 Jan 2024 11:04:47 +0000 Message-Id: <20240111110505.1563291-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently the code in target/arm/helper.c mostly checks the PAN bits in env->pstate or env->uncached_cpsr directly when it wants to know if PAN is enabled, because in most callsites we know whether we are in AArch64 or AArch32. We do have an arm_pan_enabled() function, but we only use it in a few places where the code might run in either an AArch32 or AArch64 context. For FEAT_NV, when HCR_EL2.{NV,NV1} is {1,1} PAN is always disabled even when the PSTATE.PAN bit is set, the "is PAN enabled" test becomes more complicated. Make all places that check for PAN use arm_pan_enabled(), so we have a place to put the FEAT_NV test. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c8296a9c191..1db2effb1c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -263,6 +263,15 @@ void init_cpreg_list(ARMCPU *cpu) g_list_free(keys); } +static bool arm_pan_enabled(CPUARMState *env) +{ + if (is_a64(env)) { + return env->pstate & PSTATE_PAN; + } else { + return env->uncached_cpsr & CPSR_PAN; + } +} + /* * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. */ @@ -3614,7 +3623,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ /* fall through */ case 1: - if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { + if (ri->crm == 9 && arm_pan_enabled(env)) { mmu_idx = ARMMMUIdx_Stage1_E1_PAN; } else { mmu_idx = ARMMMUIdx_Stage1_E1; @@ -3730,7 +3739,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ - if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { + if (ri->crm == 9 && arm_pan_enabled(env)) { mmu_idx = regime_e20 ? ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN; } else { @@ -12145,15 +12154,6 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) } #endif -static bool arm_pan_enabled(CPUARMState *env) -{ - if (is_a64(env)) { - return env->pstate & PSTATE_PAN; - } else { - return env->uncached_cpsr & CPSR_PAN; - } -} - ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { ARMMMUIdx idx; From patchwork Thu Jan 11 11:04:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFC66C47077 for ; Thu, 11 Jan 2024 11:08:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNsse-0001Yz-85; Thu, 11 Jan 2024 06:05:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssC-0001Nz-IS for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:25 -0500 Received: from mail-lj1-x22e.google.com ([2a00:1450:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssA-0004Sa-TJ for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:20 -0500 Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2cd7e429429so17883681fa.1 for ; Thu, 11 Jan 2024 03:05:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971117; x=1705575917; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=n1Q0rBlTI4KTEcEVYGkY0PBLOWaSrPIhGDZkzdWHU84=; b=lGTuMJfgedwizsAFf6wAW82Yt2d1uEa/UIBcP47QGKDH2esH1CwvE2zJ8o90tav3gL HpP0/v8Q5m3pnOHGw9aiSrAq9hR5DOCzBrUfSX9FeHrM278fwV+bMnKyn7RZTG4cHkrT Bs2UZpFNBEiMm/yHTMuG0map5xjwx9i1znQjpZ+mkA0VD6LH6VRnHMRtPh9OcZGtWN62 fT5VrnJgEF/16ioXOy2C2CmA9Sso6MMtBTHAoARJOICvWiC5xlWlvYT4FTYW+ipwlIi0 Qtm2VP1eWwN4/sOB/Pocb8nH8YOtLcR0rl4u33qT+NUtEa7rQLaJyEvyoi8Lfq7G/ZuX 9uGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971117; x=1705575917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n1Q0rBlTI4KTEcEVYGkY0PBLOWaSrPIhGDZkzdWHU84=; b=uCAiiyrzqF1oViQVFFlkXEd0GMExcIq8+gNQMkphf7BWqwtPkq+4q8l3ON/kyylJ56 7mLsLHIy2ehigDwwH13LcqjmmWVt5yQ7ZSo+TMRk3BtAskh5i0xB68nUOZ/tWGLi/tk4 Sh+cu85Ewwe4qSu1h9zkoJFJhE8evAYbFBznvweI9rHBu5jhdcLppbbhrV8Ja/LxXeyW ZikhEP7la+sEC04oQGc+m+msALbsOrVZkKllzmE5OelE1mFrPU/x/71ZoBSCDiT/egST CpkMoT8tlVBPxMtcpb57WQvA7xkh3tIOkjSVFPCRyYNZx+kQMrlXXoYXqO4tcW/cBf8T aKxg== X-Gm-Message-State: AOJu0Yz2uwwWqiNwaAZuo8ptsqsx1rpLULeJ7/knuqZWkZFK4sN49BnQ b3jduhC97F2JKKfWgaa9Juf+Lv9AE2wkshgQg+4T+IWjoCA= X-Google-Smtp-Source: AGHT+IGaSk503QUAVyOioAqDSIHXTGcB56JV7T6CjrHCkwoiiTZ2cKnSg4Cddt3leb0a3v/lHDAw3A== X-Received: by 2002:a2e:7a01:0:b0:2cc:2025:5bd5 with SMTP id v1-20020a2e7a01000000b002cc20255bd5mr290988ljc.51.1704971117059; Thu, 11 Jan 2024 03:05:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} Date: Thu, 11 Jan 2024 11:04:48 +0000 Message-Id: <20240111110505.1563291-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For FEAT_NV, when HCR_EL2.{NV,NV1} is {1,1} PAN is always disabled even when the PSTATE.PAN bit is set. Implement this by having arm_pan_enabled() return false in this situation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1db2effb1c0..24751e05b24 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -266,6 +266,9 @@ void init_cpreg_list(ARMCPU *cpu) static bool arm_pan_enabled(CPUARMState *env) { if (is_a64(env)) { + if ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == (HCR_NV | HCR_NV1)) { + return false; + } return env->pstate & PSTATE_PAN; } else { return env->uncached_cpsr & CPSR_PAN; From patchwork Thu Jan 11 11:04:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB035C4707B for ; Thu, 11 Jan 2024 11:07:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssd-0001XM-IO; Thu, 11 Jan 2024 06:05:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssD-0001O6-Ie for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:25 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssB-0004Sr-2h for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:21 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3368ac0f74dso3616502f8f.0 for ; Thu, 11 Jan 2024 03:05:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971117; x=1705575917; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=RirnEYNLfsDFzm/H0oZcf/uGTEF4gj6EIg0qZ7yOeDg=; b=wmOOKML4EKvI6SoJI+290LPINBJxxvUviBupFM2QAEGXMtHjP3qV7Iturtgqu5Z0SW 3uXxN02FEMmRC81xL49y3gjnGoSqlTbqpTlIc4ZE1tmKI1C83ezVxvCGCg5AA8SbQfB1 Q6bR4DMRZ6WCyqX1vFd3/i0267pZYrkR1eCWl5DgrPXbDycwQbRJls6q1XHlZOkvxceT 02AO0duwULwAndlgFNfMr8QhEdDjAfoM9qnBTjOAkqN4uvWN9HYykoBbLNj0vTLHcfVq +0Sb/Y5UpNC4C/gHIW0DeY3LvlA+4MTOCNzpTiAPrpWXZRlZjByESxO3q0hu4jDYmWaY FPkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971117; x=1705575917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RirnEYNLfsDFzm/H0oZcf/uGTEF4gj6EIg0qZ7yOeDg=; b=gtHhaSv7erIqCGdAzqLhusOo2qgnTEsawT3PHfZjqknF/EcPylPvcAchAqgvYxa2nx wq8uU37Fsbb4IQGIp9ScXq3T2ojSkwKRK0R1ZZaBe+ZZ4innxzoBHtqwDl6UREGDcos0 S41BmYCCpkg92feEedP818xoeW1oY4LMzl35futi2dK0+C04CRliqz4MYXLdWl396C4a gngBD6SWplZcB+Cap38Jf6yNK924WOu1R6ErN7NGhkK0AUM+FyBqDwExuVhwVCu6wKMQ xJCzPHnrxznN0T1slESV8BvmXoOvgKwYRbZVt539Dk5pHbZf/PtvXJd6ELWl8X+OB3WZ sqmQ== X-Gm-Message-State: AOJu0YzZi4JdrMR9rPUdp5ekaDnV4aBuCE/Arn+BghLDShEB1ajry06/ 5P3IuoGjRwqmXood6QPhcK0RGaOAga+M+l4YANnqSJgUw6g= X-Google-Smtp-Source: AGHT+IFvcvPdtweL1XeIIZv0YtYd0aCMWwX3ZCCOf3zOfZWDl77UKAYLGlzmwYqAA23WHkX2+zqwlg== X-Received: by 2002:adf:a4d0:0:b0:336:7e39:a9c7 with SMTP id h16-20020adfa4d0000000b003367e39a9c7mr514116wrb.141.1704971117470; Thu, 11 Jan 2024 03:05:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/41] target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1 Date: Thu, 11 Jan 2024 11:04:49 +0000 Message-Id: <20240111110505.1563291-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org FEAT_NV requires (per I_JKLJK) that when HCR_EL2.{NV,NV1} is {1,1} the unprivileged-access instructions LDTR, STTR etc behave as normal loads and stores. Implement the check that handles this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/tcg/hflags.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index f33c0a12741..8f254bf9ccb 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -261,8 +261,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, switch (mmu_idx) { case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - /* TODO: ARMv8.3-NV */ - DP_TBFLAG_A64(flags, UNPRIV, 1); + /* FEAT_NV: NV,NV1 == 1,1 means we don't do UNPRIV accesses */ + if ((hcr & (HCR_NV | HCR_NV1)) != (HCR_NV | HCR_NV1)) { + DP_TBFLAG_A64(flags, UNPRIV, 1); + } break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: From patchwork Thu Jan 11 11:04:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3372C47077 for ; Thu, 11 Jan 2024 11:06:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssf-0001bC-Uj; Thu, 11 Jan 2024 06:05:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssE-0001OA-3V for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:25 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssB-0004TD-Pm for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:21 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-33761e291c1so3051028f8f.0 for ; Thu, 11 Jan 2024 03:05:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971118; x=1705575918; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eJ2Bh2KqWHFGhwYEJgAtL+OLtHKA2aP7b6zI0XswIFc=; b=DsriuO8dhxbadttNkhkihV2kjaBlI3gnEnhwUomciI134r7uChbnBLUNNc68RLOS+3 zneqOPRRXVcq3TdLNU909eer9zZGsDKIRdJPtG9cEUsKuhcfVV05z3z4CErJWWMXyCxR 5+st7BqwluPO48wyyei9RoA2VGqfAGMwoUs03H9b2BCkjQ0fa9UYZ79TTQDWpQLSIjcp iDJ1AmU9c8wlMmCFM46vyUQc/p3b3RsKbeeyCAZImdpuO3kpGJcJe1hmNN6HCr8IV/uI t0L0klLWk/PjYSrEV16bQUpOj4opeH1Uz4e/uhoV77mQDa20xuMyjVHb+ks75w1l9B/I gbzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971118; x=1705575918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eJ2Bh2KqWHFGhwYEJgAtL+OLtHKA2aP7b6zI0XswIFc=; b=KkB3ZdZ6gVEOoXw2lRIDRvlOOpA7GnsXpEPglpmEWF4in9RcYfJ96XMhg7//No+rk+ TkB3OlOKFqwy566Qiguu2v/0L8FEGB3kKDZKW7fkWWjUWuS8cxBbmVOVyll50/NHxuFI QZ2ClwkGpF94FtxSdKaJ1EfFkQkXnsOGj+daqxd8A0n5/kI98fMVrh7cq/kCIlnHJZqS GRgfTmcJpXHre6R/hI0UPc3DVqzLYxvzFk6BbOPk5fBXlElpCAv/XfLREwIF85tr2F0r eHGaCTyD/QeUwr/0YJ9fbsqRiYktYvFIOvSrnv4YZ9OEWABbVKrRezxCP8zX5x1nb7o/ 7oRw== X-Gm-Message-State: AOJu0Yxe/7/jBPPmg14+e2CYFjknQPEoy7F1svfAsL2tqFFptaGFVdWD zq7sNtD3YpL8maRq/32qdT1Vf4SJ0KbYr4eupLVc4LuEYpQ= X-Google-Smtp-Source: AGHT+IGxFtRsWhV4yNdjp6bYNE+WmJYPJReM9C8o5SvFBJtCtY8oI+fxc92AAwPjDcyIRR8DOcGRIg== X-Received: by 2002:a05:600c:520d:b0:40e:622f:ebf with SMTP id fb13-20020a05600c520d00b0040e622f0ebfmr128544wmb.178.1704971118097; Thu, 11 Jan 2024 03:05:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/41] target/arm: Handle FEAT_NV page table attribute changes Date: Thu, 11 Jan 2024 11:04:50 +0000 Message-Id: <20240111110505.1563291-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,1} the handling of some of the page table attribute bits changes for the EL1&0 translation regime: * for block and page descriptors: - bit [54] holds PXN, not UXN - bit [53] is RES0, and the effective value of UXN is 0 - bit [6], AP[1], is treated as 0 * for table descriptors, when hierarchical permissions are enabled: - bit [60] holds PXNTable, not UXNTable - bit [59] is RES0 - bit [61], APTable[0] is treated as 0 Implement these changes to the page table attribute handling. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/ptw.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0ecd3a36dad..2d4fa8dbcaf 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1581,6 +1581,12 @@ static bool lpae_block_desc_valid(ARMCPU *cpu, bool ds, } } +static bool nv_nv1_enabled(CPUARMState *env, S1Translate *ptw) +{ + uint64_t hcr = arm_hcr_el2_eff_secstate(env, ptw->in_space); + return (hcr & (HCR_NV | HCR_NV1)) == (HCR_NV | HCR_NV1); +} + /** * get_phys_addr_lpae: perform one stage of page table walk, LPAE format * @@ -1989,6 +1995,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, xn = extract64(attrs, 54, 1); pxn = extract64(attrs, 53, 1); + if (el == 1 && nv_nv1_enabled(env, ptw)) { + /* + * With FEAT_NV, when HCR_EL2.{NV,NV1} == {1,1}, the block/page + * descriptor bit 54 holds PXN, 53 is RES0, and the effective value + * of UXN is 0. Similarly for bits 59 and 60 in table descriptors + * (which we have already folded into bits 53 and 54 of attrs). + * AP[1] (descriptor bit 6, our ap bit 0) is treated as 0. + * Similarly, APTable[0] from the table descriptor is treated as 0; + * we already folded this into AP[1] and squashing that to 0 does + * the right thing. + */ + pxn = xn; + xn = 0; + ap &= ~1; + } /* * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security space. From patchwork Thu Jan 11 11:04:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7FD6C47077 for ; Thu, 11 Jan 2024 11:07:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssV-0001Rk-Fl; Thu, 11 Jan 2024 06:05:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssE-0001OB-EX for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:25 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssC-0004Tf-2J for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:21 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-33748c4f33dso5005904f8f.1 for ; Thu, 11 Jan 2024 03:05:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971118; x=1705575918; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aNZhB04G9aaU3Fn26zvvYto3KEIbf3D7ndy2bXnEsD0=; b=qEIODOWJ5IZ1QXSeyYogtsKTsAJwVaTBlwyCabH5jzRSb873qVMJ5cMlh64HPVBOil 9Ik/Vv3VACXkMgu5WbnHgq5z82EmWQ+//Hf0EDfJ6h73Wog7Lh0uMG8gE71wrUFrSsfA ME9UjoOVL/T1QxplreSPdaUQ7HbKlPEqjlm2KLcNQA3+XyvOmx0UoppdLUFd3Jd847uD T8o16UqwoHw5jvmFiJpdB/p1J9roWveLoYztsAgb8C6AwYL6K6U+DIhW01e8tvbdUJ1s TeKxcCFPG8ZK/sTj+GqOGODv5E0dhKr9qes/LoYBOQeIuglPdlUFFEAL1G+X0u1jND8R 3sfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971118; x=1705575918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aNZhB04G9aaU3Fn26zvvYto3KEIbf3D7ndy2bXnEsD0=; b=XUL+rOO8WezrAe4ESHpwKCyxVBvhOboGbq/QOIMENq6LVbqA0hyoGD//sfniuDbStQ 6r8OMhAJdpWrTt9C2JIKAIH8gJ7EBXzmwovFMHGuG1cvvTZ9PmWZeCgNx4Xl7bULEtax AYA8CsCBtvyEL45vj2iRH+B8j11hiuSOD8PcMUBlWjQUH71kNOfnRv6gfEKoqUN8UVbP vPdXEfS7LvC7wX0jOzUi4ArXMqUtrPafuthOIE9+rXC9a2+mW2gQ5DJ3ppLPTYKU/YyB EnY6vo25GLxMqd8jVy56Iyvt1oIhHk/2M1J89G2TMCp8rZiNsSnN2KhMqhEZa7c/uceo 5iuQ== X-Gm-Message-State: AOJu0YwpMqqGIWS15gPZ1kY55U0KRjXmCRSXvWkG06ITQ1QsvwSbZXLB y2RR5bC1bIVA2n6wj61u/tK1F0M+iMZYKuhMLUe6ISprmrA= X-Google-Smtp-Source: AGHT+IEtLfACFX0de7KYuVTVL3HO2hHHI1LloB7c2nPQaKsGdO7+moFbur33ZjxcXpF87zPzBXSMOA== X-Received: by 2002:adf:ca0f:0:b0:336:76de:c171 with SMTP id o15-20020adfca0f000000b0033676dec171mr420446wrh.62.1704971118719; Thu, 11 Jan 2024 03:05:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/41] target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs Date: Thu, 11 Jan 2024 11:04:51 +0000 Message-Id: <20240111110505.1563291-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2 support to FEAT_NV for the latter two CPU types. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 8 +++++--- target/arm/tcg/cpu64.c | 1 + 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0b604f90059..d827b42de79 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -63,6 +63,7 @@ the following architecture extensions: - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) +- FEAT_NV (Nested Virtualization) - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) - FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm) - FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1c8b7874823..c15ad52ab3d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2238,9 +2238,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); - /* FEAT_NV (Nested Virtualization) */ - cpu->isar.id_aa64mmfr2 = - FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); + /* FEAT_NV2 (Enhanced Nested Virtualization support) */ + if (FIELD_EX64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV) > 1) { + cpu->isar.id_aa64mmfr2 = + FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 1); + } } /* MPU can be configured out of a PMSA CPU either by setting has-mpu diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 40e7a45166f..93f040e6e96 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1204,6 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t = FIELD_DP64(t, ID_AA64MMFR2, NV, 1); /* FEAT_NV */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ From patchwork Thu Jan 11 11:04:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E1EFC4725D for ; Thu, 11 Jan 2024 11:12:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssj-0001gF-Al; Thu, 11 Jan 2024 06:05:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssE-0001OC-Ed for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:25 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssC-0004To-HV for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:22 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-40d5336986cso66500435e9.1 for ; Thu, 11 Jan 2024 03:05:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971119; x=1705575919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=J8usOgs71gAybFdal5YqRiowxIC5H4fgmIvlWyQXChc=; b=kpvpAiA1OQKhMZ4a3ow+BvfnCrLsBqbAhHLeHAgW4bw8O/3atAUw5C7vktnwW95/Fd cIvdz5RGTP3GkZQgaNgsOsUMy6iaBcLHgiGCvQe7P7FAlvXHXrmh94ZKjNEJCiEIKVVv QJqGdDlW5xtctFUhe812aHQib0yrU4uB9SJBAOBhcEMqqwx1ceLZ8x05Oj/O9N2HED63 SVFXrpw8C+f8K5LrlLYAj688b/dGq0OsoD2wAvbY1qEsm1YnahZNidPUfK9ut/B0tv2H B7M4HK5X0zu0Q9KTGp+xFTULSkI6aB6xwUruMB3jickXAhf2ItxKsSAx3m/3BOOQNJt9 006w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971119; x=1705575919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J8usOgs71gAybFdal5YqRiowxIC5H4fgmIvlWyQXChc=; b=pOvMuvV8PSxR8094WPq882gXCFZpze3iqdcMaOTpQwSiBffL6z/gy52Kc3ut7xD21s E5MC1LZvLvegYrDVQvHYRJMVQZMc4rWgeMmOvCi+0BAPJYcupLe2G3vcFFmd+q1RsXo6 8TrkqdDeTolThrMaoZ8vMXs4GMhPmgzfMCdRf33RdLU9OO+OfCMuMadwwf65f9C28pn5 2ubQVrgUKpoXZG6p8QBLh/UG/65br0SgkYjL/BRTQ0dg/MbD0g0Kv/Aqiy/7O0oVSDEE tgrWDjtVKv1xfNg7N/iQz+AlPwID2SaD96ldyILNlVq1nmnVd1r2gBV2ioLcsSl545cQ qAtw== X-Gm-Message-State: AOJu0YzokDdYJBpPNrPb7eGOdgvmm6/7tUW38rGl3/E27643VbgJpKml JOsNGNR86mGymzmNvnzZGYIr6RwHgLBXhj2Xi08Z2Vaq61w= X-Google-Smtp-Source: AGHT+IEZFMZJ7DLCUYDKgI8vPK7IP05faPlhLAklipsVPZZ6bWtUzhrS01ii9BK/1JOc2hm2e3znAw== X-Received: by 2002:a05:600c:314f:b0:40d:94df:dac4 with SMTP id h15-20020a05600c314f00b0040d94dfdac4mr311971wmo.153.1704971119209; Thu, 11 Jan 2024 03:05:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/41] target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits Date: Thu, 11 Jan 2024 11:04:52 +0000 Message-Id: <20240111110505.1563291-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org FEAT_NV2 defines another new bit in HCR_EL2: NV2. When the feature is enabled, allow this bit to be written in HCR_EL2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpu-features.h | 5 +++++ target/arm/helper.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 3a43c328d9e..7a590c824cf 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -844,6 +844,11 @@ static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0; } +static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >= 2; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && diff --git a/target/arm/helper.c b/target/arm/helper.c index 24751e05b24..e3e56539594 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5857,6 +5857,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) if (cpu_isar_feature(aa64_nv, cpu)) { valid_mask |= HCR_NV | HCR_NV1 | HCR_AT; } + if (cpu_isar_feature(aa64_nv2, cpu)) { + valid_mask |= HCR_NV2; + } } if (cpu_isar_feature(any_evt, cpu)) { From patchwork Thu Jan 11 11:04:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B093C4707B for ; Thu, 11 Jan 2024 11:11:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssk-0001hJ-At; Thu, 11 Jan 2024 06:05:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssH-0001OG-Nx for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:30 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssD-0004U9-54 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:22 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3367601a301so4553504f8f.2 for ; Thu, 11 Jan 2024 03:05:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971119; x=1705575919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SaqZ9xe22tumjx3dL0fsEpY2dA8696LTi7vPLEZxD+Q=; b=IC/jNGUnDhwXTsFZFTw/3Pxbr/4H1zw2a7xiLQMJX3o2w94PvZqO2ELH5uuknLRUtR b341ay4jND3Qu+43f6GpMPdTVqMIbv8XSz3UWZujUlBFZH3YwZXqvSi1g1y41OmyKhn0 IjPJ6FhfLeD0/x675oa0XqSyadO4zwwhm1fldnpEp2fLI0jRl5S6j+d926VwX29hBmW3 P4SiLu9OwH4R55t5XRLdfEiI9nW6fv7B0fcU1K1be/PCK2KLcT+F43JqVDSC1A8yQNlQ MLQ695fwyZKDLyKVRA+0DKxzzotICv5SMKXztR3cB66wb/ne2ZHbOSbsk9CPG1BVTsUl g9iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971119; x=1705575919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SaqZ9xe22tumjx3dL0fsEpY2dA8696LTi7vPLEZxD+Q=; b=KlQ3PfAR6vUKJigR+VY8J/0Z97wsnUytJ6iSaBVr5nwNYPZachGVDeIsNmyvU3QQOP IV9UKd/CrgiCVPArgW612g+9ggaATw+4tlIrCFjP6ZD1QYo0CO7KCJNZnMO97zZDMCli mW0MOYczxealpB1opbzSq7PNzeWeCB0mVVrGaaFcVd7FchrLxgUSi4USx9wH4/mm0xm2 ymi7lxv3iuvdQnDTSy7JQnK+b0SrG/yOMf3bhpTfwPZQiyMfxzLC7PNKMCs36zN64w4j CLZfWI01gdbB5rFevR1jlZkmo1XBXKWWZCSdDbKnY9fsPvWSdiKq85w+/zYNQwRCw5H+ CCSg== X-Gm-Message-State: AOJu0YwOIM9scwEfTsehTh/C60pAeYl/Q0YYkKVYl9jP6MFHrGgsipoM Fr2aFeVlZMYGII8ZkqlasPIvcNKX/FjmWy8zctYZpVttuj4= X-Google-Smtp-Source: AGHT+IHOUft2it1rm1avw7SaLDMsfMYUH6+2i24LWP4tIGjzyE+VJoM8CF+6TTF0mZrNuQGohLe3+A== X-Received: by 2002:a05:600c:158a:b0:40e:4e06:26b4 with SMTP id r10-20020a05600c158a00b0040e4e0626b4mr211858wmf.109.1704971119737; Thu, 11 Jan 2024 03:05:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/41] target/arm: Implement VNCR_EL2 register Date: Thu, 11 Jan 2024 11:04:53 +0000 Message-Id: <20240111110505.1563291-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For FEAT_NV2, a new system register VNCR_EL2 holds the base address of the memory which nested-guest system register accesses are redirected to. Implement this register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpu.h | 3 +++ target/arm/helper.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d7a10fb4b61..0e48a1366bd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -547,6 +547,9 @@ typedef struct CPUArchState { uint64_t gpccr_el3; uint64_t gptbr_el3; uint64_t mfar_el3; + + /* NV2 register */ + uint64_t vncr_el2; } cp15; struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index e3e56539594..53bd6c85990 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8131,6 +8131,28 @@ static const ARMCPRegInfo fgt_reginfo[] = { .access = PL2_RW, .accessfn = access_fgt, .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) }, }; + +static void vncr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Clear the RES0 bottom 12 bits; this means at runtime we can guarantee + * that VNCR_EL2 + offset is 64-bit aligned. We don't need to do anything + * about the RESS bits at the top -- we choose the "generate an EL2 + * translation abort on use" CONSTRAINED UNPREDICTABLE option (i.e. let + * the ptw.c code detect the resulting invalid address). + */ + env->cp15.vncr_el2 = value & ~0xfffULL; +} + +static const ARMCPRegInfo nv2_reginfo[] = { + { .name = "VNCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 2, .opc2 = 0, + .access = PL2_RW, + .writefn = vncr_write, + .fieldoffset = offsetof(CPUARMState, cp15.vncr_el2) }, +}; + #endif /* TARGET_AARCH64 */ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, @@ -9614,6 +9636,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, rme_mte_reginfo); } } + + if (cpu_isar_feature(aa64_nv2, cpu)) { + define_arm_cp_regs(cpu, nv2_reginfo); + } #endif if (cpu_isar_feature(any_predinv, cpu)) { From patchwork Thu Jan 11 11:04:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C308C47077 for ; Thu, 11 Jan 2024 11:07:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssX-0001Rr-Em; Thu, 11 Jan 2024 06:05:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssI-0001P3-6t for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-lj1-x229.google.com ([2a00:1450:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssE-0004Ue-6c for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:24 -0500 Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2cceb5f0918so55495551fa.2 for ; Thu, 11 Jan 2024 03:05:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971120; x=1705575920; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=15rlOByBdh8+iLkfPVBVi/SbZWKpkYx6lLXZPs5/sUg=; b=eC6N9UXjVt1qnvvzfr3z9DcPxagmUb08+KiZbKptTUsFpO0rn4qYluWu+aEmP0Krua A9EURHtU5j9qcHiFxPZttrH7vZAqkxEY84nBVPPiH50uDW9uI9mUZFTkz7LtbX40oqWA 6z04TbFOk5KnNpchLM/h1sqzIXGWGXipVI+Dl5Dc4y1kAoWlWNFKt6c7dWyCiOLqa1DH HiX+xpMLJXhpXfO8DwuX5ZzgTMRbU3/hwISIGoFJ6XTmKRiUyUJpSH1IeVL9WLH7w7wv Dumg9Aqh3sx3Q3w8NwYIrbw21I44NWtVV+Lra0u4vAAAAi8q9wDRO/sVAA3cqHu8aLaT yQiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971120; x=1705575920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=15rlOByBdh8+iLkfPVBVi/SbZWKpkYx6lLXZPs5/sUg=; b=xR6HmtnQ7OYNIcK6WhSNAX0uXFNZpzXBQZswEcxkN5EETlAQCX2tLvEdS+HGkFCCqc 22V4KNsvq3MlNuuZlZRe79RMp7uOeVHiLG8Sr2elQjhsnxIgGGtg0NZMCTyVx2N6VH4j rJKmtQzbwLHhUB/QP0f8vx61sH84EtzFrvB3BgMveUEYb9UmKZI74pODjNSX5S5Oxq2M FMbtOk2F03BRdp3YbcUTe/hhuLEmtj1A8TwE/VgGapQi0jKKntdamJ6vA+0eH+w2aBs6 TUtltbKubEA5kGOYp3BfPFxlPivIldnkNB3b/I8vlyIos0gZM9STTw1D6Gixd3o5KJuh NiYQ== X-Gm-Message-State: AOJu0YwGlzeMuPMyO0VzwW+r6mJ2xk5xLJ6cFxyZsT3DjkM0kbKejiv4 P2fZbvsHSNHNl3mta/IlUIQq+yRz6TWK73HglXaZPMPcxdU= X-Google-Smtp-Source: AGHT+IHv8xiBzmsEhqKOWYGqby7963J7HeIOKru+tz36fWoRyhG8Vqb61JKwRT1n/au29gk7pUTGbA== X-Received: by 2002:a2e:9bd9:0:b0:2cc:f41d:8f41 with SMTP id w25-20020a2e9bd9000000b002ccf41d8f41mr183499ljj.39.1704971120265; Thu, 11 Jan 2024 03:05:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/41] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 Date: Thu, 11 Jan 2024 11:04:54 +0000 Message-Id: <20240111110505.1563291-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org With FEAT_NV2, the condition for when SPSR_EL1.M should report that an exception was taken from EL2 changes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 53bd6c85990..b9b3aaf4db7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11328,10 +11328,18 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] = env->pc; - if (cur_el == 1 && new_el == 1 && - ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == HCR_NV)) { - /* I_ZJRNN: report EL2 in the SPSR by setting M[3:2] to 0b10 */ - old_mode = deposit32(old_mode, 2, 2, 2); + if (cur_el == 1 && new_el == 1) { + uint64_t hcr = arm_hcr_el2_eff(env); + if ((hcr & (HCR_NV | HCR_NV1 | HCR_NV2)) == HCR_NV || + (hcr & (HCR_NV | HCR_NV2)) == (HCR_NV | HCR_NV2)) { + /* + * FEAT_NV, FEAT_NV2 may need to report EL2 in the SPSR + * by setting M[3:2] to 0b10. + * If NV2 is disabled, change SPSR when NV,NV1 == 1,0 (I_ZJRNN) + * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM) + */ + old_mode = deposit32(old_mode, 2, 2, 2); + } } } else { old_mode = cpsr_read_for_spsr_elx(env); From patchwork Thu Jan 11 11:04:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7014BC4707B for ; Thu, 11 Jan 2024 11:09:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssi-0001en-O3; Thu, 11 Jan 2024 06:05:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssL-0001PL-0V for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssF-0004V4-JL for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:27 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40e5f615a32so4440285e9.1 for ; Thu, 11 Jan 2024 03:05:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971121; x=1705575921; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HDRuFqgtgBujOw/eF1ydKefrsWrCrRnaThf36FKE+Yw=; b=RDIRyQk440TdAJnvbkJZbv2+Pu4rJ4H2sGQz0o6QluEe4H5UuqVQ1J4A0Kc7Rk8278 Do7gxUEDYdcWg809xkFHT7SWdbaypm+TXcLs7Q6QXUk8rhyVjKJZIKDraPdJa4/aOU5x gZEEXrr8qeRyagUx4pi32pdDnwsb4VXS9WbUYOiePUqO84zUcNxZnmFK4XIuMfNzOcf0 4tuY7vAiUr/eGKP7tawfbf0mbcWKXfF0t0JL3b/SliDuhOu3UhwndJ1aBaGVzpVdA8EG zoqm4zB8fIInEzVAlyXdpj9g4MSYckXhARchPpZzLkaCFI/UyaN+IXxALHU9AsIZMi+c Mfhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971121; x=1705575921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HDRuFqgtgBujOw/eF1ydKefrsWrCrRnaThf36FKE+Yw=; b=OGA4ZQjbSGH2SQ6Q4MqVodR3n/M4EzS6tXB8QpKz912Lh9oj5qu3ZzEzJcqQXHujEz HpIAq3xKHZnjMPSYmOIjTM7s+KNzlX7N0dzu1w6OCmwZtclLv3DqzE8dnnx/o+Bc0SAJ BDgczPAiO6xuIYHKwgzV/jG7lHjjTpR2W06rVLF53PWmI+7/x7YN8u5W3WbpFY6oggHJ OVm6x2EvgbxuFFDQLfRC0Oi1RocAbuv7f66WjWW5htaf+VFaTZZsx/vsCSZZS0Oj265N N2vAHsm0S+YQxWhzbrX/m6uVSkMvBCStE8o2OTcCxeUR4kwn7zu6aF5dbJmfQ/DfPcuT bp+A== X-Gm-Message-State: AOJu0Yyv9jyx8i149upjfuvOlA4sn7W1o8jrWXepcwXd4B3u/Oz8kFAP d1Fhb+fqA1/crIgXeA3SgvdTxyl5gGIiK2Qp9II1Ly6TAyE= X-Google-Smtp-Source: AGHT+IGRniTewWU+GgEFNzw/3pCcS2nuShlZvNd78PYK0/lL9EuIkhtPcQpf6bRuQy6rSV3i6/grgw== X-Received: by 2002:a05:600c:540a:b0:40e:5a83:9cea with SMTP id he10-20020a05600c540a00b0040e5a839ceamr172712wmb.14.1704971120719; Thu, 11 Jan 2024 03:05:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/41] target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 Date: Thu, 11 Jan 2024 11:04:55 +0000 Message-Id: <20240111110505.1563291-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Under FEAT_NV2, when HCR_EL2.{NV,NV2} == 0b11 at EL1, accesses to the registers SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 and TFSR_EL2 (which would UNDEF without FEAT_NV or FEAT_NV2) should instead access the equivalent EL1 registers SPSR_EL1, ELR_EL1, ESR_EL1, FAR_EL1 and TFSR_EL1. Because there are only five registers involved and the encoding for the EL1 register is identical to that of the EL2 register except that opc1 is 0, we handle this by finding the EL1 register in the hash table and using it instead. Note that traps that apply to direct accesses to the EL1 register, such as active fine-grained traps or other trap bits, do not trigger when it is accessed via the EL2 encoding in this way. However, some traps that are defined by the EL2 register may apply. We therefore call the EL2 register's accessfn first. The only one of the five which has such traps is TFSR_EL2: make sure its accessfn correctly handles both FEAT_NV (where we trap to EL2 without checking ATA bits) and FEAT_NV2 (where we check ATA bits and then redirect to TFSR_EL1). (We don't need the NV1 tbflag bit until the next patch, but we introduce it here to avoid putting the NV, NV1, NV2 bits in an odd order.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpregs.h | 5 +++++ target/arm/cpu.h | 2 ++ target/arm/tcg/translate.h | 4 ++++ target/arm/helper.c | 13 +++++++++---- target/arm/tcg/hflags.c | 6 ++++++ target/arm/tcg/translate-a64.c | 33 ++++++++++++++++++++++++++++++++- 6 files changed, 58 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 3c5f1b48879..cb795bed75b 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -118,6 +118,11 @@ enum { * ARM pseudocode function CheckSMEAccess(). */ ARM_CP_SME = 1 << 19, + /* + * Flag: one of the four EL2 registers which redirect to the + * equivalent EL1 register when FEAT_NV2 is enabled. + */ + ARM_CP_NV2_REDIRECT = 1 << 20, }; /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e48a1366bd..f521219ea95 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3239,6 +3239,8 @@ FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) FIELD(TBFLAG_A64, NAA, 30, 1) FIELD(TBFLAG_A64, ATA0, 31, 1) FIELD(TBFLAG_A64, NV, 32, 1) +FIELD(TBFLAG_A64, NV1, 33, 1) +FIELD(TBFLAG_A64, NV2, 34, 1) /* * Helpers for using the above. Note that only the A64 accessors use diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 63e075bce3a..9e13c4ef7b6 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -146,6 +146,10 @@ typedef struct DisasContext { bool naa; /* True if FEAT_NV HCR_EL2.NV is enabled */ bool nv; + /* True if NV enabled and HCR_EL2.NV1 is set */ + bool nv1; + /* True if NV enabled and HCR_EL2.NV2 is set */ + bool nv2; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index b9b3aaf4db7..93991c07b78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6135,14 +6135,16 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_ALIAS, + .type = ARM_CP_ALIAS | ARM_CP_NV2_REDIRECT, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, + .type = ARM_CP_NV2_REDIRECT, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, + .type = ARM_CP_NV2_REDIRECT, .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, { .name = "HIFAR", .state = ARM_CP_STATE_AA32, @@ -6151,7 +6153,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .access = PL2_RW, .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_ALIAS, + .type = ARM_CP_ALIAS | ARM_CP_NV2_REDIRECT, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, @@ -7876,11 +7878,13 @@ static CPAccessResult access_tfsr_el2(CPUARMState *env, const ARMCPRegInfo *ri, /* * TFSR_EL2: similar to generic access_mte(), but we need to * account for FEAT_NV. At EL1 this must be a FEAT_NV access; - * we will trap to EL2 and the HCR/SCR traps do not apply. + * if NV2 is enabled then we will redirect this to TFSR_EL1 + * after doing the HCR and SCR ATA traps; otherwise this will + * be a trap to EL2 and the HCR/SCR traps do not apply. */ int el = arm_current_el(env); - if (el == 1) { + if (el == 1 && (arm_hcr_el2_eff(env) & HCR_NV2)) { return CP_ACCESS_OK; } if (el < 2 && arm_is_el2_enabled(env)) { @@ -7917,6 +7921,7 @@ static const ARMCPRegInfo mte_reginfo[] = { .access = PL1_RW, .accessfn = access_tfsr_el1, .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NV2_REDIRECT, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, .access = PL2_RW, .accessfn = access_tfsr_el2, .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 8f254bf9ccb..d2b352663e8 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -302,6 +302,12 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, if (el == 1 && (hcr & HCR_NV)) { DP_TBFLAG_A64(flags, TRAP_ERET, 1); DP_TBFLAG_A64(flags, NV, 1); + if (hcr & HCR_NV1) { + DP_TBFLAG_A64(flags, NV1, 1); + } + if (hcr & HCR_NV2) { + DP_TBFLAG_A64(flags, NV2, 1); + } } if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ed1cc019a4c..2ada5b7e3f6 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2133,6 +2133,7 @@ static void handle_sys(DisasContext *s, bool isread, const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key); bool need_exit_tb = false; bool nv_trap_to_el2 = false; + bool nv_redirect_reg = false; bool skip_fp_access_checks = false; TCGv_ptr tcg_ri = NULL; TCGv_i64 tcg_rt; @@ -2174,7 +2175,14 @@ static void handle_sys(DisasContext *s, bool isread, * for registers accessible at EL1). */ skip_fp_access_checks = true; - if (s->nv && arm_cpreg_traps_in_nv(ri)) { + if (s->nv2 && (ri->type & ARM_CP_NV2_REDIRECT)) { + /* + * This is one of the few EL2 registers which should redirect + * to the equivalent EL1 register. We do that after running + * the EL2 register's accessfn. + */ + nv_redirect_reg = true; + } else if (s->nv && arm_cpreg_traps_in_nv(ri)) { /* * This register / instruction exists and is an EL2 register, so * we must trap to EL2 if accessed in nested virtualization EL1 @@ -2226,6 +2234,27 @@ static void handle_sys(DisasContext *s, bool isread, return; } + if (nv_redirect_reg) { + /* + * FEAT_NV2 redirection of an EL2 register to an EL1 register. + * Conveniently in all cases the encoding of the EL1 register is + * identical to the EL2 register except that opc1 is 0. + * Get the reginfo for the EL1 register to use for the actual access. + * We don't use the EL1 register's access function, and + * fine-grained-traps on EL1 also do not apply here. + */ + key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, + crn, crm, op0, 0, op2); + ri = get_arm_cp_reginfo(s->cp_regs, key); + assert(ri); + assert(cp_access_ok(s->current_el, ri, isread)); + /* + * We might not have done an update_pc earlier, so check we don't + * need it. We could support this in future if necessary. + */ + assert(!(ri->type & ARM_CP_RAISES_EXC)); + } + /* Handle special cases first */ switch (ri->type & ARM_CP_SPECIAL_MASK) { case 0: @@ -14032,6 +14061,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING); dc->naa = EX_TBFLAG_A64(tb_flags, NAA); dc->nv = EX_TBFLAG_A64(tb_flags, NV); + dc->nv1 = EX_TBFLAG_A64(tb_flags, NV1); + dc->nv2 = EX_TBFLAG_A64(tb_flags, NV2); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Thu Jan 11 11:04:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCBA5C4707B for ; Thu, 11 Jan 2024 11:12:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssj-0001gW-JN; Thu, 11 Jan 2024 06:05:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssL-0001PN-Cd for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssH-0004Ve-Gu for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:29 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3377d45c178so1040446f8f.2 for ; Thu, 11 Jan 2024 03:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971121; x=1705575921; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ImpU1WCMbgzrW+ilWcVhrg2deIUxWHoXCQYEMwhrng4=; b=wLutpyZBbNjMIQxPd38CenkgXl5EXOcbRW0rmnzyhAdF9amJTKWBakU001BFKK3A46 MYfPLTPonhx62IYrO5XpRXc/Dvl0EYBX8wVToZWJu64gazIbzlQNJFkG2UOCuJ7ArNtj vvN4QmfA0dFLJmWkLBAJEaWdNWkiQsdUMeMKGpvbQlznmQP9iCJDDIWGTvoijUrL7cWr QXuTUMQy0zRdE9gsR+D7eDNluuRHxL/bf7EmOY4DlK/GN9lPrj61gVKDU4TlFvkGaZsZ Be/IO8AQqD71fT+nAsjiviI1zO7MjQrA8Uo5y4gZa7CQipnldXTnL486DCDJQEG+qAwE DC9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971121; x=1705575921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ImpU1WCMbgzrW+ilWcVhrg2deIUxWHoXCQYEMwhrng4=; b=YfaTqYlX1enkLBDM6CQ8KRxbn3IDXX5kYXHSKtfa15XgmHYHBLnX4lJ5wTSCY8YNjf j8jeR2I7B8KoaDG/IKX0a6Gw1TS1SCH228srcw/O1eCs8Rjnl8S5I5v0tsGH8VObwk/L ZuwfOls915BHassF3nnf4mQElQQY3fExw5h/hQQUdhosLMSE3WJMUSQ7YXwFVBx8VewS WD0JHrqUJu6J1UNsv++tfkm5C0eHA66Xv/LjMppcRTKyXWYmdLYJzUtH5xUFaBMesOC0 V4URCMRmm77BCcDHcltcAQCpgoh7qT31212IvhnR61+5S+U64YlbVAh28nncwMuCHeh4 pl2g== X-Gm-Message-State: AOJu0YwI2QCZaIaPQ7vU6bBMp9WFjLpz9J4usmtuYOGUEuHwjtVnAY1I pQJDpdpmIDSBPiuZ2zR+B+yzUOLVEa0KKQJASuaTrv1OApc= X-Google-Smtp-Source: AGHT+IGNP+Qa5YxFDOAu778bJQ5VVlJsi+tmyy6qeguIfmjIF51DdXU5Wx6Jn0D/xnGniBr2LVStTA== X-Received: by 2002:adf:fd0e:0:b0:336:5964:ba7d with SMTP id e14-20020adffd0e000000b003365964ba7dmr565531wrr.85.1704971121208; Thu, 11 Jan 2024 03:05:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/41] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM Date: Thu, 11 Jan 2024 11:04:56 +0000 Message-Id: <20240111110505.1563291-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org FEAT_NV2 requires that when HCR_EL2.{NV,NV2} == 0b11 then accesses by EL1 to certain system registers are redirected to RAM. The full list of affected registers is in the table in rule R_CSRPQ in the Arm ARM. The registers may be normally accessible at EL1 (like ACTLR_EL1), or normally UNDEF at EL1 (like HCR_EL2). Some registers redirect to RAM only when HCR_EL2.NV1 is 0, and some only when HCR_EL2.NV1 is 1; others trap in both cases. Add the infrastructure for identifying which registers should be redirected and turning them into memory accesses. This code does not set the correct syndrome or arrange for the exception to be taken to the correct target EL if the access via VNCR_EL2 faults; we will do that in the next commit. Subsequent commits will mark up the relevant regdefs to set their nv2_redirect_offset, and if relevant one of the two flags which indicates that the redirect happens only for a particular value of HCR_EL2.NV1. Signed-off-by: Peter Maydell Tested-by: Miguel Luis Reviewed-by: Richard Henderson --- target/arm/cpregs.h | 12 ++++++++ target/arm/cpu.h | 4 +++ target/arm/tcg/translate.h | 6 ++++ target/arm/tcg/hflags.c | 6 ++++ target/arm/tcg/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++ 5 files changed, 84 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index cb795bed75b..b6fdd0f3eb4 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -826,6 +826,11 @@ typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); #define CP_ANY 0xff +/* Flags in the high bits of nv2_redirect_offset */ +#define NV2_REDIR_NV1 0x4000 /* Only redirect when HCR_EL2.NV1 == 1 */ +#define NV2_REDIR_NO_NV1 0x8000 /* Only redirect when HCR_EL2.NV1 == 0 */ +#define NV2_REDIR_FLAG_MASK 0xc000 + /* Definition of an ARM coprocessor register */ struct ARMCPRegInfo { /* Name of register (useful mainly for debugging, need not be unique) */ @@ -867,6 +872,13 @@ struct ARMCPRegInfo { * value encodes both the trap register and bit within it. */ FGTBit fgt; + + /* + * Offset from VNCR_EL2 when FEAT_NV2 redirects access to memory; + * may include an NV2_REDIR_* flag. + */ + uint32_t nv2_redirect_offset; + /* * The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f521219ea95..9281d74aa9d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3241,6 +3241,10 @@ FIELD(TBFLAG_A64, ATA0, 31, 1) FIELD(TBFLAG_A64, NV, 32, 1) FIELD(TBFLAG_A64, NV1, 33, 1) FIELD(TBFLAG_A64, NV2, 34, 1) +/* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ +FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) +/* Set if FEAT_NV2 RAM accesses are big-endian */ +FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) /* * Helpers for using the above. Note that only the A64 accessors use diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 9e13c4ef7b6..93be745cf33 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -150,6 +150,10 @@ typedef struct DisasContext { bool nv1; /* True if NV enabled and HCR_EL2.NV2 is set */ bool nv2; + /* True if NV2 enabled and NV2 RAM accesses use EL2&0 translation regime */ + bool nv2_mem_e20; + /* True if NV2 enabled and NV2 RAM accesses are big-endian */ + bool nv2_mem_be; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. @@ -165,6 +169,8 @@ typedef struct DisasContext { int c15_cpar; /* TCG op of the current insn_start. */ TCGOp *insn_start; + /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */ + uint32_t nv2_redirect_offset; } DisasContext; typedef struct DisasCompare { diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index d2b352663e8..8e5d35d9227 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -307,6 +307,12 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } if (hcr & HCR_NV2) { DP_TBFLAG_A64(flags, NV2, 1); + if (hcr & HCR_E2H) { + DP_TBFLAG_A64(flags, NV2_MEM_E20, 1); + } + if (env->cp15.sctlr_el[2] & SCTLR_EE) { + DP_TBFLAG_A64(flags, NV2_MEM_BE, 1); + } } } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2ada5b7e3f6..2938397d52c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2135,6 +2135,7 @@ static void handle_sys(DisasContext *s, bool isread, bool nv_trap_to_el2 = false; bool nv_redirect_reg = false; bool skip_fp_access_checks = false; + bool nv2_mem_redirect = false; TCGv_ptr tcg_ri = NULL; TCGv_i64 tcg_rt; uint32_t syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); @@ -2167,6 +2168,21 @@ static void handle_sys(DisasContext *s, bool isread, return; } + if (s->nv2 && ri->nv2_redirect_offset) { + /* + * Some registers always redirect to memory; some only do so if + * HCR_EL2.NV1 is 0, and some only if NV1 is 1 (these come in + * pairs which share an offset; see the table in R_CSRPQ). + */ + if (ri->nv2_redirect_offset & NV2_REDIR_NV1) { + nv2_mem_redirect = s->nv1; + } else if (ri->nv2_redirect_offset & NV2_REDIR_NO_NV1) { + nv2_mem_redirect = !s->nv1; + } else { + nv2_mem_redirect = true; + } + } + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { /* @@ -2182,6 +2198,12 @@ static void handle_sys(DisasContext *s, bool isread, * the EL2 register's accessfn. */ nv_redirect_reg = true; + assert(!nv2_mem_redirect); + } else if (nv2_mem_redirect) { + /* + * NV2 redirect-to-memory takes precedence over trap to EL2 or + * UNDEF to EL1. + */ } else if (s->nv && arm_cpreg_traps_in_nv(ri)) { /* * This register / instruction exists and is an EL2 register, so @@ -2255,6 +2277,38 @@ static void handle_sys(DisasContext *s, bool isread, assert(!(ri->type & ARM_CP_RAISES_EXC)); } + if (nv2_mem_redirect) { + /* + * This system register is being redirected into an EL2 memory access. + * This means it is not an IO operation, doesn't change hflags, + * and need not end the TB, because it has no side effects. + * + * The access is 64-bit single copy atomic, guaranteed aligned because + * of the definition of VCNR_EL2. Its endianness depends on + * SCTLR_EL2.EE, not on the data endianness of EL1. + * It is done under either the EL2 translation regime or the EL2&0 + * translation regime, depending on HCR_EL2.E2H. It behaves as if + * PSTATE.PAN is 0. + */ + TCGv_i64 ptr = tcg_temp_new_i64(); + MemOp mop = MO_64 | MO_ALIGN | MO_ATOM_IFALIGN; + ARMMMUIdx armmemidx = s->nv2_mem_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2; + int memidx = arm_to_core_mmu_idx(armmemidx); + + mop |= (s->nv2_mem_be ? MO_BE : MO_LE); + + tcg_gen_ld_i64(ptr, tcg_env, offsetof(CPUARMState, cp15.vncr_el2)); + tcg_gen_addi_i64(ptr, ptr, + (ri->nv2_redirect_offset & ~NV2_REDIR_FLAG_MASK)); + tcg_rt = cpu_reg(s, rt); + if (isread) { + tcg_gen_qemu_ld_i64(tcg_rt, ptr, memidx, mop); + } else { + tcg_gen_qemu_st_i64(tcg_rt, ptr, memidx, mop); + } + return; + } + /* Handle special cases first */ switch (ri->type & ARM_CP_SPECIAL_MASK) { case 0: @@ -14063,6 +14117,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->nv = EX_TBFLAG_A64(tb_flags, NV); dc->nv1 = EX_TBFLAG_A64(tb_flags, NV1); dc->nv2 = EX_TBFLAG_A64(tb_flags, NV2); + dc->nv2_mem_e20 = EX_TBFLAG_A64(tb_flags, NV2_MEM_E20); + dc->nv2_mem_be = EX_TBFLAG_A64(tb_flags, NV2_MEM_BE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Thu Jan 11 11:04:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00A7CC4707B for ; Thu, 11 Jan 2024 11:11:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssa-0001S1-V2; Thu, 11 Jan 2024 06:05:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssL-0001PO-FC for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssH-0004WQ-NB for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:29 -0500 Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2ccec119587so62363841fa.0 for ; Thu, 11 Jan 2024 03:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971121; x=1705575921; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=r7kELvk9H89WulGcKlRghZk0iXJ6Vb7McKJcJAbBpHc=; b=s4RaRlwWZu4sltNXcrk0onIhoNsPBh5Wg0NQqLJiCbj+VgLkM9xOqYe4o0jXk4btiT Vx7YcZIMl1L9bMWsUtj7eEu/yZ1LbDC34iWhEqvdSJn6l7vEwXWv+n/2+RiTkYuLu4r7 cuYG/e80Yb+m1RvCrLQyNRyIA3EicvFDbXrdLh8NcPyR7S5Mzz6lIBgy/krlt9Ur2LCe Yj6LtrFIhppJ8AB0pgY0VjIEqEvi0RNkc+CwPoLl1yZ78FqM/AUdMjpuJ/nwEXERtsgO L1CtWms7bL8KsnIhq0kVwmRKvvM8D1dk2MeBk1zMPmhC/epnvkZxphC7CgeRFETx67rS Xeuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971121; x=1705575921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7kELvk9H89WulGcKlRghZk0iXJ6Vb7McKJcJAbBpHc=; b=cjAf7Tqxg+lVgpWzySFB4hTSfNqOX02Ra6D4W+U4CrU0lLioMJfA+G4LV2MkAIjNPw Z0OYnIWaQQ01OWYfTLnhm8I78fZJsR1116cQbvKZgNPAb1w7lWN2VTs1NfvYQ8T/oGcq eittI058yKBCxrm4ldy1enNSzrFIVoLM+AwzFNA/MDrpVXrHa4grhLhfD0dT0DEpGBWq Sq65PHjb9RTa/UWwUToPnTzMzdI4Wo59TJqSLTQiJJITZsH0CKjTcFrVa6afLXAqd5Uo ksjQSxF6YXzG9XDq96n++LcTbI4kBs2VXqTz/20iiTWsD+ksFwFpvtExovoPByU5/Nu4 hCyg== X-Gm-Message-State: AOJu0YxlvdoVng2rd1PW362HMjwdTaNbRABR0dTzQNXu8PwDREwqFBEN Vw0D+spK0u0k15OgIHhc3CuFhvRzkPArVpAUcuO34lRqDFA= X-Google-Smtp-Source: AGHT+IFiTga4w3O6Bd6AJY4wLFRSs3PfRhsAHoZnbEcU63BZLZibtkpm03sGtixDx9h/+0nN5UecjQ== X-Received: by 2002:a2e:8894:0:b0:2cc:e50e:4758 with SMTP id k20-20020a2e8894000000b002cce50e4758mr330844lji.34.1704971121613; Thu, 11 Jan 2024 03:05:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/41] target/arm: Report VNCR_EL2 based faults correctly Date: Thu, 11 Jan 2024 11:04:57 +0000 Message-Id: <20240111110505.1563291-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org If FEAT_NV2 redirects a system register access to a memory offset from VNCR_EL2, that access might fault. In this case we need to report the correct syndrome information: * Data Abort, from same-EL * no ISS information * the VNCR bit (bit 13) is set and the exception must be taken to EL2. Save an appropriate syndrome template when generating code; we can then use that to: * select the right target EL * reconstitute a correct final syndrome for the data abort * report the right syndrome if we take a FEAT_RME granule protection fault on the VNCR-based write Note that because VNCR is bit 13, we must start keeping bit 13 in template syndromes, by adjusting ARM_INSN_START_WORD2_SHIFT. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpu.h | 4 ++-- target/arm/syndrome.h | 20 ++++++++++++++++---- target/arm/tcg/tlb_helper.c | 27 +++++++++++++++++++++++++-- target/arm/tcg/translate-a64.c | 4 ++++ 4 files changed, 47 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9281d74aa9d..ec276fcd57c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -120,12 +120,12 @@ enum { #define TARGET_INSN_START_EXTRA_WORDS 2 /* The 2nd extra word holding syndrome info for data aborts does not use - * the upper 6 bits nor the lower 14 bits. We mask and shift it down to + * the upper 6 bits nor the lower 13 bits. We mask and shift it down to * help the sleb128 encoder do a better job. * When restoring the CPU state, we shift it back up. */ #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) -#define ARM_INSN_START_WORD2_SHIFT 14 +#define ARM_INSN_START_WORD2_SHIFT 13 /* We currently assume float and double are IEEE single and double precision respectively. diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 95454b5b3bb..1a49767479f 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -86,6 +86,9 @@ typedef enum { #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) +/* In the Data Abort syndrome */ +#define ARM_EL_VNCR (1 << 13) + static inline uint32_t syn_get_ec(uint32_t syn) { return syn >> ARM_EL_EC_SHIFT; @@ -256,13 +259,12 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) (cv << 24) | (cond << 20) | rm; } -static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, +static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr, int cm, int s1ptw, int wnr, int fsc) { - /* TODO: FEAT_NV2 adds VNCR */ return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) - | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) - | (wnr << 6) | fsc; + | (ind << 20) | (gpcsc << 14) | (vncr << 13) | (cm << 8) + | (s1ptw << 7) | (wnr << 6) | fsc; } static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) @@ -295,6 +297,16 @@ static inline uint32_t syn_data_abort_with_iss(int same_el, | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; } +/* + * Faults due to FEAT_NV2 VNCR_EL2-based accesses report as same-EL + * Data Aborts with the VNCR bit set. + */ +static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (1 << ARM_EL_EC_SHIFT) + | ARM_EL_IL | ARM_EL_VNCR | (wnr << 6) | fsc; +} + static inline uint32_t syn_swstep(int same_el, int isv, int ex) { return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 4fdd85359e1..dd5de74ffb7 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -50,7 +50,15 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, * ST64BV, or ST64BV0 insns report syndrome info even for stage-1 * faults and regardless of the target EL. */ - if (!(template_syn & ARM_EL_ISV) || target_el != 2 + if (template_syn & ARM_EL_VNCR) { + /* + * FEAT_NV2 faults on accesses via VNCR_EL2 are a special case: + * they are always reported as "same EL", even though we are going + * from EL1 to EL2. + */ + assert(!fi->stage2); + syn = syn_data_abort_vncr(fi->ea, is_write, fsc); + } else if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw || !fi->stage2) { syn = syn_data_abort_no_iss(same_el, 0, fi->ea, 0, fi->s1ptw, is_write, fsc); @@ -169,6 +177,20 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, int current_el = arm_current_el(env); bool same_el; uint32_t syn, exc, fsr, fsc; + /* + * We know this must be a data or insn abort, and that + * env->exception.syndrome contains the template syndrome set + * up at translate time. So we can check only the VNCR bit + * (and indeed syndrome does not have the EC field in it, + * because we masked that out in disas_set_insn_syndrome()) + */ + bool is_vncr = (mmu_idx != MMU_INST_FETCH) && + (env->exception.syndrome & ARM_EL_VNCR); + + if (is_vncr) { + /* FEAT_NV2 faults on accesses via VNCR_EL2 go to EL2 */ + target_el = 2; + } if (report_as_gpc_exception(cpu, current_el, fi)) { target_el = 3; @@ -177,7 +199,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, syn = syn_gpc(fi->stage2 && fi->type == ARMFault_GPCFOnWalk, access_type == MMU_INST_FETCH, - encode_gpcsc(fi), 0, fi->s1ptw, + encode_gpcsc(fi), is_vncr, + 0, fi->s1ptw, access_type == MMU_DATA_STORE, fsc); env->cp15.mfar_el3 = fi->paddr; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2938397d52c..27335e85407 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2294,6 +2294,7 @@ static void handle_sys(DisasContext *s, bool isread, MemOp mop = MO_64 | MO_ALIGN | MO_ATOM_IFALIGN; ARMMMUIdx armmemidx = s->nv2_mem_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2; int memidx = arm_to_core_mmu_idx(armmemidx); + uint32_t syn; mop |= (s->nv2_mem_be ? MO_BE : MO_LE); @@ -2301,6 +2302,9 @@ static void handle_sys(DisasContext *s, bool isread, tcg_gen_addi_i64(ptr, ptr, (ri->nv2_redirect_offset & ~NV2_REDIR_FLAG_MASK)); tcg_rt = cpu_reg(s, rt); + + syn = syn_data_abort_vncr(0, !isread, 0); + disas_set_insn_syndrome(s, syn); if (isread) { tcg_gen_qemu_ld_i64(tcg_rt, ptr, memidx, mop); } else { From patchwork Thu Jan 11 11:04:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 019ACC47077 for ; Thu, 11 Jan 2024 11:09:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssk-0001h3-30; Thu, 11 Jan 2024 06:05:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssL-0001PK-1S for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssF-0004We-Kj for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:27 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-336746c7b6dso4417176f8f.0 for ; Thu, 11 Jan 2024 03:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971122; x=1705575922; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fWlADWMhxcWSj2fBgtd1Encmql0Bt3u3mAlUopxgc3A=; b=Y/uDy4jSr9p1NXgu8wUCZVu2lXxMWjnFMpR3t8iZdkQSh5e5fqREpWxUQRWyueaSvA cX0DFZ0TYF9eRDl1F6axRldM8MxiFkZ3rE7EyCTMuCkHMiDBp8vRjPIsIUNjlOYVe/a9 mdQHyzo7vOKj3oopt4r05MoVFbT6tLr4z0QCP4gifJr0bRHORmwf9d+z5XQIC4n3dhMR I+0WMM/eUTFwRgmfRvtD8UNc/YsBSfBmHiseL0hVDKzj1RXzdsacqcrg0jDQEsINv7lI 5JsR/qo69fBgR3Nn5d/GFXYsFw0PPTUJBMIP+tdOz0P4arE90EUVjSpRHgQhZFgNv8K5 hyMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971122; x=1705575922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fWlADWMhxcWSj2fBgtd1Encmql0Bt3u3mAlUopxgc3A=; b=e9wVFyv/2dn+YmI4mRM213dgeBbeNkzjkg59qh4ECvEWHuvluyTpCG6IfEXtlI13+t d9hGtmus57SEGhJdzaVjuO5zRUOpU6APB+yTT6s7nSk3dJvAVTipAwWwej0N5ZxpBTHR WzbSe//oT+Xmx8YdWE0zWUJBm5l+ZIU1T775arDtSybYRVcHQ7GEVkmFqv/eWx7vsjAn OlTqJBZgxGlbrKIB1EgGbdKfQOwoYxifSggvw8c8hHlHDHAbtgQsPjDgzYTNdsOZ9rXF yFSbLgf96mjcubG8iUUFbdl2ci3lV9ruj/nv1JOBT1BzYkIsaKAJuQdy32j6MhXzQb69 gSSQ== X-Gm-Message-State: AOJu0YyxyDNuOSeq3uq1m3RI2w77rQFyyx8fEJFxrxR7mc7Z6GcoUftm K04zUaYori3XIk7XT9RqTVcR5r4A0v4Ntl5X7EpDhB3S3Cg= X-Google-Smtp-Source: AGHT+IG268QGShFuZwW49gssS0NTDNqlYZO0RnnyBI+nNXIAHm07iIVi8DtDZtV/7z+Xczafwdt0jQ== X-Received: by 2002:adf:ee41:0:b0:336:6dd3:bfcf with SMTP id w1-20020adfee41000000b003366dd3bfcfmr520267wro.121.1704971122007; Thu, 11 Jan 2024 03:05:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/41] target/arm: Mark up VNCR offsets (offsets 0x0..0xff) Date: Thu, 11 Jan 2024 11:04:58 +0000 Message-Id: <20240111110505.1563291-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This commit covers offsets below 0x100; all of these registers are redirected to memory regardless of the value of HCR_EL2.NV1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 93991c07b78..bc5a0810421 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6059,6 +6059,7 @@ static const ARMCPRegInfo hcrx_el2_reginfo = { .name = "HCRX_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2, .access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen, + .nv2_redirect_offset = 0xa0, .fieldoffset = offsetof(CPUARMState, cp15.hcrx_el2), }; @@ -6125,6 +6126,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), + .nv2_redirect_offset = 0x78, .writefn = hcr_write, .raw_writefn = raw_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, .type = ARM_CP_ALIAS | ARM_CP_IO, @@ -6209,6 +6211,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .access = PL2_RW, + .nv2_redirect_offset = 0x40, /* no .writefn needed as this can't cause an ASID change */ .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, { .name = "VTTBR", .state = ARM_CP_STATE_AA32, @@ -6220,6 +6223,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, + .nv2_redirect_offset = 0x20, .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, @@ -6228,6 +6232,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, .access = PL2_RW, .resetvalue = 0, + .nv2_redirect_offset = 0x90, .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, @@ -6323,6 +6328,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, .writefn = gt_cntvoff_write, + .nv2_redirect_offset = 0x60, .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, @@ -6361,6 +6367,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, .access = PL2_RW, + .nv2_redirect_offset = 0x80, .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, }; @@ -6386,10 +6393,12 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = { { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, .access = PL2_RW, .accessfn = sel2_access, + .nv2_redirect_offset = 0x30, .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, .access = PL2_RW, .accessfn = sel2_access, + .nv2_redirect_offset = 0x48, .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, }; @@ -8155,6 +8164,7 @@ static const ARMCPRegInfo nv2_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 2, .opc2 = 0, .access = PL2_RW, .writefn = vncr_write, + .nv2_redirect_offset = 0xb0, .fieldoffset = offsetof(CPUARMState, cp15.vncr_el2) }, }; @@ -8986,6 +8996,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, .access = PL2_RW, .resetvalue = cpu->midr, .type = ARM_CP_EL3_NO_EL2_C_NZ, + .nv2_redirect_offset = 0x88, .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, @@ -8997,6 +9008,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, .access = PL2_RW, .resetvalue = vmpidr_def, .type = ARM_CP_EL3_NO_EL2_C_NZ, + .nv2_redirect_offset = 0x50, .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, }; /* From patchwork Thu Jan 11 11:04:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4275AC4707B for ; Thu, 11 Jan 2024 11:10:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssk-0001hs-Ot; Thu, 11 Jan 2024 06:05:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssN-0001PX-AA for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssH-0004X7-Tv for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:30 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40e60e13581so3470645e9.1 for ; Thu, 11 Jan 2024 03:05:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971122; x=1705575922; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MQYD8SQs+AzWTjyK2oOu6sKdgpJPRWaLpCdGPJiYEZU=; b=EoEIL8jYrBVJn6ZwxO9wJ4q61YZb+vQk8Y2+tR7M/vZl2O6a/E6Fw1Uk1FmMp6MJtY VCGYd9+QyOYjvIUxJUwQXAcuF7UW50dEX9lyVY/NwGJWWw13O8lZs1zZXTFbo2C3vbc9 uYEUL2TyHT0fuqUaCxJMwg0ubCt8FVghbiDAHQtDEot7sRJaffhRi0EXWgJKeohXyEQB ygbPVBWl4DQ5XX0VQsAcT0+my+sa7ud4qED+c4XF3gXucjIGzDj5zXDV9P83b2xNMkpN FHqx3nD5sfhbzf6AiuO/v7ipKY0iqu5vxIqC+MtuXVXhJr/RLezd8MWKPDpl70RhMi9L N8KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971122; x=1705575922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MQYD8SQs+AzWTjyK2oOu6sKdgpJPRWaLpCdGPJiYEZU=; b=R9uoWDMknZ1zTXZTrQ/U4HGYCEAZu/NLSR5mdvSTkhnFDR3yuxDAP+rmQCReAyWeq2 utQ+BzMkudX9Dgu3ppTuI73nBPypkleucDtmTV4GhEU71QIQ9SbePtCKNUyB0zWGWxux YGOeOG/HcaSUV93MqBhV5L4YmeQj0bncSx3aK9WlTh7jB+0U2XI3yz01ro3CP3WSoI/B 8u0IZkBFcjbHp5YIyrvPCMQCO73tMboBcRsr2qV8JZ70MkMnO3CmLSdIuSf2S9Mftv/a WPB2MUZYEU+Eh4UL79hYgmFkIkDTaXZdy+6ff7/0gRknTkqQZZIXX/KucwQfaGJKW+9e l87A== X-Gm-Message-State: AOJu0YzJgjpEv+f9P61UA7c1OegGLd5r5Mg4pPg7Jz69lfvfzDazGIIj wkAjZvccIb2v0vr374O3TXCZ2IV9ui/Z3b6biA1o3K6kn+c= X-Google-Smtp-Source: AGHT+IHyojjV5U3f7hlM+S8gk5qO5YAk+Tvg2VGP3GB21VRZ5fa6VCmqDEVajPxqoFLjPKWSt7a8EA== X-Received: by 2002:a05:600c:c15:b0:40d:8550:878d with SMTP id fm21-20020a05600c0c1500b0040d8550878dmr219569wmb.15.1704971122403; Thu, 11 Jan 2024 03:05:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/41] target/arm: Mark up VNCR offsets (offsets 0x100..0x160) Date: Thu, 11 Jan 2024 11:04:59 +0000 Message-Id: <20240111110505.1563291-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This commit covers offsets 0x100 to 0x160. Many (but not all) of the registers in this range have _EL12 aliases, and the slot in memory is shared between the _EL12 version of the register and the _EL1 version. Where we programmatically generate the regdef for the _EL12 register, arrange that its nv2_redirect_offset is set up correctly to do this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/debug_helper.c | 1 + target/arm/helper.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b39144d5b93..7d856acddf2 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -960,6 +960,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, .access = PL1_RW, .accessfn = access_tda, .fgt = FGT_MDSCR_EL1, + .nv2_redirect_offset = 0x158, .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), .resetvalue = 0 }, /* diff --git a/target/arm/helper.c b/target/arm/helper.c index bc5a0810421..1d62d243cdc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -647,6 +647,7 @@ static const ARMCPRegInfo cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_CONTEXTIDR_EL1, + .nv2_redirect_offset = 0x108 | NV2_REDIR_NV1, .secure = ARM_CP_SECSTATE_NS, .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, @@ -883,6 +884,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, .fgt = FGT_CPACR_EL1, + .nv2_redirect_offset = 0x100 | NV2_REDIR_NV1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, }; @@ -2250,11 +2252,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_AFSR0_EL1, + .nv2_redirect_offset = 0x128 | NV2_REDIR_NV1, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_AFSR1_EL1, + .nv2_redirect_offset = 0x130 | NV2_REDIR_NV1, .type = ARM_CP_CONST, .resetvalue = 0 }, /* * MAIR can just read-as-written because we don't implement caches @@ -2264,6 +2268,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_MAIR_EL1, + .nv2_redirect_offset = 0x140 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue = 0 }, { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, @@ -4287,6 +4292,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_ESR_EL1, + .nv2_redirect_offset = 0x138 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, @@ -4306,6 +4312,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, + .nv2_redirect_offset = 0x120 | NV2_REDIR_NV1, .writefn = vmsa_tcr_el12_write, .raw_writefn = raw_write, .resetvalue = 0, @@ -4545,6 +4552,7 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_AMAIR_EL1, + .nv2_redirect_offset = 0x148 | NV2_REDIR_NV1, .type = ARM_CP_CONST, .resetvalue = 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, @@ -5734,6 +5742,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_nv1, + .nv2_redirect_offset = 0x160 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, /* * We rely on the access checks not allowing the guest to write to the @@ -6726,6 +6735,17 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) new_reg->writefn = el2_e2h_e12_write; new_reg->accessfn = el2_e2h_e12_access; + /* + * If the _EL1 register is redirected to memory by FEAT_NV2, + * then it shares the offset with the _EL12 register, + * and which one is redirected depends on HCR_EL2.NV1. + */ + if (new_reg->nv2_redirect_offset) { + assert(new_reg->nv2_redirect_offset & NV2_REDIR_NV1); + new_reg->nv2_redirect_offset &= ~NV2_REDIR_NV1; + new_reg->nv2_redirect_offset |= NV2_REDIR_NO_NV1; + } + ok = g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)a->new_key, new_reg); g_assert(ok); @@ -9438,6 +9458,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, .access = PL1_RW, .accessfn = access_tacr, + .nv2_redirect_offset = 0x118, .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, @@ -9523,6 +9544,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_SCTLR_EL1, + .nv2_redirect_offset = 0x110 | NV2_REDIR_NV1, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, From patchwork Thu Jan 11 11:05:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7735DC47077 for ; Thu, 11 Jan 2024 11:11:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssl-0001j8-CG; Thu, 11 Jan 2024 06:05:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssL-0001PQ-JY for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssH-0004XT-UI for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:29 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-336c9acec03so4519400f8f.2 for ; Thu, 11 Jan 2024 03:05:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971123; x=1705575923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WIRlikOf+Qay01mq3PzxaBC1vuA3jtjYGSPSXLeA82A=; b=XCnQAlISTS3twzGAPwmcQJ/yD02xa19Z8AB7XEJNc9/ykP9HVPRB6Oh7gyeYL3wiFq KwjnvyYVqZSaCbp1PsSD5fCH1qMcXUwtXSszcdxCMuhZqy0+AgKy2TNOeWODu0rWuGXl WP9X4Ve4peZqEyCU/CQV3kKcAQlc53PluGASfIviCh3tmg28WrF6OOFkCWXJYXHBvxlA FYvfAL8HdkmXVKbC+BQ+dTwjWSZBZmb+NYEJHp0SWRKoOBsVXK0DoDzheRK6x6PogYKg Zzxo2Q3B+xy8qUxjVL7YVI0QQep4p3XA2terscCF/+9heaj20KTy2Z9dgf3IwAwZztgn Cutw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971123; x=1705575923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WIRlikOf+Qay01mq3PzxaBC1vuA3jtjYGSPSXLeA82A=; b=IeYgcIDeVz0fEXqzdYRe9qXIRr/mBr6EqIjYoQei6NbMVKUOwXU1qGAG1GmuTPUKFF P3Anu3oulbQGAHoEaR29rLSiAu4gon19NPTmInVYYjtDuiwY242Uhsb/MYxVuRnxSCz3 ERFUsr/giCJg7n19zNq+KD+PV+IwTNRBSnPD/kqHBBslaqk1/+c2zncRn8H+7EWi5eUl YWa2ABSypCnLlPE/vXgL7xysZajMB9Kv2BdPnfJxxsjTYSsV3I2WqbqTRw7LO7iWdPJh 5p+cVZQ5lOqHn+AujViNd2RNtqZRg0XW2c85dFTgln7hnRYM2z4hOymeb8ChopF+SBuE MRCA== X-Gm-Message-State: AOJu0Yz0ic88AyKI+u1KWdintkPM9Qo8KqB17y+ft1gmXJ7f4ixvzH1w 68CD75ee8+kl40zObfxa4+RsCPl6NCufrD5wpAeAS2kNu6Y= X-Google-Smtp-Source: AGHT+IGa6cxL7DAc35zfJHDD2MZ26BuL8DJWF3oGMjwRMvr04wWxcos8ivs8a0rtGvB5UIZA55sVOA== X-Received: by 2002:adf:cc8b:0:b0:337:3a52:9aa6 with SMTP id p11-20020adfcc8b000000b003373a529aa6mr587453wrj.39.1704971122771; Thu, 11 Jan 2024 03:05:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/41] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) Date: Thu, 11 Jan 2024 11:05:00 +0000 Message-Id: <20240111110505.1563291-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This commit covers offsets 0x168 to 0x1f8. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1d62d243cdc..aa66f5169ab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3191,6 +3191,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, .type = ARM_CP_IO, .access = PL0_RW, .accessfn = gt_ptimer_access, + .nv2_redirect_offset = 0x180 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), .resetvalue = 0, .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, @@ -3208,6 +3209,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, .type = ARM_CP_IO, .access = PL0_RW, .accessfn = gt_vtimer_access, + .nv2_redirect_offset = 0x170 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), .resetvalue = 0, .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, @@ -3287,6 +3289,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, .access = PL0_RW, .type = ARM_CP_IO, + .nv2_redirect_offset = 0x178 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), .resetvalue = 0, .accessfn = gt_ptimer_access, .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, @@ -3304,6 +3307,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, .access = PL0_RW, .type = ARM_CP_IO, + .nv2_redirect_offset = 0x168 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), .resetvalue = 0, .accessfn = gt_vtimer_access, .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, @@ -7052,6 +7056,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo zcr_reginfo[] = { { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, + .nv2_redirect_offset = 0x1e0 | NV2_REDIR_NV1, .access = PL1_RW, .type = ARM_CP_SVE, .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), .writefn = zcr_write, .raw_writefn = raw_write }, @@ -7193,6 +7198,7 @@ static const ARMCPRegInfo sme_reginfo[] = { .writefn = svcr_write, .raw_writefn = raw_write }, { .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6, + .nv2_redirect_offset = 0x1f0 | NV2_REDIR_NV1, .access = PL1_RW, .type = ARM_CP_SME, .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]), .writefn = smcr_write, .raw_writefn = raw_write }, @@ -7226,6 +7232,7 @@ static const ARMCPRegInfo sme_reginfo[] = { .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5, + .nv2_redirect_offset = 0x1f8, .access = PL2_RW, .accessfn = access_smprimap, .type = ARM_CP_CONST, .resetvalue = 0 }, }; @@ -7948,6 +7955,7 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, .access = PL1_RW, .accessfn = access_tfsr_el1, + .nv2_redirect_offset = 0x190 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NV2_REDIRECT, @@ -8122,6 +8130,7 @@ static const ARMCPRegInfo scxtnum_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, .access = PL1_RW, .accessfn = access_scxtnum_el1, .fgt = FGT_SCXTNUM_EL1, + .nv2_redirect_offset = 0x188 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, @@ -8146,22 +8155,27 @@ static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo fgt_reginfo[] = { { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, + .nv2_redirect_offset = 0x1b8, .access = PL2_RW, .accessfn = access_fgt, .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) }, { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5, + .nv2_redirect_offset = 0x1c0, .access = PL2_RW, .accessfn = access_fgt, .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) }, { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4, + .nv2_redirect_offset = 0x1d0, .access = PL2_RW, .accessfn = access_fgt, .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) }, { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5, + .nv2_redirect_offset = 0x1d8, .access = PL2_RW, .accessfn = access_fgt, .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) }, { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6, + .nv2_redirect_offset = 0x1c8, .access = PL2_RW, .accessfn = access_fgt, .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) }, }; @@ -8348,12 +8362,14 @@ static const ARMCPRegInfo vhe_reginfo[] = { .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL2_RW, .accessfn = e2h_access, + .nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL2_RW, .accessfn = e2h_access, + .nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, @@ -8370,11 +8386,13 @@ static const ARMCPRegInfo vhe_reginfo[] = { .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, .type = ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), + .nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1, .access = PL2_RW, .accessfn = e2h_access, .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, .type = ARM_CP_IO | ARM_CP_ALIAS, + .nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1, .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), .access = PL2_RW, .accessfn = e2h_access, .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, From patchwork Thu Jan 11 11:05:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F21EC4707B for ; Thu, 11 Jan 2024 11:08:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNsse-0001ZD-O3; Thu, 11 Jan 2024 06:05:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssN-0001PV-9T for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssH-0004XX-Um for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:30 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-40e54b2e437so22224005e9.2 for ; Thu, 11 Jan 2024 03:05:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971123; x=1705575923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HjbFqOWn/TNSc9et6xxdifrEZI+6S3bwTcQGRjFtcY4=; b=TkmOJpH3XsOxFLEDJc+vidQcHmFsJm4AcE4ih+O4ivlt9UWQwBGdqJuzcZy4BVqbwL VgFkCIIv1vzlVcl/BMfwkPkX+yuAwyvLW6pPr0tnLFHOfpMXvC77dPl55E7d86eFN5ws 0JQa3yKbZoJAtRsXZ5gIWyorISN6gmr40rfnmBZSLsGxzndqkuqPXRU/ck2il/VE9WgU Ka/qWB7tD3N0LnJNdJkYhIkZdL0veB6oGj3CdREaS84LqZM8Zdwn7vje4UxqVqGmYpaU 4l1CtjwKXKtnR2YO4hGaqkyCp/wdaoOMyPgIc7QAS50jAzCDX7O22LBoHd8uvthieQtI h4oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971123; x=1705575923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HjbFqOWn/TNSc9et6xxdifrEZI+6S3bwTcQGRjFtcY4=; b=r3NIXjhw+U8LKOhHJKJwD7WO0FA5LFnwFH92qkCrqNSeE03uiXo4yWJzXlhh0HcZOi 8lC8AEi0eliSr33pOdwFcZD18GF+wOET8P2jjI4MmOrYRQ2dZR2CNAyzmZTaWANGmk7i LgjKZZPG7lPHDSL5+R2CYhFEXZSnEi2puE1LUbYtr3i24jGNOaRPUEqFCO/oNfLO/WEz 0Jf9Qt1jT3jBSuFCXsujTV5Oa5zD5Be6KF59ypVj3slug/aTgBcoUmOqub2SDSGxflYp RPNNsCvMYdTem2QzfNpnOTanw+WFbQxVExkaxQKBAgodn1mRG39BrUOf6pvk/2gizhqG e6VQ== X-Gm-Message-State: AOJu0YzbXPuZa5OvRPmN5wA4SfjTRqr45bUEBicstnlyqvKuEeNgF1Cj XRDzBoExVh1HvIf9rBEEH7XwlTtScgRpx/M0iEaZFRsz33c= X-Google-Smtp-Source: AGHT+IE/sPSZZPsCY5jZsS0z5tILk+1K0PeTw31TDh9i5+dOdfwQwcpzC0osduDYVNg79evRsmycvQ== X-Received: by 2002:a05:600c:3491:b0:40e:5d36:8bb0 with SMTP id a17-20020a05600c349100b0040e5d368bb0mr271602wmq.44.1704971123180; Thu, 11 Jan 2024 03:05:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/41] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) Date: Thu, 11 Jan 2024 11:05:01 +0000 Message-Id: <20240111110505.1563291-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This covers all the remaining offsets at 0x200 and above, except for the GIC ICH_* registers. (Note that because we don't implement FEAT_SPE, FEAT_TRF, FEAT_MPAM, FEAT_BRBE or FEAT_AMUv1p1 we don't implement any of the registers that use offsets at 0x800 and above.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index aa66f5169ab..4550ff7ffde 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4287,6 +4287,7 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_FAR_EL1, + .nv2_redirect_offset = 0x220 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), .resetvalue = 0, }, }; @@ -4302,6 +4303,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TTBR0_EL1, + .nv2_redirect_offset = 0x200 | NV2_REDIR_NV1, .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, @@ -4309,6 +4311,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TTBR1_EL1, + .nv2_redirect_offset = 0x210 | NV2_REDIR_NV1, .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, @@ -5741,6 +5744,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, .access = PL1_RW, .accessfn = access_nv1, + .nv2_redirect_offset = 0x230 | NV2_REDIR_NV1, .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, @@ -5760,6 +5764,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, + .nv2_redirect_offset = 0x240, .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP, .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, @@ -6882,9 +6887,11 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = { .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, + .nv2_redirect_offset = 0x500, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, + .nv2_redirect_offset = 0x508, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, }; @@ -9548,6 +9555,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_RW, .writefn = vbar_write, .accessfn = access_nv1, .fgt = FGT_VBAR_EL1, + .nv2_redirect_offset = 0x250 | NV2_REDIR_NV1, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue = 0 }, From patchwork Thu Jan 11 11:05:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27DB8C4725D for ; Thu, 11 Jan 2024 11:10:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssT-0001Rb-J8; Thu, 11 Jan 2024 06:05:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssL-0001PP-IU for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssH-0004Xm-UR for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:29 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3374eb61cbcso4674300f8f.0 for ; Thu, 11 Jan 2024 03:05:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971123; x=1705575923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WQZ9joUzytLik4j8W+c4JeBQFuz0jyAB3AYXVmNfQ3M=; b=yIFQmENbNTkWx9E2R+KHebFYaEm+GKWSKrT6/F8Pk6QqtGh/g+Ky1Edk2yw8s778Li I5KT9Xaft6O3AeuWzVM+Rcik4k1RYAlniiGpCUZBBFqv6dNweclKb6U/43tq5tOMJvbu aR2bnjUtxPUEqSDStwGZ7N/FGqlfLBPl783GAYydf2z0N9FwlWUQwk1DUSr6o88d9Ep2 p6BH/kWmqLVFkn6i9jbSHoCbrATdV0xYNtS42Rv4UADckzCTPPOsovcjKLMFuDFT1+xU yw5dLN5oyPSKbj4qjz5TjPJQi4IwVrmwwXuojzwUVoINYysch2VNelbh79uNxqn7RqZO ZLDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971123; x=1705575923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WQZ9joUzytLik4j8W+c4JeBQFuz0jyAB3AYXVmNfQ3M=; b=RknYjNfVR/3nPoyFnEezSkb7LMsEUANfsVWLjdezdTqFPOkzDuekP97K1vstPwxGN+ 8g+uvPBoOkROxdT2HFiER0/ZgJg86XYz9GmcgxJTnG8oRS2KBgmgVarBIoZy+4J0eddq IaG5mGbvKGj3/KwaCW+7qe3fwImPQ6HrQqXzoUdoHg/1MjxrQn62KlroHgeSbZbPbshO sb66XPRp12q3Yt5vWk1LuIMw/fA+fei3nxyvxZLV5YxT2h82AIBW1MVbxDVZBc5TI2Fj p0rizatqSr005CM/zydI9EiFBJrFOhM2H/NHCIpFs2AEhW5NPjs5Kkn9Axa6Eviy8F8b mdPg== X-Gm-Message-State: AOJu0YwXgay7WywqPWUkkjzON2J7nvn1EVoxKlKsJogYDKlYDrgvNonO SvRri8J//7pfHLfFWXYmfxgc4fNkrZWykZKHAMFDs8vbbi0= X-Google-Smtp-Source: AGHT+IFUI6h5Hgo4RLVvwOug8Mr6DG68K3Z2IiQH7X28Yr3RZZxpKznqaBgX4JQSZHb28NilUFYm/g== X-Received: by 2002:adf:ec48:0:b0:337:61e3:7421 with SMTP id w8-20020adfec48000000b0033761e37421mr546032wrn.44.1704971123589; Thu, 11 Jan 2024 03:05:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/41] hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers Date: Thu, 11 Jan 2024 11:05:02 +0000 Message-Id: <20240111110505.1563291-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Mark up the cpreginfo structs for the GIC CPU registers to indicate the offsets from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- hw/intc/arm_gicv3_cpuif.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 6ac90536402..e1a60d8c15b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2684,6 +2684,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { { .name = "ICH_AP0R0_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 0, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x480, .access = PL2_RW, .readfn = ich_ap_read, .writefn = ich_ap_write, @@ -2691,6 +2692,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { { .name = "ICH_AP1R0_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 0, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x4a0, .access = PL2_RW, .readfn = ich_ap_read, .writefn = ich_ap_write, @@ -2698,6 +2700,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 0, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x4c0, .access = PL2_RW, .readfn = ich_hcr_read, .writefn = ich_hcr_write, @@ -2729,6 +2732,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { { .name = "ICH_VMCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 7, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x4c8, .access = PL2_RW, .readfn = ich_vmcr_read, .writefn = ich_vmcr_write, @@ -2739,6 +2743,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { { .name = "ICH_AP0R1_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 1, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x488, .access = PL2_RW, .readfn = ich_ap_read, .writefn = ich_ap_write, @@ -2746,6 +2751,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { { .name = "ICH_AP1R1_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 1, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x4a8, .access = PL2_RW, .readfn = ich_ap_read, .writefn = ich_ap_write, @@ -2756,6 +2762,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { { .name = "ICH_AP0R2_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 2, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x490, .access = PL2_RW, .readfn = ich_ap_read, .writefn = ich_ap_write, @@ -2763,6 +2770,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { { .name = "ICH_AP0R3_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 3, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x498, .access = PL2_RW, .readfn = ich_ap_read, .writefn = ich_ap_write, @@ -2770,6 +2778,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { { .name = "ICH_AP1R2_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 2, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x4b0, .access = PL2_RW, .readfn = ich_ap_read, .writefn = ich_ap_write, @@ -2777,6 +2786,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { { .name = "ICH_AP1R3_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 3, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x4b8, .access = PL2_RW, .readfn = ich_ap_read, .writefn = ich_ap_write, @@ -2898,6 +2908,7 @@ void gicv3_init_cpuif(GICv3State *s) .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 12 + (j >> 3), .opc2 = j & 7, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0x400 + 8 * j, .access = PL2_RW, .readfn = ich_lr_read, .writefn = ich_lr_write, From patchwork Thu Jan 11 11:05:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E81AC47077 for ; Thu, 11 Jan 2024 11:10:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssW-0001Rn-3t; Thu, 11 Jan 2024 06:05:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssN-0001PU-9N for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssH-0004Yh-V8 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:30 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-336dcebcdb9so4808302f8f.1 for ; Thu, 11 Jan 2024 03:05:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971124; x=1705575924; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1O9OPo4rv9t8UJdjCTvrRPzHe9Vt4uLDECv1wcuWN70=; b=wMDNaPujpnQPBfJ9xvfuTuuPAA+YWgj1m3fAwfdt3KDEGAsGHvNReHu9tfE0+tLyXn NwJIc7UIKJm85qNLAUPEEOK13P0Q35555pbBY97tQiQSJBI6T/GfwntnM1YsR55vAyZF RI0ZSRA9p0glZqbcOJdz7LfrOVmGQWlwjqGk2r3ePGdatLQ9FQcj4iHz+pz9fWjQdXiC 5NCtMmeIeuAD6TYJVebJ3CO4BH9q7EzVUCmm+9THB1E5sGj6DuQ6RVtevHkhNxSqnkX5 JrZD78jiKKc9O6pM+18Cw3Wj4Z1pq4O41Cm4H2mPEp8sx2Yo5IgcSPJ9RsNceiNHssaV 8Zjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971124; x=1705575924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1O9OPo4rv9t8UJdjCTvrRPzHe9Vt4uLDECv1wcuWN70=; b=VzdHbEC3/7oVXKPskWP+Olw4MTLG7XYxu3Mo4yIuwrzj+2DjY4w8lXuoWWBTjBVm4t PmWnDwuBh7DH72f/KZVBibbIDPy6ED1elCc1yMMC9s4KjNSNMykGUupcDHW8MktbmG5d 28V31SOlxReEfgOJvk18JxRUsTrrg8qiua/nXfOuK+/z+dISDKtqtHx9+ZkgeAk//372 5nzhRccvkKjHS9nbxIqJxmoXwWaLmIFlCVjhzvjvCwQSex0I3RLbIkVdQrgz1QZuSw1y pScbpZhfKJ1QLGXBAkbh9h2t2qiTdo4xHR0MYhHk9Wl/CywDlrByGNV7XZCkRRdS0goj EeCQ== X-Gm-Message-State: AOJu0Yzo/KJ/jbl3TZ5uDhXklV5nK+OPhXnYnCghoh8TmSkLjTB2nS62 0IVz9IWoNP91fscp/sAvCalNrKVEukqLdpvXLQR9LRPVdsQ= X-Google-Smtp-Source: AGHT+IH4W7Dw0MasedjXLlQVGTq317Xp5Hq4Gb0B7kyRQA/AmhYZ7ZfHc+SLBRw9CvRZ0zobmVOqMQ== X-Received: by 2002:adf:ebc8:0:b0:337:4d36:ae41 with SMTP id v8-20020adfebc8000000b003374d36ae41mr265708wrn.35.1704971124034; Thu, 11 Jan 2024 03:05:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/41] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps Date: Thu, 11 Jan 2024 11:05:03 +0000 Message-Id: <20240111110505.1563291-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When interpreting CPU dumps where FEAT_NV and FEAT_NV2 are in use, it's helpful to include the values of HCR_EL2.{NV,NV1,NV2} in the CPU dump format, as a way of distinguishing when we are in EL1 as part of executing guest-EL2 and when we are just in normal EL1. Add the bits to the end of the log line that shows PSTATE and similar information: PSTATE=000003c9 ---- EL2h BTYPE=0 NV NV2 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c15ad52ab3d..7d763786d88 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1059,6 +1059,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) uint32_t psr = pstate_read(env); int i, j; int el = arm_current_el(env); + uint64_t hcr = arm_hcr_el2_eff(env); const char *ns_status; bool sve; @@ -1096,6 +1097,10 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) if (cpu_isar_feature(aa64_bti, cpu)) { qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); } + qemu_fprintf(f, "%s%s%s", + (hcr & HCR_NV) ? " NV" : "", + (hcr & HCR_NV1) ? " NV1" : "", + (hcr & HCR_NV2) ? " NV2" : ""); if (!(flags & CPU_DUMP_FPU)) { qemu_fprintf(f, "\n"); return; From patchwork Thu Jan 11 11:05:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA948C47077 for ; Thu, 11 Jan 2024 11:09:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNsso-0001nE-7D; Thu, 11 Jan 2024 06:05:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssL-0001PM-78 for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssH-0004Yq-Uv for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:28 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40e54b2e437so22224185e9.2 for ; Thu, 11 Jan 2024 03:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971124; x=1705575924; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dPASAMQebICClfujL1GDn0UotimEe/hhOLtey9oE2+o=; b=Q/05WpzGsDdIawxHn9Z30sZQqyGHZ/PLccuxBrgFbl4TBXAuNIHoeMUFpoGPOZjM05 4KGdUwS0AUpzTT/OKxuU/zxtDYliCjnq/iL7xFiVqER12fOzBn2+E7+FY5E3sjGyArEr kVXhvzixdkJIjgllAkAu80Ncce6l+6FKHz+dljbjVEIbChxheNSD+QW4et2gfhCV/LyB kEBiSw/1LEu9HnYDS0/hlqDOA8AmY4X7f5u0gx55kMrl+yysdk1qWqqcP8CoE7g+Am6e 82vdg91YJzlQaq7xxIYWIPj76PILcjID30pF15jz+OxRO9a3GyOipQKNiQ5sFWvS85aA 6zww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971124; x=1705575924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dPASAMQebICClfujL1GDn0UotimEe/hhOLtey9oE2+o=; b=k7RdBBZO7WzqVoqD6KVbJDcUe12S0mYSMEYpnxgqCLdw/pj1jkH2mRbUhzWt2BTXsx SeLKKymHxLMZimetvgn0HVtqj1uY1qj1WRFc+XcGakxbcJ+s84gaMrofdVtYNaakn971 U2iuY98SXEcGWAywiLZggA2+CJ7sCX6l9zTd/PzcGMIJVekQQSC5ZTdc0Oo3E/fHdopw 9IlxebuxkmO3DoLR6xB1w/AF/2zpOW4yj+fEbgbiqGsNCiJdkJsYkcCLDcnQLmE+B3LN MSdtFfTb3X69ckpUM2G7abAo6R+sW8NzHT+GwuMLU6OCUwH0lyHCtC8uQaoB1GOQskwS KoMg== X-Gm-Message-State: AOJu0YzuuPGGPxW4++B5rc+HbsnzBmIsoDLbutoz6aqEtDdHdGuJOnx9 gXSOf0aHrj52iH4beGYRV5wgMu1Wjc/fvxjsHT4UpXtSHiM= X-Google-Smtp-Source: AGHT+IGMwvcc6BqpGSa5vGtMqKVa0Wze5Pp2NTg4jhuwMcqLBsNLz+/6cei7AYMHxs5mduWsKEbT2w== X-Received: by 2002:a05:600c:3c83:b0:40e:4d77:dbf7 with SMTP id bg3-20020a05600c3c8300b0040e4d77dbf7mr298265wmb.163.1704971124385; Thu, 11 Jan 2024 03:05:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/41] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry Date: Thu, 11 Jan 2024 11:05:04 +0000 Message-Id: <20240111110505.1563291-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We already print various lines of information when we take an exception, including the ELR and (if relevant) the FAR. Now that FEAT_NV means that we might report something other than the old PSTATE to the guest as the SPSR, it's worth logging this as well. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4550ff7ffde..dc8f14f4331 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11416,6 +11416,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; + qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%x\n", old_mode); qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); From patchwork Thu Jan 11 11:05:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13517189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFD8BC4725D for ; Thu, 11 Jan 2024 11:09:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNssV-0001Rl-Gf; Thu, 11 Jan 2024 06:05:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNssN-0001PW-9b for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:31 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNssI-0004Z7-2m for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:30 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-33677fb38a3so4874139f8f.0 for ; Thu, 11 Jan 2024 03:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971124; x=1705575924; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AoPQ2VhrOauUZxXZpUbSBMmD7E3ILO63LwCrzpMDSt8=; b=ITIOxvywMw7zpBoPRuxxeCHqdygMdY+MSvbAHG9SG0MAE33B9oAFlFApIHmfrctb0j Sf19gl7y7SMms0PgTfENZ4YKiQF6L86RJQoYtNYtsfN3hU0SD/VFDTsqVRSrBhQIt0VW poRb11IJULhjV35r/prHfvhhsN1N6oL9k/t81NLcm8D9WJxTpP/iT9vUh/PdCC6FthMA Vx5jAG5ZvgVhFOBsdvJ7E4KyUyiHO7o+DWoxV9oAX3FN1qbVj/JFNlMlXeTBIi89jdrM /wzB/riSYfEIHNxJdajYmFT0IIIRQHpN8WVBawBrB4EgHT/HXeD84B6O8w7gnPgBDN6h EY6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971124; x=1705575924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AoPQ2VhrOauUZxXZpUbSBMmD7E3ILO63LwCrzpMDSt8=; b=r/AhRMNVUBjIKvW74YUWU+atOeIXrLCzexN5iWRyZWic9sedi4YO1sPVxqNQ5nD2DO uMdCPyz8tvRM7nrVDYI0fBd00L/WwjP2uSIaOh4ENKy1HfHgyZDQ0afCOROMI8s7+JSm cOR9i4Ajepn4WnWHFaARV3SxdHGOLNdV7Gt8fh4z3f5YOAsWWJNlzggodaONhai8f5ae DeUgCNhZUbqCOztTr8kYIkVERJv6oBwqC199CslQh3EqREOAqdPIelJLY+UGEy8pSfNa 1M4hBhptYkfO2ah0tj8hLu3ljXjnUdAE2mq8qD7NI7p1MRNMixQL3TwrPxqtYzaZjgXb up3w== X-Gm-Message-State: AOJu0YwD75YaYdPIgDHQxvNkIB+8rD2LTkDI2y1KtYbvOQkoy9a6ByFH bY01wMJS9KOU8NfzKb0PJadXv7VbZhY7Wyxayg6dGx8edm8= X-Google-Smtp-Source: AGHT+IH7dGrEWBAsrZm8WfGyLEGWPtxAbGI1iVvka8+Hk/oEoryHVsroecxPDirFfD1ZxyvGx53Ckg== X-Received: by 2002:adf:ef43:0:b0:336:6797:485c with SMTP id c3-20020adfef43000000b003366797485cmr511605wrp.27.1704971124763; Thu, 11 Jan 2024 03:05:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/41] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs Date: Thu, 11 Jan 2024 11:05:05 +0000 Message-Id: <20240111110505.1563291-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable FEAT_NV2 on the 'max' CPU, and stop filtering it out for the Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 5 ----- target/arm/tcg/cpu64.c | 2 +- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index d827b42de79..f67aea2d836 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -64,6 +64,7 @@ the following architecture extensions: - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) - FEAT_NV (Nested Virtualization) +- FEAT_NV2 (Enhanced nested virtualization support) - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) - FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm) - FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7d763786d88..826ce842c09 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2243,11 +2243,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); - /* FEAT_NV2 (Enhanced Nested Virtualization support) */ - if (FIELD_EX64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV) > 1) { - cpu->isar.id_aa64mmfr2 = - FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 1); - } } /* MPU can be configured out of a PMSA CPU either by setting has-mpu diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 93f040e6e96..5fba2c0f040 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1204,7 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ - t = FIELD_DP64(t, ID_AA64MMFR2, NV, 1); /* FEAT_NV */ + t = FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* FEAT_NV2 */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */