From patchwork Fri Jan 12 09:59:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jedrzej Jagielski X-Patchwork-Id: 13518198 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E4BE57877 for ; Fri, 12 Jan 2024 10:09:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DGpGSF/v" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705054186; x=1736590186; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KYlwYu/JnYFP0dZJ9hFqUmlC0ICBzK/58VCU/teM4uE=; b=DGpGSF/vdVbG8amWWVrmcHgzqn3MRfEx/PBjPwDNxghnyEXaPP6mwILN AjhgsVJsJEQVZOliT1MHmEn2+tpBcHBM5CCOrrLKYNPES4/HeS5BYXVEG JJq8HFc90BQHLVMnvVgzqXzksImWhtYSzo3r5eBzcjdhqXC9g2xBSiAJ8 Azk1M5K3jw2nRDzVdNskAiVA9Qd7GQaNrF5GdEhqrha/DrRJYmfop9JOB aMF/l3HJcrJO8d1f6jVxWnTytu28oBIcpx6ZKbx2yMKelPk5pa5o5Ncev Df6THP3XPG0EfGdE1UzVlx0SkCptyV08kOOfp/rDwq/UkJJzCkztcA0wp w==; X-IronPort-AV: E=McAfee;i="6600,9927,10950"; a="5867349" X-IronPort-AV: E=Sophos;i="6.04,189,1695711600"; d="scan'208";a="5867349" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2024 02:09:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10950"; a="759083275" X-IronPort-AV: E=Sophos;i="6.04,189,1695711600"; d="scan'208";a="759083275" Received: from os-delivery.igk.intel.com ([10.102.18.218]) by orsmga006.jf.intel.com with ESMTP; 12 Jan 2024 02:09:29 -0800 From: Jedrzej Jagielski To: intel-wired-lan@lists.osuosl.org Cc: anthony.l.nguyen@intel.com, netdev@vger.kernel.org, Przemyslaw R Karpinski , Aleksandr Loktionov , Jedrzej Jagielski Subject: [PATCH iwl-next v1 1/2] i40e: Add read alternate indirect command Date: Fri, 12 Jan 2024 10:59:44 +0100 Message-Id: <20240112095945.450590-2-jedrzej.jagielski@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240112095945.450590-1-jedrzej.jagielski@intel.com> References: <20240112095945.450590-1-jedrzej.jagielski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Przemyslaw R Karpinski Introduce implementation of 0x0903 Admin Queue command. This indirect command reads a block of data from the alternate structure of memory. The command defines the number of Dwords to be read and the starting address inside the alternate structure. Reviewed-by: Aleksandr Loktionov Signed-off-by: Przemyslaw R Karpinski Signed-off-by: Jedrzej Jagielski --- .../net/ethernet/intel/i40e/i40e_adminq_cmd.h | 4 +- drivers/net/ethernet/intel/i40e/i40e_common.c | 40 +++++++++++++++++++ .../net/ethernet/intel/i40e/i40e_prototype.h | 3 ++ 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h index 18a1c3b6d72c..50785f7e6d08 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h +++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h @@ -1983,14 +1983,14 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); * Indirect read (indirect 0x0903) */ -struct i40e_aqc_alternate_ind_write { +struct i40e_aqc_alternate_ind_read_write { __le32 address; __le32 length; __le32 addr_high; __le32 addr_low; }; -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); +I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_read_write); /* Done alternate write (direct 0x0904) * uses i40e_aq_desc diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c index de6ca6295742..93971c9c98cc 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_common.c +++ b/drivers/net/ethernet/intel/i40e/i40e_common.c @@ -4375,6 +4375,46 @@ static int i40e_aq_alternate_read(struct i40e_hw *hw, return status; } +/** + * i40e_aq_alternate_read_indirect + * @hw: pointer to the hardware structure + * @addr: address of the alternate structure field + * @dw_count: number of alternate structure fields to read + * @buffer: pointer to the command buffer + * + * Read 'dw_count' dwords from alternate structure starting at 'addr' and + * place them in 'buffer'. The buffer should be allocated by caller. + * + **/ +int i40e_aq_alternate_read_indirect(struct i40e_hw *hw, u32 addr, u32 dw_count, + void *buffer) +{ + struct i40e_aqc_alternate_ind_read_write *cmd_resp; + struct i40e_aq_desc desc; + int status; + + if (!buffer) + return -EINVAL; + + cmd_resp = (struct i40e_aqc_alternate_ind_read_write *)&desc.params.raw; + + i40e_fill_default_direct_cmd_desc(&desc, + i40e_aqc_opc_alternate_read_indirect); + + desc.flags |= cpu_to_le16(I40E_AQ_FLAG_RD); + desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); + if (dw_count > I40E_AQ_LARGE_BUF / 4) + desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); + + cmd_resp->address = cpu_to_le32(addr); + cmd_resp->length = cpu_to_le32(dw_count); + + status = i40e_asq_send_command(hw, &desc, buffer, + lower_16_bits(4 * dw_count), NULL); + + return status; +} + /** * i40e_aq_suspend_port_tx * @hw: pointer to the hardware structure diff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h index af4269330581..37c23a0bded6 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h +++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h @@ -322,6 +322,9 @@ i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, u8 filter_count); int i40e_read_lldp_cfg(struct i40e_hw *hw, struct i40e_lldp_variables *lldp_cfg); + +int i40e_aq_alternate_read_indirect(struct i40e_hw *hw, u32 addr, u32 dw_count, + void *buffer); int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, struct i40e_asq_cmd_details *cmd_details); From patchwork Fri Jan 12 09:59:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jedrzej Jagielski X-Patchwork-Id: 13518197 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A26E65D8F2 for ; Fri, 12 Jan 2024 10:09:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TmOsH2l1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705054174; x=1736590174; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZvFke+XRGhfOl7Lb4+LszHZJfWeFfUICHvr9mpX/hxs=; b=TmOsH2l1KrMbgakXSEPIgpqMx5ICRIxTQbtdoyrQkyGMx5sLxYUzSmKv ckHFrKDKE8KzzxMX14Gz4NvGFhquP4sTKu3fM0MMw0E/rbFUelJDMkG7e Y1tXM9zFQJrTmgVInMYlPmT0NGraP1oBGcZMhq1ElGzyIPUbCOlN1hn52 y5AODIjp7lvRx/sD3rg6W/Bq3MU4h3fyLNkNZaGGS7bZfJhd28suuBEKT aw4BbjRNXmKhSi5lo3RmP0gJSDytMvkphQ5dhBmgk24jlRFl/fuZbGGk7 wSA7i6NjnxYQkABs+sn9bsSn2s9w5YwvK923wXf4cbr/sh/YeqgKRuKIF A==; X-IronPort-AV: E=McAfee;i="6600,9927,10950"; a="5867355" X-IronPort-AV: E=Sophos;i="6.04,189,1695711600"; d="scan'208";a="5867355" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2024 02:09:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10950"; a="759083278" X-IronPort-AV: E=Sophos;i="6.04,189,1695711600"; d="scan'208";a="759083278" Received: from os-delivery.igk.intel.com ([10.102.18.218]) by orsmga006.jf.intel.com with ESMTP; 12 Jan 2024 02:09:31 -0800 From: Jedrzej Jagielski To: intel-wired-lan@lists.osuosl.org Cc: anthony.l.nguyen@intel.com, netdev@vger.kernel.org, Jedrzej Jagielski , Jan Sokolowski Subject: [PATCH iwl-next v1 2/2] i40e-linux: Add support for reading Trace Buffer Date: Fri, 12 Jan 2024 10:59:45 +0100 Message-Id: <20240112095945.450590-3-jedrzej.jagielski@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240112095945.450590-1-jedrzej.jagielski@intel.com> References: <20240112095945.450590-1-jedrzej.jagielski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Currently after entering FW Recovery Mode we have no info in logs regarding current FW state. Add function reading content of the alternate RAM storing that info and print it into the log. Additionally print state of CSR register. Reviewed-by: Jan Sokolowski Signed-off-by: Jedrzej Jagielski --- drivers/net/ethernet/intel/i40e/i40e.h | 2 ++ drivers/net/ethernet/intel/i40e/i40e_main.c | 35 +++++++++++++++++++ .../net/ethernet/intel/i40e/i40e_register.h | 2 ++ drivers/net/ethernet/intel/i40e/i40e_type.h | 5 +++ 4 files changed, 44 insertions(+) diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h index ba24f3fa92c3..6ebd2fd15e0e 100644 --- a/drivers/net/ethernet/intel/i40e/i40e.h +++ b/drivers/net/ethernet/intel/i40e/i40e.h @@ -23,6 +23,8 @@ /* Useful i40e defaults */ #define I40E_MAX_VEB 16 +#define I40_BYTES_PER_WORD 2 + #define I40E_MAX_NUM_DESCRIPTORS 4096 #define I40E_MAX_NUM_DESCRIPTORS_XL710 8160 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index 4977ff391fed..f5abe8c9a88d 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -15414,6 +15414,39 @@ static int i40e_handle_resets(struct i40e_pf *pf) return is_empr ? -EIO : pfr; } +/** + * i40e_log_fw_recovery_mode - log current FW state in Recovery Mode + * @pf: board private structure + * + * Read alternate RAM and CSR registers and print them to the log + **/ +static void i40e_log_fw_recovery_mode(struct i40e_pf *pf) +{ + u8 buf[I40E_FW_STATE_BUFF_SIZE] = {0}; + struct i40e_hw *hw = &pf->hw; + u8 fws0b, fws1b; + u32 fwsts; + int ret; + + ret = i40e_aq_alternate_read_indirect(hw, I40E_ALT_CANARY, + I40E_ALT_BUFF_DWORD_SIZE, buf); + if (ret) { + dev_warn(&pf->pdev->dev, + "Cannot get FW trace buffer due to FW err %d aq_err %s\n", + ret, i40e_aq_str(hw, hw->aq.asq_last_status)); + return; + } + + fwsts = rd32(&pf->hw, I40E_GL_FWSTS); + fws0b = FIELD_GET(I40E_GL_FWSTS_FWS0B_MASK, fwsts); + fws1b = FIELD_GET(I40E_GL_FWSTS_FWS1B_MASK, fwsts); + + print_hex_dump(KERN_DEBUG, "Trace Buffer: ", DUMP_PREFIX_NONE, + BITS_PER_BYTE * I40_BYTES_PER_WORD, 1, buf, + I40E_FW_STATE_BUFF_SIZE, true); + dev_dbg(&pf->pdev->dev, "FWS0B=0x%x, FWS1B=0x%x\n", fws0b, fws1b); +} + /** * i40e_init_recovery_mode - initialize subsystems needed in recovery mode * @pf: board private structure @@ -15497,6 +15530,8 @@ static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw) mod_timer(&pf->service_timer, round_jiffies(jiffies + pf->service_timer_period)); + i40e_log_fw_recovery_mode(pf); + return 0; err_switch_setup: diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h index 14ab642cafdb..8e254ff9c035 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_register.h +++ b/drivers/net/ethernet/intel/i40e/i40e_register.h @@ -169,6 +169,8 @@ #define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0 #define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT) #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ +#define I40E_GL_FWSTS_FWS0B_SHIFT 0 +#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT) #define I40E_GL_FWSTS_FWS1B_SHIFT 16 #define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) #define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT) diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h index 725da7edbca3..0372a8d519ad 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_type.h +++ b/drivers/net/ethernet/intel/i40e/i40e_type.h @@ -1372,6 +1372,11 @@ struct i40e_lldp_variables { #define I40E_ALT_BW_VALUE_MASK 0xFF #define I40E_ALT_BW_VALID_MASK 0x80000000 +/* Alternate Ram Trace Buffer*/ +#define I40E_ALT_CANARY 0xABCDEFAB +#define I40E_ALT_BUFF_DWORD_SIZE 0x14 /* in dwords */ +#define I40E_FW_STATE_BUFF_SIZE 80 + /* RSS Hash Table Size */ #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000