From patchwork Sat Jan 13 20:55:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13519057 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FEE1D297 for ; Sat, 13 Jan 2024 20:55:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sOX3yMWl" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-50ea9e189ebso8471157e87.3 for ; Sat, 13 Jan 2024 12:55:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705179354; x=1705784154; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1plu6Fal9qcn1Wtuu6vQETPtirp4Q/rK0fLCOiwCIQY=; b=sOX3yMWlrYTCA72q6WHJDSVm5xlCpqai8be1yV2bVl0Xkjkv72aSE7cn4ov3WM4tix w5O6aWEYmKfBmpkExmOa4ionDobEG/4dCtVWGoyU3jrRFl2jKDhWtjRNt04U8KhhqTRX MpDv/CBZXGfbY89/xdiq1mewkA/JgWg2311eUKeBGDiDNk3CY+JTDX7iTFtJQ3569A0Z YgOL1slt80x8/ERl2hqmhG9J4i2sdgGDElkWXJX6t9BSxGAqOGX6zQCncuK2lC/fwnXP Ncvpqhok0oAkIa8hDUNTvS7EtnXkhql8JjBZMn4UslAuEraCx5WVB7gLDB1jitZepD4j mICQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705179354; x=1705784154; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1plu6Fal9qcn1Wtuu6vQETPtirp4Q/rK0fLCOiwCIQY=; b=LSqqQXdyDgaxDBGh4PQFTDbcieepKp+YyC9GNTtS0kcQDmDBH/kuTZ9kYTSR/r/Dn9 DfJhguQJdl30Y+cYYsyUvuEONHdWeBruC+IqoVZvZCQVcALEAZxiJdAKa66vNFwhKAK/ n6ZPXZizAhiuOnhAJGTV2lqJeULFT53NPpFgLbao/8ZHlwxngE6NpT++jez+Os0P8KNa SJquLuvEtRZpvpVQ8r+OA2376vwn9b+aeQ+oaOPqMDBCPk/m1IdHvPXISNnVndoIfD1V C+37JxEE0CIOnxNNIe9H0R1CIhN0r371obOx4OZKyysJ28FZA5QVOJI4mhfD/moZ5z/O 1+bQ== X-Gm-Message-State: AOJu0YwbVvfERUiOcagPNB3bIOAwbjHP9GJPqWGQsXICvpOePmbhmwZY U3Jv61iIjzHWQIZqm1RjwP8F5DfTy+sa+w== X-Google-Smtp-Source: AGHT+IHORlq9+U1/d6OKAala6qvGFXXcT/6vQiMppG/2djQE9ccrg+xAnQp4SuIWs9e263XdPhtkkg== X-Received: by 2002:a05:6512:1093:b0:50e:76ca:f772 with SMTP id j19-20020a056512109300b0050e76caf772mr1858405lfg.32.1705179354550; Sat, 13 Jan 2024 12:55:54 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id p14-20020a056512328e00b0050e9355d7eesm919802lfe.103.2024.01.13.12.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 12:55:53 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:44 +0200 Subject: [PATCH v2 01/15] dt-bindings: regulator: qcom,usb-vbus-regulator: add support for PMI632 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-1-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1073; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=VO6sCRtukMYbFqUkroEE9VOEtJ3mqzFoVaUfeIJHtBE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjW7nZvT4zErpZjmTbBBPpayrTlb/U+ld6ZT TNO51eWMViJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41gAKCRCLPIo+Aiko 1aKRB/9T87tU2zgTRJrbRdVu/6xwFDLYjttlV8t8cBlJkGj6+rNwF/WsD3D4S6v4zHiQSxjLSBH rk6JLOaz5bzEYv2q6OdZRT1yd2b5VXDhqwkOs9ofgCkv8ukCADqL5nplKN9hxwRBMR3kVNEUZLB vkXnWnSimW09fQIxo5gY2l5DbeZP+zvuwV9CDGxIVF//Q/1hhfve4JuF7nvp+gYbaFBJSW9K6H4 id1sh/0OYL6qzsCqphACfPchFXreLG1XnE1piM0TmFSLJxnwF5xMrk0WEV1MhhUgAM/j6LBs1Ng SYUbuwFIoGwU0oooy+x14OtaPUAmGCcBbkXBBXuWHKpDm59V X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The VBUS register block on the PMI632 PMIC shares the design with the PM8150B one. Define corresponding compatible string, having the qcom,pm8150b-vbus-reg as a fallback. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml index 534f87e98716..66dcd5ce03e6 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml @@ -19,8 +19,13 @@ allOf: properties: compatible: - enum: - - qcom,pm8150b-vbus-reg + oneOf: + - enum: + - qcom,pm8150b-vbus-reg + - items: + - enum: + - qcom,pmi632-vbus-reg + - const: qcom,pm8150b-vbus-reg reg: maxItems: 1 From patchwork Sat Jan 13 20:55:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13519058 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 101ACE544 for ; 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Sat, 13 Jan 2024 12:55:55 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id p14-20020a056512328e00b0050e9355d7eesm919802lfe.103.2024.01.13.12.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 12:55:54 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:45 +0200 Subject: [PATCH v2 02/15] dt-bindings: usb: qcom,pmic-typec: add support for the PMI632 block Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-2-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2092; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=71F8jVd5iMgdX+Ru5jFbd+dpcbcyYwGu9AyNI4zYLro=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjWHWJGIEWuyWFCPqYkzM6IzpKV8gOkx8Esq QsiBZqNKj6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41gAKCRCLPIo+Aiko 1V7yB/9/aC+T00w8ryeVp6EZx+UEg7KhneVJxRzKWOYpLi3HfkqUHBsgUTekq/mqCdUcOJEYmy3 I/BlFAsDsHkUWJzHruLomFa0fVRIeXAA0/QBuDsJ4Wj52WlvBO0NiEMOjCoWDX6RO3vfw8krun1 fVvp/lyNQXQNifOqUhZBBSanj9C1pjGQ7KvrGHeWvm3YjwZ4YulhKiep0mcoPSdfNLqZ2ZSqdxu bTwuHhot8B9NzoVSIbtliKnmvf8p28qOY6B8JDJ72mx3Zf40Vtq5IQwhcEL7J6jxAEMebJ43kcv ElsYoKuvQBlLclxMb/TYbjBh8TZfjYa+B8ORP41Pdv4NDgpa X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The PMI632 PMIC has the same Type-C register block as the PM8150B. However this PMIC doesn't support USB Power Delivery. As such it doesn't have the second region used by the existing pm8150b bindings. Add if clauses to handle the PMI632 usecase. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/usb/qcom,pmic-typec.yaml | 28 +++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml index 55df3129a0bc..e9f44750d580 100644 --- a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml @@ -15,6 +15,7 @@ description: properties: compatible: enum: + - qcom,pmi632-typec - qcom,pm8150b-typec connector: @@ -24,9 +25,11 @@ properties: reg: description: Type-C port and pdphy SPMI register base offsets + minItems: 1 maxItems: 2 interrupts: + minItems: 8 items: - description: Type-C CC attach notification, VBUS error, tCCDebounce done - description: Type-C VCONN powered @@ -46,6 +49,7 @@ properties: - description: Power Domain Fast Role Swap event interrupt-names: + minItems: 8 items: - const: or-rid-detect-change - const: vpd-detect @@ -81,7 +85,29 @@ required: - interrupts - interrupt-names - vdd-vbus-supply - - vdd-pdphy-supply + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pmi632-typec + then: + properties: + interrupts: + maxItems: 8 + interrupt-names: + maxItems: 8 + vdd-pdphy-supply: false + else: + properties: + interrupts: + minItems: 16 + interrupt-names: + maxItems: 16 + required: + - vdd-pdphy-supply additionalProperties: false From patchwork Sat Jan 13 20:55:46 2024 Content-Type: text/plain; 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Sat, 13 Jan 2024 12:55:56 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id p14-20020a056512328e00b0050e9355d7eesm919802lfe.103.2024.01.13.12.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 12:55:55 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:46 +0200 Subject: [PATCH v2 03/15] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: split from sc8280xp PHY schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-3-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5562; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=CnztgRTnoisu3CgikOKmKjlZnjUtPFGoAOLDjHVdlrc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjWgSDszgG526QkzvdPnaAay8pbdMhtePPnI JsmmL70clGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41gAKCRCLPIo+Aiko 1d3OB/9zvU6LOrEM7HZqtFBq2HMJAhMv70IISGUt0BPYKRQwc8/4qjysO+eQDKHFBZ43WIGgiLO o1q01crazGs28C45IMOjCqoHSh/3iGKMYcgCwXbxcQnXLIXaaoj41jxw+ZIsxDUm23GbDxbE+W6 TBR2JqH48e6HAVk51iPYD00mn4dbPTg0SJKlTagYuekPxGKUoXw904YJ6zahRqbkfy9E6RpgDo+ buiySKkig+2fEourHLVpTqYZTzP15dR3v2dL7GtwhuOXE9Wt8bb8aGYQN1M6sZB/UZOEFssYNbJ +Gn84Xh0hh72lCXxVi0VneTTpbJOdQKV44gp4H92dy4Hrgjk X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A In preparation to defining the USB-C handling on MSM8998, QCM2290 and SM6115 split existing QMP USB3 PHY schema into pure USB3 and USB-C schema definitions. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 132 +++++++++++++++++++++ .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 22 ---- 2 files changed, 132 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml new file mode 100644 index 000000000000..868fabd44d72 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (USB, MSM8998) + +maintainers: + - Vinod Koul + +description: + The QMP PHY controller supports physical layer functionality for USB-C on + several Qualcomm chipsets. + +properties: + compatible: + enum: + - qcom,msm8998-qmp-usb3-phy + - qcom,qcm2290-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: phy_phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_ahb + - const: ref + - const: com_aux + - const: pipe + +additionalProperties: false + +examples: + - | + #include + #include + + phy@c010000 { + compatible = "qcom,msm8998-qmp-usb3-phy"; + reg = <0x0c010000 0x1000>; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3_phy_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index 15d82c67f157..1e2d4ddc5391 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -20,15 +20,12 @@ properties: - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - - qcom,msm8998-qmp-usb3-phy - - qcom,qcm2290-qmp-usb3-phy - qcom,sa8775p-qmp-usb3-uni-phy - qcom,sc8280xp-qmp-usb3-uni-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy - qcom,sdx75-qmp-usb3-uni-phy - - qcom,sm6115-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-usb3-uni-phy - qcom,sm8350-qmp-usb3-uni-phy @@ -93,7 +90,6 @@ allOf: - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - - qcom,msm8998-qmp-usb3-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy - qcom,sdx75-qmp-usb3-uni-phy @@ -108,24 +104,6 @@ allOf: - const: cfg_ahb - const: pipe - - if: - properties: - compatible: - contains: - enum: - - qcom,qcm2290-qmp-usb3-phy - - qcom,sm6115-qmp-usb3-phy - then: - properties: - clocks: - maxItems: 4 - clock-names: - items: - - const: cfg_ahb - - const: ref - - const: com_aux - - const: pipe - - if: properties: compatible: From patchwork Sat Jan 13 20:55:47 2024 Content-Type: text/plain; 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Sat, 13 Jan 2024 12:55:57 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id p14-20020a056512328e00b0050e9355d7eesm919802lfe.103.2024.01.13.12.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 12:55:56 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:47 +0200 Subject: [PATCH v2 04/15] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support USB-C data Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-4-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml index 868fabd44d72..da5d4cbca24c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -50,6 +50,22 @@ properties: "#phy-cells": const: 0 + orientation-switch: + description: + Flag the PHY as possible handler of USB Type-C orientation switching + type: boolean + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the PHY + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB controller + required: - compatible - reg @@ -129,4 +145,27 @@ examples: vdda-phy-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l2a_1p2>; + + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&pmic_typec_mux_in>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; }; From patchwork Sat Jan 13 20:55:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13519061 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80AB3171D8 for ; Sat, 13 Jan 2024 20:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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Sat, 13 Jan 2024 12:55:57 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:48 +0200 Subject: [PATCH v2 05/15] usb: typec: tcpm: fix the PD disabled case Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-5-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1623; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=th0VPhhVwgxzRi9BZeZWRGueot5zBad9lANgJUi6Tq0=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjW6dxyBLqmgIkLKgBNIXZP2morYd4M6kKeF 0II/6WztImJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41gAKCRCLPIo+Aiko 1XoOB/4qZ/5yHK3+7TdrBie0roUiq0G242K8R7XP22EtAdGvBmxWVzee55dJ3/+oHlrEWLpYiw2 DHiVF7OJ/T04vnoqHN8vU0dEEcLmyBFKnkDWphBp4QAdHmbTg0iT+Mwu+2K9Uk8NaUK9mLk5OEU gImtz0ysLNcFI5mqe1mW4WPgD6QE5lMnn3wkNHC2DRpC7t0C+wv/DnjZGqO830bXqSBuzt9fg3s XHHZ8VZGmKb1ZoZZM6+GEtCj3ZooFds2sPN481vkCGiaIpPvuBzQSNtK9VbNuUb+0GSPopAiGhi C6Rc3vDxLup3pyubKVLVMyfD7EOZ5A7a0r8t2zlaWsVdn5RP X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A If the PD is disabled for the port, port->pds will be left as NULL, which causes the following crash during caps intilisation. Fix the crash. Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 Call trace: tcpm_register_port+0xaec/0xc44 qcom_pmic_typec_probe+0x1a4/0x254 platform_probe+0x68/0xc0 really_probe+0x148/0x2ac __driver_probe_device+0x78/0x12c driver_probe_device+0xd8/0x160 Bluetooth: hci0: QCA Product ID :0x0000000a __device_attach_driver+0xb8/0x138 bus_for_each_drv+0x80/0xdc Bluetooth: hci0: QCA SOC Version :0x40020150 __device_attach+0x9c/0x188 device_initial_probe+0x14/0x20 bus_probe_device+0xac/0xb0 deferred_probe_work_func+0x8c/0xc8 process_one_work+0x1ec/0x51c worker_thread+0x1ec/0x3e4 kthread+0x120/0x124 ret_from_fork+0x10/0x20 Fixes: cd099cde4ed2 ("usb: typec: tcpm: Support multiple capabilities") Signed-off-by: Dmitry Baryshkov Reviewed-by: Heikki Krogerus --- drivers/usb/typec/tcpm/tcpm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c index 5945e3a2b0f7..a0978ed1a257 100644 --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c @@ -6848,7 +6848,8 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc) if (err) goto out_role_sw_put; - port->typec_caps.pd = port->pds[0]; + if (port->pds) + port->typec_caps.pd = port->pds[0]; port->typec_port = typec_register_port(port->dev, &port->typec_caps); if (IS_ERR(port->typec_port)) { From patchwork Sat Jan 13 20:55:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13519062 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 449DB18050 for ; Sat, 13 Jan 2024 20:56:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="e1BuafaD" Received: by mail-lj1-f170.google.com with SMTP id 38308e7fff4ca-2cd8b661cb8so27320921fa.0 for ; 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a=openpgp-sha256; l=3329; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=z5+t2zMtCUTK2jAH3Na6Dy0WZ3qbhWesIMT9Xe4mLP0=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjWutHD8dgmfbirhS+ilRzPSltZh4mmoLSRw 7qlo8M1gr+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41gAKCRCLPIo+Aiko 1Ul2CACZOa4wBBNnNriCeL6gs9SGIyTin6NraWodtejNTjEut+tW+Kyau1DYOqb3qSDeSrtEIuv gzWQygA23AfEa/91MziX9+4/F4MPiIrHvrXefEgMJmE47SfDP+wvtde2SdpEJupQ0KoJuc99WY1 EHHPHvR/R+8SGhz2yQvD/XI6ExtpqKOH1PSq5JNLWZ04/3rdytEqVIXijszSTeJTmH7PDlNCe7N braqXqgTx8MK9iMCBlN4scbuQr9Zf1maCVRw5H6j7af4livmCeSeYyOPw+69GFXKnur6zO7PSdU iqcZi+H9BhfTL8n3umcXHL/kDZRu4wcx/jTpXYgULmFcrt4Z X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The function qcom_pmic_typec_set_roles() passes enum values as boolean values to qcom_pmic_typec_pdphy_set_roles(), which then interprets them as bit values. Be more explicit about it, pass enum values directly and compute corresponding bit masks in qcom_pmic_typec_pdphy_set_roles(). Signed-off-by: Dmitry Baryshkov Acked-by: Bryan O'Donoghue Reviewed-by: Bryan O'Donoghue Acked-by: Bryan O'Donoghue --- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c | 2 +- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c | 8 +++++--- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h | 3 ++- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c index 1a2b4bddaa97..a243648abb4a 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c @@ -123,7 +123,7 @@ static int qcom_pmic_typec_set_roles(struct tcpc_dev *tcpc, bool attached, struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); return qcom_pmic_typec_pdphy_set_roles(tcpm->pmic_typec_pdphy, - data_role, power_role); + power_role, data_role); } static int qcom_pmic_typec_set_pd_rx(struct tcpc_dev *tcpc, bool on) diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c index 52c81378e36e..44d8342ed0ad 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c @@ -354,7 +354,8 @@ int qcom_pmic_typec_pdphy_set_pd_rx(struct pmic_typec_pdphy *pmic_typec_pdphy, b } int qcom_pmic_typec_pdphy_set_roles(struct pmic_typec_pdphy *pmic_typec_pdphy, - bool data_role_host, bool power_role_src) + enum typec_role power_role, + enum typec_data_role data_role) { struct device *dev = pmic_typec_pdphy->dev; unsigned long flags; @@ -366,12 +367,13 @@ int qcom_pmic_typec_pdphy_set_roles(struct pmic_typec_pdphy *pmic_typec_pdphy, pmic_typec_pdphy->base + USB_PDPHY_MSG_CONFIG_REG, MSG_CONFIG_PORT_DATA_ROLE | MSG_CONFIG_PORT_POWER_ROLE, - data_role_host << 3 | power_role_src << 2); + (data_role == TYPEC_HOST ? MSG_CONFIG_PORT_DATA_ROLE : 0) | + (power_role == TYPEC_SOURCE ? MSG_CONFIG_PORT_POWER_ROLE : 0)); spin_unlock_irqrestore(&pmic_typec_pdphy->lock, flags); dev_dbg(dev, "pdphy_set_roles: data_role_host=%d power_role_src=%d\n", - data_role_host, power_role_src); + data_role, power_role); return ret; } diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h index e67954e31b14..070822dc6f17 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h @@ -107,7 +107,8 @@ int qcom_pmic_typec_pdphy_start(struct pmic_typec_pdphy *pmic_typec_pdphy, void qcom_pmic_typec_pdphy_stop(struct pmic_typec_pdphy *pmic_typec_pdphy); int qcom_pmic_typec_pdphy_set_roles(struct pmic_typec_pdphy *pmic_typec_pdphy, - bool power_role_src, bool data_role_host); + enum typec_role power_role, + enum typec_data_role data_role); int qcom_pmic_typec_pdphy_set_pd_rx(struct pmic_typec_pdphy *pmic_typec_pdphy, bool on); From patchwork Sat Jan 13 20:55:50 2024 Content-Type: text/plain; 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Sat, 13 Jan 2024 12:55:59 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id p14-20020a056512328e00b0050e9355d7eesm919802lfe.103.2024.01.13.12.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 12:55:58 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:50 +0200 Subject: [PATCH v2 07/15] usb: typec: qcom-pmic-typec: allow different implementations for the PD PHY Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-7-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=18738; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=FpV3mWAJeYNC5njvp3M2TJhjiJJSyONyWk1ydvxodyg=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+qiH9fDvU3Pl/6NLdAtKEt4l15z41SRSVONxw3O5P+ZJ xkWCTJ2MhqzMDByMciKKbL4FLRMjdmUHPZhx9R6mEGsTCBTGLg4BWAivFvZ/8oee+FbZfVd8Xj8 lCncLaZzOn46srxf7HGg6GXn3C+RdQZXDxv1XxNyeu6S+6pB+0Wicrvy7RfXLZkUTsjopk0LPr/ qcajD3DOWwgV8QXGNp7hVVNPzFrsWOq10ks2t+PHxA7OA95TP8maXBV7KJDc+m+rIuuWW4bPgpR +7FZu+ic2rl5GvfPOtSyr/1G1JiZDUzHWu578VCD+33zNVflehx5ncW6l3yjIP/Ov68/jFFKa1r jkO90+WGppp/uB5onW+fMW53N/8RopCykevtPSemCiw4qip1ARtI6XWm6q6CzIUJ8+Qnf1fY22E ZKZv3+K7Iv3HGwVsAn4ULi7f/Wp/tG7WT2cf+9J1wsqtAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Rework Qualcomm PMIC TCPM driver to allow different platform-specific implementations of the PD PHY interface. While majority of platforms has the same of register for the PD PHY, some obscure ones (PMI632) do not have real PD PHY support. Add proper interface between the main module and the PD PHY backend to allow switching the PD PHY implementation. Tested-by: Bryan O'Donoghue Acked-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c | 91 +----------- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h | 25 ++++ .../usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c | 153 ++++++++++++++++++--- .../usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h | 93 +------------ drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h | 4 +- 5 files changed, 171 insertions(+), 195 deletions(-) diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c index a243648abb4a..4c7c38c58a02 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c @@ -20,26 +20,15 @@ #include +#include "qcom_pmic_typec.h" #include "qcom_pmic_typec_pdphy.h" #include "qcom_pmic_typec_port.h" struct pmic_typec_resources { - struct pmic_typec_pdphy_resources *pdphy_res; + const struct pmic_typec_pdphy_resources *pdphy_res; struct pmic_typec_port_resources *port_res; }; -struct pmic_typec { - struct device *dev; - struct tcpm_port *tcpm_port; - struct tcpc_dev tcpc; - struct pmic_typec_pdphy *pmic_typec_pdphy; - struct pmic_typec_port *pmic_typec_port; - bool vbus_enabled; - struct mutex lock; /* VBUS state serialization */ -}; - -#define tcpc_to_tcpm(_tcpc_) container_of(_tcpc_, struct pmic_typec, tcpc) - static int qcom_pmic_typec_get_vbus(struct tcpc_dev *tcpc) { struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); @@ -116,34 +105,6 @@ static int qcom_pmic_typec_start_toggling(struct tcpc_dev *tcpc, port_type, cc); } -static int qcom_pmic_typec_set_roles(struct tcpc_dev *tcpc, bool attached, - enum typec_role power_role, - enum typec_data_role data_role) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - - return qcom_pmic_typec_pdphy_set_roles(tcpm->pmic_typec_pdphy, - power_role, data_role); -} - -static int qcom_pmic_typec_set_pd_rx(struct tcpc_dev *tcpc, bool on) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - - return qcom_pmic_typec_pdphy_set_pd_rx(tcpm->pmic_typec_pdphy, on); -} - -static int qcom_pmic_typec_pd_transmit(struct tcpc_dev *tcpc, - enum tcpm_transmit_type type, - const struct pd_message *msg, - unsigned int negotiated_rev) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - - return qcom_pmic_typec_pdphy_pd_transmit(tcpm->pmic_typec_pdphy, type, - msg, negotiated_rev); -} - static int qcom_pmic_typec_init(struct tcpc_dev *tcpc) { return 0; @@ -177,9 +138,6 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) tcpm->tcpc.set_polarity = qcom_pmic_typec_set_polarity; tcpm->tcpc.set_vconn = qcom_pmic_typec_set_vconn; tcpm->tcpc.start_toggling = qcom_pmic_typec_start_toggling; - tcpm->tcpc.set_pd_rx = qcom_pmic_typec_set_pd_rx; - tcpm->tcpc.set_roles = qcom_pmic_typec_set_roles; - tcpm->tcpc.pd_transmit = qcom_pmic_typec_pd_transmit; regmap = dev_get_regmap(dev->parent, NULL); if (!regmap) { @@ -195,16 +153,12 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) if (IS_ERR(tcpm->pmic_typec_port)) return PTR_ERR(tcpm->pmic_typec_port); - tcpm->pmic_typec_pdphy = qcom_pmic_typec_pdphy_alloc(dev); - if (IS_ERR(tcpm->pmic_typec_pdphy)) - return PTR_ERR(tcpm->pmic_typec_pdphy); - ret = qcom_pmic_typec_port_probe(pdev, tcpm->pmic_typec_port, res->port_res, regmap, base[0]); if (ret) return ret; - ret = qcom_pmic_typec_pdphy_probe(pdev, tcpm->pmic_typec_pdphy, + ret = qcom_pmic_typec_pdphy_probe(pdev, tcpm, res->pdphy_res, regmap, base[1]); if (ret) return ret; @@ -231,8 +185,7 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) if (ret) goto fwnode_remove; - ret = qcom_pmic_typec_pdphy_start(tcpm->pmic_typec_pdphy, - tcpm->tcpm_port); + ret = tcpm->pdphy_start(tcpm, tcpm->tcpm_port); if (ret) goto fwnode_remove; @@ -248,46 +201,12 @@ static void qcom_pmic_typec_remove(struct platform_device *pdev) { struct pmic_typec *tcpm = platform_get_drvdata(pdev); - qcom_pmic_typec_pdphy_stop(tcpm->pmic_typec_pdphy); + tcpm->pdphy_stop(tcpm); qcom_pmic_typec_port_stop(tcpm->pmic_typec_port); tcpm_unregister_port(tcpm->tcpm_port); fwnode_remove_software_node(tcpm->tcpc.fwnode); } -static struct pmic_typec_pdphy_resources pm8150b_pdphy_res = { - .irq_params = { - { - .virq = PMIC_PDPHY_SIG_TX_IRQ, - .irq_name = "sig-tx", - }, - { - .virq = PMIC_PDPHY_SIG_RX_IRQ, - .irq_name = "sig-rx", - }, - { - .virq = PMIC_PDPHY_MSG_TX_IRQ, - .irq_name = "msg-tx", - }, - { - .virq = PMIC_PDPHY_MSG_RX_IRQ, - .irq_name = "msg-rx", - }, - { - .virq = PMIC_PDPHY_MSG_TX_FAIL_IRQ, - .irq_name = "msg-tx-failed", - }, - { - .virq = PMIC_PDPHY_MSG_TX_DISCARD_IRQ, - .irq_name = "msg-tx-discarded", - }, - { - .virq = PMIC_PDPHY_MSG_RX_DISCARD_IRQ, - .irq_name = "msg-rx-discarded", - }, - }, - .nr_irqs = 7, -}; - static struct pmic_typec_port_resources pm8150b_port_res = { .irq_params = { { diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h new file mode 100644 index 000000000000..da035916c12a --- /dev/null +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Linaro Ltd. All rights reserved. + */ + +#ifndef __QCOM_PMIC_TYPEC_H__ +#define __QCOM_PMIC_TYPEC_H__ + +struct pmic_typec { + struct device *dev; + struct tcpm_port *tcpm_port; + struct tcpc_dev tcpc; + struct pmic_typec_pdphy *pmic_typec_pdphy; + struct pmic_typec_port *pmic_typec_port; + bool vbus_enabled; + struct mutex lock; /* VBUS state serialization */ + + int (*pdphy_start)(struct pmic_typec *tcpm, + struct tcpm_port *tcpm_port); + void (*pdphy_stop)(struct pmic_typec *tcpm); +}; + +#define tcpc_to_tcpm(_tcpc_) container_of(_tcpc_, struct pmic_typec, tcpc) + +#endif diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c index 44d8342ed0ad..984d90b0d763 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.c @@ -14,8 +14,74 @@ #include #include #include +#include "qcom_pmic_typec.h" #include "qcom_pmic_typec_pdphy.h" +/* PD PHY register offsets and bit fields */ +#define USB_PDPHY_MSG_CONFIG_REG 0x40 +#define MSG_CONFIG_PORT_DATA_ROLE BIT(3) +#define MSG_CONFIG_PORT_POWER_ROLE BIT(2) +#define MSG_CONFIG_SPEC_REV_MASK (BIT(1) | BIT(0)) + +#define USB_PDPHY_EN_CONTROL_REG 0x46 +#define CONTROL_ENABLE BIT(0) + +#define USB_PDPHY_RX_STATUS_REG 0x4A +#define RX_FRAME_TYPE (BIT(0) | BIT(1) | BIT(2)) + +#define USB_PDPHY_FRAME_FILTER_REG 0x4C +#define FRAME_FILTER_EN_HARD_RESET BIT(5) +#define FRAME_FILTER_EN_SOP BIT(0) + +#define USB_PDPHY_TX_SIZE_REG 0x42 +#define TX_SIZE_MASK 0xF + +#define USB_PDPHY_TX_CONTROL_REG 0x44 +#define TX_CONTROL_RETRY_COUNT(n) (((n) & 0x3) << 5) +#define TX_CONTROL_FRAME_TYPE(n) (((n) & 0x7) << 2) +#define TX_CONTROL_FRAME_TYPE_CABLE_RESET (0x1 << 2) +#define TX_CONTROL_SEND_SIGNAL BIT(1) +#define TX_CONTROL_SEND_MSG BIT(0) + +#define USB_PDPHY_RX_SIZE_REG 0x48 + +#define USB_PDPHY_RX_ACKNOWLEDGE_REG 0x4B +#define RX_BUFFER_TOKEN BIT(0) + +#define USB_PDPHY_BIST_MODE_REG 0x4E +#define BIST_MODE_MASK 0xF +#define BIST_ENABLE BIT(7) +#define PD_MSG_BIST 0x3 +#define PD_BIST_TEST_DATA_MODE 0x8 + +#define USB_PDPHY_TX_BUFFER_HDR_REG 0x60 +#define USB_PDPHY_TX_BUFFER_DATA_REG 0x62 + +#define USB_PDPHY_RX_BUFFER_REG 0x80 + +/* VDD regulator */ +#define VDD_PDPHY_VOL_MIN 2800000 /* uV */ +#define VDD_PDPHY_VOL_MAX 3300000 /* uV */ +#define VDD_PDPHY_HPM_LOAD 3000 /* uA */ + +/* Message Spec Rev field */ +#define PD_MSG_HDR_REV(hdr) (((hdr) >> 6) & 3) + +/* timers */ +#define RECEIVER_RESPONSE_TIME 15 /* tReceiverResponse */ +#define HARD_RESET_COMPLETE_TIME 5 /* tHardResetComplete */ + +/* Interrupt numbers */ +#define PMIC_PDPHY_SIG_TX_IRQ 0x0 +#define PMIC_PDPHY_SIG_RX_IRQ 0x1 +#define PMIC_PDPHY_MSG_TX_IRQ 0x2 +#define PMIC_PDPHY_MSG_RX_IRQ 0x3 +#define PMIC_PDPHY_MSG_TX_FAIL_IRQ 0x4 +#define PMIC_PDPHY_MSG_TX_DISCARD_IRQ 0x5 +#define PMIC_PDPHY_MSG_RX_DISCARD_IRQ 0x6 +#define PMIC_PDPHY_FR_SWAP_IRQ 0x7 + + struct pmic_typec_pdphy_irq_data { int virq; int irq; @@ -231,11 +297,13 @@ qcom_pmic_typec_pdphy_pd_transmit_payload(struct pmic_typec_pdphy *pmic_typec_pd return ret; } -int qcom_pmic_typec_pdphy_pd_transmit(struct pmic_typec_pdphy *pmic_typec_pdphy, - enum tcpm_transmit_type type, - const struct pd_message *msg, - unsigned int negotiated_rev) +static int qcom_pmic_typec_pdphy_pd_transmit(struct tcpc_dev *tcpc, + enum tcpm_transmit_type type, + const struct pd_message *msg, + unsigned int negotiated_rev) { + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_pdphy *pmic_typec_pdphy = tcpm->pmic_typec_pdphy; struct device *dev = pmic_typec_pdphy->dev; int ret; @@ -336,8 +404,10 @@ static irqreturn_t qcom_pmic_typec_pdphy_isr(int irq, void *dev_id) return IRQ_HANDLED; } -int qcom_pmic_typec_pdphy_set_pd_rx(struct pmic_typec_pdphy *pmic_typec_pdphy, bool on) +static int qcom_pmic_typec_pdphy_set_pd_rx(struct tcpc_dev *tcpc, bool on) { + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_pdphy *pmic_typec_pdphy = tcpm->pmic_typec_pdphy; unsigned long flags; int ret; @@ -353,10 +423,12 @@ int qcom_pmic_typec_pdphy_set_pd_rx(struct pmic_typec_pdphy *pmic_typec_pdphy, b return ret; } -int qcom_pmic_typec_pdphy_set_roles(struct pmic_typec_pdphy *pmic_typec_pdphy, - enum typec_role power_role, - enum typec_data_role data_role) +static int qcom_pmic_typec_pdphy_set_roles(struct tcpc_dev *tcpc, bool attached, + enum typec_role power_role, + enum typec_data_role data_role) { + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_pdphy *pmic_typec_pdphy = tcpm->pmic_typec_pdphy; struct device *dev = pmic_typec_pdphy->dev; unsigned long flags; int ret; @@ -437,9 +509,10 @@ static int pmic_typec_pdphy_reset(struct pmic_typec_pdphy *pmic_typec_pdphy) return ret; } -int qcom_pmic_typec_pdphy_start(struct pmic_typec_pdphy *pmic_typec_pdphy, - struct tcpm_port *tcpm_port) +static int qcom_pmic_typec_pdphy_start(struct pmic_typec *tcpm, + struct tcpm_port *tcpm_port) { + struct pmic_typec_pdphy *pmic_typec_pdphy = tcpm->pmic_typec_pdphy; int i; int ret; @@ -459,8 +532,9 @@ int qcom_pmic_typec_pdphy_start(struct pmic_typec_pdphy *pmic_typec_pdphy, return 0; } -void qcom_pmic_typec_pdphy_stop(struct pmic_typec_pdphy *pmic_typec_pdphy) +static void qcom_pmic_typec_pdphy_stop(struct pmic_typec *tcpm) { + struct pmic_typec_pdphy *pmic_typec_pdphy = tcpm->pmic_typec_pdphy; int i; for (i = 0; i < pmic_typec_pdphy->nr_irqs; i++) @@ -471,21 +545,21 @@ void qcom_pmic_typec_pdphy_stop(struct pmic_typec_pdphy *pmic_typec_pdphy) regulator_disable(pmic_typec_pdphy->vdd_pdphy); } -struct pmic_typec_pdphy *qcom_pmic_typec_pdphy_alloc(struct device *dev) -{ - return devm_kzalloc(dev, sizeof(struct pmic_typec_pdphy), GFP_KERNEL); -} - int qcom_pmic_typec_pdphy_probe(struct platform_device *pdev, - struct pmic_typec_pdphy *pmic_typec_pdphy, - struct pmic_typec_pdphy_resources *res, + struct pmic_typec *tcpm, + const struct pmic_typec_pdphy_resources *res, struct regmap *regmap, u32 base) { + struct pmic_typec_pdphy *pmic_typec_pdphy; struct device *dev = &pdev->dev; struct pmic_typec_pdphy_irq_data *irq_data; int i, ret, irq; + pmic_typec_pdphy = devm_kzalloc(dev, sizeof(*pmic_typec_pdphy), GFP_KERNEL); + if (!pmic_typec_pdphy) + return -ENOMEM; + if (!res->nr_irqs || res->nr_irqs > PMIC_PDPHY_MAX_IRQS) return -EINVAL; @@ -524,5 +598,48 @@ int qcom_pmic_typec_pdphy_probe(struct platform_device *pdev, return ret; } + tcpm->pmic_typec_pdphy = pmic_typec_pdphy; + + tcpm->tcpc.set_pd_rx = qcom_pmic_typec_pdphy_set_pd_rx; + tcpm->tcpc.set_roles = qcom_pmic_typec_pdphy_set_roles; + tcpm->tcpc.pd_transmit = qcom_pmic_typec_pdphy_pd_transmit; + + tcpm->pdphy_start = qcom_pmic_typec_pdphy_start; + tcpm->pdphy_stop = qcom_pmic_typec_pdphy_stop; + return 0; } + +const struct pmic_typec_pdphy_resources pm8150b_pdphy_res = { + .irq_params = { + { + .virq = PMIC_PDPHY_SIG_TX_IRQ, + .irq_name = "sig-tx", + }, + { + .virq = PMIC_PDPHY_SIG_RX_IRQ, + .irq_name = "sig-rx", + }, + { + .virq = PMIC_PDPHY_MSG_TX_IRQ, + .irq_name = "msg-tx", + }, + { + .virq = PMIC_PDPHY_MSG_RX_IRQ, + .irq_name = "msg-rx", + }, + { + .virq = PMIC_PDPHY_MSG_TX_FAIL_IRQ, + .irq_name = "msg-tx-failed", + }, + { + .virq = PMIC_PDPHY_MSG_TX_DISCARD_IRQ, + .irq_name = "msg-tx-discarded", + }, + { + .virq = PMIC_PDPHY_MSG_RX_DISCARD_IRQ, + .irq_name = "msg-rx-discarded", + }, + }, + .nr_irqs = 7, +}; diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h index 070822dc6f17..5f428e67ccfe 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h @@ -8,74 +8,6 @@ #include #include -#include - -#define USB_PDPHY_MAX_DATA_OBJ_LEN 28 -#define USB_PDPHY_MSG_HDR_LEN 2 - -/* PD PHY register offsets and bit fields */ -#define USB_PDPHY_MSG_CONFIG_REG 0x40 -#define MSG_CONFIG_PORT_DATA_ROLE BIT(3) -#define MSG_CONFIG_PORT_POWER_ROLE BIT(2) -#define MSG_CONFIG_SPEC_REV_MASK (BIT(1) | BIT(0)) - -#define USB_PDPHY_EN_CONTROL_REG 0x46 -#define CONTROL_ENABLE BIT(0) - -#define USB_PDPHY_RX_STATUS_REG 0x4A -#define RX_FRAME_TYPE (BIT(0) | BIT(1) | BIT(2)) - -#define USB_PDPHY_FRAME_FILTER_REG 0x4C -#define FRAME_FILTER_EN_HARD_RESET BIT(5) -#define FRAME_FILTER_EN_SOP BIT(0) - -#define USB_PDPHY_TX_SIZE_REG 0x42 -#define TX_SIZE_MASK 0xF - -#define USB_PDPHY_TX_CONTROL_REG 0x44 -#define TX_CONTROL_RETRY_COUNT(n) (((n) & 0x3) << 5) -#define TX_CONTROL_FRAME_TYPE(n) (((n) & 0x7) << 2) -#define TX_CONTROL_FRAME_TYPE_CABLE_RESET (0x1 << 2) -#define TX_CONTROL_SEND_SIGNAL BIT(1) -#define TX_CONTROL_SEND_MSG BIT(0) - -#define USB_PDPHY_RX_SIZE_REG 0x48 - -#define USB_PDPHY_RX_ACKNOWLEDGE_REG 0x4B -#define RX_BUFFER_TOKEN BIT(0) - -#define USB_PDPHY_BIST_MODE_REG 0x4E -#define BIST_MODE_MASK 0xF -#define BIST_ENABLE BIT(7) -#define PD_MSG_BIST 0x3 -#define PD_BIST_TEST_DATA_MODE 0x8 - -#define USB_PDPHY_TX_BUFFER_HDR_REG 0x60 -#define USB_PDPHY_TX_BUFFER_DATA_REG 0x62 - -#define USB_PDPHY_RX_BUFFER_REG 0x80 - -/* VDD regulator */ -#define VDD_PDPHY_VOL_MIN 2800000 /* uV */ -#define VDD_PDPHY_VOL_MAX 3300000 /* uV */ -#define VDD_PDPHY_HPM_LOAD 3000 /* uA */ - -/* Message Spec Rev field */ -#define PD_MSG_HDR_REV(hdr) (((hdr) >> 6) & 3) - -/* timers */ -#define RECEIVER_RESPONSE_TIME 15 /* tReceiverResponse */ -#define HARD_RESET_COMPLETE_TIME 5 /* tHardResetComplete */ - -/* Interrupt numbers */ -#define PMIC_PDPHY_SIG_TX_IRQ 0x0 -#define PMIC_PDPHY_SIG_RX_IRQ 0x1 -#define PMIC_PDPHY_MSG_TX_IRQ 0x2 -#define PMIC_PDPHY_MSG_RX_IRQ 0x3 -#define PMIC_PDPHY_MSG_TX_FAIL_IRQ 0x4 -#define PMIC_PDPHY_MSG_TX_DISCARD_IRQ 0x5 -#define PMIC_PDPHY_MSG_RX_DISCARD_IRQ 0x6 -#define PMIC_PDPHY_FR_SWAP_IRQ 0x7 /* Resources */ #define PMIC_PDPHY_MAX_IRQS 0x08 @@ -87,34 +19,17 @@ struct pmic_typec_pdphy_irq_params { struct pmic_typec_pdphy_resources { unsigned int nr_irqs; - struct pmic_typec_pdphy_irq_params irq_params[PMIC_PDPHY_MAX_IRQS]; + const struct pmic_typec_pdphy_irq_params irq_params[PMIC_PDPHY_MAX_IRQS]; }; /* API */ struct pmic_typec_pdphy; -struct pmic_typec_pdphy *qcom_pmic_typec_pdphy_alloc(struct device *dev); - +extern const struct pmic_typec_pdphy_resources pm8150b_pdphy_res; int qcom_pmic_typec_pdphy_probe(struct platform_device *pdev, - struct pmic_typec_pdphy *pmic_typec_pdphy, - struct pmic_typec_pdphy_resources *res, + struct pmic_typec *tcpm, + const struct pmic_typec_pdphy_resources *res, struct regmap *regmap, u32 base); -int qcom_pmic_typec_pdphy_start(struct pmic_typec_pdphy *pmic_typec_pdphy, - struct tcpm_port *tcpm_port); - -void qcom_pmic_typec_pdphy_stop(struct pmic_typec_pdphy *pmic_typec_pdphy); - -int qcom_pmic_typec_pdphy_set_roles(struct pmic_typec_pdphy *pmic_typec_pdphy, - enum typec_role power_role, - enum typec_data_role data_role); - -int qcom_pmic_typec_pdphy_set_pd_rx(struct pmic_typec_pdphy *pmic_typec_pdphy, bool on); - -int qcom_pmic_typec_pdphy_pd_transmit(struct pmic_typec_pdphy *pmic_typec_pdphy, - enum tcpm_transmit_type type, - const struct pd_message *msg, - unsigned int negotiated_rev); - #endif /* __QCOM_PMIC_TYPEC_PDPHY_H__ */ diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h index d4d358c680b6..4a892048908e 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h @@ -3,8 +3,8 @@ * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * Copyright (c) 2023, Linaro Ltd. All rights reserved. */ -#ifndef __QCOM_PMIC_TYPEC_H__ -#define __QCOM_PMIC_TYPEC_H__ +#ifndef __QCOM_PMIC_TYPEC_PORT_H__ +#define __QCOM_PMIC_TYPEC_PORT_H__ #include #include From patchwork Sat Jan 13 20:55:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13519065 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C278D182BE for ; Sat, 13 Jan 2024 20:56:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fl7oZv/f" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-50edf4f478eso4380641e87.3 for ; Sat, 13 Jan 2024 12:56:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705179360; x=1705784160; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IrYbtSQLEwecmvY7mVOmkjv0hdobg9yVp8LjVqDvEtc=; b=fl7oZv/fcOQ3y5P75te6xfqt9bUG7FEasxIltRuTgu8lh13z4vYq5BLBqQ1kBmR73X yWz+uXmSw4JINSQQPTnTLSataPbrRaXfjaskPID7sqUyfZ3gByZklFJx85VU4hWmkgZk zKKtSfi0AuUED+2gHDHow3FpMsojonuvzbpWM+x2YgUEBAkYOpmMX+3J3p8jibSLbOyr FYoT0NslK00+1z722Wppboa2/OvXcVF6QyAu5HXFYmnPqR0LXJt1nQ2KxfYn2zPYdghP SiJxqt9fUsJP0jWr4XXqcjuPKvjcOxB3Q0AGkl4bDRfXomgxOyO2e5oAWB3SXR8yZrbZ 2eBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705179360; x=1705784160; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IrYbtSQLEwecmvY7mVOmkjv0hdobg9yVp8LjVqDvEtc=; b=ZpaC+KUIJ6g8PrD9kZZfvd6Wc2VpbTJSPUxQwMjMDGlIc7ERQ52eZxwz1GY1P19aSD jMaBqw132GW4ico9yWDommpXmH6T/6/rhjsS3AgcMP/Rp7CY40gojGBTvXqTt7D0tUdR DraqxN3+UVr4bth81v5nb2u+uShEdr+q7OGVxBhaDvhNXtHNylUfvRmtoSCOBWLnK6Nq P+4AeWWfV1XaruwBgMo540N/EGW99H7OA2m5WVWTI6NLU7sTIniP5hwMTbSCjVmRfo3P u++fMrwWYOnKEWLHh7KaH9vXVelJ+rqxMu0poM5SwmmMiGVmyeicmynD6E+iQaAMjDlo kPlg== X-Gm-Message-State: AOJu0YwDdo2INoLGGPREqac7BSI+A6lHksZiyEyCdF1MPRYpdEUYj6ye s1Qyoofs0qKkwcVn0HhZGLhThAlnx1j0rA== X-Google-Smtp-Source: AGHT+IFgvseC4amvEk45BurCDgiV2AShck55v8bBlZ8h6AzSDGUJFN3jnxDK/ZE+tfUF2/FmeUU00A== X-Received: by 2002:a19:6719:0:b0:50e:242a:775e with SMTP id b25-20020a196719000000b0050e242a775emr1547228lfc.106.1705179359911; Sat, 13 Jan 2024 12:55:59 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id p14-20020a056512328e00b0050e9355d7eesm919802lfe.103.2024.01.13.12.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 12:55:59 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:51 +0200 Subject: [PATCH v2 08/15] usb: typec: qcom-pmic-typec: allow different implementations for the port backend Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-8-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=27314; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=M70a8nwyM9k8KEGyiEZ97LlW387QdaOfmeDb4AQE5xg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjXf6zAUhb2+UviRjMteGH41TQ8GN6nM/7X0 vTIXJCFLdGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41wAKCRCLPIo+Aiko 1bxIB/44GGAvYFpBShz4UeLL4BUaaKGTphwG39W4eMeIcbTYWwXn7lJ4oy4yH2vKK8F2ozerW6t jgbJn+Wgj04UzuPCrlV51NECMxiH8pZHfj56bs5iD7bPIeTHBT6mbm1OACcDLQArlNvXwIQwvn2 vtat0dZhKHg5YJjkrNLHDWew2Zj5GhCDA0TZfCgDoPCHpaBd5g+vsWTmh0mQb2UuLIruQRS0il3 +xV5nk78N8jS/Yuxsx7vXFlwOIPb9figiMnl0Rv2UeDSl9YuhoAVGyPsqRXFpJbItt0ZQOTIpGb wrJpqlATc9/isA0VYk49P1SzYeWujgS/vH3WGwwtvr5a1VCe X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow the PD PHY changes and rework Type-C port implementation to become an encapsulated backend. While this is not required for the PMI632, it will us later to enable Type-C handling on earlier platforms, including, but not limited to SDM845, SDM660 and MSM8998. Signed-off-by: Dmitry Baryshkov Tested-by: Bryan O'Donoghue Acked-by: Bryan O'Donoghue --- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c | 137 +--------- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h | 6 +- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c | 290 +++++++++++++++++++-- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h | 168 +----------- 4 files changed, 282 insertions(+), 319 deletions(-) diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c index 4c7c38c58a02..82e3f59ea471 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c @@ -26,85 +26,9 @@ struct pmic_typec_resources { const struct pmic_typec_pdphy_resources *pdphy_res; - struct pmic_typec_port_resources *port_res; + const struct pmic_typec_port_resources *port_res; }; -static int qcom_pmic_typec_get_vbus(struct tcpc_dev *tcpc) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - int ret; - - mutex_lock(&tcpm->lock); - ret = tcpm->vbus_enabled || qcom_pmic_typec_port_get_vbus(tcpm->pmic_typec_port); - mutex_unlock(&tcpm->lock); - - return ret; -} - -static int qcom_pmic_typec_set_vbus(struct tcpc_dev *tcpc, bool on, bool sink) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - int ret = 0; - - mutex_lock(&tcpm->lock); - if (tcpm->vbus_enabled == on) - goto done; - - ret = qcom_pmic_typec_port_set_vbus(tcpm->pmic_typec_port, on); - if (ret) - goto done; - - tcpm->vbus_enabled = on; - tcpm_vbus_change(tcpm->tcpm_port); - -done: - dev_dbg(tcpm->dev, "set_vbus set: %d result %d\n", on, ret); - mutex_unlock(&tcpm->lock); - - return ret; -} - -static int qcom_pmic_typec_set_vconn(struct tcpc_dev *tcpc, bool on) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - - return qcom_pmic_typec_port_set_vconn(tcpm->pmic_typec_port, on); -} - -static int qcom_pmic_typec_get_cc(struct tcpc_dev *tcpc, - enum typec_cc_status *cc1, - enum typec_cc_status *cc2) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - - return qcom_pmic_typec_port_get_cc(tcpm->pmic_typec_port, cc1, cc2); -} - -static int qcom_pmic_typec_set_cc(struct tcpc_dev *tcpc, - enum typec_cc_status cc) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - - return qcom_pmic_typec_port_set_cc(tcpm->pmic_typec_port, cc); -} - -static int qcom_pmic_typec_set_polarity(struct tcpc_dev *tcpc, - enum typec_cc_polarity pol) -{ - /* Polarity is set separately by phy-qcom-qmp.c */ - return 0; -} - -static int qcom_pmic_typec_start_toggling(struct tcpc_dev *tcpc, - enum typec_port_type port_type, - enum typec_cc_status cc) -{ - struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); - - return qcom_pmic_typec_port_start_toggling(tcpm->pmic_typec_port, - port_type, cc); -} - static int qcom_pmic_typec_init(struct tcpc_dev *tcpc) { return 0; @@ -131,13 +55,6 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) tcpm->dev = dev; tcpm->tcpc.init = qcom_pmic_typec_init; - tcpm->tcpc.get_vbus = qcom_pmic_typec_get_vbus; - tcpm->tcpc.set_vbus = qcom_pmic_typec_set_vbus; - tcpm->tcpc.set_cc = qcom_pmic_typec_set_cc; - tcpm->tcpc.get_cc = qcom_pmic_typec_get_cc; - tcpm->tcpc.set_polarity = qcom_pmic_typec_set_polarity; - tcpm->tcpc.set_vconn = qcom_pmic_typec_set_vconn; - tcpm->tcpc.start_toggling = qcom_pmic_typec_start_toggling; regmap = dev_get_regmap(dev->parent, NULL); if (!regmap) { @@ -149,11 +66,7 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) if (ret) return ret; - tcpm->pmic_typec_port = qcom_pmic_typec_port_alloc(dev); - if (IS_ERR(tcpm->pmic_typec_port)) - return PTR_ERR(tcpm->pmic_typec_port); - - ret = qcom_pmic_typec_port_probe(pdev, tcpm->pmic_typec_port, + ret = qcom_pmic_typec_port_probe(pdev, tcpm, res->port_res, regmap, base[0]); if (ret) return ret; @@ -163,7 +76,6 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) if (ret) return ret; - mutex_init(&tcpm->lock); platform_set_drvdata(pdev, tcpm); tcpm->tcpc.fwnode = device_get_named_child_node(tcpm->dev, "connector"); @@ -180,8 +92,7 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) goto fwnode_remove; } - ret = qcom_pmic_typec_port_start(tcpm->pmic_typec_port, - tcpm->tcpm_port); + ret = tcpm->port_start(tcpm, tcpm->tcpm_port); if (ret) goto fwnode_remove; @@ -202,50 +113,12 @@ static void qcom_pmic_typec_remove(struct platform_device *pdev) struct pmic_typec *tcpm = platform_get_drvdata(pdev); tcpm->pdphy_stop(tcpm); - qcom_pmic_typec_port_stop(tcpm->pmic_typec_port); + tcpm->port_stop(tcpm); tcpm_unregister_port(tcpm->tcpm_port); fwnode_remove_software_node(tcpm->tcpc.fwnode); } -static struct pmic_typec_port_resources pm8150b_port_res = { - .irq_params = { - { - .irq_name = "vpd-detect", - .virq = PMIC_TYPEC_VPD_IRQ, - }, - - { - .irq_name = "cc-state-change", - .virq = PMIC_TYPEC_CC_STATE_IRQ, - }, - { - .irq_name = "vconn-oc", - .virq = PMIC_TYPEC_VCONN_OC_IRQ, - }, - - { - .irq_name = "vbus-change", - .virq = PMIC_TYPEC_VBUS_IRQ, - }, - - { - .irq_name = "attach-detach", - .virq = PMIC_TYPEC_ATTACH_DETACH_IRQ, - }, - { - .irq_name = "legacy-cable-detect", - .virq = PMIC_TYPEC_LEGACY_CABLE_IRQ, - }, - - { - .irq_name = "try-snk-src-detect", - .virq = PMIC_TYPEC_TRY_SNK_SRC_IRQ, - }, - }, - .nr_irqs = 7, -}; - -static struct pmic_typec_resources pm8150b_typec_res = { +static const struct pmic_typec_resources pm8150b_typec_res = { .pdphy_res = &pm8150b_pdphy_res, .port_res = &pm8150b_port_res, }; diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h index da035916c12a..3c75820c9187 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.h @@ -12,12 +12,14 @@ struct pmic_typec { struct tcpc_dev tcpc; struct pmic_typec_pdphy *pmic_typec_pdphy; struct pmic_typec_port *pmic_typec_port; - bool vbus_enabled; - struct mutex lock; /* VBUS state serialization */ int (*pdphy_start)(struct pmic_typec *tcpm, struct tcpm_port *tcpm_port); void (*pdphy_stop)(struct pmic_typec *tcpm); + + int (*port_start)(struct pmic_typec *tcpm, + struct tcpm_port *tcpm_port); + void (*port_stop)(struct pmic_typec *tcpm); }; #define tcpc_to_tcpm(_tcpc_) container_of(_tcpc_, struct pmic_typec, tcpc) diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c index a8f3f4d3a450..a747baa29784 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.c @@ -16,8 +16,147 @@ #include #include #include + +#include "qcom_pmic_typec.h" #include "qcom_pmic_typec_port.h" +#define TYPEC_SNK_STATUS_REG 0x06 +#define DETECTED_SNK_TYPE_MASK GENMASK(6, 0) +#define SNK_DAM_MASK GENMASK(6, 4) +#define SNK_DAM_500MA BIT(6) +#define SNK_DAM_1500MA BIT(5) +#define SNK_DAM_3000MA BIT(4) +#define SNK_RP_STD BIT(3) +#define SNK_RP_1P5 BIT(2) +#define SNK_RP_3P0 BIT(1) +#define SNK_RP_SHORT BIT(0) + +#define TYPEC_SRC_STATUS_REG 0x08 +#define DETECTED_SRC_TYPE_MASK GENMASK(4, 0) +#define SRC_HIGH_BATT BIT(5) +#define SRC_DEBUG_ACCESS BIT(4) +#define SRC_RD_OPEN BIT(3) +#define SRC_RD_RA_VCONN BIT(2) +#define SRC_RA_OPEN BIT(1) +#define AUDIO_ACCESS_RA_RA BIT(0) + +#define TYPEC_STATE_MACHINE_STATUS_REG 0x09 +#define TYPEC_ATTACH_DETACH_STATE BIT(5) + +#define TYPEC_SM_STATUS_REG 0x0A +#define TYPEC_SM_VBUS_VSAFE5V BIT(5) +#define TYPEC_SM_VBUS_VSAFE0V BIT(6) +#define TYPEC_SM_USBIN_LT_LV BIT(7) + +#define TYPEC_MISC_STATUS_REG 0x0B +#define TYPEC_WATER_DETECTION_STATUS BIT(7) +#define SNK_SRC_MODE BIT(6) +#define TYPEC_VBUS_DETECT BIT(5) +#define TYPEC_VBUS_ERROR_STATUS BIT(4) +#define TYPEC_DEBOUNCE_DONE BIT(3) +#define CC_ORIENTATION BIT(1) +#define CC_ATTACHED BIT(0) + +#define LEGACY_CABLE_STATUS_REG 0x0D +#define TYPEC_LEGACY_CABLE_STATUS BIT(1) +#define TYPEC_NONCOMP_LEGACY_CABLE_STATUS BIT(0) + +#define TYPEC_U_USB_STATUS_REG 0x0F +#define U_USB_GROUND_NOVBUS BIT(6) +#define U_USB_GROUND BIT(4) +#define U_USB_FMB1 BIT(3) +#define U_USB_FLOAT1 BIT(2) +#define U_USB_FMB2 BIT(1) +#define U_USB_FLOAT2 BIT(0) + +#define TYPEC_MODE_CFG_REG 0x44 +#define TYPEC_TRY_MODE_MASK GENMASK(4, 3) +#define EN_TRY_SNK BIT(4) +#define EN_TRY_SRC BIT(3) +#define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0) +#define EN_SRC_ONLY BIT(2) +#define EN_SNK_ONLY BIT(1) +#define TYPEC_DISABLE_CMD BIT(0) + +#define TYPEC_VCONN_CONTROL_REG 0x46 +#define VCONN_EN_ORIENTATION BIT(2) +#define VCONN_EN_VALUE BIT(1) +#define VCONN_EN_SRC BIT(0) + +#define TYPEC_CCOUT_CONTROL_REG 0x48 +#define TYPEC_CCOUT_BUFFER_EN BIT(2) +#define TYPEC_CCOUT_VALUE BIT(1) +#define TYPEC_CCOUT_SRC BIT(0) + +#define DEBUG_ACCESS_SRC_CFG_REG 0x4C +#define EN_UNORIENTED_DEBUG_ACCESS_SRC BIT(0) + +#define TYPE_C_CRUDE_SENSOR_CFG_REG 0x4e +#define EN_SRC_CRUDE_SENSOR BIT(1) +#define EN_SNK_CRUDE_SENSOR BIT(0) + +#define TYPEC_EXIT_STATE_CFG_REG 0x50 +#define BYPASS_VSAFE0V_DURING_ROLE_SWAP BIT(3) +#define SEL_SRC_UPPER_REF BIT(2) +#define USE_TPD_FOR_EXITING_ATTACHSRC BIT(1) +#define EXIT_SNK_BASED_ON_CC BIT(0) + +#define TYPEC_CURRSRC_CFG_REG 0x52 +#define TYPEC_SRC_RP_SEL_330UA BIT(1) +#define TYPEC_SRC_RP_SEL_180UA BIT(0) +#define TYPEC_SRC_RP_SEL_80UA 0 +#define TYPEC_SRC_RP_SEL_MASK GENMASK(1, 0) + +#define TYPEC_INTERRUPT_EN_CFG_1_REG 0x5E +#define TYPEC_LEGACY_CABLE_INT_EN BIT(7) +#define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN BIT(6) +#define TYPEC_TRYSOURCE_DETECT_INT_EN BIT(5) +#define TYPEC_TRYSINK_DETECT_INT_EN BIT(4) +#define TYPEC_CCOUT_DETACH_INT_EN BIT(3) +#define TYPEC_CCOUT_ATTACH_INT_EN BIT(2) +#define TYPEC_VBUS_DEASSERT_INT_EN BIT(1) +#define TYPEC_VBUS_ASSERT_INT_EN BIT(0) + +#define TYPEC_INTERRUPT_EN_CFG_2_REG 0x60 +#define TYPEC_SRC_BATT_HPWR_INT_EN BIT(6) +#define MICRO_USB_STATE_CHANGE_INT_EN BIT(5) +#define TYPEC_STATE_MACHINE_CHANGE_INT_EN BIT(4) +#define TYPEC_DEBUG_ACCESS_DETECT_INT_EN BIT(3) +#define TYPEC_WATER_DETECTION_INT_EN BIT(2) +#define TYPEC_VBUS_ERROR_INT_EN BIT(1) +#define TYPEC_DEBOUNCE_DONE_INT_EN BIT(0) + +#define TYPEC_DEBOUNCE_OPTION_REG 0x62 +#define REDUCE_TCCDEBOUNCE_TO_2MS BIT(2) + +#define TYPE_C_SBU_CFG_REG 0x6A +#define SEL_SBU1_ISRC_VAL 0x04 +#define SEL_SBU2_ISRC_VAL 0x01 + +#define TYPEC_U_USB_CFG_REG 0x70 +#define EN_MICRO_USB_FACTORY_MODE BIT(1) +#define EN_MICRO_USB_MODE BIT(0) + +#define TYPEC_PMI632_U_USB_WATER_PROTECTION_CFG_REG 0x72 + +#define TYPEC_U_USB_WATER_PROTECTION_CFG_REG 0x73 +#define EN_MICRO_USB_WATER_PROTECTION BIT(4) +#define MICRO_USB_DETECTION_ON_TIME_CFG_MASK GENMASK(3, 2) +#define MICRO_USB_DETECTION_PERIOD_CFG_MASK GENMASK(1, 0) + +#define TYPEC_PMI632_MICRO_USB_MODE_REG 0x73 +#define MICRO_USB_MODE_ONLY BIT(0) + +/* Interrupt numbers */ +#define PMIC_TYPEC_OR_RID_IRQ 0x0 +#define PMIC_TYPEC_VPD_IRQ 0x1 +#define PMIC_TYPEC_CC_STATE_IRQ 0x2 +#define PMIC_TYPEC_VCONN_OC_IRQ 0x3 +#define PMIC_TYPEC_VBUS_IRQ 0x4 +#define PMIC_TYPEC_ATTACH_DETACH_IRQ 0x5 +#define PMIC_TYPEC_LEGACY_CABLE_IRQ 0x6 +#define PMIC_TYPEC_TRY_SNK_SRC_IRQ 0x7 + struct pmic_typec_port_irq_data { int virq; int irq; @@ -33,6 +172,8 @@ struct pmic_typec_port { struct pmic_typec_port_irq_data *irq_data; struct regulator *vdd_vbus; + bool vbus_enabled; + struct mutex vbus_lock; /* VBUS state serialization */ int cc; bool debouncing_cc; @@ -131,7 +272,7 @@ static irqreturn_t pmic_typec_port_isr(int irq, void *dev_id) return IRQ_HANDLED; } -int qcom_pmic_typec_port_get_vbus(struct pmic_typec_port *pmic_typec_port) +static int qcom_pmic_typec_port_vbus_detect(struct pmic_typec_port *pmic_typec_port) { struct device *dev = pmic_typec_port->dev; unsigned int misc; @@ -148,7 +289,7 @@ int qcom_pmic_typec_port_get_vbus(struct pmic_typec_port *pmic_typec_port) return !!(misc & TYPEC_VBUS_DETECT); } -int qcom_pmic_typec_port_set_vbus(struct pmic_typec_port *pmic_typec_port, bool on) +static int qcom_pmic_typec_port_vbus_toggle(struct pmic_typec_port *pmic_typec_port, bool on) { u32 sm_stat; u32 val; @@ -179,10 +320,49 @@ int qcom_pmic_typec_port_set_vbus(struct pmic_typec_port *pmic_typec_port, bool return 0; } -int qcom_pmic_typec_port_get_cc(struct pmic_typec_port *pmic_typec_port, - enum typec_cc_status *cc1, - enum typec_cc_status *cc2) +static int qcom_pmic_typec_port_get_vbus(struct tcpc_dev *tcpc) +{ + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port; + int ret; + + mutex_lock(&pmic_typec_port->vbus_lock); + ret = pmic_typec_port->vbus_enabled || qcom_pmic_typec_port_vbus_detect(pmic_typec_port); + mutex_unlock(&pmic_typec_port->vbus_lock); + + return ret; +} + +static int qcom_pmic_typec_port_set_vbus(struct tcpc_dev *tcpc, bool on, bool sink) +{ + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port; + int ret = 0; + + mutex_lock(&pmic_typec_port->vbus_lock); + if (pmic_typec_port->vbus_enabled == on) + goto done; + + ret = qcom_pmic_typec_port_vbus_toggle(pmic_typec_port, on); + if (ret) + goto done; + + pmic_typec_port->vbus_enabled = on; + tcpm_vbus_change(tcpm->tcpm_port); + +done: + dev_dbg(tcpm->dev, "set_vbus set: %d result %d\n", on, ret); + mutex_unlock(&pmic_typec_port->vbus_lock); + + return ret; +} + +static int qcom_pmic_typec_port_get_cc(struct tcpc_dev *tcpc, + enum typec_cc_status *cc1, + enum typec_cc_status *cc2) { + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port; struct device *dev = pmic_typec_port->dev; unsigned int misc, val; bool attached; @@ -275,9 +455,11 @@ static void qcom_pmic_set_cc_debounce(struct pmic_typec_port *pmic_typec_port) msecs_to_jiffies(2)); } -int qcom_pmic_typec_port_set_cc(struct pmic_typec_port *pmic_typec_port, - enum typec_cc_status cc) +static int qcom_pmic_typec_port_set_cc(struct tcpc_dev *tcpc, + enum typec_cc_status cc) { + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port; struct device *dev = pmic_typec_port->dev; unsigned int mode, currsrc; unsigned int misc; @@ -341,8 +523,17 @@ int qcom_pmic_typec_port_set_cc(struct pmic_typec_port *pmic_typec_port, return ret; } -int qcom_pmic_typec_port_set_vconn(struct pmic_typec_port *pmic_typec_port, bool on) +static int qcom_pmic_typec_port_set_polarity(struct tcpc_dev *tcpc, + enum typec_cc_polarity pol) +{ + /* Polarity is set separately by phy-qcom-qmp.c */ + return 0; +} + +static int qcom_pmic_typec_port_set_vconn(struct tcpc_dev *tcpc, bool on) { + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port; struct device *dev = pmic_typec_port->dev; unsigned int orientation, misc, mask, value; unsigned long flags; @@ -377,10 +568,12 @@ int qcom_pmic_typec_port_set_vconn(struct pmic_typec_port *pmic_typec_port, bool return ret; } -int qcom_pmic_typec_port_start_toggling(struct pmic_typec_port *pmic_typec_port, - enum typec_port_type port_type, - enum typec_cc_status cc) +static int qcom_pmic_typec_port_start_toggling(struct tcpc_dev *tcpc, + enum typec_port_type port_type, + enum typec_cc_status cc) { + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port; struct device *dev = pmic_typec_port->dev; unsigned int misc; u8 mode = 0; @@ -441,9 +634,10 @@ int qcom_pmic_typec_port_start_toggling(struct pmic_typec_port *pmic_typec_port, (TYPEC_STATE_MACHINE_CHANGE_INT_EN | TYPEC_VBUS_ERROR_INT_EN | \ TYPEC_DEBOUNCE_DONE_INT_EN) -int qcom_pmic_typec_port_start(struct pmic_typec_port *pmic_typec_port, - struct tcpm_port *tcpm_port) +static int qcom_pmic_typec_port_start(struct pmic_typec *tcpm, + struct tcpm_port *tcpm_port) { + struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port; int i; int mask; int ret; @@ -491,29 +685,30 @@ int qcom_pmic_typec_port_start(struct pmic_typec_port *pmic_typec_port, return ret; } -void qcom_pmic_typec_port_stop(struct pmic_typec_port *pmic_typec_port) +static void qcom_pmic_typec_port_stop(struct pmic_typec *tcpm) { + struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port; int i; for (i = 0; i < pmic_typec_port->nr_irqs; i++) disable_irq(pmic_typec_port->irq_data[i].irq); } -struct pmic_typec_port *qcom_pmic_typec_port_alloc(struct device *dev) -{ - return devm_kzalloc(dev, sizeof(struct pmic_typec_port), GFP_KERNEL); -} - int qcom_pmic_typec_port_probe(struct platform_device *pdev, - struct pmic_typec_port *pmic_typec_port, - struct pmic_typec_port_resources *res, + struct pmic_typec *tcpm, + const struct pmic_typec_port_resources *res, struct regmap *regmap, u32 base) { struct device *dev = &pdev->dev; struct pmic_typec_port_irq_data *irq_data; + struct pmic_typec_port *pmic_typec_port; int i, ret, irq; + pmic_typec_port = devm_kzalloc(dev, sizeof(*pmic_typec_port), GFP_KERNEL); + if (!pmic_typec_port) + return -ENOMEM; + if (!res->nr_irqs || res->nr_irqs > PMIC_TYPEC_MAX_IRQS) return -EINVAL; @@ -522,6 +717,8 @@ int qcom_pmic_typec_port_probe(struct platform_device *pdev, if (!irq_data) return -ENOMEM; + mutex_init(&pmic_typec_port->vbus_lock); + pmic_typec_port->vdd_vbus = devm_regulator_get(dev, "vdd-vbus"); if (IS_ERR(pmic_typec_port->vdd_vbus)) return PTR_ERR(pmic_typec_port->vdd_vbus); @@ -556,5 +753,56 @@ int qcom_pmic_typec_port_probe(struct platform_device *pdev, return ret; } + tcpm->pmic_typec_port = pmic_typec_port; + + tcpm->tcpc.get_vbus = qcom_pmic_typec_port_get_vbus; + tcpm->tcpc.set_vbus = qcom_pmic_typec_port_set_vbus; + tcpm->tcpc.set_cc = qcom_pmic_typec_port_set_cc; + tcpm->tcpc.get_cc = qcom_pmic_typec_port_get_cc; + tcpm->tcpc.set_polarity = qcom_pmic_typec_port_set_polarity; + tcpm->tcpc.set_vconn = qcom_pmic_typec_port_set_vconn; + tcpm->tcpc.start_toggling = qcom_pmic_typec_port_start_toggling; + + tcpm->port_start = qcom_pmic_typec_port_start; + tcpm->port_stop = qcom_pmic_typec_port_stop; + return 0; } + +const struct pmic_typec_port_resources pm8150b_port_res = { + .irq_params = { + { + .irq_name = "vpd-detect", + .virq = PMIC_TYPEC_VPD_IRQ, + }, + + { + .irq_name = "cc-state-change", + .virq = PMIC_TYPEC_CC_STATE_IRQ, + }, + { + .irq_name = "vconn-oc", + .virq = PMIC_TYPEC_VCONN_OC_IRQ, + }, + + { + .irq_name = "vbus-change", + .virq = PMIC_TYPEC_VBUS_IRQ, + }, + + { + .irq_name = "attach-detach", + .virq = PMIC_TYPEC_ATTACH_DETACH_IRQ, + }, + { + .irq_name = "legacy-cable-detect", + .virq = PMIC_TYPEC_LEGACY_CABLE_IRQ, + }, + + { + .irq_name = "try-snk-src-detect", + .virq = PMIC_TYPEC_TRY_SNK_SRC_IRQ, + }, + }, + .nr_irqs = 7, +}; diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h index 4a892048908e..2ca83a46cf3b 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_port.h @@ -9,143 +9,6 @@ #include #include -#define TYPEC_SNK_STATUS_REG 0x06 -#define DETECTED_SNK_TYPE_MASK GENMASK(6, 0) -#define SNK_DAM_MASK GENMASK(6, 4) -#define SNK_DAM_500MA BIT(6) -#define SNK_DAM_1500MA BIT(5) -#define SNK_DAM_3000MA BIT(4) -#define SNK_RP_STD BIT(3) -#define SNK_RP_1P5 BIT(2) -#define SNK_RP_3P0 BIT(1) -#define SNK_RP_SHORT BIT(0) - -#define TYPEC_SRC_STATUS_REG 0x08 -#define DETECTED_SRC_TYPE_MASK GENMASK(4, 0) -#define SRC_HIGH_BATT BIT(5) -#define SRC_DEBUG_ACCESS BIT(4) -#define SRC_RD_OPEN BIT(3) -#define SRC_RD_RA_VCONN BIT(2) -#define SRC_RA_OPEN BIT(1) -#define AUDIO_ACCESS_RA_RA BIT(0) - -#define TYPEC_STATE_MACHINE_STATUS_REG 0x09 -#define TYPEC_ATTACH_DETACH_STATE BIT(5) - -#define TYPEC_SM_STATUS_REG 0x0A -#define TYPEC_SM_VBUS_VSAFE5V BIT(5) -#define TYPEC_SM_VBUS_VSAFE0V BIT(6) -#define TYPEC_SM_USBIN_LT_LV BIT(7) - -#define TYPEC_MISC_STATUS_REG 0x0B -#define TYPEC_WATER_DETECTION_STATUS BIT(7) -#define SNK_SRC_MODE BIT(6) -#define TYPEC_VBUS_DETECT BIT(5) -#define TYPEC_VBUS_ERROR_STATUS BIT(4) -#define TYPEC_DEBOUNCE_DONE BIT(3) -#define CC_ORIENTATION BIT(1) -#define CC_ATTACHED BIT(0) - -#define LEGACY_CABLE_STATUS_REG 0x0D -#define TYPEC_LEGACY_CABLE_STATUS BIT(1) -#define TYPEC_NONCOMP_LEGACY_CABLE_STATUS BIT(0) - -#define TYPEC_U_USB_STATUS_REG 0x0F -#define U_USB_GROUND_NOVBUS BIT(6) -#define U_USB_GROUND BIT(4) -#define U_USB_FMB1 BIT(3) -#define U_USB_FLOAT1 BIT(2) -#define U_USB_FMB2 BIT(1) -#define U_USB_FLOAT2 BIT(0) - -#define TYPEC_MODE_CFG_REG 0x44 -#define TYPEC_TRY_MODE_MASK GENMASK(4, 3) -#define EN_TRY_SNK BIT(4) -#define EN_TRY_SRC BIT(3) -#define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0) -#define EN_SRC_ONLY BIT(2) -#define EN_SNK_ONLY BIT(1) -#define TYPEC_DISABLE_CMD BIT(0) - -#define TYPEC_VCONN_CONTROL_REG 0x46 -#define VCONN_EN_ORIENTATION BIT(2) -#define VCONN_EN_VALUE BIT(1) -#define VCONN_EN_SRC BIT(0) - -#define TYPEC_CCOUT_CONTROL_REG 0x48 -#define TYPEC_CCOUT_BUFFER_EN BIT(2) -#define TYPEC_CCOUT_VALUE BIT(1) -#define TYPEC_CCOUT_SRC BIT(0) - -#define DEBUG_ACCESS_SRC_CFG_REG 0x4C -#define EN_UNORIENTED_DEBUG_ACCESS_SRC BIT(0) - -#define TYPE_C_CRUDE_SENSOR_CFG_REG 0x4e -#define EN_SRC_CRUDE_SENSOR BIT(1) -#define EN_SNK_CRUDE_SENSOR BIT(0) - -#define TYPEC_EXIT_STATE_CFG_REG 0x50 -#define BYPASS_VSAFE0V_DURING_ROLE_SWAP BIT(3) -#define SEL_SRC_UPPER_REF BIT(2) -#define USE_TPD_FOR_EXITING_ATTACHSRC BIT(1) -#define EXIT_SNK_BASED_ON_CC BIT(0) - -#define TYPEC_CURRSRC_CFG_REG 0x52 -#define TYPEC_SRC_RP_SEL_330UA BIT(1) -#define TYPEC_SRC_RP_SEL_180UA BIT(0) -#define TYPEC_SRC_RP_SEL_80UA 0 -#define TYPEC_SRC_RP_SEL_MASK GENMASK(1, 0) - -#define TYPEC_INTERRUPT_EN_CFG_1_REG 0x5E -#define TYPEC_LEGACY_CABLE_INT_EN BIT(7) -#define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN BIT(6) -#define TYPEC_TRYSOURCE_DETECT_INT_EN BIT(5) -#define TYPEC_TRYSINK_DETECT_INT_EN BIT(4) -#define TYPEC_CCOUT_DETACH_INT_EN BIT(3) -#define TYPEC_CCOUT_ATTACH_INT_EN BIT(2) -#define TYPEC_VBUS_DEASSERT_INT_EN BIT(1) -#define TYPEC_VBUS_ASSERT_INT_EN BIT(0) - -#define TYPEC_INTERRUPT_EN_CFG_2_REG 0x60 -#define TYPEC_SRC_BATT_HPWR_INT_EN BIT(6) -#define MICRO_USB_STATE_CHANGE_INT_EN BIT(5) -#define TYPEC_STATE_MACHINE_CHANGE_INT_EN BIT(4) -#define TYPEC_DEBUG_ACCESS_DETECT_INT_EN BIT(3) -#define TYPEC_WATER_DETECTION_INT_EN BIT(2) -#define TYPEC_VBUS_ERROR_INT_EN BIT(1) -#define TYPEC_DEBOUNCE_DONE_INT_EN BIT(0) - -#define TYPEC_DEBOUNCE_OPTION_REG 0x62 -#define REDUCE_TCCDEBOUNCE_TO_2MS BIT(2) - -#define TYPE_C_SBU_CFG_REG 0x6A -#define SEL_SBU1_ISRC_VAL 0x04 -#define SEL_SBU2_ISRC_VAL 0x01 - -#define TYPEC_U_USB_CFG_REG 0x70 -#define EN_MICRO_USB_FACTORY_MODE BIT(1) -#define EN_MICRO_USB_MODE BIT(0) - -#define TYPEC_PMI632_U_USB_WATER_PROTECTION_CFG_REG 0x72 - -#define TYPEC_U_USB_WATER_PROTECTION_CFG_REG 0x73 -#define EN_MICRO_USB_WATER_PROTECTION BIT(4) -#define MICRO_USB_DETECTION_ON_TIME_CFG_MASK GENMASK(3, 2) -#define MICRO_USB_DETECTION_PERIOD_CFG_MASK GENMASK(1, 0) - -#define TYPEC_PMI632_MICRO_USB_MODE_REG 0x73 -#define MICRO_USB_MODE_ONLY BIT(0) - -/* Interrupt numbers */ -#define PMIC_TYPEC_OR_RID_IRQ 0x0 -#define PMIC_TYPEC_VPD_IRQ 0x1 -#define PMIC_TYPEC_CC_STATE_IRQ 0x2 -#define PMIC_TYPEC_VCONN_OC_IRQ 0x3 -#define PMIC_TYPEC_VBUS_IRQ 0x4 -#define PMIC_TYPEC_ATTACH_DETACH_IRQ 0x5 -#define PMIC_TYPEC_LEGACY_CABLE_IRQ 0x6 -#define PMIC_TYPEC_TRY_SNK_SRC_IRQ 0x7 - /* Resources */ #define PMIC_TYPEC_MAX_IRQS 0x08 @@ -156,40 +19,17 @@ struct pmic_typec_port_irq_params { struct pmic_typec_port_resources { unsigned int nr_irqs; - struct pmic_typec_port_irq_params irq_params[PMIC_TYPEC_MAX_IRQS]; + const struct pmic_typec_port_irq_params irq_params[PMIC_TYPEC_MAX_IRQS]; }; /* API */ -struct pmic_typec; -struct pmic_typec_port *qcom_pmic_typec_port_alloc(struct device *dev); +extern const struct pmic_typec_port_resources pm8150b_port_res; int qcom_pmic_typec_port_probe(struct platform_device *pdev, - struct pmic_typec_port *pmic_typec_port, - struct pmic_typec_port_resources *res, + struct pmic_typec *tcpm, + const struct pmic_typec_port_resources *res, struct regmap *regmap, u32 base); -int qcom_pmic_typec_port_start(struct pmic_typec_port *pmic_typec_port, - struct tcpm_port *tcpm_port); - -void qcom_pmic_typec_port_stop(struct pmic_typec_port *pmic_typec_port); - -int qcom_pmic_typec_port_get_cc(struct pmic_typec_port *pmic_typec_port, - enum typec_cc_status *cc1, - enum typec_cc_status *cc2); - -int qcom_pmic_typec_port_set_cc(struct pmic_typec_port *pmic_typec_port, - enum typec_cc_status cc); - -int qcom_pmic_typec_port_get_vbus(struct pmic_typec_port *pmic_typec_port); - -int qcom_pmic_typec_port_set_vconn(struct pmic_typec_port *pmic_typec_port, bool on); - -int qcom_pmic_typec_port_start_toggling(struct pmic_typec_port *pmic_typec_port, - enum typec_port_type port_type, - enum typec_cc_status cc); - -int qcom_pmic_typec_port_set_vbus(struct pmic_typec_port *pmic_typec_port, bool on); - #endif /* __QCOM_PMIC_TYPE_C_PORT_H__ */ From patchwork Sat Jan 13 20:55:52 2024 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09/15] usb: typec: qcom-pmic-typec: add support for PMI632 PMIC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-9-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=6288; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=YAFW/4mrIAbAiMjNUbGgByzdIfRhqwoyh7K7k/Tq5n8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjXrRuRRhjKDD7Mp1LMhUW1DuaZiQLjxmErO gSqvmw6q7qJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41wAKCRCLPIo+Aiko 1djlB/9DMtoyIYFdhyxr2oEoqXJI844mQEKqxTm+3VeOIh0Tf5r0hntWC3IURRpmhdqb6Vlvi3g whNMAiW/GWWfbs9P47eJcUerEzT8Ss9Lk3Y9f8KsHqrmCLuZU7yiLu8TWu+Pl5N0uNuMeohu6Zh Nd7QvuUzDaKJqXpi/HJ49MTl14Te+VaYamrdbVY65CcusfQ0Vu8c7BP+QXzUftXKXACj6NIm/XF ibKmpJ5FxMNpUb3SVBbAwsBTB8cyPhmLEoTZ58zRcDcZvz3gtgkCmcoxcbK2A2TO4cfMAa/xARi A5Cn8i4BAswX+aiWR7TRpoWSLlhI7tws2oxoatsn/WI4V3QD X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The PMI632 PMIC support Type-C port handling, but lacks USB PowerDelivery support. The TCPM requires all callbacks to be provided by the implementation. Implement a special, 'stub' Qcom PD PHY implementation to enable the PMI632 support. Acked-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Acked-by: Heikki Krogerus --- drivers/usb/typec/tcpm/qcom/Makefile | 3 +- drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c | 30 ++++++-- .../usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h | 2 + .../typec/tcpm/qcom/qcom_pmic_typec_pdphy_stub.c | 80 ++++++++++++++++++++++ 4 files changed, 107 insertions(+), 8 deletions(-) diff --git a/drivers/usb/typec/tcpm/qcom/Makefile b/drivers/usb/typec/tcpm/qcom/Makefile index dc1e8832e197..cc23042b9487 100644 --- a/drivers/usb/typec/tcpm/qcom/Makefile +++ b/drivers/usb/typec/tcpm/qcom/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_TYPEC_QCOM_PMIC) += qcom_pmic_tcpm.o qcom_pmic_tcpm-y += qcom_pmic_typec.o \ qcom_pmic_typec_port.o \ - qcom_pmic_typec_pdphy.o + qcom_pmic_typec_pdphy.o \ + qcom_pmic_typec_pdphy_stub.o \ diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c index 82e3f59ea471..e48412cdcb0f 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c @@ -42,7 +42,7 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) const struct pmic_typec_resources *res; struct regmap *regmap; struct device *bridge_dev; - u32 base[2]; + u32 base; int ret; res = of_device_get_match_data(dev); @@ -62,19 +62,29 @@ static int qcom_pmic_typec_probe(struct platform_device *pdev) return -ENODEV; } - ret = of_property_read_u32_array(np, "reg", base, 2); + ret = of_property_read_u32_index(np, "reg", 0, &base); if (ret) return ret; ret = qcom_pmic_typec_port_probe(pdev, tcpm, - res->port_res, regmap, base[0]); + res->port_res, regmap, base); if (ret) return ret; - ret = qcom_pmic_typec_pdphy_probe(pdev, tcpm, - res->pdphy_res, regmap, base[1]); - if (ret) - return ret; + if (res->pdphy_res) { + ret = of_property_read_u32_index(np, "reg", 1, &base); + if (ret) + return ret; + + ret = qcom_pmic_typec_pdphy_probe(pdev, tcpm, + res->pdphy_res, regmap, base); + if (ret) + return ret; + } else { + ret = qcom_pmic_typec_pdphy_stub_probe(pdev, tcpm); + if (ret) + return ret; + } platform_set_drvdata(pdev, tcpm); @@ -123,8 +133,14 @@ static const struct pmic_typec_resources pm8150b_typec_res = { .port_res = &pm8150b_port_res, }; +static const struct pmic_typec_resources pmi632_typec_res = { + /* PD PHY not present */ + .port_res = &pm8150b_port_res, +}; + static const struct of_device_id qcom_pmic_typec_table[] = { { .compatible = "qcom,pm8150b-typec", .data = &pm8150b_typec_res }, + { .compatible = "qcom,pmi632-typec", .data = &pmi632_typec_res }, { } }; MODULE_DEVICE_TABLE(of, qcom_pmic_typec_table); diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h index 5f428e67ccfe..04dee20293cf 100644 --- a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy.h @@ -31,5 +31,7 @@ int qcom_pmic_typec_pdphy_probe(struct platform_device *pdev, const struct pmic_typec_pdphy_resources *res, struct regmap *regmap, u32 base); +int qcom_pmic_typec_pdphy_stub_probe(struct platform_device *pdev, + struct pmic_typec *tcpm); #endif /* __QCOM_PMIC_TYPEC_PDPHY_H__ */ diff --git a/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy_stub.c b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy_stub.c new file mode 100644 index 000000000000..df79059cda67 --- /dev/null +++ b/drivers/usb/typec/tcpm/qcom/qcom_pmic_typec_pdphy_stub.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024, Linaro Ltd. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qcom_pmic_typec.h" +#include "qcom_pmic_typec_pdphy.h" + +static int qcom_pmic_typec_pdphy_stub_pd_transmit(struct tcpc_dev *tcpc, + enum tcpm_transmit_type type, + const struct pd_message *msg, + unsigned int negotiated_rev) +{ + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct device *dev = tcpm->dev; + + dev_dbg(dev, "pdphy_transmit: type=%d\n", type); + + tcpm_pd_transmit_complete(tcpm->tcpm_port, + TCPC_TX_SUCCESS); + + return 0; +} + +static int qcom_pmic_typec_pdphy_stub_set_pd_rx(struct tcpc_dev *tcpc, bool on) +{ + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct device *dev = tcpm->dev; + + dev_dbg(dev, "set_pd_rx: %s\n", on ? "on" : "off"); + + return 0; +} + +static int qcom_pmic_typec_pdphy_stub_set_roles(struct tcpc_dev *tcpc, bool attached, + enum typec_role power_role, + enum typec_data_role data_role) +{ + struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc); + struct device *dev = tcpm->dev; + + dev_dbg(dev, "pdphy_set_roles: data_role_host=%d power_role_src=%d\n", + data_role, power_role); + + return 0; +} + +static int qcom_pmic_typec_pdphy_stub_start(struct pmic_typec *tcpm, + struct tcpm_port *tcpm_port) +{ + return 0; +} + +static void qcom_pmic_typec_pdphy_stub_stop(struct pmic_typec *tcpm) +{ +} + +int qcom_pmic_typec_pdphy_stub_probe(struct platform_device *pdev, + struct pmic_typec *tcpm) +{ + tcpm->tcpc.set_pd_rx = qcom_pmic_typec_pdphy_stub_set_pd_rx; + tcpm->tcpc.set_roles = qcom_pmic_typec_pdphy_stub_set_roles; + tcpm->tcpc.pd_transmit = qcom_pmic_typec_pdphy_stub_pd_transmit; + + tcpm->pdphy_start = qcom_pmic_typec_pdphy_stub_start; + tcpm->pdphy_stop = qcom_pmic_typec_pdphy_stub_stop; + + return 0; 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Sat, 13 Jan 2024 12:56:01 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id p14-20020a056512328e00b0050e9355d7eesm919802lfe.103.2024.01.13.12.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 12:56:01 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:53 +0200 Subject: [PATCH v2 10/15] phy: qcom: qmp-usb: split USB-C PHY driver Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-10-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=52063; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ZJg4llfngILa9DKYLjjUSnilWTJVmR2p/HyBq6ZRuBk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjXevVlO2/3hvjBy92h1dpjQ12SmyosUCCzh 9AQXdQt8ieJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41wAKCRCLPIo+Aiko 1SgOB/4z3fagPguxENktyiefsNhfYJGHZF5sO/eXraQ/9INyX0gV8qVUHdqSMcV+KZqjnv5DfpX +1XHCB6iNk5eV6coswWoqyxezw90nfGGUEq34xh1AWV8P/Yiiwc9gsHG5IhFqvoI5WPbZvk4THP R9ujkOcydN9KhrBO4ZGy5lrIHMB5cc9OR6yn1z2guyIREZwFDafngdObmFPuHWuhx4Ry3703Dv4 97M+cXy6UQJXn8mWSjkVtZG+G8R2OuHNWOkWMwhHHbxlXWlfAEzPdcPUcDRgAq55WoASzAzHdHk lR0ngKmvt4vBl1onPai1wd7Ihlm6Qkyz2jbbsiQWcy03cO8r X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A In preparation to adding Type-C handling for MSM8998, QCM2290 and SM6115 platforms, create new QMP USB-C PHY driver by splitting mentioned platforms to a separate file. In future it will also be extended with support for the DisplayPort handling. It will also be reused later for such platforms as SDM660, SM6125, SM6150. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio --- drivers/phy/qualcomm/Makefile | 2 +- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 266 -------- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 1078 ++++++++++++++++++++++++++++++ 3 files changed, 1079 insertions(+), 267 deletions(-) diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index ffd609ac6233..eb60e950ad53 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o -obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o +obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o obj-$(CONFIG_PHY_QCOM_QMP_PCIE_8996) += phy-qcom-qmp-pcie-msm8996.o obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 243cc2b9a0fb..c7698369d3dc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -121,15 +121,6 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE, }; -static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, - [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, - [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, - [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, -}; - static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, @@ -514,115 +505,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), }; -static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), - QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), -}; - -static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), -}; - -static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), -}; - -static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), -}; - static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), @@ -1089,99 +971,6 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), }; -static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), -}; - -static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), -}; - -static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), -}; - -static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), - QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), -}; - static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), @@ -1571,16 +1360,6 @@ static const struct qmp_usb_offsets qmp_usb_offsets_v3 = { .rx = 0x400, }; -static const struct qmp_usb_offsets qmp_usb_offsets_v3_qcm2290 = { - .serdes = 0x0, - .pcs = 0xc00, - .pcs_misc = 0xa00, - .tx = 0x200, - .rx = 0x400, - .tx2 = 0x600, - .rx2 = 0x800, -}; - static const struct qmp_usb_offsets qmp_usb_offsets_v4 = { .serdes = 0, .pcs = 0x0800, @@ -1727,24 +1506,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { .has_pwrdn_delay = true, }; -static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { - .lanes = 2, - - .offsets = &qmp_usb_offsets_v3_qcm2290, - - .serdes_tbl = msm8998_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), - .tx_tbl = msm8998_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), - .rx_tbl = msm8998_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), - .pcs_tbl = msm8998_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v3_usb3phy_regs_layout, -}; - static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { .lanes = 1, @@ -1882,24 +1643,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { .has_pwrdn_delay = true, }; -static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { - .lanes = 2, - - .offsets = &qmp_usb_offsets_v3_qcm2290, - - .serdes_tbl = qcm2290_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), - .tx_tbl = qcm2290_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), - .rx_tbl = qcm2290_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), - .pcs_tbl = qcm2290_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v3_usb3phy_regs_layout_qcm2290, -}; - static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = { .lanes = 1, @@ -2573,12 +2316,6 @@ static const struct of_device_id qmp_usb_of_match_table[] = { }, { .compatible = "qcom,msm8996-qmp-usb3-phy", .data = &msm8996_usb3phy_cfg, - }, { - .compatible = "qcom,msm8998-qmp-usb3-phy", - .data = &msm8998_usb3phy_cfg, - }, { - .compatible = "qcom,qcm2290-qmp-usb3-phy", - .data = &qcm2290_usb3phy_cfg, }, { .compatible = "qcom,sa8775p-qmp-usb3-uni-phy", .data = &sa8775p_usb3_uniphy_cfg, @@ -2597,9 +2334,6 @@ static const struct of_device_id qmp_usb_of_match_table[] = { }, { .compatible = "qcom,sdx75-qmp-usb3-uni-phy", .data = &sdx75_usb3_uniphy_cfg, - }, { - .compatible = "qcom,sm6115-qmp-usb3-phy", - .data = &qcm2290_usb3phy_cfg, }, { .compatible = "qcom,sm8150-qmp-usb3-uni-phy", .data = &sm8150_usb3_uniphy_cfg, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c new file mode 100644 index 000000000000..52f1b3f7b81e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -0,0 +1,1078 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-qcom-qmp.h" +#include "phy-qcom-qmp-pcs-misc-v3.h" + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +/* QPHY_POWER_DOWN_CONTROL */ +#define SW_PWRDN BIT(0) +/* QPHY_START_CONTROL bits */ +#define SERDES_START BIT(0) +#define PCS_START BIT(1) +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) + +/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ +/* DP PHY soft reset */ +#define SW_DPPHY_RESET BIT(0) +/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ +#define SW_DPPHY_RESET_MUX BIT(1) +/* USB3 PHY soft reset */ +#define SW_USB3PHY_RESET BIT(2) +/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ +#define SW_USB3PHY_RESET_MUX BIT(3) + +/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ +#define USB3_MODE BIT(0) /* enables USB3 mode */ +#define DP_MODE BIT(1) /* enables DP mode */ + +/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ +#define ARCVR_DTCT_EN BIT(0) +#define ALFPS_DTCT_EN BIT(1) +#define ARCVR_DTCT_EVENT_SEL BIT(4) + +/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ +#define IRQ_CLEAR BIT(0) + +/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ +#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ + +#define PHY_INIT_COMPLETE_TIMEOUT 10000 + +struct qmp_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * mask of lanes for which this register is written + * for cases when second lane needs different values + */ + u8 lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = l, \ + } + +/* set of registers with offsets different per-PHY */ +enum qphy_reg_layout { + /* PCS registers */ + QPHY_SW_RESET, + QPHY_START_CTRL, + QPHY_PCS_STATUS, + QPHY_PCS_AUTONOMOUS_MODE_CTRL, + QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, + QPHY_PCS_POWER_DOWN_CONTROL, + QPHY_PCS_MISC_CLAMP_ENABLE, + /* Keep last to ensure regs_layout arrays are properly initialized */ + QPHY_LAYOUT_SIZE +}; + +static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE, +}; + +static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), +}; + +static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +}; + +static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), +}; + +static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), +}; + +static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), +}; + +static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), +}; + +struct qmp_usbc_offsets { + u16 serdes; + u16 pcs; + u16 pcs_misc; + u16 tx; + u16 rx; + /* for PHYs with >= 2 lanes */ + u16 tx2; + u16 rx2; +}; + +/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_phy_cfg { + const struct qmp_usbc_offsets *offsets; + + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + + /* regulators to be requested */ + const char * const *vreg_list; + int num_vregs; + + /* array of registers with different offsets */ + const unsigned int *regs; + + /* true, if PHY needs delay after POWER_DOWN */ + bool has_pwrdn_delay; +}; + +struct qmp_usbc { + struct device *dev; + + const struct qmp_phy_cfg *cfg; + + void __iomem *serdes; + void __iomem *pcs; + void __iomem *pcs_misc; + void __iomem *tx; + void __iomem *rx; + void __iomem *tx2; + void __iomem *rx2; + + struct clk *pipe_clk; + struct clk_bulk_data *clks; + int num_clks; + int num_resets; + struct reset_control_bulk_data *resets; + struct regulator_bulk_data *vregs; + + enum phy_mode mode; + + struct phy *phy; + + struct clk_fixed_rate pipe_clk_fixed; +}; + +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg |= val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +/* list of clocks required by phy */ +static const char * const qmp_usbc_phy_clk_l[] = { + "aux", "cfg_ahb", "ref", "com_aux", +}; + +/* list of resets */ +static const char * const usb3phy_legacy_reset_l[] = { + "phy", "common", +}; + +static const char * const usb3phy_reset_l[] = { + "phy_phy", "phy", +}; + +/* list of regulators */ +static const char * const qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", +}; + +static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 = { + .serdes = 0x0, + .pcs = 0xc00, + .pcs_misc = 0xa00, + .tx = 0x200, + .rx = 0x400, + .tx2 = 0x600, + .rx2 = 0x800, +}; + +static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { + .offsets = &qmp_usbc_offsets_v3_qcm2290, + + .serdes_tbl = msm8998_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), + .tx_tbl = msm8998_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), + .rx_tbl = msm8998_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), + .pcs_tbl = msm8998_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, +}; + +static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { + .offsets = &qmp_usbc_offsets_v3_qcm2290, + + .serdes_tbl = qcm2290_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), + .tx_tbl = qcm2290_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), + .rx_tbl = qcm2290_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), + .pcs_tbl = qcm2290_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout_qcm2290, +}; + +static void qmp_usbc_configure_lane(void __iomem *base, + const struct qmp_phy_init_tbl tbl[], + int num, + u8 lane_mask) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & lane_mask)) + continue; + + writel(t->val, base + t->offset); + } +} + +static void qmp_usbc_configure(void __iomem *base, + const struct qmp_phy_init_tbl tbl[], + int num) +{ + qmp_usbc_configure_lane(base, tbl, num, 0xff); +} + +static int qmp_usbc_init(struct phy *phy) +{ + struct qmp_usbc *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *pcs = qmp->pcs; + int ret; + + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); + return ret; + } + + ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; + } + + ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_disable_regulators; + } + + ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); + if (ret) + goto err_assert_reset; + + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); + + return 0; + +err_assert_reset: + reset_control_bulk_assert(qmp->num_resets, qmp->resets); +err_disable_regulators: + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return ret; +} + +static int qmp_usbc_exit(struct phy *phy) +{ + struct qmp_usbc *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; + + reset_control_bulk_assert(qmp->num_resets, qmp->resets); + + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); + + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + + return 0; +} + +static int qmp_usbc_power_on(struct phy *phy) +{ + struct qmp_usbc *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *status; + unsigned int val; + int ret; + + qmp_usbc_configure(qmp->serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); + + ret = clk_prepare_enable(qmp->pipe_clk); + if (ret) { + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); + return ret; + } + + /* Tx, Rx, and PCS configurations */ + qmp_usbc_configure_lane(qmp->tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); + qmp_usbc_configure_lane(qmp->rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); + + qmp_usbc_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); + qmp_usbc_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); + + qmp_usbc_configure(qmp->pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); + + if (cfg->has_pwrdn_delay) + usleep_range(10, 20); + + /* Pull PHY out of reset state */ + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); + + status = qmp->pcs + cfg->regs[QPHY_PCS_STATUS]; + ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_disable_pipe_clk; + } + + return 0; + +err_disable_pipe_clk: + clk_disable_unprepare(qmp->pipe_clk); + + return ret; +} + +static int qmp_usbc_power_off(struct phy *phy) +{ + struct qmp_usbc *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; + + clk_disable_unprepare(qmp->pipe_clk); + + /* PHY reset */ + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], + SERDES_START | PCS_START); + + /* Put PHY into POWER DOWN state: active low */ + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + SW_PWRDN); + + return 0; +} + +static int qmp_usbc_enable(struct phy *phy) +{ + int ret; + + ret = qmp_usbc_init(phy); + if (ret) + return ret; + + ret = qmp_usbc_power_on(phy); + if (ret) + qmp_usbc_exit(phy); + + return ret; +} + +static int qmp_usbc_disable(struct phy *phy) +{ + int ret; + + ret = qmp_usbc_power_off(phy); + if (ret) + return ret; + return qmp_usbc_exit(phy); +} + +static int qmp_usbc_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct qmp_usbc *qmp = phy_get_drvdata(phy); + + qmp->mode = mode; + + return 0; +} + +static const struct phy_ops qmp_usbc_phy_ops = { + .init = qmp_usbc_enable, + .exit = qmp_usbc_disable, + .set_mode = qmp_usbc_set_mode, + .owner = THIS_MODULE, +}; + +static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) +{ + const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *pcs = qmp->pcs; + void __iomem *pcs_misc = qmp->pcs_misc; + u32 intr_mask; + + if (qmp->mode == PHY_MODE_USB_HOST_SS || + qmp->mode == PHY_MODE_USB_DEVICE_SS) + intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; + else + intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; + + /* Clear any pending interrupts status */ + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + /* Writing 1 followed by 0 clears the interrupt */ + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], + ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); + + /* Enable required PHY autonomous mode interrupts */ + qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); + + /* Enable i/o clamp_n for autonomous mode */ + if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE]) + qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN); +} + +static void qmp_usbc_disable_autonomous_mode(struct qmp_usbc *qmp) +{ + const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *pcs = qmp->pcs; + void __iomem *pcs_misc = qmp->pcs_misc; + + /* Disable i/o clamp_n on resume for normal mode */ + if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE]) + qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN); + + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], + ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); + + qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + /* Writing 1 followed by 0 clears the interrupt */ + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); +} + +static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev) +{ + struct qmp_usbc *qmp = dev_get_drvdata(dev); + + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); + + if (!qmp->phy->init_count) { + dev_vdbg(dev, "PHY not initialized, bailing out\n"); + return 0; + } + + qmp_usbc_enable_autonomous_mode(qmp); + + clk_disable_unprepare(qmp->pipe_clk); + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); + + return 0; +} + +static int __maybe_unused qmp_usbc_runtime_resume(struct device *dev) +{ + struct qmp_usbc *qmp = dev_get_drvdata(dev); + int ret = 0; + + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); + + if (!qmp->phy->init_count) { + dev_vdbg(dev, "PHY not initialized, bailing out\n"); + return 0; + } + + ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); + if (ret) + return ret; + + ret = clk_prepare_enable(qmp->pipe_clk); + if (ret) { + dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); + return ret; + } + + qmp_usbc_disable_autonomous_mode(qmp); + + return 0; +} + +static const struct dev_pm_ops qmp_usbc_pm_ops = { + SET_RUNTIME_PM_OPS(qmp_usbc_runtime_suspend, + qmp_usbc_runtime_resume, NULL) +}; + +static int qmp_usbc_vreg_init(struct qmp_usbc *qmp) +{ + const struct qmp_phy_cfg *cfg = qmp->cfg; + struct device *dev = qmp->dev; + int num = cfg->num_vregs; + int i; + + qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->vregs[i].supply = cfg->vreg_list[i]; + + return devm_regulator_bulk_get(dev, num, qmp->vregs); +} + +static int qmp_usbc_reset_init(struct qmp_usbc *qmp, + const char *const *reset_list, + int num_resets) +{ + struct device *dev = qmp->dev; + int i; + int ret; + + qmp->resets = devm_kcalloc(dev, num_resets, + sizeof(*qmp->resets), GFP_KERNEL); + if (!qmp->resets) + return -ENOMEM; + + for (i = 0; i < num_resets; i++) + qmp->resets[i].id = reset_list[i]; + + qmp->num_resets = num_resets; + + ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); + + return 0; +} + +static int qmp_usbc_clk_init(struct qmp_usbc *qmp) +{ + struct device *dev = qmp->dev; + int num = ARRAY_SIZE(qmp_usbc_phy_clk_l); + int i; + + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i = 0; i < num; i++) + qmp->clks[i].id = qmp_usbc_phy_clk_l[i]; + + qmp->num_clks = num; + + return devm_clk_bulk_get_optional(dev, num, qmp->clks); +} + +static void phy_clk_release_provider(void *res) +{ + of_clk_del_provider(res); +} + +/* + * Register a fixed rate pipe clock. + * + * The _pipe_clksrc generated by PHY goes to the GCC that gate + * controls it. The _pipe_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _pipe_clksrc here. The gcc driver takes care + * of assigning this _pipe_clksrc as parent to _pipe_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node *np) +{ + struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string(np, "clock-output-names", &init.name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); + return ret; + } + + init.ops = &clk_fixed_rate_ops; + + /* controllers using QMP phys use 125MHz pipe clock interface */ + fixed->fixed_rate = 125000000; + fixed->hw.init = &init; + + ret = devm_clk_hw_register(qmp->dev, &fixed->hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); +} + +static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_node *np) +{ + struct platform_device *pdev = to_platform_device(qmp->dev); + struct device *dev = qmp->dev; + int ret; + + qmp->serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qmp->serdes)) + return PTR_ERR(qmp->serdes); + + /* + * Get memory resources for the PHY: + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ + qmp->tx = devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qmp->tx)) + return PTR_ERR(qmp->tx); + + qmp->rx = devm_of_iomap(dev, np, 1, NULL); + if (IS_ERR(qmp->rx)) + return PTR_ERR(qmp->rx); + + qmp->pcs = devm_of_iomap(dev, np, 2, NULL); + if (IS_ERR(qmp->pcs)) + return PTR_ERR(qmp->pcs); + + qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); + if (IS_ERR(qmp->tx2)) + return PTR_ERR(qmp->tx2); + + qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qmp->rx2)) + return PTR_ERR(qmp->rx2); + + qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); + if (IS_ERR(qmp->pcs_misc)) { + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + qmp->pcs_misc = NULL; + } + + qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); + if (IS_ERR(qmp->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), + "failed to get pipe clock\n"); + } + + ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); + if (ret < 0) + return ret; + + qmp->num_clks = ret; + + ret = qmp_usbc_reset_init(qmp, usb3phy_legacy_reset_l, + ARRAY_SIZE(usb3phy_legacy_reset_l)); + if (ret) + return ret; + + return 0; +} + +static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) +{ + struct platform_device *pdev = to_platform_device(qmp->dev); + const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_usbc_offsets *offs = cfg->offsets; + struct device *dev = qmp->dev; + void __iomem *base; + int ret; + + if (!offs) + return -EINVAL; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + qmp->serdes = base + offs->serdes; + qmp->pcs = base + offs->pcs; + if (offs->pcs_misc) + qmp->pcs_misc = base + offs->pcs_misc; + qmp->tx = base + offs->tx; + qmp->rx = base + offs->rx; + + qmp->tx2 = base + offs->tx2; + qmp->rx2 = base + offs->rx2; + + ret = qmp_usbc_clk_init(qmp); + if (ret) + return ret; + + qmp->pipe_clk = devm_clk_get(dev, "pipe"); + if (IS_ERR(qmp->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), + "failed to get pipe clock\n"); + } + + ret = qmp_usbc_reset_init(qmp, usb3phy_reset_l, + ARRAY_SIZE(usb3phy_reset_l)); + if (ret) + return ret; + + return 0; +} + +static int qmp_usbc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *phy_provider; + struct device_node *np; + struct qmp_usbc *qmp; + int ret; + + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; + + qmp->dev = dev; + + qmp->cfg = of_device_get_match_data(dev); + if (!qmp->cfg) + return -EINVAL; + + ret = qmp_usbc_vreg_init(qmp); + if (ret) + return ret; + + /* Check for legacy binding with child node. */ + np = of_get_next_available_child(dev->of_node, NULL); + if (np) { + ret = qmp_usbc_parse_dt_legacy(qmp, np); + } else { + np = of_node_get(dev->of_node); + ret = qmp_usbc_parse_dt(qmp); + } + if (ret) + goto err_node_put; + + pm_runtime_set_active(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + goto err_node_put; + /* + * Prevent runtime pm from being ON by default. Users can enable + * it using power/control in sysfs. + */ + pm_runtime_forbid(dev); + + ret = phy_pipe_clk_register(qmp, np); + if (ret) + goto err_node_put; + + qmp->phy = devm_phy_create(dev, np, &qmp_usbc_phy_ops); + if (IS_ERR(qmp->phy)) { + ret = PTR_ERR(qmp->phy); + dev_err(dev, "failed to create PHY: %d\n", ret); + goto err_node_put; + } + + phy_set_drvdata(qmp->phy, qmp); + + of_node_put(np); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); + +err_node_put: + of_node_put(np); + return ret; +} + +static const struct of_device_id qmp_usbc_of_match_table[] = { + { + .compatible = "qcom,msm8998-qmp-usb3-phy", + .data = &msm8998_usb3phy_cfg, + }, { + .compatible = "qcom,qcm2290-qmp-usb3-phy", + .data = &qcm2290_usb3phy_cfg, + }, { + .compatible = "qcom,sm6115-qmp-usb3-phy", + .data = &qcm2290_usb3phy_cfg, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, qmp_usbc_of_match_table); + +static struct platform_driver qmp_usbc_driver = { + .probe = qmp_usbc_probe, + .driver = { + .name = "qcom-qmp-usbc-phy", + .pm = &qmp_usbc_pm_ops, + .of_match_table = qmp_usbc_of_match_table, + }, +}; + +module_platform_driver(qmp_usbc_driver); + +MODULE_AUTHOR("Vivek Gautam "); +MODULE_DESCRIPTION("Qualcomm QMP USB-C PHY driver"); +MODULE_LICENSE("GPL"); From patchwork Sat Jan 13 20:55:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13519066 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 328C718633 for ; Sat, 13 Jan 2024 20:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G4SdBUG3" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-50e759ece35so8500618e87.3 for ; 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a=openpgp-sha256; l=6460; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=8Dls26g2bshLZ1TTPkRX3m67fZ2HP79XYN3bxXtlmvY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjXoLHSPe5bguIF7nWwQTULJ0mFKEIWGZ9uH ssM6WbKDu+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41wAKCRCLPIo+Aiko 1TBcB/4tjZdrNuWkAPNFXEmUdlxAvzKC4QXcW7OQDxsDYCnfU/tlD3s/EYbBgouQ8iiJDa41VxG NNQO04oEQHhK4PhxapxxAZgPjKRhXzladm8pFBKdJ3Vi0lRF5LVi57z77maJz1WYuSw7lrEYFFA KksvNvJh7rWKveQ+WhOP0R6sBbkR5tuUrRTG7cowz1DKOl4mnwsxqFnsSAU2FSeTogtVMKII+j5 5Poege+FQcF9opKheZQ6wBbpVlj6kqIDLHb2puznXZw5PV9FSBuguytF5Bc/s0mh+T/7Lx0nfZi U+nTpYg9yveN40oaQSAq2faTGcrTEnmi1RWo/D+ZWlbLm9lq X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Now as all dual-lane PHYs have been migrated to a new driver, drop support for dual lanes configuration. If the PHY uses two lanes for USB, it is symthom that it should use either a combo USB+DP or a USB-C PHY driver. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 57 +-------------------------------- 1 file changed, 1 insertion(+), 56 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index c7698369d3dc..e62539ce99a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1237,15 +1237,10 @@ struct qmp_usb_offsets { u16 pcs_usb; u16 tx; u16 rx; - /* for PHYs with >= 2 lanes */ - u16 tx2; - u16 rx2; }; /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { - int lanes; - const struct qmp_usb_offsets *offsets; /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ @@ -1285,8 +1280,6 @@ struct qmp_usb { void __iomem *pcs_usb; void __iomem *tx; void __iomem *rx; - void __iomem *tx2; - void __iomem *rx2; struct clk *pipe_clk; struct clk_bulk_data *clks; @@ -1393,8 +1386,6 @@ static const struct qmp_usb_offsets qmp_usb_offsets_v7 = { }; static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v3, .serdes_tbl = ipq8074_usb3_serdes_tbl, @@ -1411,8 +1402,6 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { }; static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_ipq9574, .serdes_tbl = ipq9574_usb3_serdes_tbl, @@ -1429,8 +1418,6 @@ static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { }; static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v3, .serdes_tbl = msm8996_usb3_serdes_tbl, @@ -1447,8 +1434,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { }; static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v5, .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, @@ -1467,8 +1452,6 @@ static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v5, .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, @@ -1487,8 +1470,6 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v3, .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, @@ -1507,8 +1488,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v4, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -1530,8 +1509,6 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v4, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -1553,8 +1530,6 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v4, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -1576,8 +1551,6 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v5, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -1599,7 +1572,6 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = { - .lanes = 1, .offsets = &qmp_usb_offsets_v6, .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl, @@ -1621,8 +1593,6 @@ static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v5, .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, @@ -1644,8 +1614,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { }; static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = { - .lanes = 1, - .offsets = &qmp_usb_offsets_v7, .serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl, @@ -1780,11 +1748,6 @@ static int qmp_usb_power_on(struct phy *phy) qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->lanes >= 2) { - qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); - qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); - } - qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); if (pcs_usb) @@ -2131,7 +2094,6 @@ static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) /* * Get memory resources for the PHY: * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. - * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 * For single lane PHYs: pcs_misc (optional) -> 3. */ qmp->tx = devm_of_iomap(dev, np, 0, NULL); @@ -2149,19 +2111,7 @@ static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) if (cfg->pcs_usb_offset) qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; - if (cfg->lanes >= 2) { - qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); - if (IS_ERR(qmp->tx2)) - return PTR_ERR(qmp->tx2); - - qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); - if (IS_ERR(qmp->rx2)) - return PTR_ERR(qmp->rx2); - - qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); - } else { - qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); - } + qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); if (IS_ERR(qmp->pcs_misc)) { dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); @@ -2213,11 +2163,6 @@ static int qmp_usb_parse_dt(struct qmp_usb *qmp) qmp->tx = base + offs->tx; qmp->rx = base + offs->rx; - if (cfg->lanes >= 2) { - qmp->tx2 = base + offs->tx2; - qmp->rx2 = base + offs->rx2; - } - ret = qmp_usb_clk_init(qmp); if (ret) return ret; From patchwork Sat Jan 13 20:55:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13519067 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D88F418645 for ; Sat, 13 Jan 2024 20:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="raUpzt/Q" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-50edf4f478eso4380678e87.3 for ; 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a=openpgp-sha256; l=5165; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=AyyWXpZHbJcJG3JSjU+Vci0NPOyVsEJSPF3MW67UenM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjX7Ul2DQgqlUqachDmhog01C0SodaYjP0t9 arg9gqjLj+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL41wAKCRCLPIo+Aiko 1fQzB/9dVLzfCNGXvel2vaFvwwCyM21MknDLKlm3leyef7xE88Jdl9+nbbt3kj9MfA9d9Xn6wyA yBfU6HRvwfp1OVgmyThFk2EDROuv+X0PvZC4X3G8e7xr65Fz/Paxmqnces5ZnBKuma6GkVPqadP 35jX0Aum4tkSU6bm25JxH1A+7k0Kt6wVWMP4vLmWJGKnjZ6LKsc5CyHtcBGgG4vscnUJ5NR+RMp xz0bUqc0+mzyImP+VUKj6UGoJfFzEVFy7zT+8pmoJENX8dgV+c/FzNUSG2T/7mJvt4CKLz1tmiS IiFAKIbS2O1ZTCNavaofNoyC/gzi8OVFAmtnT1kFgbDbEj4a X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The USB-C PHYs on the msm8998, QCM2290 and SM6115 platforms use special register to control which lanes of the Type-C port are used for the SuperSpeed USB connection. Mimic the qmp-combo driver and handle this register. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 97 +++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c index 52f1b3f7b81e..214cf4203de4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include "phy-qcom-qmp.h" #include "phy-qcom-qmp-pcs-misc-v3.h" @@ -374,11 +376,17 @@ struct qmp_usbc { struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; + struct mutex phy_mutex; + enum phy_mode mode; + unsigned int usb_init_count; struct phy *phy; struct clk_fixed_rate pipe_clk_fixed; + + struct typec_switch_dev *sw; + enum typec_orientation orientation; }; static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -497,6 +505,7 @@ static int qmp_usbc_init(struct phy *phy) struct qmp_usbc *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; void __iomem *pcs = qmp->pcs; + u32 val = 0; int ret; ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); @@ -523,6 +532,14 @@ static int qmp_usbc_init(struct phy *phy) qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); +#define SW_PORTSELECT_VAL BIT(0) +#define SW_PORTSELECT_MUX BIT(1) + /* Use software based port select and switch on typec orientation */ + val = SW_PORTSELECT_MUX; + if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) + val |= SW_PORTSELECT_VAL; + writel(val, qmp->pcs_misc); + return 0; err_assert_reset: @@ -620,23 +637,34 @@ static int qmp_usbc_power_off(struct phy *phy) static int qmp_usbc_enable(struct phy *phy) { + struct qmp_usbc *qmp = phy_get_drvdata(phy); int ret; + mutex_lock(&qmp->phy_mutex); + ret = qmp_usbc_init(phy); if (ret) - return ret; + goto out_unlock; ret = qmp_usbc_power_on(phy); - if (ret) + if (ret) { qmp_usbc_exit(phy); + goto out_unlock; + } + + qmp->usb_init_count++; +out_unlock: + mutex_unlock(&qmp->phy_mutex); return ret; } static int qmp_usbc_disable(struct phy *phy) { + struct qmp_usbc *qmp = phy_get_drvdata(phy); int ret; + qmp->usb_init_count--; ret = qmp_usbc_power_off(phy); if (ret) return ret; @@ -874,6 +902,61 @@ static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node *np) return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } +#if IS_ENABLED(CONFIG_TYPEC) +static int qmp_usbc_typec_switch_set(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct qmp_usbc *qmp = typec_switch_get_drvdata(sw); + + if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) + return 0; + + mutex_lock(&qmp->phy_mutex); + qmp->orientation = orientation; + + if (qmp->usb_init_count) { + qmp_usbc_power_off(qmp->phy); + qmp_usbc_exit(qmp->phy); + + qmp_usbc_init(qmp->phy); + qmp_usbc_power_on(qmp->phy); + } + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static void qmp_usbc_typec_unregister(void *data) +{ + struct qmp_usbc *qmp = data; + + typec_switch_unregister(qmp->sw); +} + +static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp) +{ + struct typec_switch_desc sw_desc = {}; + struct device *dev = qmp->dev; + + sw_desc.drvdata = qmp; + sw_desc.fwnode = dev->fwnode; + sw_desc.set = qmp_usbc_typec_switch_set; + qmp->sw = typec_switch_register(dev, &sw_desc); + if (IS_ERR(qmp->sw)) { + dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); + return PTR_ERR(qmp->sw); + } + + return devm_add_action_or_reset(dev, qmp_usbc_typec_unregister, qmp); +} +#else +static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp) +{ + return 0; +} +#endif + static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_node *np) { struct platform_device *pdev = to_platform_device(qmp->dev); @@ -994,16 +1077,24 @@ static int qmp_usbc_probe(struct platform_device *pdev) qmp->dev = dev; + qmp->orientation = TYPEC_ORIENTATION_NORMAL; + qmp->cfg = of_device_get_match_data(dev); if (!qmp->cfg) return -EINVAL; + mutex_init(&qmp->phy_mutex); + ret = qmp_usbc_vreg_init(qmp); if (ret) return ret; + ret = qmp_usbc_typec_switch_register(qmp); + if (ret) + return ret; + /* Check for legacy binding with child node. */ - np = of_get_next_available_child(dev->of_node, NULL); + np = of_get_child_by_name(dev->of_node, "phy"); if (np) { ret = qmp_usbc_parse_dt_legacy(qmp, np); } else { From patchwork Sat Jan 13 20:55:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13519069 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4BD218658 for ; Sat, 13 Jan 2024 20:56:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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Sat, 13 Jan 2024 12:56:03 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:56 +0200 Subject: [PATCH v2 13/15] arm64: dts: qcom: pmi632: define USB-C related blocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-13-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1709; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; 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Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmi632.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index 4eb79e0ce40a..d6832f0b7b80 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -45,6 +45,36 @@ pmic@2 { #address-cells = <1>; #size-cells = <0>; + pmi632_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pmi632-vbus-reg", "qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pmi632_typec: typec@1500 { + compatible = "qcom,pmi632-typec"; + reg = <0x1500>; + interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x07 IRQ_TYPE_EDGE_RISING>; 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Sat, 13 Jan 2024 12:56:04 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:57 +0200 Subject: [PATCH v2 14/15] arm64: dts: qcom: sm6115: drop pipe clock selection Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-14-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org, Vladimir Zapolskiy X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1548; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=PByUN+WAixFhUZidNT3kE48yA7k+ACS3q0ToQ5RNUeQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjYHS9liGQDgqchYSNifXDFPFLI53DOsb+/p HdUvWrwW7WJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL42AAKCRCLPIo+Aiko 1XcOB/0UurL9UkPJGLs6cbe4VVnAcRJgSKAPzl6lDHeo8QV1EVryu71ynQ/1z+Sc1Hiqp1clqqz hCaPXjqKBsArlbZu1Att0QTPAIK5badK9qegvFaR9iCtsZoXRGOSt3qDMz5wBOp8PhZecAAGyAF 0D7oNwyHIbUTbf+8nD+HvHcHFfiB4eOx2QJF+RqQL/aOpM4yRYXstYRWysKmAoRBPmXAMgLpVzd QESZq5fXyMmp+BxOeuudaSGuSVNmuHetTH6UivpWZrNAlUuv3p1JGTtcBh1MEHaUU19CFjcTkOI 8LQ4eSDFTDAVJl7QhTxJ/8CIwIsmJZa4FLTmLgYXD8dNHAjU X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A From: Vladimir Zapolskiy Stop selecting UTMI clock as the USB3 PIPE clock. This setting is incompatible with the USB host working in USB3 (SuperSpeed) mode. While we are at it, also drop the default setting for the port speed. Fixes: 9dd5f6dba729 ("arm64: dts: qcom: sm6115: Add USB SS qmp phy node") Signed-off-by: Vladimir Zapolskiy [DB: fixed commit message, dropped dr_mode setting] Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 4 ---- arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 - 2 files changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 7c19f874fa71..52f31f3166c2 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -607,10 +607,6 @@ &usb { status = "okay"; }; -&usb_dwc3 { - maximum-speed = "super-speed"; -}; - &usb_hsphy { vdd-supply = <&vreg_l4a_0p9>; vdda-pll-supply = <&vreg_l12a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 160e098f1075..76c429e8ebab 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1600,7 +1600,6 @@ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, interconnect-names = "usb-ddr", "apps-usb"; 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Sat, 13 Jan 2024 12:56:05 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id p14-20020a056512328e00b0050e9355d7eesm919802lfe.103.2024.01.13.12.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 12:56:04 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 13 Jan 2024 22:55:58 +0200 Subject: [PATCH v2 15/15] arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240113-pmi632-typec-v2-15-182d9aa0a5b3@linaro.org> References: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> In-Reply-To: <20240113-pmi632-typec-v2-0-182d9aa0a5b3@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Bryan O'Donoghue , Greg Kroah-Hartman , Vinod Koul , Kishon Vijay Abraham I , Guenter Roeck , Heikki Krogerus , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3380; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=XAUYT0JI8EGw2t2EwxsMog3tphSISbkThFhkLyZxRdY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlovjYIg71eDGgUhWPH+SjPHm4oIIik1Y2R/pIb 75l3i29BimJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaL42AAKCRCLPIo+Aiko 1WqdB/9CYDUoI9k27gvPkw54OvJgUI9rmwd+I3OFtDqKSGk7n6Z0slhDzwM92kwibCzirbZS2Qs PoRsEZAKV17iiz5fDVaPou+GBqVywPM81njziMdDRXt0lQJG3K3HXEKJpNOtiTFVeTzDtr3ggE/ lSTQwGkRddo14aBxz0l5ud1+f/g8VHtY3+FTwRUcXvDkfaxeTh11D+DnPlpr9UrSlnel3kh8HXH lUagL5gLd4TOe6C2f+MyCF/jHTbrzcTWBhLlGL2wDSOCL5R6ahy9wvzeeMB3tFaoZumbCNjXpul BO9jy4WDFuoyPoQTEYTf//6ZuOKXychZTbkJSxqolEKHEX1r X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Plug in USB-C related bits and pieces to enable USB role switching and USB-C orientation handling for the Qualcomm RB2 board. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 50 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sm6115.dtsi | 43 +++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 52f31f3166c2..696d6d43c56b 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -6,8 +6,10 @@ /dts-v1/; #include +#include #include "sm4250.dtsi" #include "pm6125.dtsi" +#include "pmi632.dtsi" / { model = "Qualcomm Technologies, Inc. QRB4210 RB2"; @@ -256,6 +258,46 @@ kypd_vol_up_n: kypd-vol-up-n-state { }; }; +&pmi632_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pmi632_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + pmi632_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; +}; + +&pmi632_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; @@ -607,6 +649,10 @@ &usb { status = "okay"; }; +&usb_dwc3_hs { + remote-endpoint = <&pmi632_hs_in>; +}; + &usb_hsphy { vdd-supply = <&vreg_l4a_0p9>; vdda-pll-supply = <&vreg_l12a_1p8>; @@ -622,6 +668,10 @@ &usb_qmpphy { status = "okay"; }; +&usb_qmpphy_out { + remote-endpoint = <&pmi632_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>; vdd-1.8-xo-supply = <&vreg_l16a_1p3>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 76c429e8ebab..01dff6641280 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -878,8 +878,29 @@ usb_qmpphy: phy@1615000 { clock-output-names = "usb3_phy_pipe_clk_src"; #phy-cells = <0>; + orientation-switch; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; }; system_noc: interconnect@1880000 { @@ -1614,6 +1635,28 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; + }; + }; + }; }; };