From patchwork Thu Jan 18 22:02:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13523239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3394C47422 for ; Thu, 18 Jan 2024 22:03:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BF4610E910; Thu, 18 Jan 2024 22:03:36 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id EC11110E910 for ; Thu, 18 Jan 2024 22:03:34 +0000 (UTC) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id B75CC87835; Thu, 18 Jan 2024 23:02:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1705615377; bh=G1m6PHzvt/1r5P+ktO+irDL34MiP2jnxjjZenTJ526I=; h=From:To:Cc:Subject:Date:From; b=YhkBRJJe8iWwb+vxB2WCLZarDUc6BkDWOUJSmlBLT7nZjds3sk/bouGH4p5bS50GN ShQIK2xZQo2WIb8QiFFNa+MVLW7Lf92JK9RqF9ubZM0HAT3cklpHutkNhJBFgtmmyR zHBMa4RlIabDZIlp3YeGWmKPhKO1CzT7AkrHJdqgJiiaQCv6iLvDdoALHY2R+FGZQl DxpOV3x+E+sTmqwAAFyckd8lCpoZ/OYDjN4T8gfNaKX1poyRsjX/wWODhZ+hiDvmMJ 7H63hB6hpWvs9PAqW0yTrkXbUu7AlOQJgkRod4PGxjyjoJcVKfk1lxTaRcf/90lWUy 8m8SJn1mgmCGw== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH] drm/bridge: tc358767: Limit the Pixel PLL input range Date: Thu, 18 Jan 2024 23:02:31 +0100 Message-ID: <20240118220243.203655-1-marex@denx.de> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Neil Armstrong , Robert Foss , Andrzej Hajda , Jonas Karlman , Jernej Skrabec , Laurent Pinchart , Daniel Vetter , David Airlie Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" According to new configuration spreadsheet from Toshiba for TC9595, the Pixel PLL input clock have to be in range 6..40 MHz. The sheet calculates those PLL input clock as reference clock divided by both pre-dividers. Add the extra limit. Signed-off-by: Marek Vasut Reviewed-by: Lucas Stach --- Cc: Andrzej Hajda Cc: Daniel Vetter Cc: David Airlie Cc: Jernej Skrabec Cc: Jonas Karlman Cc: Laurent Pinchart Cc: Lucas Stach Cc: Neil Armstrong Cc: Robert Foss Cc: dri-devel@lists.freedesktop.org --- drivers/gpu/drm/bridge/tc358767.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 615cc8f950d7b..0c29a8f81cc9e 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -546,9 +546,14 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) continue; for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { for (div = 1; div <= 16; div++) { - u32 clk; + u32 clk, iclk; u64 tmp; + /* PCLK PLL input unit clock ... 6..40 MHz */ + iclk = refclk / (div * ext_div[i_pre]); + if (iclk < 6000000 || iclk > 40000000) + continue; + tmp = pixelclock * ext_div[i_pre] * ext_div[i_post] * div; do_div(tmp, refclk);