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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm3341868wrv.20.2024.01.19.03.11.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:11:46 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: andi.shyti@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus , Rob Herring Subject: [PATCH v4 1/8] dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit Date: Fri, 19 Jan 2024 11:11:25 +0000 Message-ID: <20240119111132.1290455-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119111132.1290455-1-tudor.ambarus@linaro.org> References: <20240119111132.1290455-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add dt-schema documentation for the Connectivity Peripheral 0 (PERIC0) clock management unit. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Rob Herring Signed-off-by: Tudor Ambarus --- .../bindings/clock/google,gs101-clock.yaml | 25 +++++- include/dt-bindings/clock/google,gs101.h | 81 +++++++++++++++++++ 2 files changed, 104 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index ca7fdada3ff2..03698cdecf7a 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -30,14 +30,15 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-peric0 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 "#clock-cells": const: 1 @@ -88,6 +89,26 @@ allOf: - const: bus - const: sss + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Connectivity Peripheral 0 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + additionalProperties: false examples: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 21adec22387c..64e6bdc6359c 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -389,4 +389,85 @@ #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_I3C_USER 2 +#define CLK_MOUT_PERIC0_USI0_UART_USER 3 +#define CLK_MOUT_PERIC0_USI14_USI_USER 4 +#define CLK_MOUT_PERIC0_USI1_USI_USER 5 +#define CLK_MOUT_PERIC0_USI2_USI_USER 6 +#define CLK_MOUT_PERIC0_USI3_USI_USER 7 +#define CLK_MOUT_PERIC0_USI4_USI_USER 8 +#define CLK_MOUT_PERIC0_USI5_USI_USER 9 +#define CLK_MOUT_PERIC0_USI6_USI_USER 10 +#define CLK_MOUT_PERIC0_USI7_USI_USER 11 +#define CLK_MOUT_PERIC0_USI8_USI_USER 12 +#define CLK_DOUT_PERIC0_I3C 13 +#define CLK_DOUT_PERIC0_USI0_UART 14 +#define CLK_DOUT_PERIC0_USI14_USI 15 +#define CLK_DOUT_PERIC0_USI1_USI 16 +#define CLK_DOUT_PERIC0_USI2_USI 17 +#define CLK_DOUT_PERIC0_USI3_USI 18 +#define CLK_DOUT_PERIC0_USI4_USI 19 +#define CLK_DOUT_PERIC0_USI5_USI 20 +#define CLK_DOUT_PERIC0_USI6_USI 21 +#define CLK_DOUT_PERIC0_USI7_USI 22 +#define CLK_DOUT_PERIC0_USI8_USI 23 +#define CLK_GOUT_PERIC0_IP 24 +#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25 +#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26 +#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27 +#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28 +#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29 +#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66 +#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67 +#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78 +#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From patchwork Fri Jan 19 11:11:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13523654 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E9424CB26 for ; Fri, 19 Jan 2024 11:11:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm3341868wrv.20.2024.01.19.03.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:11:48 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: andi.shyti@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus , Wolfram Sang , Rob Herring Subject: [PATCH v4 2/8] dt-bindings: i2c: exynos5: add google,gs101-hsi2c compatible Date: Fri, 19 Jan 2024 11:11:26 +0000 Message-ID: <20240119111132.1290455-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119111132.1290455-1-tudor.ambarus@linaro.org> References: <20240119111132.1290455-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add google,gs101-hsi2c dedicated compatible for representing I2C of Google GS101 SoC. Acked-by: Wolfram Sang Acked-by: Rob Herring Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index df9c57bca2a8..cc8bba5537b9 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -33,6 +33,7 @@ properties: - const: samsung,exynos7-hsi2c - items: - enum: + - google,gs101-hsi2c - samsung,exynos850-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 From patchwork Fri Jan 19 11:11:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13523655 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AB224CB5A for ; Fri, 19 Jan 2024 11:11:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705662714; cv=none; b=b962GtW/CuKj0w6KWJdD7VFLTMCGPdIVSwsKueNDgB//YZWd+kA7nJOjZTuou2tGs5Ol4SGqTRjdhwqisJS9VEdLe3xzlirykRQnat0bzcaHyz8qa0f0seW8uq+Ig9k3CE7RbYW71diK9OaTFUIFnwdQP3y+0JCrC9NpJX/v2co= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705662714; c=relaxed/simple; bh=ui042f0WmAu1CcYDhAaMFfFskM7qu/aiOq1BgLVFAJU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ddu5usgEGItR0WVMkimobCnzdltEMSFsfWvE6pvHGOaVbGm9GRQZgp2rn/41d3VaRxa1edo0YShzuMbAyTYUb1RYI/eLMqDuaT+bVu9QJ8mNnSKeAwsGtafi2khK4amQbSmzgdDeAkpuH0Y4TvJCfIvzcOgJ24PlBhYi/KGGeLQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=HywNT2xG; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HywNT2xG" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40ea045f29eso1921715e9.1 for ; Fri, 19 Jan 2024 03:11:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705662710; x=1706267510; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FNwUybKWSt1VQzy7DcQTwcOaWKRFY9PuVnwe/OfWzP0=; b=HywNT2xG3IYxp/sIkoZPpxAU+2tfMfn0/dyYOxjvvvQtTzHcul/keLhRvnQKJ6RKw8 13Z45FQeOrNf7Tkq0+SY+D0ZMPNUF//WMVXwPDXOSwEtrz+s16Ev1arskbfZCC0uPagY x9gjT0FAu0uieDmhWKN+bhoc14iK6AZUPSqdgKcf1Bz6QuOgv8VllWeYeV7HRh8WJWH1 e30btgH4n2bxQWFeGssXE1j1nR2F2MvwtClp2A44KDKKxss5zv14iQlL+tXUgLL4wg5K o5iWiuQ4KyQza3yS7YfF0j0v15KgWcnPpDS5nRi5/y6LZesttyok9e6xqVOcT2wka2Jm ENuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705662710; x=1706267510; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FNwUybKWSt1VQzy7DcQTwcOaWKRFY9PuVnwe/OfWzP0=; b=M0lFScrQ18jHw9QoBOPHmsLlaaOW/Y+DaVP6guyEooNk7tSehdGXC/lGCHYkbRG5q+ QRLejjDqZEpXOc0Oi8VV4YfVAq2SycA2k4+HFwnXs8UZJr9Qk/bdI5b7uTxReEb9PNXC OSoJYuZzpLV3u5O8l1uvDa61ifI5oaGhIFw8yS+xiiOakpPwgW5EvHwiQ3Hva9zLxBaY 7xxGbasqJbVYF7qOyuDzC2XFEp3TQBpBiVANS1HSCksnOzCikMrhph7wsWuK76tpbrbq HF2EnoGduEMHF91vELCtXYtNvUC1PY1nnKMRm4wF0zoM3VkwPEc1s2c4zothCgEkdqJ3 Jbyw== X-Gm-Message-State: AOJu0Yxyhiu3K/VKKI4g1A0D5be1aejUzuM+psXQM3nwyfQ3d6Ph3Do0 pjuWncqqk2/rAUVwAn/2q6VcbSOPhzEycqyLTzy3E3/HdmQSWB8FPza4Ib6HqyU= X-Google-Smtp-Source: AGHT+IFeNXmllm8uNGhke9PUPoX45dVduzB5R1Xs/zVFCEZ8tzeqmH4C8EbUtuqINlmGuPHbJ0pOPQ== X-Received: by 2002:a05:600c:5124:b0:40e:9706:9a44 with SMTP id o36-20020a05600c512400b0040e97069a44mr694442wms.44.1705662710224; Fri, 19 Jan 2024 03:11:50 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm3341868wrv.20.2024.01.19.03.11.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:11:49 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: andi.shyti@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v4 3/8] clk: samsung: gs101: add support for cmu_peric0 Date: Fri, 19 Jan 2024 11:11:27 +0000 Message-ID: <20240119111132.1290455-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119111132.1290455-1-tudor.ambarus@linaro.org> References: <20240119111132.1290455-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CMU_PERIC0 is the clock management unit used for the peric0 block which is used for USI and I3C. Add support for all cmu_peric0 clocks but CLK_GOUT_PERIC0_IP (not enough info in the datasheet). Few clocks are marked as critical because when either of them is disabled, the system hangs even if their clock parents are enabled. Reviewed-by: Peter Griffin Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- drivers/clk/samsung/clk-gs101.c | 583 ++++++++++++++++++++++++++++++++ 1 file changed, 583 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 782993951fff..d9ea559ca36e 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -20,6 +20,7 @@ #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ @@ -2478,6 +2479,585 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = { .clk_name = "bus", }; +/* ---- CMU_PERIC0 ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10800000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 +#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 +#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c +#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c +#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 +#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 +#define QCH_CON_GPC_PERIC0_QCH 0x3028 +#define QCH_CON_GPIO_PERIC0_QCH 0x302c +#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 +#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 +#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 +#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c +#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 +#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 +#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 +#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c +#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 +#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 +#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 +#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c +#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 +#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 +#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 +#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c +#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 +#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 +#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 +#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c +#define QCH_CON_SYSREG_PERIC0_QCH 0x3080 +#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 + +static const unsigned long peric0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PERIC0_CMU_PERIC0_CONTROLLER_OPTION, + CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, + CLK_CON_BUF_CLKBUF_PERIC0_IP, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + DMYQCH_CON_PERIC0_TOP0_QCH_S1, + DMYQCH_CON_PERIC0_TOP0_QCH_S2, + DMYQCH_CON_PERIC0_TOP0_QCH_S3, + DMYQCH_CON_PERIC0_TOP0_QCH_S4, + DMYQCH_CON_PERIC0_TOP0_QCH_S5, + DMYQCH_CON_PERIC0_TOP0_QCH_S6, + DMYQCH_CON_PERIC0_TOP0_QCH_S7, + DMYQCH_CON_PERIC0_TOP0_QCH_S8, + PCH_CON_LHM_AXI_P_PERIC0_PCH, + QCH_CON_D_TZPC_PERIC0_QCH, + QCH_CON_GPC_PERIC0_QCH, + QCH_CON_GPIO_PERIC0_QCH, + QCH_CON_LHM_AXI_P_PERIC0_QCH, + QCH_CON_PERIC0_CMU_PERIC0_QCH, + QCH_CON_PERIC0_TOP0_QCH_I3C1, + QCH_CON_PERIC0_TOP0_QCH_I3C2, + QCH_CON_PERIC0_TOP0_QCH_I3C3, + QCH_CON_PERIC0_TOP0_QCH_I3C4, + QCH_CON_PERIC0_TOP0_QCH_I3C5, + QCH_CON_PERIC0_TOP0_QCH_I3C6, + QCH_CON_PERIC0_TOP0_QCH_I3C7, + QCH_CON_PERIC0_TOP0_QCH_I3C8, + QCH_CON_PERIC0_TOP0_QCH_USI1_USI, + QCH_CON_PERIC0_TOP0_QCH_USI2_USI, + QCH_CON_PERIC0_TOP0_QCH_USI3_USI, + QCH_CON_PERIC0_TOP0_QCH_USI4_USI, + QCH_CON_PERIC0_TOP0_QCH_USI5_USI, + QCH_CON_PERIC0_TOP0_QCH_USI6_USI, + QCH_CON_PERIC0_TOP0_QCH_USI7_USI, + QCH_CON_PERIC0_TOP0_QCH_USI8_USI, + QCH_CON_PERIC0_TOP1_QCH_USI0_UART, + QCH_CON_PERIC0_TOP1_QCH_USI14_UART, + QCH_CON_SYSREG_PERIC0_QCH, + QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, +}; + +/* List of parent clocks for Muxes in CMU_PERIC0 */ +PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; +PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", + mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI0_UART_USER, + "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI14_USI_USER, + "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI1_USI_USER, + "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI2_USI_USER, + "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI3_USI_USER, + "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI4_USI_USER, + "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI5_USI_USER, + "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI6_USI_USER, + "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI7_USI_USER, + "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI8_USI_USER, + "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4), + DIV(CLK_DOUT_PERIC0_USI0_UART, + "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4), + DIV(CLK_DOUT_PERIC0_USI14_USI, + "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI1_USI, + "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI2_USI, + "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI3_USI, + "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI4_USI, + "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI5_USI, + "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI6_USI, + "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI7_USI, + "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI8_USI, + "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4), +}; + +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, + "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, + "gout_peric0_clk_peric0_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, + "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, + "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, + "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, + "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, + "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, + "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, + "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, + "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, + "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, + "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, + "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, + "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, + "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, + "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, + "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, + "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, + "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, + "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, + "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, + "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, + "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, + "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, + "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, + "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, + "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, + "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, + "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, + "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, + "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, + "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, + "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, + "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, + "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, + "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, + "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, + "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, + "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, + "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, + "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, + "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, + "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, + "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, + "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, + "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, + "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, + "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, + "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, + "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, + "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, + "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, + "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, + "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, + "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst = { + .mux_clks = peric0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), + .div_clks = peric0_div_clks, + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), + .gate_clks = peric0_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC0, + .clk_regs = peric0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), + .clk_name = "bus", +}; + /* ---- platform_driver ----------------------------------------------------- */ static int __init gs101_cmu_probe(struct platform_device *pdev) @@ -2498,6 +3078,9 @@ static const struct of_device_id gs101_cmu_of_match[] = { }, { .compatible = "google,gs101-cmu-misc", .data = &misc_cmu_info, + }, { + .compatible = "google,gs101-cmu-peric0", + .data = &peric0_cmu_info, }, { }, }; From patchwork Fri Jan 19 11:11:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13523656 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AF8A4CE0E for ; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm3341868wrv.20.2024.01.19.03.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:11:50 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: andi.shyti@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v4 4/8] arm64: dts: exynos: gs101: remove reg-io-width from serial Date: Fri, 19 Jan 2024 11:11:28 +0000 Message-ID: <20240119111132.1290455-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119111132.1290455-1-tudor.ambarus@linaro.org> References: <20240119111132.1290455-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove the reg-io-width property in order to comply with the bindings. The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Reviewed-by: Peter Griffin Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index d838e3a7af6e..4e5f4c748906 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -366,7 +366,6 @@ usi_uart: usi@10a000c0 { serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - reg-io-width = <4>; interrupts = ; clocks = <&dummy_clk 0>, <&dummy_clk 0>; From patchwork Fri Jan 19 11:11:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13523657 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D08CE4D117 for ; Fri, 19 Jan 2024 11:11:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705662716; cv=none; b=eK9TvfbZ2BajhHRFeXAEl1gZTAzQ6KGHL6fTP4b6U9iFY4h7I2u3bm34q473mxBQGE8chVVnBeAtbkrP91rYewgi1ZgCEY/x4ell43JqIPH5Np1ew+MQqZUn1zrTWIz6W2JvQgoStImMzvq+ZdTd9Ulhcln76OYoWsJbBbZPM/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705662716; c=relaxed/simple; bh=Kv/qgN5wdHjnG8VF1fPyW8eUb5V4sWqohtBHYU2gKCI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HD8ZtZFjGlHSDVWhluCQI/jj5FqGFp4q0+ixOPVwhp7Lu31fp937oS7s2rM5FXqcGDdN6o65eFulrsL4JO/OlNLV5SKuzywXrLEqyi+L+5RVLXzcRTSp0WZClf/OvxF0aiav52jX0K+F3EcPGKMyJSY9J6vnmkyMFogzYh5aK2E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=NxBqbEPN; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NxBqbEPN" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-336746c7b6dso506148f8f.0 for ; Fri, 19 Jan 2024 03:11:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705662713; x=1706267513; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G1HT8eUHAUE1J0rcUA9FGL6+fb4DKBSfdgo51wbL26s=; b=NxBqbEPNsSra+DDi35B+rjysLGKL2Nc3YF6bCAQvDGokze3KftWC8HyktsAZmOik4A 4Ck4IAkNgkaFRYjj+xUNGz/2uPc+mb0XajqRPKa0z6Wt6c8OoH7jaNDbV21kL6WMYUrp sC0DE+O9tLnwLIl3nXt/CoCFFVEIAxpw5adklD8kQIHSn/BkI5EOU489cjINxzENk59P B4efuCQgvZ20VuvaRNvUv0m3uXT5ndghpMgpDe9Iouap5KP0Ue26EBhj2f6zD1VCBIgO InopM1SuAgIUI8Cu5fBOeOXAoB34ceOLrDLYFP9NXYb81vHG1boWhjBWHO8LltxdvPUW +7/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705662713; x=1706267513; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G1HT8eUHAUE1J0rcUA9FGL6+fb4DKBSfdgo51wbL26s=; b=nOYkFyCrxjwXy5gv1lvv9zXJMErPnffxEbMPCYQkFs3cMwjk4gxI34QgToPFpBUtFa o3VEJqX5jV0lV52hS+GKiTTIFh1rxgl/Iw1ZnkmMqSQCru6sZb40n8XvjO38xnKBjUzz 14kGEGIcLoDRw9E9lAf3CaFsuJnnhoqCgauvwDv2X6o9Dcy+MHtDDUKCpzHNfcrkknDg XNAARU9unOE5GRoRaRc3S95MvxTgExnI52NBBwt1DdIpUN3NrwA8Vom6QO+GkWIhVd3s 6sEHhMsbbcKiZ2NjrE3Ga58tdMQmMiukV/p+xzqsHIW4FQ+iR/uHxbswUmzB/irZCvoi gH6Q== X-Gm-Message-State: AOJu0YwU3VSGnOjr/jlSGtDjbplzO6CmwvSlskQ6Jw8Onoh6UI3BGHbc LzpPDWuBIPPxiqU59WBsyyWlkjTBJqHBKFVFkLyBIGoQC6wivf4vf+f+O5pN8AQ= X-Google-Smtp-Source: AGHT+IHaBc6eJWWwfsyXPpEBpMT+qK4nQa/Ck3+GDDBnNhmmA3Miv7rIcU2p6oIK13S23wdfYvCWEA== X-Received: by 2002:a5d:456c:0:b0:337:be12:3261 with SMTP id a12-20020a5d456c000000b00337be123261mr1308033wrc.68.1705662713261; Fri, 19 Jan 2024 03:11:53 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm3341868wrv.20.2024.01.19.03.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:11:52 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: andi.shyti@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v4 5/8] arm64: dts: exynos: gs101: enable cmu-peric0 clock controller Date: Fri, 19 Jan 2024 11:11:29 +0000 Message-ID: <20240119111132.1290455-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119111132.1290455-1-tudor.ambarus@linaro.org> References: <20240119111132.1290455-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable the cmu-peric0 clock controller. It feeds USI and I3c. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 4e5f4c748906..2d1344a202a9 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -339,6 +339,16 @@ ppi_cluster2: interrupt-partition-2 { }; }; + cmu_peric0: clock-controller@10800000 { + compatible = "google,gs101-cmu-peric0"; + reg = <0x10800000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric0: syscon@10820000 { compatible = "google,gs101-peric0-sysreg", "syscon"; reg = <0x10820000 0x10000>; From patchwork Fri Jan 19 11:11:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13523658 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D35B4D589 for ; Fri, 19 Jan 2024 11:11:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705662718; cv=none; b=F/LuBAPgWO4iebQnnMseuFFjv1X3GyRCX8lR2/vCfMVqlwgw+bY1E8mF6TLoX6dT0O25IytO/LTxc3RQdEs0V+OG8Op3KBPKHeQ0Rn8zsMWOiJpGmIsyqfFQdqQuNPLKaXjgbKHj3po7tsd0rZV9htvIT0xmCBjj3Q17qkMtiRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705662718; c=relaxed/simple; bh=+Z9aKQjWJRg1t8puc2H7wIKhN59qiSCcrvi1W3ZMQJ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C0KK0dMtbSBLZCOAcSbusXdmabfDZ54z97q7oHgiTcKjmlq6rRU6OnJlNsg4CftRKff+11Ht3bXLJxrd75P9zaIQib2mUaQssvNkcoTtKS8mzWLq9uDf0CAwRkEgQEPSAhp3LMrP5eLEsWHpPuE3sIyA9Owv2oniBlHyEHACQGQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Bsax9cj5; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Bsax9cj5" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-336c8ab0b20so568400f8f.1 for ; Fri, 19 Jan 2024 03:11:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705662714; x=1706267514; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tDx9IJeu4q4vg7sxnjP3+o90/kYREKpXEiMwOte9XSc=; b=Bsax9cj537jCBdindCqwlsLm7YKFMR4zjAMKweP53fOK10AajxYubcGUpIKgfakUsW 3oE2LMTL8W0w96ZraPq9fw55ZIJFnK99LhUh1yX61yhbNXp/4b70E6rcFIESSLbG2Ezb +cz6U2goQ7pP7yC/FpT8/Lij826zogV+RxNX4G7I8XEZgXvFxzvdXnJmrqJAJPUIe1pp hqloRsJARVokBXzKv4FEfcwmBfvnFKb2gQJ9hJuYeM24oLN2Ui1ItZfXnJXrwQZHtJqQ sYOStcVQ6+tBVqF+RegH+HcgpqyMtug49BcXSfJPFC3TgGvpIBGdNUIYu/Icgg/UHE0J SNZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705662714; x=1706267514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tDx9IJeu4q4vg7sxnjP3+o90/kYREKpXEiMwOte9XSc=; b=vTfHheGB1gCW+0S8cCtroZdOH4Mun86kPj+vtyuktLMCfWvF47EVBcg+MJyLg3Rd8E UHWDjoRikjZqU6MiIRNrKtr6meRp1iwrhjVcLQao+0PZM+ZKkWeIeem1F6wsIPbkaqZM 7l7xMd7MFaVpdY0yWCZJNjLs3EFJv1UvfCh0AWaXihrEuK15bLaIMbXa9bJjynWtKGE7 fV/Q15QI3JHDq/ERT/vBZPFxoTAdK3ifg17KRS/TormXwLkKk0elKYNx+5GKXPMd2xpb N42I56u/MWH04xEvb31isOrp/C8BgQYL0ZJ1gm5AovZVd3Qr7CYTLaiobThDMEWmwhdb kc3w== X-Gm-Message-State: AOJu0Yz/KZcHJseJiLENmvUwOy0zmIG+BUWESpdA4/J7JA1KElHfjbT/ LXSE1ySh4a5Hy/1yqwQ3pvIJv3WPdrkAALFjCHsHSBWnoakB2gupWzSaqHiijIQ= X-Google-Smtp-Source: AGHT+IFa9EXNILXQkEvGWQUIOOA63etKevXkmw5q28slYY6iHwHtb/9wtgcuyorN42OKWTa9d7vFYg== X-Received: by 2002:a05:6000:1010:b0:337:c642:7acf with SMTP id a16-20020a056000101000b00337c6427acfmr1422410wrx.108.1705662714705; Fri, 19 Jan 2024 03:11:54 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm3341868wrv.20.2024.01.19.03.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:11:53 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: andi.shyti@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v4 6/8] arm64: dts: exynos: gs101: update USI UART to use peric0 clocks Date: Fri, 19 Jan 2024 11:11:30 +0000 Message-ID: <20240119111132.1290455-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119111132.1290455-1-tudor.ambarus@linaro.org> References: <20240119111132.1290455-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Get rid of the dummy clock and start using the cmu_peric0 clocks for the usi_uart and serial_0 nodes. Tested the serial at 115200, 1000000 and 3000000 baudrates, everthing went fine. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 2d1344a202a9..6aa25cc4676e 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -180,14 +180,6 @@ HERA_CPU_SLEEP: cpu-hera-sleep { }; }; - /* TODO replace with CCF clock */ - dummy_clk: clock-3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12345>; - clock-output-names = "pclk"; - }; - /* ect node is required to be present by bootloader */ ect { }; @@ -367,7 +359,8 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&dummy_clk>, <&dummy_clk>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm3341868wrv.20.2024.01.19.03.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:11:55 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: andi.shyti@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v4 7/8] arm64: dts: exynos: gs101: define USI8 with I2C configuration Date: Fri, 19 Jan 2024 11:11:31 +0000 Message-ID: <20240119111132.1290455-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119111132.1290455-1-tudor.ambarus@linaro.org> References: <20240119111132.1290455-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 USI8 I2C is used to communicate with an eeprom found on the battery connector. Define USI8 in I2C configuration. USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 6aa25cc4676e..f14a24628d04 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 { interrupts = ; }; + usi8: usi@109700c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_8: i2c@10970000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = ; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm3341868wrv.20.2024.01.19.03.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:11:56 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: andi.shyti@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v4 8/8] arm64: dts: exynos: gs101: enable eeprom on gs101-oriole Date: Fri, 19 Jan 2024 11:11:32 +0000 Message-ID: <20240119111132.1290455-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119111132.1290455-1-tudor.ambarus@linaro.org> References: <20240119111132.1290455-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable the eeprom found on the battery connector. The selection of the USI protocol is done in the board dts file because the USI CONFIG register comes with a 0x0 reset value, meaning that USI8 does not have a default protocol (I2C, SPI, UART) at reset. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 4a71f752200d..cb4d17339b6b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -63,6 +63,15 @@ &ext_200m { clock-frequency = <200000000>; }; +&hsi2c_8 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + &pinctrl_far_alive { key_voldown: key-voldown-pins { samsung,pins = "gpa7-3"; @@ -99,6 +108,11 @@ &usi_uart { status = "okay"; }; +&usi8 { + samsung,mode = ; + status = "okay"; +}; + &watchdog_cl0 { timeout-sec = <30>; status = "okay";