From patchwork Sun Jan 21 10:40:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13524530 Received: from ahti.lucaweiss.eu (ahti.lucaweiss.eu [128.199.32.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A07BA12E59; Sun, 21 Jan 2024 10:40:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=128.199.32.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705833650; cv=none; b=bQ5n7SaXQ1EwbZVQsJbmMvIoK6IvmbHdC+Z1tr+seE3JXrPHiX2sbHahjlwSfnpN+/7YiJME6CHCRq/3KNdWzdfGP5gsoy991URlnmhHhV0bWtcxaW5uf8YylBBv4JtHDcfUiXTyPGRzbLAJnqvSSJlaMcJf7CkESkx2YbSoHco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705833650; c=relaxed/simple; bh=v1/V8yxynbgaJGBY5IHCbJPMSnPaAg0Cc58Fpy0/0eM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eZOZfkv9NJB4jScSAiNEhS0a+U9YHsQAaTPplXRV2n/wuNeEdTIECKAgkt34Ka/6FROjuxHXAO69H/2hsw05qRn9u6zjlDYKmmOPLvGhcmYWhcGpOI+8KZyWGItRzsSxD43qIRNzvf9P6dS0uqZi0gRcy9cgCIwfs8b/aog+eVI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=z3ntu.xyz; spf=pass smtp.mailfrom=z3ntu.xyz; dkim=pass (1024-bit key) header.d=z3ntu.xyz header.i=@z3ntu.xyz header.b=PKsohBEF; arc=none smtp.client-ip=128.199.32.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=z3ntu.xyz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=z3ntu.xyz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=z3ntu.xyz header.i=@z3ntu.xyz header.b="PKsohBEF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=s1; t=1705833646; bh=v1/V8yxynbgaJGBY5IHCbJPMSnPaAg0Cc58Fpy0/0eM=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=PKsohBEFeSSc51TOewqkghUWEmTiL3f2nXI/71JcyM/OCu/midFeDoZ+L+MMwouY/ NjUMcTdbNktnieiIlDM+YoOJdVLUQrL7/vumVaHrxVhE8aR6Fov5qMY1JoU92T3rI8 YbCNu4ufrqyO8sAhY+U3SwKU3RnFknTPjnOCYQY8= From: Luca Weiss Date: Sun, 21 Jan 2024 11:40:38 +0100 Subject: [PATCH v2 1/2] dt-bindings: display/msm: gpu: Allow multiple digits for patchid Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240121-msm8226-gpu-v2-1-77f4a6fbbca4@z3ntu.xyz> References: <20240121-msm8226-gpu-v2-0-77f4a6fbbca4@z3ntu.xyz> In-Reply-To: <20240121-msm8226-gpu-v2-0-77f4a6fbbca4@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1665; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=v1/V8yxynbgaJGBY5IHCbJPMSnPaAg0Cc58Fpy0/0eM=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBlrPSrBqo6O3RxUO+wPi4zf0JipGyXEKiNmkwKe i/xAsC3PFSJAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZaz0qwAKCRBy2EO4nU3X VqKnEADKPbwniYpsgch1XFFVEdcdVqCqWvfqfgzCUAC6QlHDcMs/JQ4JNq8w7owtiRCkOT0Bhpa FGNC1zPT6Ze991JA9l2l17Q4xrwAOYwpcx11zBhx0Ad10WUOuUav6U8HSm+nyKUYcE/n78tQGLF uXvS4ezPoVqfqQuo9/lXp3x5K5pbcLNa1JKVEDM09Zksycl/CyF/909l9TrioZsBykUpwVpyCJD NlOIhACuKFFGJCbID9QKld1xz6pDYZp56kmSvMogd370qw1WV2F6kB+/5kY9tNJBLoQ487pIdIS xxzIpB2NZliygoJ/ecX56KhalRPCP9lMauMoPXo4q+1zeVGCEJ21vvUWK6S/69xOHTCghrXOkzx CPxkp7A68PpRpLBBWtW4e0Rle/wq19nBUmb8dVxGgqxNWl7y2u2O/7v1jsOwGsZkkewFeA64/aY 5txGENH2xGzbLF0CwlDkaqiVuzjjnsHzng6VbiDL8FMKZLwAavjVzXY6k/tU5uzZXfbyM2Ahuzq 0gNppMEnK3mea3yMho+WdHGAn8lKsEYxbd2Acz2+exI63SYfj9WLQgU1RIjgxBG6XUrA2BLuWe+ QIVO/dLBe3JbW4bU8ZpFpX6jCpkWME9rg2N29fdvae7Osi1D3iNnjvpIJKzqaMEvu1WNZokZd/M d2NbOTPbdlo3gYw== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Some GPUs like the Adreno A305B has a patchid higher than 9, in this case 18. Make sure the regexes can account for that. Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Reviewed-by: David Heidelberg --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index b019db954793..40b5c6bd11f8 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -23,7 +23,7 @@ properties: The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. items: - - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' - const: qcom,adreno - description: | The driver is parsing the compat string for Imageon to @@ -127,7 +127,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' then: properties: @@ -203,7 +203,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: From patchwork Sun Jan 21 10:40:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13524531 Received: from ahti.lucaweiss.eu (ahti.lucaweiss.eu [128.199.32.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7374512E61; Sun, 21 Jan 2024 10:40:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=128.199.32.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705833650; cv=none; b=j0Bljdp66ecAfpx/G4bDeDjOuJ5OnzK6SStoa+eawaN3NL76Z/HbDzxRplUIyNbzfg+1KblwMK2t/RDwZQpq5HfCTc+d6bVFSETqvHJiWtALRoLlKg37YOXXQG52h6wbBEoqIuZ/V2xVRH9yinI58jXWoRXwWfhErKFfx/ULexU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705833650; c=relaxed/simple; bh=nBjQLwAVrLOtDklPZXhl6mSYmrwebasaPOxc4Nq5ooI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC. Previously this was mistakenly claimed to be supported but using wrong a configuration. In MSM8226v1 there's also a A305B but with chipid 0x03000510 which should work with the same configuration but due to lack of hardware for testing this is not added. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: David Heidelberg --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 13 ++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 15 +++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ 3 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index c86b377f6f0d..5273dc849838 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -134,6 +134,13 @@ static int a3xx_hw_init(struct msm_gpu *gpu) /* Set up AOOO: */ gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); + } else if (adreno_is_a305b(adreno_gpu)) { + gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818); + gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818); + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018); + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018); + gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303); + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); } else if (adreno_is_a306(adreno_gpu)) { gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a); @@ -230,7 +237,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001); /* Enable Clock gating: */ - if (adreno_is_a306(adreno_gpu)) + if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); else if (adreno_is_a320(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff); @@ -333,7 +340,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu) AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14)); - } else if (adreno_is_a330(adreno_gpu)) { + } else if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) { /* NOTE: this (value take from downstream android driver) * includes some bits outside of the known bitfields. But * A330 has this "MERCIU queue" thing too, which might @@ -559,7 +566,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) goto fail; /* if needed, allocate gmem: */ - if (adreno_is_a330(adreno_gpu)) { + if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) { ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev, adreno_gpu, &a3xx_gpu->ocmem); if (ret) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..f2768e52ed12 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -55,10 +55,17 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x03000512, - 0x03000520 - ), + .chip_ids = ADRENO_CHIP_IDS(0x03000512), + .family = ADRENO_3XX, + .fw = { + [ADRENO_FW_PM4] = "a330_pm4.fw", + [ADRENO_FW_PFP] = "a330_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x03000520), .family = ADRENO_3XX, .revn = 305, .fw = { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..d3c41af706df 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -256,6 +256,11 @@ static inline bool adreno_is_a305(const struct adreno_gpu *gpu) return adreno_is_revn(gpu, 305); } +static inline bool adreno_is_a305b(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x03000512; +} + static inline bool adreno_is_a306(const struct adreno_gpu *gpu) { /* yes, 307, because a305c is 306 */