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Sun, 21 Jan 2024 12:42:55 +0000 Received: from TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0]) by TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0%7]) with mapi id 15.20.7181.019; Sun, 21 Jan 2024 12:42:55 +0000 From: Ziyang Huang To: mcoquelin.stm32@gmail.com Cc: alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, Ziyang Huang Subject: [PATCH 1/8] net: phy: Introduce Qualcomm IPQ5018 internal PHY driver Date: Sun, 21 Jan 2024 20:42:30 +0800 Message-ID: X-Mailer: git-send-email 2.40.1 In-Reply-To: References: X-TMN: [nfEoGlwwp8/ShSyGEZ809gEznySqDSjYDALQWyLowDbaoJai5WxIrw==] X-ClientProxiedBy: PH8PR21CA0009.namprd21.prod.outlook.com (2603:10b6:510:2ce::26) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <20240121124237.3328702-1-hzyitc@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|OSQPR01MB6119:EE_ X-MS-Office365-Filtering-Correlation-Id: 980c753f-cf0a-4d35-0300-08dc1a7e7d91 X-Microsoft-Antispam: BCL:0; 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+ struct clk_bulk_data *clks; + struct reset_control *rst; + + struct clk_hw *clk_rx, *clk_tx; + struct clk_hw_onecell_data *clk_data; +}; + +static int ipq5018_probe(struct phy_device *phydev) +{ + struct ipq5018_phy *priv; + struct device *dev = &phydev->mdio.dev; + char name[64]; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate priv\n"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 0) + return dev_err_probe(dev, priv->num_clks, + "failed to acquire clocks\n"); + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable clocks\n"); + + priv->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR_OR_NULL(priv->rst)) + return dev_err_probe(dev, PTR_ERR(priv->rst), + "failed to acquire reset\n"); + + ret = reset_control_reset(priv->rst); + if (ret) + return dev_err_probe(dev, ret, + "failed to reset\n"); + + snprintf(name, sizeof(name), "%s#rx", dev_name(dev)); + priv->clk_rx = clk_hw_register_fixed_rate(dev, name, NULL, 0, + TX_RX_CLK_RATE); + if (IS_ERR_OR_NULL(priv->clk_rx)) + return dev_err_probe(dev, PTR_ERR(priv->clk_rx), + "failed to register rx clock\n"); + + snprintf(name, sizeof(name), "%s#tx", dev_name(dev)); + priv->clk_tx = clk_hw_register_fixed_rate(dev, name, NULL, 0, + TX_RX_CLK_RATE); + if (IS_ERR_OR_NULL(priv->clk_tx)) + return dev_err_probe(dev, PTR_ERR(priv->clk_tx), + "failed to register tx clock\n"); + + priv->clk_data = devm_kzalloc(dev, + struct_size(priv->clk_data, hws, 2), + GFP_KERNEL); + if (!priv->clk_data) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate clk_data\n"); + + priv->clk_data->num = 2; + priv->clk_data->hws[0] = priv->clk_rx; + priv->clk_data->hws[1] = priv->clk_tx; + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + priv->clk_data); + if (ret) + return dev_err_probe(dev, ret, + "fail to register clock provider\n"); + + return 0; +} + +static int ipq5018_soft_reset(struct phy_device *phydev) +{ + int ret; + + ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL, + IPQ5018_PHY_FIFO_RESET, 0); + if (ret < 0) + return ret; + + msleep(50); + + ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL, + IPQ5018_PHY_FIFO_RESET, IPQ5018_PHY_FIFO_RESET); + if (ret < 0) + return ret; + + return 0; +} + +static struct phy_driver ipq5018_internal_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), + .name = "Qualcomm IPQ5018 internal PHY", + .flags = PHY_IS_INTERNAL, + .probe = ipq5018_probe, + .soft_reset = ipq5018_soft_reset, + }, +}; +module_phy_driver(ipq5018_internal_phy_driver); + +static struct mdio_device_id __maybe_unused ipq5018_internal_phy_ids[] = { + { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, + { } +}; +MODULE_DEVICE_TABLE(mdio, ipq5018_internal_phy_ids); + +MODULE_DESCRIPTION("Qualcomm IPQ5018 internal PHY driver"); +MODULE_AUTHOR("Ziyang Huang "); From patchwork Sun Jan 21 12:42:31 2024 Content-Type: text/plain; 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Sun, 21 Jan 2024 12:43:04 +0000 Received: from TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0]) by TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0%7]) with mapi id 15.20.7181.019; Sun, 21 Jan 2024 12:43:04 +0000 From: Ziyang Huang To: mcoquelin.stm32@gmail.com Cc: alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, Ziyang Huang Subject: [PATCH 2/8] phy: Introduce Qualcomm ethernet uniphy driver Date: Sun, 21 Jan 2024 20:42:31 +0800 Message-ID: X-Mailer: git-send-email 2.40.1 In-Reply-To: References: X-TMN: [kV5Ly6/5oO4AGfwD/o4AHprlfetwjX3LAlGd2heNgymp5Zj+imTcnA==] X-ClientProxiedBy: PH8PR21CA0009.namprd21.prod.outlook.com (2603:10b6:510:2ce::26) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <20240121124237.3328702-2-hzyitc@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|OSQPR01MB6119:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a83ba4c-b354-4fba-3f06-08dc1a7e82bc X-Microsoft-Antispam: BCL:0; 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Depends on different SoC, it can support + * SGMII/SGMII+/USXGMII. What's more, in some SoC it also support + * QSGMII/PSGMII which combine multi SGMII line into single physical port. + * + * ======================================================================= + * ________________________________ + * | _______ IPQ807x | + * | | GMAC0 |__ | + * | |_______| \ | _________ + * | _______ \ | ____| GPHY | + * | | GMAC1 |__ \ _________ | / | /Switch | + * | |_______| \ \___| | | SGMII(+) |_________| + * | _______ \_____| | | P0 / + * | | GMAC2 |_________| UNIPHY0 |--|-----or + * | |_______| _____| | | \ + * | _______ / __| | | (Q/P)SGMII __________ + * | | GMAC3 |__/ / |_________| | \____| (Q/P)PHY | + * | |_______| / | |__________| + * | _______ / | + * | | GMAC4 |--or | _________ + * | |_______| \ _________ | P1 | (X)GPHY | + * | ________ or--| UNIPHY1 |--|----SGMII(+)--| /Switch | + * | | XGMAC0 |___/ |_________| | /USXGMII |_________| + * | |________| | + * | ________ | + * | | GMAC5 |___ | _________ + * | |________| \ _________ | P2 | (X)GPHY | + * | ________ or--| UNIPHY2 |--|----SGMII(+)--| /Switch | + * | | XGMAC1 |___/ |_________| | /USXGMII |_________| + * | |________| | + * |________________________________| + * + * ======================================================================= + * _________________________________ + * | _______ IPQ50xx ______ | P0 ______ + * | | GMAC0 |___________| GPHY |---|------UTP------| RJ45 | + * | |_______| |______| | |______| + * | _______ _________ | _________ + * | | GMAC1 |_________| UNIPHY0 | | P1 | GPHY | + * | |_______| |_________|--|----SGMII(+)--| /Switch | + * |________________________________| |_________| + * + * ======================================================================= + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define TCSR_ETH_CMN 0x0 +#define TCSR_ETH_CMN_ENABLE BIT(0) + + +#define CMN_PLL_REFCLK_SRC 0x28 +#define CMN_PLL_REFCLK_SRC_FROM_MASK GENMASK(9, 8) +#define CMN_PLL_REFCLK_SRC_FROM(x) FIELD_PREP(CMN_PLL_REFCLK_SRC_FROM_MASK, (x)) +#define CMN_PLL_REFCLK_SRC_FROM_REG CMN_PLL_REFCLK_SRC_FROM(0) +#define CMN_PLL_REFCLK_SRC_FROM_LOGIC CMN_PLL_REFCLK_SRC_FROM(1) +#define CMN_PLL_REFCLK_SRC_FROM_PCS CMN_PLL_REFCLK_SRC_FROM(2) + +#define CMN_PLL_REFCLK 0x784 +#define CMN_PLL_REFCLK_EXTERNAL BIT(9) +#define CMN_PLL_REFCLK_DIV_MASK GENMASK(8, 4) +#define CMN_PLL_REFCLK_DIV(x) FIELD_PREP(CMN_PLL_REFCLK_DIV_MASK, (x)) +#define CMN_PLL_REFCLK_FREQ_MASK GENMASK(3, 0) +#define CMN_PLL_REFCLK_FREQ(x) FIELD_PREP(CMN_PLL_REFCLK_FREQ_MASK, (x)) +#define CMN_PLL_REFCLK_FREQ_25M CMN_PLL_REFCLK_FREQ(3) +#define CMN_PLL_REFCLK_FREQ_31250K CMN_PLL_REFCLK_FREQ(4) +#define CMN_PLL_REFCLK_FREQ_40M CMN_PLL_REFCLK_FREQ(6) +#define CMN_PLL_REFCLK_FREQ_48M CMN_PLL_REFCLK_FREQ(7) +#define CMN_PLL_REFCLK_FREQ_50M CMN_PLL_REFCLK_FREQ(8) + +#define CMN_PLL_CTRL 0x780 +#define CMN_PLL_CTRL_RST_N BIT(6) + +#define CMN_PLL_STATUS 0x64 +#define CMN_PLL_STATUS_LOCKED BIT(2) + + +#define IPQ50XX_UNIPHY_CLKOUT 0x74 +#define IPQ50XX_UNIPHY_CLKOUT_DS_MASK GENMASK(3, 2) +#define IPQ50XX_UNIPHY_CLKOUT_DS(x) FIELD_PREP(IPQ50XX_UNIPHY_CLKOUT_DS_MASK, (x)) +#define IPQ50XX_UNIPHY_CLKOUT_DS_2_8V IPQ50XX_UNIPHY_CLKOUT_DS(0) +#define IPQ50XX_UNIPHY_CLKOUT_DS_1_5V IPQ50XX_UNIPHY_CLKOUT_DS(1) +#define IPQ50XX_UNIPHY_CLKOUT_DIV_MASK GENMASK(1, 1) +#define IPQ50XX_UNIPHY_CLKOUT_DIV(x) FIELD_PREP(IPQ50XX_UNIPHY_CLKOUT_DIV_MASK, (x)) +#define IPQ50XX_UNIPHY_CLKOUT_DIV_50M IPQ50XX_UNIPHY_CLKOUT_DIV(0) +#define IPQ50XX_UNIPHY_CLKOUT_DIV_25M IPQ50XX_UNIPHY_CLKOUT_DIV(1) +#define IPQ50XX_UNIPHY_CLKOUT_ENABLE BIT(0) + +#define IPQ53XX_UNIPHY_CLKOUT 0x610 +#define IPQ53XX_UNIPHY_CLKOUT_LDO_LEVEL_MASK GENMASK(10, 8) +#define IPQ53XX_UNIPHY_CLKOUT_DIV_MASK GENMASK(5, 5) +#define IPQ53XX_UNIPHY_CLKOUT_DIV(x) FIELD_PREP(IPQ53XX_UNIPHY_CLKOUT_DIV_MASK, (x)) +#define IPQ53XX_UNIPHY_CLKOUT_DIV_50M IPQ53XX_UNIPHY_CLKOUT_DIV(0) +#define IPQ53XX_UNIPHY_CLKOUT_DIV_25M IPQ53XX_UNIPHY_CLKOUT_DIV(1) +#define IPQ53XX_UNIPHY_CLKOUT_PULLDOWN BIT(3) +#define IPQ53XX_UNIPHY_CLKOUT_DS_MASK GENMASK(2, 1) +#define IPQ53XX_UNIPHY_CLKOUT_DS(x) FIELD_PREP(IPQ53XX_UNIPHY_CLKOUT_DS_MASK, (x)) +#define IPQ53XX_UNIPHY_CLKOUT_DS_2_8V IPQ53XX_UNIPHY_CLKOUT_DS(0) +#define IPQ53XX_UNIPHY_CLKOUT_DS_1_5V IPQ53XX_UNIPHY_CLKOUT_DS(1) +#define IPQ53XX_UNIPHY_CLKOUT_ENABLE BIT(0) + + +#define UNIPHY_MODE 0x46c +#define UNIPHY_MODE_USXG BIT(13) +#define UNIPHY_MODE_XPCS BIT(12) +#define UNIPHY_MODE_SGMIIPLUS BIT(11) +#define UNIPHY_MODE_SGMII BIT(10) +#define UNIPHY_MODE_PSGMII BIT(9) +#define UNIPHY_MODE_QSGMII BIT(8) +#define UNIPHY_MODE_CH0_MODE_MASK GENMASK(6, 4) +#define UNIPHY_MODE_CH0_MODE(x) FIELD_PREP(UNIPHY_MODE_CH0_MODE_MASK, (x)) +#define UNIPHY_MODE_CH0_MODE_1000BASEX UNIPHY_MODE_CH0_MODE(0) +#define UNIPHY_MODE_CH0_MODE_MAC UNIPHY_MODE_CH0_MODE(2) +#define UNIPHY_MODE_SGMII_CHANNEL_MASK GENMASK(2, 1) +#define UNIPHY_MODE_SGMII_CHANNEL(x) FIELD_PREP(UNIPHY_MODE_SGMII_CHANNEL_MASK, (x)) +#define UNIPHY_MODE_SGMII_CHANNEL_0 UNIPHY_MODE_SGMII_CHANNEL(0) +#define UNIPHY_MODE_SGMII_CHANNEL_1 UNIPHY_MODE_SGMII_CHANNEL(1) +#define UNIPHY_MODE_SGMII_CHANNEL_4 UNIPHY_MODE_SGMII_CHANNEL(2) +#define UNIPHY_MODE_AN_MODE_MASK BIT(0) +#define UNIPHY_MODE_AN_MODE(x) FIELD_PREP(UNIPHY_MODE_AN_MODE_MASK, (x)) +#define UNIPHY_MODE_AN_MODE_ATHEROS UNIPHY_MODE_AN_MODE(0) +#define UNIPHY_MODE_AN_MODE_STANDARD UNIPHY_MODE_AN_MODE(1) + +#define UNIPHY_PLL_CTRL 0x780 +#define UNIPHY_PLL_CTRL_RST_N BIT(6) + +#define UNIPHY_CALIBRATION 0x1E0 +#define UNIPHY_CALIBRATION_DONE BIT(7) + + +#define UNIPHY_CHANNEL(x) (0x480 + 0x18 * (x)) +#define UNIPHY_CHANNEL_RSTN BIT(11) +#define UNIPHY_CHANNEL_FORCE_SPEED_25M BIT(3) + +#define UNIPHY_SGMII 0x218 +#define UNIPHY_SGMII_MODE_MASK GENMASK(6, 4) +#define UNIPHY_SGMII_MODE(x) FIELD_PREP(UNIPHY_SGMII_MODE_MASK, (x)) +#define UNIPHY_SGMII_MODE_SGMII UNIPHY_SGMII_MODE(3) +#define UNIPHY_SGMII_MODE_SGMIIPLUS UNIPHY_SGMII_MODE(5) +#define UNIPHY_SGMII_MODE_USXGMII UNIPHY_SGMII_MODE(7) +#define UNIPHY_SGMII_RATE_MASK GENMASK(1, 0) +#define UNIPHY_SGMII_RATE(x) FIELD_PREP(UNIPHY_SGMII_RATE_MASK, (x)) + + +#define SGMII_CLK_RATE 125000000 /* 125M */ +#define SGMII_PLUS_CLK_RATE 312500000 /* 312.5M */ + + +struct qcom_eth_uniphy { + struct device *dev; + void __iomem *base; + int num_clks; + struct clk_bulk_data *clks; + struct reset_control *rst; + + int mode; + + struct clk_hw *clk_rx, *clk_tx; + struct clk_hw_onecell_data *clk_data; +}; + + +#define rmwl(addr, mask, val) \ + writel(((readl(addr) & ~(mask)) | ((val) & (mask))), addr) + +static int cmn_init(struct platform_device *pdev) +{ + struct resource *res; + void __iomem *cmn_base; + void __iomem *tcsr_base; + u32 val; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cmn"); + if (!res) + return 0; + + cmn_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR_OR_NULL(cmn_base)) + return PTR_ERR(cmn_base); + + /* For IPQ50xx, tcsr is necessary to enable cmn block */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr"); + if (res) { + tcsr_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR_OR_NULL(tcsr_base)) + return PTR_ERR(tcsr_base); + + rmwl((tcsr_base + TCSR_ETH_CMN), TCSR_ETH_CMN_ENABLE, + TCSR_ETH_CMN_ENABLE); + } + + rmwl((cmn_base + CMN_PLL_REFCLK_SRC), + CMN_PLL_REFCLK_SRC_FROM_MASK, + CMN_PLL_REFCLK_SRC_FROM_REG); + rmwl((cmn_base + CMN_PLL_REFCLK), + (CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_FREQ_MASK + | CMN_PLL_REFCLK_DIV_MASK), + (CMN_PLL_REFCLK_FREQ_48M | CMN_PLL_REFCLK_DIV(2))); + + rmwl((cmn_base + CMN_PLL_CTRL), CMN_PLL_CTRL_RST_N, 0); + msleep(1); + rmwl((cmn_base + CMN_PLL_CTRL), CMN_PLL_CTRL_RST_N, + CMN_PLL_CTRL_RST_N); + msleep(1); + + return read_poll_timeout(readl, val, + (val & CMN_PLL_STATUS_LOCKED), + 100, 200000, false, + (cmn_base + CMN_PLL_STATUS)); +} + + +static void uniphy_write(struct qcom_eth_uniphy *uniphy, int addr, u32 val) +{ + writel(val, (uniphy->base + addr)); +} + +static u32 uniphy_read(struct qcom_eth_uniphy *uniphy, int addr) +{ + return readl((uniphy->base + addr)); +} + +static void uniphy_rmw(struct qcom_eth_uniphy *uniphy, int addr, u32 mask, u32 val) +{ + u32 v = uniphy_read(uniphy, addr); + v &= ~mask; + v |= val & mask; + uniphy_write(uniphy, addr, v); +} + +static int uniphy_clkout_init(struct qcom_eth_uniphy *uniphy) +{ + u32 val; + int ret; + + ret = of_property_read_u32(uniphy->dev->of_node, "clkout-frequency", &val); + if (ret == -EINVAL) + return 0; + else if (ret < 0) + return ret; + + switch(val) { + case QCOM_ETH_UNIPHY_CLKOUT_FREQ_25M: + uniphy_rmw(uniphy, IPQ50XX_UNIPHY_CLKOUT, + IPQ50XX_UNIPHY_CLKOUT_DIV_MASK, + IPQ50XX_UNIPHY_CLKOUT_DIV_25M); + break; + case QCOM_ETH_UNIPHY_CLKOUT_FREQ_50M: + uniphy_rmw(uniphy, IPQ50XX_UNIPHY_CLKOUT, + IPQ50XX_UNIPHY_CLKOUT_DIV_MASK, + IPQ50XX_UNIPHY_CLKOUT_DIV_50M); + break; + default: + dev_err(uniphy->dev, "Unsupported clkout-frequency: %d\n", val); + return -EINVAL; + } + + ret = of_property_read_u32(uniphy->dev->of_node, "clkout-drive-strength", &val); + if (ret != -EINVAL) { + if (ret < 0) + return ret; + + switch(val) { + case QCOM_ETH_UNIPHY_CLKOUT_DS_1_5V: + uniphy_rmw(uniphy, IPQ50XX_UNIPHY_CLKOUT, + IPQ50XX_UNIPHY_CLKOUT_DS_MASK, + IPQ50XX_UNIPHY_CLKOUT_DS_1_5V); + break; + case QCOM_ETH_UNIPHY_CLKOUT_DS_2_8V: + uniphy_rmw(uniphy, IPQ50XX_UNIPHY_CLKOUT, + IPQ50XX_UNIPHY_CLKOUT_DS_MASK, + IPQ50XX_UNIPHY_CLKOUT_DS_2_8V); + break; + default: + dev_err(uniphy->dev, "Unsupported clkout-drive-strength: %d\n", val); + return -EINVAL; + } + + } + + uniphy_rmw(uniphy, IPQ50XX_UNIPHY_CLKOUT, + IPQ50XX_UNIPHY_CLKOUT_ENABLE, + IPQ50XX_UNIPHY_CLKOUT_ENABLE); + + return 0; +} + +static int uniphy_mode_set(struct qcom_eth_uniphy *uniphy) +{ + int ret; + + ret = of_property_read_u32(uniphy->dev->of_node, "mode", + &uniphy->mode); + if (ret < 0) + return ret; + + switch(uniphy->mode) { + case QCOM_ETH_UNIPHY_MODE_SGMII: + uniphy_write(uniphy, UNIPHY_MODE, + UNIPHY_MODE_SGMII); + uniphy_rmw(uniphy, UNIPHY_SGMII, + UNIPHY_SGMII_MODE_MASK, + UNIPHY_SGMII_MODE_SGMII); + break; + default: + dev_err(uniphy->dev, "Unsupported mode: %d\n", + uniphy->mode); + return -EINVAL; + } + + return 0; +} + +static int uniphy_calibrate(struct qcom_eth_uniphy *uniphy) +{ + u32 val; + + uniphy_rmw(uniphy, UNIPHY_PLL_CTRL, UNIPHY_PLL_CTRL_RST_N, 0); + msleep(1); + uniphy_rmw(uniphy, UNIPHY_PLL_CTRL, UNIPHY_PLL_CTRL_RST_N, + UNIPHY_PLL_CTRL_RST_N); + msleep(1); + + return read_poll_timeout(uniphy_read, val, + (val & UNIPHY_CALIBRATION_DONE), + 100, 200000, false, + uniphy, UNIPHY_CALIBRATION); +} + +static int uniphy_clk_register(struct qcom_eth_uniphy *uniphy) +{ + unsigned long rate; + char name[64]; + int ret; + + switch (uniphy->mode) { + case QCOM_ETH_UNIPHY_MODE_SGMII: + rate = SGMII_CLK_RATE; + break; + } + + snprintf(name, sizeof(name), "%s#rx", dev_name(uniphy->dev)); + uniphy->clk_rx = clk_hw_register_fixed_rate(uniphy->dev, name, + NULL, 0, rate); + if (IS_ERR_OR_NULL(uniphy->clk_rx)) + return dev_err_probe(uniphy->dev, PTR_ERR(uniphy->clk_rx), + "failed to register rx clock\n"); + + snprintf(name, sizeof(name), "%s#tx", dev_name(uniphy->dev)); + uniphy->clk_tx = clk_hw_register_fixed_rate(uniphy->dev, name, + NULL, 0, rate); + if (IS_ERR_OR_NULL(uniphy->clk_tx)) + return dev_err_probe(uniphy->dev, PTR_ERR(uniphy->clk_tx), + "failed to register rx clock\n"); + + uniphy->clk_data = devm_kzalloc(uniphy->dev, + struct_size(uniphy->clk_data, hws, 2), + GFP_KERNEL); + if (!uniphy->clk_data) + return dev_err_probe(uniphy->dev, -ENOMEM, + "failed to allocate clk_data\n"); + + uniphy->clk_data->num = 2; + uniphy->clk_data->hws[0] = uniphy->clk_rx; + uniphy->clk_data->hws[1] = uniphy->clk_tx; + ret = of_clk_add_hw_provider(uniphy->dev->of_node, + of_clk_hw_onecell_get, + uniphy->clk_data); + if (ret) + return dev_err_probe(uniphy->dev, ret, + "fail to register clock provider\n"); + + return 0; +} + +static int qcom_eth_uniphy_calibrate(struct phy *phy) +{ + struct qcom_eth_uniphy *uniphy = phy_get_drvdata(phy); + dev_info(uniphy->dev, "calibrating\n"); + return uniphy_calibrate(uniphy); +} + +static const struct phy_ops qcom_eth_uniphy_ops = { + .calibrate = qcom_eth_uniphy_calibrate, + .owner = THIS_MODULE, +}; + +static int qcom_eth_uniphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct qcom_eth_uniphy *uniphy; + struct phy *phy; + struct phy_provider *phy_provider; + int ret; + + ret = cmn_init(pdev); + if (ret) + return dev_err_probe(dev, ret, + "failed to init cmn block\n"); + + uniphy = devm_kzalloc(dev, sizeof(*uniphy), GFP_KERNEL); + if (!uniphy) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate priv\n"); + + uniphy->dev = dev; + uniphy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(uniphy->base)) + return dev_err_probe(dev, PTR_ERR(uniphy->base), + "failed to ioremap base\n"); + + uniphy->num_clks = devm_clk_bulk_get_all(uniphy->dev, &uniphy->clks); + if (uniphy->num_clks < 0) + return dev_err_probe(uniphy->dev, uniphy->num_clks, + "failed to acquire clocks\n"); + + ret = clk_bulk_prepare_enable(uniphy->num_clks, uniphy->clks); + if (ret) + return dev_err_probe(uniphy->dev, ret, + "failed to enable clocks\n"); + + uniphy->rst = devm_reset_control_array_get_exclusive(uniphy->dev); + if (IS_ERR_OR_NULL(uniphy->rst)) + return dev_err_probe(uniphy->dev, PTR_ERR(uniphy->rst), + "failed to acquire reset\n"); + + ret = reset_control_reset(uniphy->rst); + if (ret) + return dev_err_probe(uniphy->dev, ret, + "failed to reset\n"); + + ret = uniphy_clkout_init(uniphy); + if (ret) + return dev_err_probe(dev, ret, + "failed to init clkout\n"); + + ret = uniphy_mode_set(uniphy); + if (ret) + return dev_err_probe(dev, ret, + "failed to set mode\n"); + + ret = uniphy_calibrate(uniphy); + if (ret) + return dev_err_probe(dev, ret, + "failed to calibrate\n"); + + ret = uniphy_clk_register(uniphy); + if (ret) + return dev_err_probe(dev, ret, + "failed to register clocks\n"); + + phy = devm_phy_create(dev, dev->of_node, &qcom_eth_uniphy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "failed to register phy\n"); + + phy_set_drvdata(phy, uniphy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return dev_err_probe(dev, PTR_ERR(phy_provider), + "failed to register phy provider\n"); + + return 0; +} + +static const struct of_device_id qcom_eth_uniphy_of_match[] = { + { .compatible = "qcom,ipq5018-eth-uniphy" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_eth_uniphy_of_match); + +static struct platform_driver qcom_eth_uniphy_driver = { + .probe = qcom_eth_uniphy_probe, + .driver = { + .name = "qcom-eth-uniphy", + .of_match_table = qcom_eth_uniphy_of_match, + }, +}; +module_platform_driver(qcom_eth_uniphy_driver); + +MODULE_DESCRIPTION("Qualcomm ethernet uniphy driver"); +MODULE_AUTHOR("Ziyang Huang "); diff --git a/include/dt-bindings/phy/qcom-eth-uniphy.h b/include/dt-bindings/phy/qcom-eth-uniphy.h new file mode 100644 index 000000000000..038f82522ccd --- /dev/null +++ b/include/dt-bindings/phy/qcom-eth-uniphy.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_PHY_QCOM_ETH_UNIPHY +#define _DT_BINDINGS_PHY_QCOM_ETH_UNIPHY + +#define QCOM_ETH_UNIPHY_MODE_SGMII 0 +#define QCOM_ETH_UNIPHY_MODE_SGMII_PLUS 1 + +#define QCOM_ETH_UNIPHY_CLKOUT_FREQ_25M 25000000 +#define QCOM_ETH_UNIPHY_CLKOUT_FREQ_50M 50000000 + +#define QCOM_ETH_UNIPHY_CLKOUT_DS_1_5V 1500 +#define QCOM_ETH_UNIPHY_CLKOUT_DS_2_8V 2800 + +#endif From patchwork Sun Jan 21 12:42:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Huang X-Patchwork-Id: 13524555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org 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linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Signed-off-by: Ziyang Huang --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 7 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-ipq50xx.c | 155 ++++++++++++++++++ 3 files changed, 163 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq50xx.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 06c6871f8788..baf6601d759c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -78,6 +78,13 @@ config DWMAC_INGENIC device driver. This driver is used on for the Ingenic SoCs MAC ethernet controller. +config DWMAC_IPQ50XX + tristate "Qualcomm IPQ50xx DWMAC driver" + default ARCH_QCOM + depends on OF && (ARCH_QCOM || COMPILE_TEST) + help + Support for the Qualcomm IPQ50xx DWMAC. + config DWMAC_IPQ806X tristate "QCA IPQ806x DWMAC support" default ARCH_QCOM diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index 5b57aee19267..eec4405d76d2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -15,6 +15,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o obj-$(CONFIG_DWMAC_ANARION) += dwmac-anarion.o obj-$(CONFIG_DWMAC_INGENIC) += dwmac-ingenic.o +obj-$(CONFIG_DWMAC_IPQ50XX) += dwmac-ipq50xx.o obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-mediatek.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq50xx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq50xx.c new file mode 100644 index 000000000000..de8e9a0b2cb6 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq50xx.c @@ -0,0 +1,155 @@ +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +enum { + IPQ50XX_GMAC_CLK_SYS, + IPQ50XX_GMAC_CLK_CFG, + IPQ50XX_GMAC_CLK_AHB, + IPQ50XX_GMAC_CLK_AXI, + IPQ50XX_GMAC_CLK_RX, + IPQ50XX_GMAC_CLK_TX, + IPQ50XX_GMAC_CLK_PTP, +}; + +static const struct clk_bulk_data ipq50xx_gmac_clks[] = { + [IPQ50XX_GMAC_CLK_SYS] = { .id = "sys" }, + [IPQ50XX_GMAC_CLK_CFG] = { .id = "cfg" }, + [IPQ50XX_GMAC_CLK_AHB] = { .id = "ahb" }, + [IPQ50XX_GMAC_CLK_AXI] = { .id = "axi" }, + [IPQ50XX_GMAC_CLK_RX] = { .id = "rx" }, + [IPQ50XX_GMAC_CLK_TX] = { .id = "tx" }, + [IPQ50XX_GMAC_CLK_PTP] = { .id = "ptp" }, +}; + +struct ipq50xx_gmac { + struct device *dev; + struct clk_bulk_data clks[ARRAY_SIZE(ipq50xx_gmac_clks)]; + struct reset_control *rst; + struct phy *uniphy; +}; + +static int ipq50xx_gmac_powerup(struct net_device *ndev, void *priv) +{ + struct ipq50xx_gmac *gmac = priv; + int ret; + + ret = phy_init(gmac->uniphy); + if (ret) + return ret; + + ret = phy_power_on(gmac->uniphy); + if (ret) + return ret; + + return 0; +} + +static void ipq50xx_gmac_fix_speed(void *priv, unsigned int speed, unsigned int mode) +{ + struct ipq50xx_gmac *gmac = priv; + unsigned long rate; + + switch(speed) { + case SPEED_10: + rate = 2500000; + break; + case SPEED_100: + rate = 25000000; + break; + case SPEED_1000: + rate = 125000000; + break; + case SPEED_2500: + rate = 312500000; + break; + default: + dev_err(gmac->dev, "Unsupported speed: %d\n", speed); + rate = 125000000; + break; + } + + clk_set_rate(gmac->clks[IPQ50XX_GMAC_CLK_RX].clk, rate); + clk_set_rate(gmac->clks[IPQ50XX_GMAC_CLK_TX].clk, rate); + phy_calibrate(gmac->uniphy); +} + +static int ipq50xx_gmac_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct stmmac_resources stmmac_res; + struct plat_stmmacenet_data *plat_dat; + struct ipq50xx_gmac *gmac; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return dev_err_probe(dev, ret, + "failed to get stmmac platform resources\n"); + + plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR_OR_NULL(plat_dat)) + return dev_err_probe(dev, PTR_ERR(plat_dat), + "failed to parse stmmac dt parameters\n"); + + gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); + if (!gmac) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate priv\n"); + + gmac->dev = dev; + + memcpy(gmac->clks, ipq50xx_gmac_clks, sizeof(gmac->clks)); + ret = devm_clk_bulk_get_optional(dev, ARRAY_SIZE(gmac->clks), gmac->clks); + if (ret) + return dev_err_probe(dev, ret, + "failed to acquire clocks\n"); + + ret = clk_bulk_prepare_enable(ARRAY_SIZE(gmac->clks), gmac->clks); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable clocks\n"); + + gmac->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR_OR_NULL(gmac->rst)) + return dev_err_probe(dev, PTR_ERR(gmac->rst), + "failed to acquire reset\n"); + + ret = reset_control_reset(gmac->rst); + if (ret) + return dev_err_probe(dev, ret, + "failed to reset\n"); + + gmac->uniphy = devm_phy_optional_get(dev, "uniphy"); + if (IS_ERR(gmac->uniphy)) + return dev_err_probe(dev, PTR_ERR(gmac->uniphy), + "failed to acquire uniphy\n"); + + plat_dat->bsp_priv = gmac; + plat_dat->serdes_powerup = ipq50xx_gmac_powerup; + plat_dat->fix_mac_speed = ipq50xx_gmac_fix_speed; + + return stmmac_dvr_probe(dev, plat_dat, &stmmac_res); +} + +static const struct of_device_id ipq50xx_gmac_dwmac_match[] = { + { .compatible = "qcom,ipq50xx-gmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, ipq50xx_gmac_dwmac_match); + +static struct platform_driver ipq50xx_gmac_dwmac_driver = { + .probe = ipq50xx_gmac_probe, + .driver = { + .name = "ipq50xx-gmac-dwmac", + .of_match_table = ipq50xx_gmac_dwmac_match, + }, +}; +module_platform_driver(ipq50xx_gmac_dwmac_driver); + +MODULE_DESCRIPTION("Qualcomm IPQ50xx DWMAC driver"); +MODULE_AUTHOR("Ziyang Huang "); From patchwork Sun Jan 21 12:42:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Huang X-Patchwork-Id: 13524559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55DF4C47422 for ; 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Sun, 21 Jan 2024 12:43:20 +0000 Received: from TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0]) by TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0%7]) with mapi id 15.20.7181.019; Sun, 21 Jan 2024 12:43:20 +0000 From: Ziyang Huang To: mcoquelin.stm32@gmail.com Cc: alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, Ziyang Huang Subject: [PATCH 4/8] clk: qcom: gcc-ipq5018: correct gcc_gmac0_sys_clk reg Date: Sun, 21 Jan 2024 20:42:33 +0800 Message-ID: X-Mailer: git-send-email 2.40.1 In-Reply-To: References: X-TMN: [ww+btxZZBQOC2wakAs5+sapyWmbpq5X6IyU85vlcnhJasKmaU1aNdw==] X-ClientProxiedBy: PH8PR21CA0009.namprd21.prod.outlook.com (2603:10b6:510:2ce::26) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <20240121124237.3328702-4-hzyitc@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|OSQPR01MB6119:EE_ X-MS-Office365-Filtering-Correlation-Id: 0b4a16b5-8d74-4bac-8578-08dc1a7e8c1f X-Microsoft-Antispam: BCL:0; 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X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Signed-off-by: Ziyang Huang --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 19dc2b71cacf..3ba2fd53262d 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -1756,7 +1756,7 @@ static struct clk_branch gcc_gmac0_sys_clk = { .halt_check = BRANCH_HALT_DELAY, .halt_bit = 31, .clkr = { - .enable_reg = 0x683190, + .enable_reg = 0x68190, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "gcc_gmac0_sys_clk", From patchwork Sun Jan 21 12:42:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ziyang Huang X-Patchwork-Id: 13524560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B46BAC47422 for ; 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Sun, 21 Jan 2024 12:43:30 +0000 Received: from TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0]) by TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0%7]) with mapi id 15.20.7181.019; Sun, 21 Jan 2024 12:43:30 +0000 From: Ziyang Huang To: mcoquelin.stm32@gmail.com Cc: alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, Praveenkumar I , Abhishek Sahu , Ziyang Huang Subject: [PATCH 5/8] clk: qcom: support for duplicate freq in RCG2 freq table Date: Sun, 21 Jan 2024 20:42:34 +0800 Message-ID: X-Mailer: git-send-email 2.40.1 In-Reply-To: References: X-TMN: [eYikeWM2GM7qK/WtHoB+cI/jJ5r4GrkIov4uetos/j1E8TsBXaboEw==] X-ClientProxiedBy: PH8PR21CA0009.namprd21.prod.outlook.com (2603:10b6:510:2ce::26) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <20240121124237.3328702-5-hzyitc@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|OSQPR01MB6119:EE_ X-MS-Office365-Filtering-Correlation-Id: 1605bcff-1402-43c9-7ccb-08dc1a7e9247 X-Microsoft-Antispam: BCL:0; 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If CLK_SET_RATE_PARENT flag is set then the set_rate request will go to its parent otherwise the clock framework will configure pre-div, m and n according to the returned frequency table entry. In this case, it is assuming that parent clock will run in the same frequency with which pre-div, m and n has been derived. But it may be possible that the parent clock supports multiple frequency and the same frequency can be derived with different pre-div, m and n values depending upon current frequency. Also, the same frequency can be derived from different parent sources and currently there is no option for having duplicate frequencies in frequency table and choosing the best one according to current rate. Now this patch adds the support for having duplicate frequencies in frequency table. During set rate, it will compare the actual rate for each entry with requested rate and will select the best entry in which the difference will be less. The existing functionality won’t be affected with this code change since this code change will hit only if frequency table has duplicate values. Change-Id: I97d9e1b55d8f3ee095f6f01729af527ba90e50e5 Signed-off-by: Abhishek Sahu (cherry picked from commit 775e7d3b69ffc97afb5bd5a6c9c423f2f4d8a0b2) Signed-off-by: Praveenkumar I Change-Id: If10193fc79a3c1375ab73597813745ff1f4df0ad Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/6dfb368bae130bee58e00ddf8330b55066e1c8c5 Signed-off-by: Ziyang Huang --- drivers/clk/qcom/clk-rcg2.c | 86 ++++++++++++++++++++++++++++--------- 1 file changed, 66 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index e22baf3a7112..6141e4991fbc 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -209,26 +209,82 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) return __clk_rcg2_recalc_rate(hw, parent_rate, cfg); } -static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, - struct clk_rate_request *req, - enum freq_policy policy) +static const struct freq_tbl * +clk_rcg2_find_best_freq(struct clk_hw *hw, const struct freq_tbl *f, + unsigned long rate, enum freq_policy policy) { - unsigned long clk_flags, rate = req->rate; - struct clk_hw *p; + unsigned long req_rate = rate, best = 0, freq; struct clk_rcg2 *rcg = to_clk_rcg2(hw); int index; + u64 tmp; + const struct freq_tbl *best_ftable = NULL; switch (policy) { case FLOOR: - f = qcom_find_freq_floor(f, rate); + f = qcom_find_freq_floor(rcg->freq_tbl, rate); break; case CEIL: - f = qcom_find_freq(f, rate); + f = qcom_find_freq(rcg->freq_tbl, rate); break; default: - return -EINVAL; + return best_ftable; } + /* + * Check for duplicate frequencies in frequency table if + * CLK_SET_RATE_PARENT flag is not set + */ + if (!f || (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) || + ((f->freq && (f + 1)->freq != f->freq))) + return f; + + /* + * Check for all the duplicate entries in frequency table and + * calculate the actual rate from current parent rate with each + * entries pre_div, m and n values. The entry, which gives the + * minimum difference in requested rate and actual rate, will be + * selected as the best one. + */ + for (freq = f->freq; freq == f->freq; f++) { + index = qcom_find_src_index(hw, rcg->parent_map, f->src); + if (index < 0) + continue; + + rate = clk_hw_get_rate(clk_hw_get_parent_by_index(hw, index)); + if (rcg->hid_width && f->pre_div) { + rate *= 2; + rate /= f->pre_div + 1; + } + + if (rcg->mnd_width && f->n) { + tmp = rate; + tmp = tmp * f->n; + do_div(tmp, f->m); + rate = tmp; + } + + if (abs(req_rate - rate) < abs(best - rate)) { + best_ftable = f; + best = rate; + + if (req_rate == rate) + break; + } + } + + return best_ftable; +} + +static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, + struct clk_rate_request *req, + enum freq_policy policy) +{ + unsigned long clk_flags, rate = req->rate; + struct clk_hw *p; + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + int index; + + f = clk_rcg2_find_best_freq(hw, f, rate, policy); if (!f) return -EINVAL; @@ -360,17 +416,7 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f; - switch (policy) { - case FLOOR: - f = qcom_find_freq_floor(rcg->freq_tbl, rate); - break; - case CEIL: - f = qcom_find_freq(rcg->freq_tbl, rate); - break; - default: - return -EINVAL; - } - + f = clk_rcg2_find_best_freq(hw, rcg->freq_tbl, rate, policy); if (!f) return -EINVAL; @@ -1032,7 +1078,7 @@ static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f; - f = qcom_find_freq(rcg->freq_tbl, rate); + f = clk_rcg2_find_best_freq(hw, rcg->freq_tbl, rate, CEIL); if (!f) return -EINVAL; From patchwork Sun Jan 21 12:42:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Huang X-Patchwork-Id: 13524561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3278DC47DB7 for ; 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Sun, 21 Jan 2024 12:43:36 +0000 Received: from TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0]) by TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0%7]) with mapi id 15.20.7181.019; Sun, 21 Jan 2024 12:43:36 +0000 From: Ziyang Huang To: mcoquelin.stm32@gmail.com Cc: alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, Ziyang Huang Subject: [PATCH 6/8] net: mdio: ipq4019: support reset control Date: Sun, 21 Jan 2024 20:42:35 +0800 Message-ID: X-Mailer: git-send-email 2.40.1 In-Reply-To: References: X-TMN: [6eQm7VelkNsE2KT1NBJq/W242KG1dVYWwqvIXC+ZwKZnQo77a+eDuw==] X-ClientProxiedBy: PH8PR21CA0009.namprd21.prod.outlook.com (2603:10b6:510:2ce::26) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <20240121124237.3328702-6-hzyitc@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|OSQPR01MB6119:EE_ X-MS-Office365-Filtering-Correlation-Id: 9af9ed1d-9519-4440-ef77-08dc1a7e95e6 X-Microsoft-Antispam: BCL:0; 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void __iomem *eth_ldo_rdy; + struct reset_control *rst; struct clk *mdio_clk; }; @@ -219,6 +221,10 @@ static int ipq_mdio_reset(struct mii_bus *bus) fsleep(IPQ_PHY_SET_DELAY_US); } + ret = reset_control_reset(priv->rst); + if (ret) + return ret; + /* Configure MDIO clock source frequency if clock is specified in the device tree */ ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); if (ret) @@ -248,6 +254,10 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->membase)) return PTR_ERR(priv->membase); + priv->rst = devm_reset_control_array_get_optional_exclusive(&pdev->dev); + if (IS_ERR(priv->rst)) + return PTR_ERR(priv->rst); + priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk"); if (IS_ERR(priv->mdio_clk)) return PTR_ERR(priv->mdio_clk); From patchwork Sun Jan 21 12:42:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Huang X-Patchwork-Id: 13524562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D9F7C47DAF for ; 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X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Signed-off-by: Ziyang Huang --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 120 +++++++++++++++++++++++++- 1 file changed, 116 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index e502a3ecf4b7..b36e5c2136b7 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -94,6 +94,63 @@ soc: soc@0 { #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + mdio0: mdio@88000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio"; + reg = <0x88000 0x64>; + resets = <&gcc GCC_GEPHY_MDC_SW_ARES>, + <&gcc GCC_GEPHY_DSP_HW_ARES>; + clocks = <&gcc GCC_MDIO0_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + + gephy: ethernet-phy@7 { + #clock-cells = <1>; + reg = <7>; + resets = <&gcc GCC_GEPHY_BCR>, + <&gcc GCC_GEPHY_RX_ARES>, + <&gcc GCC_GEPHY_TX_ARES>; + clocks = <&gcc GCC_GEPHY_RX_CLK>, + <&gcc GCC_GEPHY_TX_CLK>; + }; + }; + + mdio1: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq5018-mdio"; + reg = <0x90000 0x64>; + clocks = <&gcc GCC_MDIO1_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + + uniphy0: eth-uniphy@98000 { + compatible = "qcom,ipq5018-eth-uniphy"; + #clock-cells = <1>; + #phy-cells = <0>; + reg = <0x98000 0x800>, + <0x9b000 0x800>, + <0x19475c4 0x4>; + reg-names = "uniphy", + "cmn", + "tcsr"; + clocks = <&gcc GCC_CMN_BLK_AHB_CLK>, + <&gcc GCC_CMN_BLK_SYS_CLK>, + <&gcc GCC_UNIPHY_AHB_CLK>, + <&gcc GCC_UNIPHY_SYS_CLK>, + <&gcc GCC_UNIPHY_RX_CLK>, + <&gcc GCC_UNIPHY_TX_CLK>; + resets = <&gcc GCC_UNIPHY_BCR>, + <&gcc GCC_UNIPHY_AHB_ARES>, + <&gcc GCC_UNIPHY_SYS_ARES>, + <&gcc GCC_UNIPHY_RX_ARES>, + <&gcc GCC_UNIPHY_TX_ARES>; + + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -120,10 +177,10 @@ gcc: clock-controller@1800000 { <0>, <0>, <0>, - <0>, - <0>, - <0>, - <0>; + <&gephy 0>, + <&gephy 1>, + <&uniphy0 0>, + <&uniphy0 1>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -244,6 +301,61 @@ frame@b128000 { status = "disabled"; }; }; + + gmac0: ethernet@39c00000 { + compatible = "qcom,ipq50xx-gmac", "snps,dwmac"; + reg = <0x39C00000 0x10000>; + clocks = <&gcc GCC_GMAC0_SYS_CLK>, + <&gcc GCC_GMAC0_CFG_CLK>, + <&gcc GCC_SNOC_GMAC0_AHB_CLK>, + <&gcc GCC_SNOC_GMAC0_AXI_CLK>, + <&gcc GCC_GMAC0_RX_CLK>, + <&gcc GCC_GMAC0_TX_CLK>, + <&gcc GCC_GMAC0_PTP_CLK>; + clock-names = "sys", + "cfg", + "ahb", + "axi", + "rx", + "tx", + "ptp"; + resets = <&gcc GCC_GMAC0_BCR>; + interrupts = ; + interrupt-names = "macirq"; + + phy-handle = <&gephy>; + phy-mode = "sgmii"; + + status = "disabled"; + }; + + gmac1: ethernet@39d00000 { + compatible = "qcom,ipq50xx-gmac", "snps,dwmac"; + reg = <0x39D00000 0x10000>; + reg-names = "stmmaceth"; + clocks = <&gcc GCC_GMAC1_SYS_CLK>, + <&gcc GCC_GMAC1_CFG_CLK>, + <&gcc GCC_SNOC_GMAC1_AHB_CLK>, + <&gcc GCC_SNOC_GMAC1_AXI_CLK>, + <&gcc GCC_GMAC1_RX_CLK>, + <&gcc GCC_GMAC1_TX_CLK>, + <&gcc GCC_GMAC1_PTP_CLK>; + clock-names = "sys", + "cfg", + "ahb", + "axi", + "rx", + "tx", + "ptp"; + resets = <&gcc GCC_GMAC1_BCR>; + interrupts = ; + interrupt-names = "macirq"; + + phys = <&uniphy0>; + phy-names = "uniphy"; + + status = "disabled"; + }; }; timer { From patchwork Sun Jan 21 12:42:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Huang X-Patchwork-Id: 13524563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2084C47422 for ; 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Sun, 21 Jan 2024 12:43:49 +0000 Received: from TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0]) by TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::bcb7:50f4:7a16:4ec0%7]) with mapi id 15.20.7181.019; Sun, 21 Jan 2024 12:43:49 +0000 From: Ziyang Huang To: mcoquelin.stm32@gmail.com Cc: alexandre.torgue@foss.st.com, richardcochran@gmail.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, Ziyang Huang Subject: [PATCH 8/8] arm64: dts: qcom: ipq5018-rdp432-c2: enable ethernet support Date: Sun, 21 Jan 2024 20:42:37 +0800 Message-ID: X-Mailer: git-send-email 2.40.1 In-Reply-To: References: X-TMN: [2qElDWZdksYkyOHEY7OFc81AJPO6++sP9sL6QwoTbGpWTEt6sYOgLg==] X-ClientProxiedBy: PH8PR21CA0009.namprd21.prod.outlook.com (2603:10b6:510:2ce::26) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <20240121124237.3328702-8-hzyitc@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|OSQPR01MB6119:EE_ X-MS-Office365-Filtering-Correlation-Id: 5de4b3fd-4367-43b9-74b8-08dc1a7e9d42 X-Microsoft-Antispam: BCL:0; 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X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Signed-off-by: Ziyang Huang --- .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index e636a1cb9b77..074b78d7939c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -15,6 +15,9 @@ / { aliases { serial0 = &blsp1_uart1; + + ethernet0 = &gmac0; + ethernet1 = &gmac1; }; chosen { @@ -43,6 +46,22 @@ &sleep_clk { }; &tlmm { + mdio1_pins: mdio1_pins { + mdc { + pins = "gpio36"; + function = "mdc"; + drive-strength = <8>; + bias-pull-up; + }; + + mdio { + pins = "gpio37"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio9"; @@ -70,3 +89,36 @@ data-pins { &xo_board_clk { clock-frequency = <24000000>; }; + +&mdio0 { + status = "ok"; +}; + +&mdio1 { + pinctrl-0 = <&mdio1_pins>; + pinctrl-names = "default"; + status = "ok"; + + reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + + qca8081: ethernet-phy@28 { + reg = <28>; + }; +}; + +&uniphy0 { + mode = ; + clkout-frequency = ; + clkout-drive-strength = ; + status = "ok"; +}; + +&gmac0 { + status = "ok"; +}; + +&gmac1 { + phy-handle = <&qca8081>; + phy-mode = "sgmii"; + status = "ok"; +};