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[92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:26 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/9] dt-bindings: watchdog: samsung-wdt: deprecate samsung,syscon-phandle Date: Mon, 22 Jan 2024 22:57:02 +0000 Message-ID: <20240122225710.1952066-2-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The watchdog driver no longer requires a phandle to obtain a regmap to the PMU registers. So mark this as deprecated. Signed-off-by: Peter Griffin --- .../devicetree/bindings/watchdog/samsung-wdt.yaml | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index 77a5ddd0426e..3970d6bf8576 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -56,6 +56,7 @@ properties: description: Phandle to the PMU system controller node (in case of Exynos5250, Exynos5420, Exynos7, Exynos850 and gs101). + deprecated: true required: - compatible @@ -66,20 +67,6 @@ required: allOf: - $ref: watchdog.yaml# - - if: - properties: - compatible: - contains: - enum: - - google,gs101-wdt - - samsung,exynos5250-wdt - - samsung,exynos5420-wdt - - samsung,exynos7-wdt - - samsung,exynos850-wdt - - samsung,exynosautov9-wdt - then: - required: - - samsung,syscon-phandle - if: properties: compatible: From patchwork Mon Jan 22 22:57:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13526386 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3707F1F5FA for ; Mon, 22 Jan 2024 22:57:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964253; cv=none; b=W1479gJBmYPWNjsxG0Z0zgIFzpKGE/FR6naOLweUtqEUV297xX5oEIrxlFqrxNabDkKTD+RKpmoITFw+RC5ilnQ1enNqHIQ4cQj9PsSDqNmRNWl4psCbJapl5DgLaaY1kjc49GB+6vgvzJBt02c5WD2+ZqS5qOezaottwML+lHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964253; c=relaxed/simple; bh=U1+KXcli4NL1ac1CPhNG+FdVI8hN+zTTVbZpOOz+6tY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s6RX8uCCU5VJG6w1wiG7WdgFZcOzUHvMjPz2M6nWmelugxfZ7CLevQDIuNlqNmGZ8F8Hu93o1G59d+q+MTsNCauJzZTBWW8Zl/96rez2nfkx6mPA5SIXFRJ+WutRtZJx0/1eLcnnKdQpmT6otIQ5uVyNQh3OpKFd7OrhPSad4bg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=T05qkwEC; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="T05qkwEC" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40e72a567eeso44839835e9.0 for ; Mon, 22 Jan 2024 14:57:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705964249; x=1706569049; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EkT1f8/auJS4w5tPSadT4tBL2vbp3PChzChd9rePwv0=; b=T05qkwECDeJbqNuo9xfac+xmo7BjyxF2yPrguHGFXqLAxfUAANrQK1lGpbckCqodx4 GbhxMI0Nk6jy5ai/7nISDDMelTVmelWdfewxX4kOAgW7bYmIXMwRQ8zu8wJqjBzD6w91 LasK5jyxIzHyC+CkHQaiFUiBALPowBPNIdxx+AtrmUu/KWBiLiKgBiH2HljZ5TTVW6n4 3+mEpWpnxdBATX6+eEYS799+MwUVQIPxfbHDj5O5cRWvH2bfa4F0peLEDSpeheHBznYV xG5qJDWm3EOWX8aHjSZNBI2FQZTTDcWXMQY+5Xz/053cz2Id7Nm3nbLzOFw3nFLYnhQf 5MgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705964249; x=1706569049; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EkT1f8/auJS4w5tPSadT4tBL2vbp3PChzChd9rePwv0=; b=QhaQeTGVNRRsLmTr0WEMyIDzo54Jy3etOZro6LqLMjCZpaY07C4JRCydhUHubhfKzj JIdkslSRkFyb60I8OxzbArd7840vH31l9Bxu5VOSeTYeOhBDx4prVN85VHwpHJL2Jl87 ZoC+9XBrLt2EJ2U2OYrY5G3MkDp7FVkq0gfRKW97IjEnMGlzGZ38/v6eDudk6NWRvCXz 5VnmOCsChnJA/n+Ugk7sULsXpJ26NasJTS96xt5QO7w0WPJDfLgVe+8+6Bae99WVejnK h/oF7IJQqJnLVD01AMGS6b9tCVS8NvUSchYIADHBiq/oQV6BQnH3pENWUUF+zXr+nzZZ xo8g== X-Gm-Message-State: AOJu0Yw61fa/EAmDxTUDR9WjkRtR5XraWM3Lw56pkZ/UpZq+P8kgC6Jk SL+CWtPUUGqLCRPHGEnu+vtfVdY/HSKHZhvdcZFw6b23G3rP6vMHqW7EH4yG27k= X-Google-Smtp-Source: AGHT+IHkc9S01pb4+H9jQwA2GpQSFpzYPum9UGXBQkktPuNZUGJVOV7WCzXUX8o5u0vmioR+ISGUrw== X-Received: by 2002:a05:600c:5250:b0:40e:6930:4c99 with SMTP id fc16-20020a05600c525000b0040e69304c99mr1381965wmb.113.1705964248744; Mon, 22 Jan 2024 14:57:28 -0800 (PST) Received: from gpeter-l.lan (host-92-18-76-30.as13285.net. [92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:28 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/9] soc: samsung: exynos-pmu: Add exynos_pmu_update/read/write APIs and SoC quirks Date: Mon, 22 Jan 2024 22:57:03 +0000 Message-ID: <20240122225710.1952066-3-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Newer Exynos SoCs have atomic set/clear bit hardware for PMU registers as these registers can be accessed by multiple masters. Some platforms also protect the PMU registers for security hardening reasons so they can't be written by normal world and are only write acessible in el3 via a SMC call. Add support for both of these usecases using SoC specific quirks that are determined from the DT compatible string. Drivers which need to read and write PMU registers should now use these new exynos_pmu_*() APIs instead of obtaining a regmap using syscon_regmap_lookup_by_phandle() Depending on the SoC specific quirks, the exynos_pmu_*() APIs will access the PMU register in the appropriate way. Signed-off-by: Peter Griffin --- drivers/soc/samsung/exynos-pmu.c | 209 ++++++++++++++++++++++++- drivers/soc/samsung/exynos-pmu.h | 4 + include/linux/soc/samsung/exynos-pmu.h | 28 ++++ 3 files changed, 234 insertions(+), 7 deletions(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index 250537d7cfd6..e9e933ede568 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -5,6 +5,7 @@ // // Exynos - CPU PMU(Power Management Unit) support +#include #include #include #include @@ -12,29 +13,204 @@ #include #include #include +#include #include #include #include "exynos-pmu.h" +/** + * DOC: Quirk flags for different Exynos PMU IP-cores + * + * This driver supports multiple Exynos based SoCs, each of which might have a + * different set of registers and features supported. + * + * Quirk flags described below serve the purpose of telling the driver about + * mentioned SoC traits, and can be specified in driver data for each particular + * supported device. + * + * %QUIRK_HAS_ATOMIC_BITSETHW: PMU IP has special atomic bit set/clear HW + * to protect against PMU registers being accessed from multiple bus masters. + * + * %QUIRK_PMU_ALIVE_WRITE_SEC: PMU registers are *not* write accesible from + * normal world. This is found on some SoCs as a security hardening measure. PMU + * registers on these SoCs can only be written via a SMC call and registers are + * checked by EL3 firmware against an allowlist before the write can procede. + * Note: This quirk should only be set for platforms whose el3 firmware + * implements the TENSOR_SMC_PMU_SEC_REG interface below. + */ + +#define QUIRK_HAS_ATOMIC_BITSETHW BIT(0) +#define QUIRK_PMU_ALIVE_WRITE_SEC BIT(1) + +#define PMUALIVE_MASK GENMASK(14, 0) + struct exynos_pmu_context { struct device *dev; const struct exynos_pmu_data *pmu_data; + struct regmap *pmureg; + void __iomem *pmu_base_addr; + phys_addr_t pmu_base_pa; + /* protect PMU reg atomic update operations */ + spinlock_t update_lock; }; -void __iomem *pmu_base_addr; static struct exynos_pmu_context *pmu_context; +/* + * Some SoCs are configured so that PMU_ALIVE registers can only be written + * from el3. As Linux needs to write some of these registers, the following + * SMC register read/write/read,write,modify interface is used. + * + * Note: This SMC interface is known to be implemented on gs101 and derivative + * SoCs. + */ +#define TENSOR_SMC_PMU_SEC_REG (0x82000504) +#define TENSOR_PMUREG_READ 0 +#define TENSOR_PMUREG_WRITE 1 +#define TENSOR_PMUREG_RMW 2 + +int set_priv_reg(phys_addr_t reg, u32 val) +{ + struct arm_smccc_res res; + + arm_smccc_smc(TENSOR_SMC_PMU_SEC_REG, + reg, + TENSOR_PMUREG_WRITE, + val, 0, 0, 0, 0, &res); + + if (res.a0) + pr_warn("%s(): SMC failed: %lu\n", __func__, res.a0); + + return (int)res.a0; +} + +int rmw_priv_reg(phys_addr_t reg, u32 mask, u32 val) +{ + struct arm_smccc_res res; + + arm_smccc_smc(TENSOR_SMC_PMU_SEC_REG, + reg, + TENSOR_PMUREG_RMW, + mask, val, 0, 0, 0, &res); + + if (res.a0) + pr_warn("%s(): SMC failed: %lu\n", __func__, res.a0); + + return (int)res.a0; +} + +/* + * For SoCs that have set/clear bit hardware (as indicated by + * QUIRK_HAS_ATOMIC_BITSETHW) this function can be used when + * the PMU register will be accessed by multiple masters. + * + * For example, to set bits 13:8 in PMU reg offset 0x3e80 + * exynos_pmu_set_bit_atomic(0x3e80, 0x3f00, 0x3f00); + * + * To clear bits 13:8 in PMU offset 0x3e80 + * exynos_pmu_set_bit_atomic(0x3e80, 0x0, 0x3f00); + */ +static inline void exynos_pmu_set_bit_atomic(unsigned int offset, + u32 val, u32 mask) +{ + unsigned long flags; + unsigned int i; + + spin_lock_irqsave(&pmu_context->update_lock, flags); + for (i = 0; i < 32; i++) { + if (mask & BIT(i)) { + if (val & BIT(i)) { + offset |= 0xc000; + pmu_raw_writel(i, offset); + } else { + offset |= 0x8000; + pmu_raw_writel(i, offset); + } + } + } + spin_unlock_irqrestore(&pmu_context->update_lock, flags); +} + +int exynos_pmu_update_bits(unsigned int offset, unsigned int mask, + unsigned int val) +{ + if (pmu_context->pmu_data && + pmu_context->pmu_data->quirks & QUIRK_PMU_ALIVE_WRITE_SEC) + return rmw_priv_reg(pmu_context->pmu_base_pa + offset, + mask, val); + + return regmap_update_bits(pmu_context->pmureg, offset, mask, val); +} +EXPORT_SYMBOL(exynos_pmu_update_bits); + void pmu_raw_writel(u32 val, u32 offset) { - writel_relaxed(val, pmu_base_addr + offset); + if (pmu_context->pmu_data && + pmu_context->pmu_data->quirks & QUIRK_PMU_ALIVE_WRITE_SEC) + return (void)set_priv_reg(pmu_context->pmu_base_pa + offset, + val); + + return writel_relaxed(val, pmu_context->pmu_base_addr + offset); } u32 pmu_raw_readl(u32 offset) { - return readl_relaxed(pmu_base_addr + offset); + return readl_relaxed(pmu_context->pmu_base_addr + offset); +} + +int exynos_pmu_read(unsigned int offset, unsigned int *val) +{ + if (!pmu_context) + return -ENODEV; + + /* + * For platforms that protect PMU registers they + * are still accessible to read from normal world + */ + return regmap_read(pmu_context->pmureg, offset, val); +} +EXPORT_SYMBOL(exynos_pmu_read); + +int exynos_pmu_write(unsigned int offset, unsigned int val) +{ + if (!pmu_context) + return -ENODEV; + + if (pmu_context->pmu_data && + pmu_context->pmu_data->quirks & QUIRK_PMU_ALIVE_WRITE_SEC) + return set_priv_reg(pmu_context->pmu_base_pa + offset, val); + + return regmap_write(pmu_context->pmureg, offset, val); +} +EXPORT_SYMBOL(exynos_pmu_write); + +int exynos_pmu_update(unsigned int offset, unsigned int mask, unsigned int val) +{ + int ret = 0; + + if (!pmu_context) + return -ENODEV; + + if (pmu_context->pmu_data && + pmu_context->pmu_data->quirks & QUIRK_HAS_ATOMIC_BITSETHW) { + /* + * Use atomic operations for PMU_ALIVE registers (offset 0~0x3FFF) + * as the target registers can be accessed by multiple masters. + */ + if (offset > PMUALIVE_MASK) + return exynos_pmu_update_bits(offset, mask, val); + + exynos_pmu_set_bit_atomic(offset, val, mask); + + } else { + return exynos_pmu_update_bits(offset, mask, val); + } + + return ret; } +EXPORT_SYMBOL(exynos_pmu_update); void exynos_sys_powerdown_conf(enum sys_powerdown mode) { @@ -75,11 +251,18 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) #define exynos_pmu_data_arm_ptr(data) NULL #endif +static const struct exynos_pmu_data gs101_pmu_data = { + .quirks = QUIRK_HAS_ATOMIC_BITSETHW | QUIRK_PMU_ALIVE_WRITE_SEC, +}; + /* * PMU platform driver and devicetree bindings. */ static const struct of_device_id exynos_pmu_of_device_ids[] = { { + .compatible = "google,gs101-pmu", + .data = &gs101_pmu_data, + }, { .compatible = "samsung,exynos3250-pmu", .data = exynos_pmu_data_arm_ptr(exynos3250_pmu_data), }, { @@ -125,18 +308,30 @@ EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap); static int exynos_pmu_probe(struct platform_device *pdev) { + struct resource *res; struct device *dev = &pdev->dev; int ret; - pmu_base_addr = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(pmu_base_addr)) - return PTR_ERR(pmu_base_addr); - pmu_context = devm_kzalloc(&pdev->dev, sizeof(struct exynos_pmu_context), GFP_KERNEL); if (!pmu_context) return -ENOMEM; + + pmu_context->pmu_base_addr = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pmu_context->pmu_base_addr)) + return PTR_ERR(pmu_context->pmu_base_addr); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + pmu_context->pmu_base_pa = res->start; + pmu_context->pmureg = exynos_get_pmu_regmap(); + if (IS_ERR(pmu_context->pmureg)) + return PTR_ERR(pmu_context->pmureg); + + spin_lock_init(&pmu_context->update_lock); pmu_context->dev = dev; pmu_context->pmu_data = of_device_get_match_data(dev); diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 1c652ffd79b4..570c6e4dc8c3 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -25,8 +25,12 @@ struct exynos_pmu_data { void (*pmu_init)(void); void (*powerdown_conf)(enum sys_powerdown); void (*powerdown_conf_extra)(enum sys_powerdown); + u32 quirks; }; +int set_priv_reg(phys_addr_t reg, u32 val); +int rmw_priv_reg(phys_addr_t reg, u32 mask, u32 val); + extern void __iomem *pmu_base_addr; #ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS diff --git a/include/linux/soc/samsung/exynos-pmu.h b/include/linux/soc/samsung/exynos-pmu.h index a4f5516cc956..2c5ce21fb00b 100644 --- a/include/linux/soc/samsung/exynos-pmu.h +++ b/include/linux/soc/samsung/exynos-pmu.h @@ -21,11 +21,39 @@ enum sys_powerdown { extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); #ifdef CONFIG_EXYNOS_PMU extern struct regmap *exynos_get_pmu_regmap(void); +extern int exynos_pmu_update_bits(unsigned int offset, unsigned int mask, + unsigned int val); +extern int exynos_pmu_update(unsigned int offset, unsigned int mask, + unsigned int val); +extern int exynos_pmu_write(unsigned int offset, unsigned int val); +extern int exynos_pmu_read(unsigned int offset, unsigned int *val); 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[92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:29 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 3/9] watchdog: s3c2410_wdt: update to use new exynos_pmu_*() apis Date: Mon, 22 Jan 2024 22:57:04 +0000 Message-ID: <20240122225710.1952066-4-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Instead of obtaining the PMU regmap directly use the new exynos_pmu_*() APIs. The exynos_pmu_ APIs allow support of newer Exynos SoCs that have atomic set/clear bit hardware and platforms where the PMU registers can only be accessed via SMC call. As all platforms that have PMU registers use these new APIs, remove the syscon regmap lookup code, as it is now redundant. Signed-off-by: Peter Griffin --- drivers/watchdog/Kconfig | 1 + drivers/watchdog/s3c2410_wdt.c | 25 +++++++++---------------- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 7d22051b15a2..b3e90e1ddf14 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -513,6 +513,7 @@ config S3C2410_WATCHDOG depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST select WATCHDOG_CORE select MFD_SYSCON if ARCH_EXYNOS + select EXYNOS_PMU help Watchdog timer block in the Samsung S3C64xx, S5Pv210 and Exynos SoCs. This will reboot the system when the timer expires with diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 349d30462c8c..fd3a9ce870a0 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -28,6 +28,8 @@ #include #include +#include + #define S3C2410_WTCON 0x00 #define S3C2410_WTDAT 0x04 #define S3C2410_WTCNT 0x08 @@ -187,7 +189,6 @@ struct s3c2410_wdt { struct watchdog_device wdt_device; struct notifier_block freq_transition; const struct s3c2410_wdt_variant *drv_data; - struct regmap *pmureg; }; static const struct s3c2410_wdt_variant drv_data_s3c2410 = { @@ -355,8 +356,8 @@ static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask) const u32 val = mask ? mask_val : 0; int ret; - ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg, - mask_val, val); + ret = exynos_pmu_update(wdt->drv_data->disable_reg, + mask_val, val); if (ret < 0) dev_err(wdt->dev, "failed to update reg(%d)\n", ret); @@ -370,8 +371,8 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) const u32 val = (mask ^ val_inv) ? mask_val : 0; int ret; - ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg, - mask_val, val); + ret = exynos_pmu_update(wdt->drv_data->mask_reset_reg, + mask_val, val); if (ret < 0) dev_err(wdt->dev, "failed to update reg(%d)\n", ret); @@ -384,8 +385,8 @@ static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) const u32 val = en ? mask_val : 0; int ret; - ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg, - mask_val, val); + ret = exynos_pmu_update(wdt->drv_data->cnt_en_reg, + mask_val, val); if (ret < 0) dev_err(wdt->dev, "failed to update reg(%d)\n", ret); @@ -617,7 +618,7 @@ static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT)) return 0; - ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); + ret = exynos_pmu_read(wdt->drv_data->rst_stat_reg, &rst_stat); if (ret) dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) @@ -698,14 +699,6 @@ static int s3c2410wdt_probe(struct platform_device *pdev) if (ret) return ret; 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[92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:30 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 4/9] arm64: dts: fsd: remove deprecated samsung,syscon-phandle Date: Mon, 22 Jan 2024 22:57:05 +0000 Message-ID: <20240122225710.1952066-5-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 samsung,syscon-phandle is no longer used by the Samsung watchdog driver to access PMU registers. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/tesla/fsd.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index aaffb50b8b60..9b55e44c1db0 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -625,7 +625,6 @@ watchdog_0: watchdog@100a0000 { compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; reg = <0x0 0x100a0000 0x0 0x100>; interrupts = ; - samsung,syscon-phandle = <&pmu_system_controller>; clocks = <&fin_pll>; clock-names = "watchdog"; }; @@ -634,7 +633,6 @@ watchdog_1: watchdog@100b0000 { compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; reg = <0x0 0x100b0000 0x0 0x100>; interrupts = ; - samsung,syscon-phandle = <&pmu_system_controller>; clocks = <&fin_pll>; clock-names = "watchdog"; }; @@ -643,7 +641,6 @@ watchdog_2: watchdog@100c0000 { compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; reg = <0x0 0x100c0000 0x0 0x100>; interrupts = ; - samsung,syscon-phandle = <&pmu_system_controller>; clocks = <&fin_pll>; clock-names = "watchdog"; }; From patchwork Mon Jan 22 22:57:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13526389 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2CEF405E3 for ; Mon, 22 Jan 2024 22:57:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964256; cv=none; b=WbK5uodEJm1SaniQOTAEJasL43HhtbmuvqB3vN/nLJgnnugapuYqAoZTIekswkcp22SQwHyxv2N+cC+36Owc7D2g/0D6yS7BK5GCr7Lc21kh7WSBKiJGWnJH0EJyGPUdUUpod+Uj6IKMuZJOiq2S9VGSK2M8q4LDG9jk0FMu0bo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964256; c=relaxed/simple; bh=NU25j/nRSRJjYdR9Xkbm95iBy1+9quhbyDaHdu07SNc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aVmLOWb19eLCderdUdjcxwvpaXfPvtSwXHPmeFfJq+Y1bDncws1SWJ9Ka8FSYuJeC+4rUODDwN+NBDphSrBqpjUxl51/x9mViDaeDlY4EJHO7sGcuZ4mEY1b+2Bjw0CVALLzHtogIuKFRZYkwVB+ddEZpdqIXkaitOV0ksLztXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=uQYLpdmd; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="uQYLpdmd" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-337cf4eabc9so3018279f8f.3 for ; Mon, 22 Jan 2024 14:57:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705964253; x=1706569053; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pJbJnRKpWToFu2q+V6O7FlsxtcgPK6P8cGRt1rv+n50=; b=uQYLpdmdMVOzzWipAtTQ459d+DbOM3ZuixH/tzo2gFJ4sj15tsIs6nlNHNcL5A7//7 yaxdYwtGdqQzmYqFqDZk9/h8y35ZiYcqFeeW0g8sQ2Aa3tYNaZBxOUYIAu4kpVZg9rga r33t3Cd7Yd1QoYs8tagh1vrX20KOYBzTs5kvW8X0RYV4jE2M+KPrSzIBLRy0/d3mHZeR GQ7ifuTLDJEWD8JW1/tTBdkriGHkBCpQ6qjbRrociOQjnYqB6t2cLiJpeH8v+BeW9OwD JRQPBBHa6pg2vcMa9IFaSyq25bbHpU1DgLlE5ikapiIA2htHyNi6lYf/CAmqCA/CdY5d R8AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705964253; x=1706569053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pJbJnRKpWToFu2q+V6O7FlsxtcgPK6P8cGRt1rv+n50=; b=E/nCQ6YD1hIIaDxuxYu4In1k7FRRKq8G9Hwc9kDQaFfBh6cRo94epGeBWaSJUzCyo2 My0GM+xJlzIyJWxB6Z1s7sZNf2eXMEYsFEiuJcbXpRhrhkUvA9ZnrI06LB6S9FQXlj7Z Q7LZoyV83PcBMyiuj7abicXD8WOmtrYEeAJdT5Zu1jNAOLaaVjhvOajneRGHRyDftEIx LZ6Up7A0Dpn9uj/krhE3hYGLp3iSYxryKgmnk07eRjSq4DcnxkyXYAVyEhUNsmvfSFQj nqKCaVpRdjjCJntl7LqGxG6W6HFx5roWGZfECYCFoLKTMrOGKd3xuvSauv8V8LGod0jm /ELw== X-Gm-Message-State: AOJu0Yw6XybPgNAcpcUtHje8Dtbfp5A8XeCkmWqh6L6thpZ4rwpw1WXo mhOooMuEI6wZ5q+qhHy9bh0MpTLpg2Ft2VwU/uIJRXcwIa3LhTyDmmH8xfsvLJo= X-Google-Smtp-Source: AGHT+IG/jFOxju1LtglICeFEljCYH82Da8abwgt9uhjEC3EDk+nmoQu4sACeu8Vd9SIMCqy6XTt4bg== X-Received: by 2002:a05:600c:ace:b0:40e:46b2:24da with SMTP id c14-20020a05600c0ace00b0040e46b224damr2627569wmr.71.1705964253325; Mon, 22 Jan 2024 14:57:33 -0800 (PST) Received: from gpeter-l.lan (host-92-18-76-30.as13285.net. [92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:32 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 5/9] arm64: dts: exynosautov9: remove deprecated samsung,syscon-phandle Date: Mon, 22 Jan 2024 22:57:06 +0000 Message-ID: <20240122225710.1952066-6-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 samsung,syscon-phandle is no longer used by the Samsung watchdog driver to access PMU registers. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index c871a2f49fda..94c8d68fe92c 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -1551,7 +1551,6 @@ watchdog_cl0: watchdog@10050000 { interrupts = ; clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>; clock-names = "watchdog", "watchdog_src"; - samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <0>; }; @@ -1561,7 +1560,6 @@ watchdog_cl1: watchdog@10060000 { interrupts = ; clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>; clock-names = "watchdog", "watchdog_src"; - samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <1>; }; From patchwork Mon Jan 22 22:57:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13526390 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA5E48CFF for ; Mon, 22 Jan 2024 22:57:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964258; cv=none; b=COJrzdjRtVwf5G7hBxP3LOKxc96/YFO13p2ZDDzM0iNcUdGPblNGh9XMI03vkxJSW7D7SCAjdAlxaju1X8I7FXPE0ToFs/wrOa0PVGysRZIuppZWJj0e91p3A4HlTHSlFt5YZUKlddE8V59hMcNw8w+r5N1mKB8v5xBVHFbhld0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964258; c=relaxed/simple; bh=ZgVtAIKrhtdCLGsKgWlIaERKd0KusdG4ZWad/DmmfvI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=diNgID8nVusf05LRkgXpVHXOI2mj+O8gUZzDGZnq1pQrmYJ2BtXkG1FY1+lfVQv3iexkSKdvKdCdCTX+/XoBBsKgxxGkzpjDOkQVSANg9hHCM+9/oth2vyd1MEHpAxt9E6F1QRXeHj5B/6mJCsuc5lmUCIVeRAg5/PxWcuJ5ppE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WQhmuVoa; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WQhmuVoa" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-40e880121efso41001105e9.3 for ; Mon, 22 Jan 2024 14:57:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705964255; x=1706569055; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7y+1O2dDRcam6iTMZXdaVDgBYCAnl5nZ5iJ12xvO9iQ=; b=WQhmuVoarWFIGtqtGwscjgHLusKzOTmo7CZPnJ3x6zaPkP+FRhKGGgvnR5v6gc9crx ZlVGVQ1k72+2OqS5KNyXOS3mhKQdTeUGTWgeT1KEnGud12Gr9TE0kQhJ6Ou5h+VJRt84 odcjzIkD4qenZk+nNiVFtlXMaGDHdJgi0VWk7McGLgoTNtZPzjjjyvL6kD43rAjV54Ro KyYYk50UdefbRF856JC5c2qnLORX1hqHoDoMUlhZ9zykgCDS5u77P49k3xSX/k3diMq0 JO+gJzS3KOnSjf8rnFh5CEHiG1S8zbUp7TkPbg40x+PN0CPyNqW3ZD/moSmqddDoB/1H g1Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705964255; x=1706569055; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7y+1O2dDRcam6iTMZXdaVDgBYCAnl5nZ5iJ12xvO9iQ=; b=SSmLQNMXWZ3myzTBLJFbkUgfXl5PtA7c/KGQoczXcYiIx4UWAhUoqq9nMKaTJRyhl4 yC/Wvr1ZzAuyVgDluba4GHnRk5IB2NAMXO27Lgigds6xukCyl9xs/mVwrZ3cqXOKvZjY eYPAbk+eCdSP8Wm7k9ICHCw9JqqffZg+sj8nfauYIAF2Zy41tVtkek7cRNttg+Y3uK8T Ow5nnnMcAdnmSH6rPh+YUw0cH403o7Uiq6BTi7h10naVXo75SYrElAE318UWeivR1hWI Kipp4e/pZUkON0hprzRNKA2N+T15hFzcnzuJP25inmAdlZvH+nXpkUmwbabHVUrku8i6 bniw== X-Gm-Message-State: AOJu0Yxfe+mT2ipbWq633iWVk96f7P+874UNvhlmeAPACOdDop/WYYHw sqLFCOjh3p/jYoE19Rlg5OLDhc64pCV0bdI0jzBfOG5l4ef3ektB0aUFvEOs23U= X-Google-Smtp-Source: AGHT+IHqRrOEHIHhSifFZN302yhKTakQXstI0NxfnOUmXlruuoJ4Ui4e3EJWHkPdJKGLM3ndNTcg/w== X-Received: by 2002:a05:600c:5107:b0:40e:4782:fea7 with SMTP id o7-20020a05600c510700b0040e4782fea7mr2785067wms.180.1705964255173; Mon, 22 Jan 2024 14:57:35 -0800 (PST) Received: from gpeter-l.lan (host-92-18-76-30.as13285.net. [92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:34 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 6/9] arm64: dts: exynos850: remove deprecated samsung,syscon-phandle Date: Mon, 22 Jan 2024 22:57:07 +0000 Message-ID: <20240122225710.1952066-7-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 samsung,syscon-phandle is no longer used by the Samsung watchdog driver to access PMU registers and is deprecated. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index da3f4a791e68..6d4789c77a1c 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -216,7 +216,6 @@ watchdog_cl0: watchdog@10050000 { interrupts = ; clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; clock-names = "watchdog", "watchdog_src"; - samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <0>; status = "disabled"; }; @@ -227,7 +226,6 @@ watchdog_cl1: watchdog@10060000 { interrupts = ; clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; clock-names = "watchdog", "watchdog_src"; - samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <1>; status = "disabled"; }; From patchwork Mon Jan 22 22:57:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13526391 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E72148CFF for ; Mon, 22 Jan 2024 22:57:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964260; cv=none; b=DgT59OkwdfDw1H9BKoGVWOly7M/huuF/GDU2vi8zwjdqUKQX+47wer+WYw8cf42VFXQTBhO+wxUkhBSPI4tBjxDZ05H/pFc0nLk2Q+S1ebGBBVn2Vc0xEv66XHbV7A9SNNhbcc3RWdfHaC72rPdRLOtCrH8ixi8DULEJTVphKgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964260; c=relaxed/simple; bh=VbkBWnzy+0UFddPvAXBKeoRNgIhOC3IP1F6/lPbA/gA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rN7nU4e/z9tqAw6Ft7qPccQ5ErdUBeA37FaaDD0qUTGrLQjOUmrT6jlDCMyDWTDfef2Qs+cW0mWr5zQRFyOUiSrlOKLvylsV5WoJf8HarHcR2OWlJcICBIcmFap+5wsGCCqfVG8VJRjbcUvQ5I74B32KDr4b+zNPG9DkY9OnT8U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WOnk8lb+; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WOnk8lb+" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-337d58942c9so3999414f8f.0 for ; Mon, 22 Jan 2024 14:57:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705964257; x=1706569057; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e6ViflgtGKoar4JoRupvo6UR3+8nq9fr7o9SkHHwUZY=; b=WOnk8lb+B85aeoOIuthPlyiCSOwnxdQ5+kTfxa72PIquEmDgDtBSC9UpqWBTxPSTQh 08j66f9IS8VxIEUXV9Sid87pId/9t2bYJ+kcLZ4uCPJP0vrQYba4wfO9WEgumANLmCUh 4nB6LqYI0A+WAULwntiyoOmSn9IqRmyQGBk1yjR9hMBKoTUqijiU0CDR5JGMbfxPYHng HQSPU+sj+1XfBabLG4FudjAo6xcfSSH2Mxg97OagYwB2bTbdP7ynL6FoYVnVidxFg1R3 b+P1bH1/82DFIbarP82nDHxXWH5Tp5pUO56fR7rURJt9DW9vLmOktHDYqQTD9jf2T+vL 0zuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705964257; x=1706569057; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e6ViflgtGKoar4JoRupvo6UR3+8nq9fr7o9SkHHwUZY=; b=uJhPPyTwrY1rDl2PoTuWkqXuXVwjoMTNDMljaqR/OSD2AHAP7qoayAQYWbljQ4btAU h0ndsgIYuAA93RgkoB2WdLWS8NxPaSOfZeAokbmnNpaWm7PVYMr3Skq9AvWtJ0G6DVXR gePmVR2G6/LRAx/yRlwGwVqKGmHnI2ImKOlPnGCR9Vwz8nPE2xdRZtsLqA88XQCPcP4n Q4Mdo2+jq+OTa4vMWkjnHB8cCXfvCjXe+iAOP6kFLDXnCHYo1tS5vfpFt/VDVuS3OfmQ Nm1vMF+KNLmmAYL0en77w+P0vlnVkY8EJ29RUHZfKFYKjJ3KXA8QRz+25HuUBocoXMXe JEEg== X-Gm-Message-State: AOJu0YwUj5AgAfwgZl1GSYmn6o171qVbaBTcuQgZelqJT4pZgnDqHOyH efATEYzaieubxSj68IpXXXQEAmfOX7NHJtYcY93hUnIuivNVfFhwetMxtjU5KAI= X-Google-Smtp-Source: AGHT+IHwPlPcC1gFMy2RUxu4+dzTot/pZ/X/gGnPYFqMXOZZ3nFzZdmylLHz87taKykx7APs0vxeGw== X-Received: by 2002:a05:600c:358a:b0:40e:93b4:25ef with SMTP id p10-20020a05600c358a00b0040e93b425efmr2798923wmq.26.1705964256708; Mon, 22 Jan 2024 14:57:36 -0800 (PST) Received: from gpeter-l.lan (host-92-18-76-30.as13285.net. [92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:35 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 7/9] arm64: dts: exynos7: remove deprecated samsung,syscon-phandle Date: Mon, 22 Jan 2024 22:57:08 +0000 Message-ID: <20240122225710.1952066-8-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 samsung,syscon-phandle is no longer used by the Samsung watchdog driver to access PMU registers. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 9cb6bd61262e..347c346e3cfb 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -555,7 +555,6 @@ watchdog: watchdog@101d0000 { interrupts = ; clocks = <&clock_peris PCLK_WDT>; clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; From patchwork Mon Jan 22 22:57:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13526392 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B01E24A9BC for ; Mon, 22 Jan 2024 22:57:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964261; cv=none; b=MFmae5IhXTRsU2qRK5e/MzMOfSoKZEHChqby33j4xjyiPmgO7UIUfNqVM58K/r2oyvAcirinZBLNrHr+kF9gypc1khN56bc2okNQEtXeBVP1vFVcDm3rs1DnjY6FmokuqFa+G0KOV7k2pEIa4BqATl/pLlrgvrU2y4LXuuplezk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964261; c=relaxed/simple; bh=t8ZhB9Hu7K4Ql69piBPtPrEhaMrRJa2GJ7YXvafwt4A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kUKfsSeUzCuZ93SWpNlVy8W7sX+EupVfGTjTiywDipwZnPjPFeN8Gns8E6kKgJ5/L9tDbDmRstYt5bsAeMNIMcTZ0D2JF3PxM7C0wSOjXy9bUSUrkUJkOTn/uXdo2SNC/2zqKWOELgrs10YqcYCOWSXF1Ja5hr/JsCFh97q1Ixo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PqEfn9aQ; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PqEfn9aQ" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-40ea5654271so26721235e9.0 for ; Mon, 22 Jan 2024 14:57:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705964258; x=1706569058; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9+yXcHZUiMblwUqkt8towiLq/bcfaAns/f7tUicypCM=; b=PqEfn9aQMDjMpVjxcwU3m06SInZctx95KFmBTKBsntncoscyHDc2lliCVayNpxOYQQ SnUEnO6h/F9bl26o4vmJUAbbewhFPTnJ5YybFJYUC83L0RUIswVo3MBNhhYt/fWyPlL+ HcyAhfzlNdTng9JeUiraWKSWJ1tbi//VRhnXxGc773QVcIxczQKJuHQfD/BgjGgnKMcn uVAYpVymfpBIRn5Kj6bbwowYemvkNzgaiRuzl0X/iJGbjrBN3ls8xOXcmIk60hgX/Eyq vB1sp/akhwPkY5bKsuA8zxAyxlqgLRbRFPIpHA6duuUl1Yw0vr24hJA86lbWCcxX90Wo lrKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705964258; x=1706569058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9+yXcHZUiMblwUqkt8towiLq/bcfaAns/f7tUicypCM=; b=mmni/FNzxOemAenTqXHr95UPn7dzKhNYY5rmEdbqOfGMPehc22F5jyyIdCRyHT45xT 01Rfw3TmnWEQvDhuPw+MLRjB5CxuwZVZaaStOpoYdG9NxFGn4OKumKwHFrShNLrdod7Y 36reOYHcnbFvxZq+pJ3WGT1bNdzIwU2vLyC3VTAbjbRXk8bMBAWD+MKDHB51Rq1nYcnY 2bM1Txwft16JrghZDDUyBMLS7PkUpoLZyy0HwmAuH6mko3V8VlbxXSQJJ9YAEc0bR1ot ZvKl7tX+N+ktRv8b0Q/CJYWtUlCSiQ3SizommwyLroFHtn3TA52UOKpm7VqV+Cxglnc4 zSCA== X-Gm-Message-State: AOJu0Yzw6jG+CUmcHw816UgQLewsnOhxlJWnbejIYbPbPlSvATmmHIgl H/hSlLOUSTTZf5gbR16HrzJiBsqlLeRDduoZ1UBRElUslHBnntT5E0TyTfraLOU= X-Google-Smtp-Source: AGHT+IGTxTra3oeT53FfIH97Y2Gx41002Oxx5G+brDmtK77zTRluoeyF5o89lKBl/s6gRCsv7yvONw== X-Received: by 2002:a05:600c:1ca6:b0:40e:b0a1:b96e with SMTP id k38-20020a05600c1ca600b0040eb0a1b96emr676113wms.69.1705964258092; Mon, 22 Jan 2024 14:57:38 -0800 (PST) Received: from gpeter-l.lan (host-92-18-76-30.as13285.net. [92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:37 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 8/9] ARM: dts: samsung: exynos4: remove deprecated samsung,syscon-phandle Date: Mon, 22 Jan 2024 22:57:09 +0000 Message-ID: <20240122225710.1952066-9-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 samsung,syscon-phandle is no longer used by the Samsung watchdog driver to access PMU registers. Signed-off-by: Peter Griffin --- arch/arm/boot/dts/samsung/exynos4x12.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/exynos4x12.dtsi b/arch/arm/boot/dts/samsung/exynos4x12.dtsi index b4b5e769145b..0fea32616c89 100644 --- a/arch/arm/boot/dts/samsung/exynos4x12.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4x12.dtsi @@ -311,7 +311,6 @@ watchdog: watchdog@10060000 { interrupts = ; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; }; adc: adc@126c0000 { From patchwork Mon Jan 22 22:57:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13526393 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D8DA4A991 for ; Mon, 22 Jan 2024 22:57:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964263; cv=none; b=WWOSPkk1beF72RbB6i9TVLACsmFVODv3jQgHPYF7V6pPCV1jR90H34v58U2F/Scs8foqLNjy6ezhasucVDWxwVkXK0O/cSX9DDuoZEpBn+1p++G1nJcDHp28s3Ue+izAwuQxJykuonjtxUjJPIteX4Xt/YzqHGM0bBK13ItDIqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705964263; c=relaxed/simple; bh=6Fww45r8KMq9qH9gjFBGszYrLznUeDKKB4S+eDk2dqU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IEjnGDnRVLLx6JnGE8Xgv5Iur7kU4yWNlNWF3UP15/C8ykUNxkGy4R1pwKGHi/ZIBFYic7J6FByt8saI/uW+riDZI3b0JNamDijCgxOOgnpxINDlvk1RBZSgkM3CNEYsbU7t3SWOVQnl7ifESExajXpZFcamoRlltIEp0RrABGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=jKiFJ1GC; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jKiFJ1GC" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-40e80046264so47533615e9.0 for ; Mon, 22 Jan 2024 14:57:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705964260; x=1706569060; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yR0AO5T3Lm52GetAuhWGDlBbvPmAefipWgZrjsJSJcM=; b=jKiFJ1GCKKlFtDaECgZa64YK1ExR9aWypvp9vvl5lhUd3K49tl7R+MojlpME9pL3kq kw8ZdngSy98q2b2gXYSYMe8q27mIlvuHx6AuErBItlaEVq7tNhQDYianBmVG3OqxIaBw gQ9G1Ls1UhJ0gP25eqJT5lh2JyYYXJTcdb8AC1aIzgfHb78kaIhG4CP+J8lojdYa7hkP UhO6PqcWlXyAzRb68oBZfnI5SOC582eMaQ8GRL06xtO7EgB2Urtv70hFKDsAKHnURPM0 JO2ahBDkOViF8pBzCm0/tBNkketXwBEvDzynQpYUCC3DM+vnmUDQokXnaCUYU8UdLxlv CdsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705964260; x=1706569060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yR0AO5T3Lm52GetAuhWGDlBbvPmAefipWgZrjsJSJcM=; b=oKY/dp35sHoB3j1+aUMPji33uAzx3Xa051XQHlps3YqYrVEHuVkraNQUboC+O868L1 5IM2gett7yTf6WFtFBwh92Do/+8KDHnWPTSA3x5idX++E6LalFttWkW1j0o2kLIVZYFS lpWzEYGHcZViJXHtTxTWv8SQNl3dZ0pDBggignnKbFLrJrrXzw2QERPxnfPmgqrQC9fW MTlH6o1zK7++afl7jaEuFDwOpge2KK1tLAYNkXSqKLYCvC9vxc3JZrsXZMqxopNTaxQv WToHhH2FNd5UMO3BoumEjtmHshUn2lfkonO6wTUyeH4OC8u+JG180EUPbp4lDTX9MZkS +Wvg== X-Gm-Message-State: AOJu0Yxlp3HRfsucyjVr75NTPIIu34AkDqZNXON4nHaCWdUYPmU5mWYK cgHTwM4g1I3dq9Vs4VZGo5QzHOAOla7LefvNDAfN2a4yjazC0EQiX6UryRFF6kQ= X-Google-Smtp-Source: AGHT+IE/3oSYmQaHmUVIEZrmPeRaKj7ezaMnrpX2IRhfyS/TY5XiBAOhqPClwNkExF4LwyWJ4DWvjA== X-Received: by 2002:a05:600c:a43:b0:40e:62aa:fa7b with SMTP id c3-20020a05600c0a4300b0040e62aafa7bmr2887046wmq.111.1705964260529; Mon, 22 Jan 2024 14:57:40 -0800 (PST) Received: from gpeter-l.lan (host-92-18-76-30.as13285.net. [92.18.76.30]) by smtp.gmail.com with ESMTPSA id fa26-20020a05600c519a00b0040e89ff10f5sm19776847wmb.1.2024.01.22.14.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 14:57:38 -0800 (PST) From: Peter Griffin To: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, semen.protsenko@linaro.org Cc: kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 9/9] ARM: dts: exynos5250: remove deprecated samsung,syscon-phandle Date: Mon, 22 Jan 2024 22:57:10 +0000 Message-ID: <20240122225710.1952066-10-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240122225710.1952066-1-peter.griffin@linaro.org> References: <20240122225710.1952066-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 samsung,syscon-phandle is no longer used by the Samsung watchdog driver to access PMU registers. Signed-off-by: Peter Griffin --- arch/arm/boot/dts/samsung/exynos5250.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/exynos5250.dtsi b/arch/arm/boot/dts/samsung/exynos5250.dtsi index 99c84bebf25a..2bbeb0f0d898 100644 --- a/arch/arm/boot/dts/samsung/exynos5250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250.dtsi @@ -312,7 +312,6 @@ watchdog@101d0000 { interrupts = ; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; }; mfc: codec@11000000 {