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Tue, 23 Jan 2024 23:36:48 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.36.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:36:47 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:29 +0530 Subject: [PATCH 01/14] dt-bindings: phy: qcom,ipq8074-qmp-pcie: Drop PCIE_AUX_CLK from pcie_phy node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-1-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This clock is only required by the PCIe controller. Hence drop it from the binding. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index 634cec5d57ea..a953ac197dfd 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -25,11 +25,10 @@ properties: - description: serdes clocks: - maxItems: 3 + maxItems: 2 clock-names: items: - - const: aux - const: cfg_ahb - const: pipe @@ -72,11 +71,9 @@ examples: compatible = "qcom,ipq6018-qmp-pcie-phy"; reg = <0x00084000 0x1000>; - clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, + clocks = <&gcc GCC_PCIE0_AHB_CLK>, <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "pipe"; clock-output-names = "gcc_pcie0_pipe_clk_src"; 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Tue, 23 Jan 2024 23:36:53 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.36.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:36:53 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:30 +0530 Subject: [PATCH 02/14] arm64: dts: qcom: ipq6018: Drop PCIE_AUX_CLK from pcie_phy node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-2-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=979; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=fGj8Hc8YGkorO50XWw23uE3LCV1avN5lQsXZGvyanM8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4CGTLW5PHE4v+QOjUwEzMEiiZ5MfA5DaNcj cyvMk7JDkGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+AgAKCRBVnxHm/pHO 9fWvB/42xwjITFqhAyVbIdl55fGwYHKR5rjdxAep68tNBpd/TDx47zwOB4CQorP44+PsGLFCCuJ Kd+miwAqOtGDcUbCdlmEtGByRdfJ4lYIJSThJHw+8cZMHdJfPOTbQgQx72cRm21eTxP62gerfNU ghiEAGHcO4Cn7M0s4yznO6JUcBxCJJh2ZvD0Xrq1pMZXtErnpGMvMTxcI2qlSzVHLqCFvfUVViK 1lMyaKbezsLE8Erot6tjnO8oqu+s8kQL2Fz/eSWOPxygbqdJhwiBM5sfhFSJjeu91I3ZFhfE7Jv 1SRvB5M7rigAG/cuuo3CWLPvKtwZAMZt/sdlvK8ka2s6b+m6 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy node. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 5e1277fea725..1767e5abd76d 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -283,11 +283,9 @@ pcie_phy: phy@84000 { reg = <0x0 0x00084000 0x0 0x1000>; status = "disabled"; - clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, + clocks = <&gcc GCC_PCIE0_AHB_CLK>, <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "pipe"; clock-output-names = "gcc_pcie0_pipe_clk_src"; From patchwork Wed Jan 24 07:36:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13528702 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4C991759E for ; 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Tue, 23 Jan 2024 23:36:59 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:36:58 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:31 +0530 Subject: [PATCH 03/14] arm64: dts: qcom: ipq8074: Drop PCIE_AUX_CLK from pcie_phy nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-3-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index cf295bed3299..6ae6833e8969 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -201,11 +201,9 @@ pcie_qmp0: phy@84000 { compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; reg = <0x00084000 0x1000>; - clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, + clocks = <&gcc GCC_PCIE0_AHB_CLK>, <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "pipe"; clock-output-names = "pcie20_phy0_pipe_clk"; @@ -224,11 +222,9 @@ pcie_qmp1: phy@8e000 { compatible = "qcom,ipq8074-qmp-pcie-phy"; reg = <0x0008e000 0x1000>; - clocks = <&gcc GCC_PCIE1_AUX_CLK>, - <&gcc GCC_PCIE1_AHB_CLK>, + clocks = <&gcc GCC_PCIE1_AHB_CLK>, <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "pipe"; 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a=openpgp-sha256; l=6248; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=FUkkiV+2vDk+h8Fu4sCklCuzOARyg+ribP0i686xTfw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4DHLbLRu4/rLPOQs1IQsAM94Al1MnHSEL/G wX5JYbKC+uJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+AwAKCRBVnxHm/pHO 9V8RB/4lFYgeiPK6H+XbHF+JN0qyPo58sySDUBLf/BX0tIhPOzwJ6npj041l/nk5ec9gDfo+CaN tJN7h8IN6S8zqtRZrIy2JpUo2nctn7HEPPoeRuk2DLVh6rTPwxGcFa01gSuDGZ+ajytR+/0Z+wd 3ZtZXVcUaHBxJXJEznY8SUrE24e99wXNhCJBIvKGT9+b/6eo0RPdy9m+dDm6a0R4zbL8QQg60Mb e2WBw9v+QGK8KSPyaBupTaM4ycBHxC82P3Ryvw7RmdJTuym6QexRpM5wLaAqPrStq4S4NXq95Il 5yImBNw7KWTyGuutHy0uYxDMv9X3sk3SwQGY3o6cFYpOehfw X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On some platforms, PHY block requires PCIE_PHY_AUX_CLK to be used when the PCIe link enters L1SS state. On those platforms, a dedicated PCIE_PHY_AUX_CLK is available from GCC. Other than this, the PHY block doesn't require any other "aux" clock, including PCIE_AUX_CLK which only required by the PCIe controller. Historically, the DTs of the platforms requiring "aux" clock passed PCIE_PHY_AUX_CLK as "aux" clock. But over the period of time, platforms that do not require this dedicated "aux" clock mistakenly started passing the PCIE_AUX_CLK as the "aux" clock. More recently, SA8775P platform passed both "aux" (PCIE_AUX_CLK) and "phy_aux" (PCIE_PHY_AUX_CLK) clocks. So to clean up this mess, let's remove the newly introduced "phy_aux" clock and just use "aux" clock to supply PCIE_PHY_AUX_CLK for platforms that require it. For the platforms that do not require a dedicated "aux" clock, the clock is removed from DT. While at it, let's also define "qcom,sc7280-qmp-pcie-phy" compatible for SC7280 SoC which was earlier using the compatible "qcom,sm8250-qmp-gen3x2-pcie-phy" as the clock requirement has changed and also restructure the "clock-names" property for the affected platforms. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 79 ++++++++++++++-------- 1 file changed, 52 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 6c03f2d5fca3..2396a457f9c8 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy + - qcom,sc7280-qmp-pcie-phy - qcom,sc8180x-qmp-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy @@ -44,19 +45,12 @@ properties: maxItems: 2 clocks: - minItems: 5 - maxItems: 7 + minItems: 4 + maxItems: 6 clock-names: - minItems: 5 - items: - - const: aux - - const: cfg_ahb - - const: ref - - enum: [rchng, refgen] - - const: pipe - - const: pipediv2 - - const: phy_aux + minItems: 4 + maxItems: 6 power-domains: maxItems: 1 @@ -130,6 +124,28 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-qmp-pcie-phy + - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8650-qmp-gen3x2-pcie-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_ahb + - const: ref + - enum: [rchng, refgen] + - const: pipe + - if: properties: compatible: @@ -144,19 +160,19 @@ allOf: - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8350-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen3x2-pcie-phy - - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy then: properties: clocks: maxItems: 5 clock-names: - maxItems: 5 + items: + - const: aux + - const: cfg_ahb + - const: ref + - enum: [rchng, refgen] + - const: pipe - if: properties: @@ -169,9 +185,14 @@ allOf: then: properties: clocks: - minItems: 6 + maxItems: 5 clock-names: - minItems: 6 + items: + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: pipediv2 - if: properties: @@ -183,9 +204,15 @@ allOf: then: properties: clocks: - minItems: 7 + minItems: 6 clock-names: - minItems: 7 + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: pipediv2 - if: properties: @@ -215,13 +242,12 @@ examples: compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x01c18000 0x2000>; - clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, - <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2B_PIPE_CLK>, <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; power-domains = <&gcc PCIE_2B_GDSC>; @@ -242,13 +268,12 @@ examples: compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>; - clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, - <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2A_PIPE_CLK>, <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; power-domains = <&gcc PCIE_2A_GDSC>; From patchwork Wed Jan 24 07:36:33 2024 Content-Type: text/plain; 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Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 2396a457f9c8..77338184cdb4 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -33,6 +33,7 @@ properties: - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen4x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy @@ -131,6 +132,7 @@ allOf: enum: - qcom,sc7280-qmp-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy From patchwork Wed Jan 24 07:36:34 2024 Content-Type: text/plain; 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a=openpgp-sha256; l=941; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=zeX+jh65HInrDo/RwQDt8aTaE8xiSCz2Utb21fD2lmY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4DPIrhoZpasm0P2lW3phBrp9L8uQenezf2i GE6tEIxzAGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+AwAKCRBVnxHm/pHO 9ei7B/9RToHX5l2RmHvp4lJTQYUyyAWAKvGhetr7g8UkSowxxLzt9SI0p28kQVEWSeR5q2TlaOE fAwneBwub3bWVMESD+kmppRH5QblNn09PQHyw0yHQat1Zd73WI+qADs5cH6epiSkGxXnbOleJKN lD7oo9jgQ2AXnpVt7PU+dKYjgWakTEGwoXwX+Uv3FgbQnU8UonNs/7al7khJ2BPIXIuqUUw8iz5 vBX8JYDX6nDOW7ER8lYt7R9Ku47EUof15a3zXe1K5et4wHusFYsAt5jKx6XgSzZg7Bx4fjR3YSn bUmZ7IF5jCwOuX+6J21ks3UoA4mLdVR8pqbmT5zUMCSxYKfb X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Since this platform requires different clocks compared to SM8250, use a different compatible. But the drvdata of SM8250 can be reused safely. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2af7115ef968..9a220cbd9615 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3822,6 +3822,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy", .data = &sa8775p_qmp_gen4x4_pciephy_cfg, + }, { + .compatible = "qcom,sc7280-qmp-pcie-phy", + .data = &sm8250_qmp_gen3x2_pciephy_cfg, }, { .compatible = "qcom,sc8180x-qmp-pcie-phy", .data = &sc8180x_pciephy_cfg, From patchwork Wed Jan 24 07:36:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13528706 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C641A17BA3 for ; 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Tue, 23 Jan 2024 23:37:20 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:19 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:35 +0530 Subject: [PATCH 07/14] phy: qcom: qmp-pcie: Add a comment to clarify the use of "aux and "phy_aux" clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-7-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Historically, DTs of those SoCs passed this clock as "aux" clock. But, SA8775P passed PCIE_PHY_AUX_CLK as "phy_aux" and PCIE_AUX_CLK as "aux" mistakenly as the latter is not needed at all. Even though the SA8775P DT got fixed, both of these clocks are kept here for backwards compatibility. So add a comment to make it clear. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 9a220cbd9615..044e3c5ba341 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2328,7 +2328,15 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) readl(base + offset); } -/* list of clocks required by phy */ +/* list of clocks required by phy + * + * PCIe PHY hw on some SoCs require PCIE_PHY_AUX_CLK when the link enters L1SS + * state. Historically, DTs of those SoCs passed this clock as "aux" clock. But, + * SA8775P passed PCIE_PHY_AUX_CLK as "phy_aux" and PCIE_AUX_CLK as "aux" + * mistakenly as the latter is not needed at all. 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a=openpgp-sha256; l=1245; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=xQGmJ609x5rY5WnQZu2UiuYBmCFSMa/qh9a8EVqrblk=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4E35ElitvKxvgn52B7cnJz0JUaxM9PnNc0A YZLT3RUs1+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+BAAKCRBVnxHm/pHO 9WzEB/9AWVJHzHB6yiYRzLzH5QMJyCI3Uey/WEyC9zrlInlCFP8ttR0TRYGIqNPMtlsudajr4Gh RwpC8CAwS3A4Jf0oosP/6RXE1zNUfu2UjlcdqwOOxHs8AHMNKKM3toEfV0hFTdMklLboKyoEpgW sj2l+ax0lyo1k2+nMyO9dzjY/ydeqp96BnCqc+N/TRwcJ3md0oC/ZejQjOYqewn84720yaqyduf kstWJuleC/arnJeAq0oQL/W/vG4KnHN0bm+4Do+Ab2t+dKkViydZvkDALc8juNUZ0jUrVUJ5ndh KHNGEK7XglGMRE/SqBmQdOXjH9s7XvhAlHttDhKii90je4kW X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy node. This also warrants a new compatible as the clocks differ between SC7280 and SM8250. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 83b5b76ba179..00fa14777417 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2238,15 +2238,13 @@ pcie1: pcie@1c08000 { }; pcie1_phy: phy@1c0e000 { - compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + compatible = "qcom,sc7280-qmp-pcie-phy"; reg = <0 0x01c0e000 0 0x1000>; - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "ref", "refgen", "pipe"; From patchwork Wed Jan 24 07:36:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13528708 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20F0017C62 for ; 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Tue, 23 Jan 2024 23:37:30 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:30 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:37 +0530 Subject: [PATCH 09/14] arm64: dts: qcom: sc8280xp: Drop PCIE_AUX_CLK from pcie_phy nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-9-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3664; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5NPwNoYz985HYek6uHJDI/5wY+uuiyXnKa4opvBCJj8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4EVGO3TtV6DQzvJ/PExud2tothVXBlk9nJc KgeDCk+AGuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+BAAKCRBVnxHm/pHO 9ae/B/45By/VPGVbVxv8n0z7xSGfU/JGiMFrTjUS69Gmsob8PF7fxftlTWwZCLkrUgIuJRBzdkb ZkHzrSGbdR0j2Foxfp/j51A4pVzGBC45wverE1WOVAm7SXjE1RiAe+KFpN70Jnciy0gDs0voIsC I8h+my8LE3a9yTp9A2F0se8GWbdtNlTIXQLB3l5n1QNEohi+6AaJMXKXo2RAZ0T91aPbtOmcn9z tkxrffCFt8jriWYRyJB7Nw1aHfs7LoWB70dND9G+MqYRK9dMhufB9K7BXZgQniBJZ9xkoe29Tzt jJRaUqkSIdQFvvfxsXfrJN5i+O0TgUj8StTbu76AE2zXoRtv X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index febf28356ff8..cc33ef47d5a7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1785,13 +1785,12 @@ pcie4_phy: phy@1c06000 { compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; reg = <0x0 0x01c06000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_4_AUX_CLK>, - <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_4_CFG_AHB_CLK>, <&gcc GCC_PCIE_4_CLKREF_CLK>, <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_4_PIPE_CLK>, <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; @@ -1883,13 +1882,12 @@ pcie3b_phy: phy@1c0e000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, - <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3B_PIPE_CLK>, <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; @@ -1982,13 +1980,12 @@ pcie3a_phy: phy@1c14000 { reg = <0x0 0x01c14000 0x0 0x2000>, <0x0 0x01c16000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, - <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3A_PIPE_CLK>, <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; @@ -2082,13 +2079,12 @@ pcie2b_phy: phy@1c1e000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c1e000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, - <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2B_PIPE_CLK>, <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; @@ -2181,13 +2177,12 @@ pcie2a_phy: phy@1c24000 { reg = <0x0 0x01c24000 0x0 0x2000>, <0x0 0x01c26000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, - <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2A_PIPE_CLK>, <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; From patchwork Wed Jan 24 07:36:38 2024 Content-Type: text/plain; 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Tue, 23 Jan 2024 23:37:36 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:35 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:38 +0530 Subject: [PATCH 10/14] arm64: dts: qcom: sm8350: Drop PCIE_AUX_CLK from pcie_phy nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-10-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e78c83a897c2..23a9060f21d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1571,12 +1571,11 @@ pcie0: pcie@1c00000 { pcie0_phy: phy@1c06000 { compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; + clock-names = "cfg_ahb", "ref", "rchng", "pipe"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -1654,12 +1653,11 @@ pcie1: pcie@1c08000 { pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; reg = <0 0x01c0e000 0 0x2000>; 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Tue, 23 Jan 2024 23:37:41 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:40 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:39 +0530 Subject: [PATCH 11/14] arm64: dts: qcom: sm8450: Drop PCIE_AUX_CLK from pcie_phy node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-11-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This clock is only required by the PCIe controller. Hence drop it from pcie_phy node. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..1e0091dabaf1 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1830,13 +1830,11 @@ pcie0_phy: phy@1c06000 { compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "ref", "rchng", "pipe"; From patchwork Wed Jan 24 07:36:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13528711 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F7231862F for ; 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Tue, 23 Jan 2024 23:37:46 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:46 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:40 +0530 Subject: [PATCH 12/14] arm64: dts: qcom: sm8550: Drop PCIE_AUX_CLK from pcie_phy node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-12-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1138; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=qbS3T4RFVlJivCmN4hJ4Xsqqhf8ddqNIBdThgGXkGnY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4FTWuUoQIXeVx6vSsYrfv+1E10lScR+ZHtL eUWXb94QZmJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+BQAKCRBVnxHm/pHO 9dc8B/98bZbvZy8V9hBe0ncd/s65E4uiIGidQTmD+Dz0V9tH1ytXtu/tD2tpMNqK+QTIAJJq59X 3cuKmhgSQDgXiiz98Shz+xCq8TjmqYMNfyjopeq7+mHoGbS3y54BhY8pW7V+cpQmzMDJ/UcZNMp X1+8h+POmcY90EJ38NkAv16uOlwkv1dNyv/SpsV1vBSuc2OQ0tZhf2HGq7ukHPlPspq+0YO5ibA ABdoRog+r63cOF0yzw9CvkVacAQNkPK9y4qOhgNjk2AtcHR1Lt3K28V07t0RiIqWQK1X/kf9xvw T835vebbz9UYnVxLEPB23lI58DzhZjWFzE50unZQ6Wmdhubs X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy node. Signed-off-by: Manivannan Sadhasivam Tested-by: Neil Armstrong # on SM8550-HDK --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..f074683f7940 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1760,13 +1760,11 @@ pcie0_phy: phy@1c06000 { compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + clock-names = "cfg_ahb", "ref", "rchng", "pipe"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; From patchwork Wed Jan 24 07:36:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13528712 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39D731865B for ; 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Tue, 23 Jan 2024 23:37:51 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:51 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:41 +0530 Subject: [PATCH 13/14] arm64: dts: qcom: sm8650: Drop PCIE_AUX_CLK from pcie_phy node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-13-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1080; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=xR8wvtP+QITH8T8kLA9WFdRX9QC0BEnzA8VfMLDLOeM=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4F9I2jnHfAODN1h6LhID1P5M4ffX5SDTNOK tmbdlVDGn2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+BQAKCRBVnxHm/pHO 9e9HB/9IOUcSo3ViZRQJMCk/7G0FlXlhNFCiC5rUFKMDKuWujGHro13gDGJjTczje/BKnWxULGQ xvxbYT108gLh5mEcp90g5HVfToMp1AArsS3Fqnai8z0TkKnd+2dfxOFFow35x16YJnZmlE502Ae gw/DKa8Yi3+H7Pogj6id8NcfMHlRwkwwzBE6psr1YYv4uIIdIlKAqJvtav8irLGgRCHnD+IfL2L wYgrv/PZB13YCBXxVS2lSTYEgTY9HHM2SpVutjUixxncsHPi+v+Ic0I6Wu5T8Y+f2yaBax3w9Ll E80RfnrBnVFBA/a+DyEiXU1+AXBZ1W0D07uUrZBUR2iYa8GH X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy node. Signed-off-by: Manivannan Sadhasivam Tested-by: Neil Armstrong # on SM8650-QRD --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 2df77123a8c7..b31e60599891 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2276,13 +2276,11 @@ pcie0_phy: phy@1c06000 { compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "ref", "rchng", "pipe"; From patchwork Wed Jan 24 07:36:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13528713 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DF7018E02 for ; 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Tue, 23 Jan 2024 23:37:56 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:56 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:42 +0530 Subject: [PATCH 14/14] arm64: dts: qcom: sa8775p: Drop PCIE_AUX_CLK from pcie_phy nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-14-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2114; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=AV0AQVKEuKDRIth7QZV7qLd22LfBtighoMaozbvkXAg=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4Fhhiw+ROelMo4VRCj1+Kx7T9cS2AThYZkc DknKia3ul+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+BQAKCRBVnxHm/pHO 9bthCACRQjvyFRVJy3hTYxwCqypCA959YVl640Spi+/5TQUxSwUS5HOza3ZjI6ZCE6ZAV0awrPp Ma31wRRoKSgL0QcvLroRMpG1W5pN5E1/CJq/7joMoTGV0Gytn1w4fGIB6/kSXkiPqOPMbNMCVFF Ngelg4E2chxrplR8oOICcl/mKuhw922a3poiiA+oCWhEqfmYWYYtsF2apAswH19tebHdmBaK1SZ R6CuqE5X5TaD+C9YLOpC2/R0IwNZhXa5IF44UqN+Z2XWohLPbBrvLIpcPH81pLIQtrGgFaeeM8N gbnY/iNcmWsx9j3N5iilOXhEMCW5MWYCIzifzYfgmlKRHqBf X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. While at it, let's also rename "phy_aux" clock to "aux" clock and move it to first entry to maintain uniformity with other SoCs. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index a7eaca33d326..b99626c52800 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3590,16 +3590,15 @@ pcie0_phy: phy@1c04000 { compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_0_PHY_AUX_CLK>; + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; @@ -3690,16 +3689,15 @@ pcie1_phy: phy@1c14000 { compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg = <0x0 0x1c14000 0x0 0x4000>; - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>;