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Thu, 25 Jan 2024 01:28:03 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id f19-20020a056402005300b00554af5ec62asm17356391edu.8.2024.01.25.01.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 01:28:02 -0800 (PST) From: Abel Vesa Date: Thu, 25 Jan 2024 11:27:45 +0200 Subject: [PATCH 1/5] dt-bindings: clock: sm8550-dispcc: Drop the Disp AHB clock Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-1-0f8d96156156@linaro.org> References: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-0-0f8d96156156@linaro.org> In-Reply-To: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-0-0f8d96156156@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Disp AHB clock is not registered, but enabled on probe, by the SM8650 and SM8550 GCC drivers. So drop the clock from dispcc node. Fixes: 553f9bd45554 ("dt-bindings: clock: document SM8550 DISPCC clock controller") Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index c129f8c16b50..6660d38bef86 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -25,7 +25,6 @@ properties: items: - description: Board XO source - description: Board Always On XO source - - description: Display's AHB clock - description: sleep clock - description: Byte clock from DSI PHY0 - description: Pixel clock from DSI PHY0 @@ -82,7 +81,6 @@ examples: reg = <0x0af00000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, <&dsi0_phy 0>, <&dsi0_phy 1>, From patchwork Thu Jan 25 09:27:46 2024 Content-Type: text/plain; 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Thu, 25 Jan 2024 01:28:04 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id f19-20020a056402005300b00554af5ec62asm17356391edu.8.2024.01.25.01.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 01:28:04 -0800 (PST) From: Abel Vesa Date: Thu, 25 Jan 2024 11:27:46 +0200 Subject: [PATCH 2/5] arm64: dts: qcom: sm8550: Drop the Disp AHB clock from dispcc node Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-2-0f8d96156156@linaro.org> References: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-0-0f8d96156156@linaro.org> In-Reply-To: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-0-0f8d96156156@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Disp AHB clock is not registered, but is enabled on probe, by the GCC driver. So drop it from the dispcc node. Fixes: d7da51db5b81 ("arm64: dts: qcom: sm8550: add display hardware devices") Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..59c23d0696a9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3026,7 +3026,6 @@ dispcc: clock-controller@af00000 { reg = <0 0x0af00000 0 0x20000>; clocks = <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, - <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, From patchwork Thu Jan 25 09:27:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 13530318 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2476D1C6B8 for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Disp AHB clock is not registered, but is enabled on probe, by the GCC driver. So drop it from the dispcc node. Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 2df77123a8c7..1bf16636371c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3442,7 +3442,6 @@ dispcc: clock-controller@af00000 { clocks = <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, - <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, From patchwork Thu Jan 25 09:27:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 13530319 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C25C1CA9B for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The GCC doesn't even register the Disp AHB clock. It enables it on probe though. So drop it from the list of DT provided clocks as well. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Abel Vesa --- drivers/clk/qcom/dispcc-sm8550.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index f96d8b81fd9a..b33795f8e8cf 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -31,7 +31,6 @@ enum { DT_BI_TCXO, DT_BI_TCXO_AO, - DT_AHB_CLK, DT_SLEEP_CLK, DT_DSI0_PHY_PLL_OUT_BYTECLK, From patchwork Thu Jan 25 09:27:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 13530320 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93BB51CABE for ; Thu, 25 Jan 2024 09:28:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 25 Jan 2024 01:28:08 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id f19-20020a056402005300b00554af5ec62asm17356391edu.8.2024.01.25.01.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 01:28:08 -0800 (PST) From: Abel Vesa Date: Thu, 25 Jan 2024 11:27:49 +0200 Subject: [PATCH 5/5] clk: qcom: dispcc-sm8650: Drop the Disp AHB DT provided clock Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-5-0f8d96156156@linaro.org> References: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-0-0f8d96156156@linaro.org> In-Reply-To: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-0-0f8d96156156@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The GCC doesn't even register the Disp AHB clock. It enables it on probe though. So drop it from the list of DT provided clocks as well. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Abel Vesa --- drivers/clk/qcom/dispcc-sm8650.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c index f3b1d9d16bae..382ebc1866b9 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -29,7 +29,6 @@ enum { DT_BI_TCXO, DT_BI_TCXO_AO, - DT_AHB_CLK, DT_SLEEP_CLK, DT_DSI0_PHY_PLL_OUT_BYTECLK,