From patchwork Fri Jan 26 08:56:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13532256 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDDD313E23C for ; Fri, 26 Jan 2024 08:56:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259419; cv=none; b=EjQB46eYuC9+DgsnF76aosR6xgZqlihUtPnqG+IKc77AtH9/Fv2RgG019bvGkosAKJVGdB/TNhwsDWdRtxutLZSTkYZDEaO6Z42pFD2iG0RVQDzbZnoiEf+i0sHTXGekZ85P9HG38umIe0hVIUuIW+aq415Hc8OoiwYT1kusvis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259419; c=relaxed/simple; bh=AD9m1Tc3JH0KdVSduNbc60lgjjhiyGGP68IdBbBdqnI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vhk/u2PuVHkh3vOeUf4l9oz23oEBAaVdAplS1+PihZUojMbRRHwn7EmOj3/uvHWQbogNlBc6/zjlszsh1KL8+1vHVkM6lEZjJGSlLYEG88YOYJheEBaB18EtTgOm2l192UAzS2Z80G/tN4XbXbQ2vJ2ct/0ctQomtmtcX8EZ0+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ceymd7dK; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ceymd7dK" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-40e9101b5f9so1775895e9.3 for ; Fri, 26 Jan 2024 00:56:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706259415; x=1706864215; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kzOVeuE69v/d3EzLsuJBODa/XxSCc4J0jffACJapMek=; b=ceymd7dKaEAc6CcQ8tBdvlz9TCspjaIYpm6Ul5nzMZhFNRncJ+V+NmQZtoTNsbnuCN 6KcqqiMWFeQCyLKovs7lhj7wPB/GdWQpRO1QZ84wKm0WorQ6wnnoNog5q4voPKXAig1F NXd+LXKqWT6389ahpXSuDK6kTb31krwH1vHirZfpuh4cK4wuHd09NPFvPd+kKkPo1f/e xS/BjWB4xYa1UrC9lS6Hq2eS+x/AgJ3q7nWn/+scyK2/BT7TSHTgbHQG1KxSaqFG/1Tq g8S6w0QJfuAZNhSQMiLrQMEIkBn6J2ehYhlLKgnTbLpn3lgrNT9RlxdbpWxUNAmF092Q pAHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706259415; x=1706864215; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kzOVeuE69v/d3EzLsuJBODa/XxSCc4J0jffACJapMek=; b=AFIjeyhJbA/ph274+zh04BJe0FiIA/c2FetUJAbQq60GsYOVfEmvYX01BI5J7cHwH8 jhjf5Tp7Olna3uiTuyVYW0xvNmcSAbe4QTD8pDQQsiuzJ7BtK1qBMxHSfPqMZeBsLlkb z39yE5CW8BijaYdrnuvUPz9ZfD5Qt+qPpk91MDuFEDbVIRHdn18Mqgqy+45cm/GDRs0z UsgPYWdHnRrhOrWsb+KZ/RBbr+h5OizFnR2m8DcC+1ufgq/uRAGx+g82BEtWe/A7HegN VWopvO8IYkvjg7/ctPT/6ouE5YZU/y2LLiQXbqWgLEa7bp9vU7Mujy+SbShXP7s879w0 kwjw== X-Gm-Message-State: AOJu0YzoipasIOQfHi/DVmYGT8ZojR+/MVFYdAf/A8jXB4id0PylG6r1 KdEKXOdBJmLCLM3QvL7A4L9hVtpXOU78xXtS9F77qZ4ovsOULY9OYsZUUJ84lu8= X-Google-Smtp-Source: AGHT+IEeuBcEWwVxKGnhXLhhaYf8dQ6dKAM6IyBYHbj46NkXMHL8+O166fL+ZowfCLqZ+7gHFEZhVA== X-Received: by 2002:a05:600c:a385:b0:40e:5c7c:f357 with SMTP id hn5-20020a05600ca38500b0040e5c7cf357mr628361wmb.133.1706259414890; Fri, 26 Jan 2024 00:56:54 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id q15-20020a170906b28f00b00a31710c0d32sm390522ejz.203.2024.01.26.00.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 00:56:54 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 26 Jan 2024 09:56:42 +0100 Subject: [PATCH v3 1/6] dt-bindings: PCI: qcom,pcie-sm8550: move SM8550 to dedicated schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-dt-bindings-pci-qcom-split-v3-1-f23cda4d74c0@linaro.org> References: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> In-Reply-To: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=11515; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=AD9m1Tc3JH0KdVSduNbc60lgjjhiyGGP68IdBbBdqnI=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBls3PO2J3/JHJ2ApYWW27i94ESWMFoCO4+x2FtI mnPK8ity4aJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbNzzgAKCRDBN2bmhouD 18IrD/9UuaPx1DzV5Vj4g7DpHVKjtG0NgUkVhSAKKJooOq4GsYyhLI2wl2Ur1bX4Bswvg5yg1YK 4XDnYl1eDiKsQGwCoRKqPoHnzX7qBirh6+bYVkjvn06rsEaOgJDyMZjBTcVeEx0kXFqhzu6+ekc 48ABXhiMDocYW8QtUD30ySQJAiUGjrDBbLbqaIubpg7St6UkErExXKjZd/674jz/wBdn44+Hy6s TqfYsOMRoplK2aWDtaIS0BMpGW8kMX5DCuKre4DBBS7rIXGqwLAv9L1WsDeWtio62/PxXVbyzOU DyHKetIlaPHHdH/VguSn2Kyx65Nck9LlDVnoWiUuLwPV6RLEP1GTBjAewzFts21f9oYm1/58LF0 ISudXCpaAxrn/ZVJIECq6ATINmlJnTsdY6gwKAXy9v1SEWhx7sl5Q8sTMC64xzBLrN3F4oMNKIz 8Wlon4UahKHVuE7v6GWV2BX5I3i9Ph/ZidoIS6rugefl/Szvm7VTotzYlmL4bdZwyP8UY6+DCza dL+15hiWI8gxEDkBcrUWBH0oEjdovEjHFvV+wRFLktY7uSDEXD4YyHeYRakpQik0K8dBq8KkO1R dkGBd+5mvHDgprCiI2B1YY/QlsLBcmbrivnOjgdSt2GrSww5YGOHF7m/jbPt7ZBJo7Q0t28wwle 0mlDiZVbRMCyQZA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The qcom,pcie.yaml binding file containing all possible Qualcomm SoC PCIe root complexes gets quite complicated with numerous if:then: conditions customizing clocks, interrupts, regs and resets. Adding and reviewing new devices is difficult, so simplify it by having shared common binding and file with only one group of compatible devices: 1. Copy all common qcom,pcie.yaml properties (so everything except supplies) to a new shared qcom,pcie-common.yaml schema. 2. Move SM8550 PCIe compatible devices to dedicated binding file. This creates equivalent SM8550 schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 98 ++++++++++++ .../devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 171 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 38 ----- 3 files changed, 269 insertions(+), 38 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml new file mode 100644 index 000000000000..125136176f93 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCI Express Root Complex Common Properties + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +properties: + reg: + minItems: 4 + maxItems: 6 + + reg-names: + minItems: 4 + maxItems: 6 + + interrupts: + minItems: 1 + maxItems: 8 + + interrupt-names: + minItems: 1 + maxItems: 8 + + iommu-map: + minItems: 1 + maxItems: 16 + + clocks: + minItems: 3 + maxItems: 13 + + clock-names: + minItems: 3 + maxItems: 13 + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: pcie-mem + - const: cpu-pcie + + phys: + maxItems: 1 + + phy-names: + items: + - const: pciephy + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 12 + + reset-names: + minItems: 1 + maxItems: 12 + + perst-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + +required: + - reg + - reg-names + - interrupt-map-mask + - interrupt-map + - clocks + - clock-names + +anyOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + - msi-map-mask + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml new file mode 100644 index 000000000000..24cb38673581 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + oneOf: + - const: qcom,pcie-sm8550 + - items: + - enum: + - qcom,pcie-sm8650 + - const: qcom,pcie-sm8550 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 7 + maxItems: 8 + + clock-names: + minItems: 7 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8550"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr"; + + dma-coherent; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..3b7dd9a4ef60 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -40,11 +40,6 @@ properties: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 - - items: - - enum: - - qcom,pcie-sm8650 - - const: qcom,pcie-sm8550 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -226,7 +221,6 @@ allOf: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: properties: reg: @@ -715,37 +709,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8550 - then: - properties: - clocks: - minItems: 7 - maxItems: 8 - clock-names: - minItems: 7 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr # Aggre NoC PCIe AXI clock - - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock - resets: - minItems: 1 - maxItems: 2 - reset-names: - minItems: 1 - items: - - const: pci # PCIe core reset - - const: link_down # PCIe link down reset - - if: properties: compatible: @@ -883,7 +846,6 @@ allOf: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: oneOf: - properties: From patchwork Fri Jan 26 08:56:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13532257 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C128286B3 for ; Fri, 26 Jan 2024 08:56:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259420; cv=none; b=nP0FyzW/ZLbs3ffkrzmk8I9cOKUq7U955DCwvdRCnq4LNy+aDld2XUNWRbjzUDdDiB1zympIYxLssyNsb0VHJSD05yGHDxtldL3Cxb/HSuFV9nx9gQRgUgN8NNWhSNKfie77Vek8zK+Rf5u6OGYvxJsWZPmTSSp8G7YJwOQaOw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259420; c=relaxed/simple; bh=XhAcg0QYBx9ubfzmIVUUsWDWIxssYMoM0+StLqp8MFo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f60g5DobDbDp8kK2N36rVwTLslXsJfOpgGA/ukaLmdZuBpGWP7qFuX+tmlA5ukz76QLCZk4AiqxFaU/seQptFigErXcZPnXeh2aVUg9Xr8ZyzA6xdmL5BFexY/ia5u4nXmdlbQHafW2GPe2hgSJ95sN/BBdXyZCijbvRt41arrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=jJLZtqDG; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jJLZtqDG" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a277339dcf4so12727066b.2 for ; Fri, 26 Jan 2024 00:56:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706259416; x=1706864216; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=b/Hyf+ii2vngvt1+jF9pUc5XMJgEB9A2SXkhaKt2OpI=; b=jJLZtqDGdfTb1nWKVlhzl+somtXagBiLpT1jdQGAXIBl0L5BvGu5+dND6xH6zvEIV5 FVhFrmh+6xjJR7jXdG5bb0k43YsQWpCATojMppjq1oZw139KKXX74umv3M6PLqi34gyW C/cyNBpwDfx8pQyGRy1ZjzJxTC0beDwsfGjyw9PQGYIwhurIh7LlRSMh+dr2TejgUHyH 9ho+JtRaJDFuSnBaEmhNbDQpZ0e4yy3kJTiMVkqOKWAd6IZnyS3HN2wDXcSaz9MeFkYn riCY4MpBx7yW388YEhmOF70lWnQ9UXSJzDswCgyuai4OE5dl6U2+Rnu9s9xPFAKUVmtY OK2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706259416; x=1706864216; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b/Hyf+ii2vngvt1+jF9pUc5XMJgEB9A2SXkhaKt2OpI=; b=gljGHoVF2ACCVICXnJJX6E7/skRPjL0jTxxCCMv4cBZi93b3TxxinC/1XI3nxozc+R 5WQsISeV1ZyixcD8PyW1TaRJ9ap9DxJH4EF/4kg5JEm8lbEzUFRrw+KC4mYMdqdgZACc /NnPUEWthEmrLH4ib8IVg0x4UyixnokllwTXSpfq+QCYIt4Cg2+OPoGprimIQNCloryc QgE0nlbJc7By+fUcx/M7Rzw5ervG12xK92xrBsmap7hsjVQc6CxaPUr0UFIM6ayIeott j8PuPX1kMqFUvhu1bFXmr1JftakYFrR2q+8y7E1lWvM3psyy0GZ9y+8Hy5yj6SXunsro ilAw== X-Gm-Message-State: AOJu0YyYWpGfJsv+EEzIF4xosRzs4N9aqH3lrrUj2QG1fBUz8R1EvsPW PkzRjs+8DU3cUHpM8DD5ke5HQDfJvnkynxj7YcQq+ifUrYnp24pAudfZGIxTHN0= X-Google-Smtp-Source: AGHT+IFdB6ifMXjUATF1ESfEGoJYFnCdA5+uvFdBWAzebUhLMG5ntvzJ7a6i6Q6VA+l8tidNqQKQEQ== X-Received: by 2002:a17:906:f758:b0:a30:ab56:b5c9 with SMTP id jp24-20020a170906f75800b00a30ab56b5c9mr496823ejb.54.1706259416526; Fri, 26 Jan 2024 00:56:56 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id q15-20020a170906b28f00b00a31710c0d32sm390522ejz.203.2024.01.26.00.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 00:56:56 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 26 Jan 2024 09:56:43 +0100 Subject: [PATCH v3 2/6] dt-bindings: PCI: qcom,pcie-sm8450: move SM8450 to dedicated schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-dt-bindings-pci-qcom-split-v3-2-f23cda4d74c0@linaro.org> References: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> In-Reply-To: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=10285; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=XhAcg0QYBx9ubfzmIVUUsWDWIxssYMoM0+StLqp8MFo=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBls3PPbgZqZZcGY9YAdNTNcKr+q15dRfflfBDfB sDXLh7NnCuJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbNzzwAKCRDBN2bmhouD 17GOD/9Q/49S6jJJ5aPSrpruHbRABpI1Ozq9xE9oxLe9lWR8rsv24GyquKoQaZm6mQnk9IgK5UL LuCYxsU2qemIWlqeRqqGKn7Y7oA896J1Q1x0u+LNQTRFlknU9muhhMhkIwPvk24UA68UtX7Omc4 3Gu7LXAz6U/aJI3WgW9E79FUL7cGarzq94WaM6Dj5oyQZitPgbTG/PoCKVzLLBzhYYkurt1AgPv 0NtcGmrZ4QP0WjcvnQ7GSJASCe0HH1dUbHmUaz6K/tCXbxrBRRuoWRDP+5Sdi4haGDofL+Oi3k3 3iNed8PSX9JU/8uboqlt5MO7n29bVDxbTnQYsttYJbIAMxzLopvdi52WdiNOUCvEZz1WzspiLqh x6IssMUb2sChwXr6u/udXAqEPGsKI8S3wp7L/gQNWVIsPiTRLev4DscnkRuUKlL++dhB19wz47z bxc6+/AUCKq6hq+tl9O/FmI7Cns+j2xpb8T0ymwAZCvxepq5EJxjAD+46bxv/2zqOYGA+FdKkL4 m6NJyDsc+CWXLllqKYb2Pvh6A73IC6SHW/u2C50rJ+u64MlzUmfOQFZzE2dScRmEikKVZozYdGm kOsexBwhfyBvStQC6HYkDg8qSqCkxkqH+3/UFGM50GOcqy0XyN0MseZjPbg1LOY/MRI9z/Q/ibO 7i8Qs8+JVSPE6vA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8450 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 178 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 67 -------- 2 files changed, 178 insertions(+), 67 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml new file mode 100644 index 000000000000..1496d6993ab4 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 11 + maxItems: 12 + + clock-names: + minItems: 11 + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8450-pcie0"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + msi-map = <0x0 &gic_its 0x5981 0x1>, + <0x100 &gic_its 0x5980 0x1>; + msi-map-mask = <0xff00>; + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 3b7dd9a4ef60..791ddab8ddc7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -38,8 +38,6 @@ properties: - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -219,8 +217,6 @@ allOf: - qcom,pcie-sdx55 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 then: properties: reg: @@ -648,67 +644,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie0 - then: - properties: - clocks: - minItems: 12 - maxItems: 12 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie1 - then: - properties: - clocks: - minItems: 11 - maxItems: 11 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -844,8 +779,6 @@ allOf: - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 then: oneOf: - properties: From patchwork Fri Jan 26 08:56:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13532258 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44A86140769 for ; Fri, 26 Jan 2024 08:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259422; cv=none; b=MpP1UbYKOWaMeiRpAGo+Qsxo8ORXO3DSQcl2c8iw9o90n93VUoiOT2exm6WFgbQHs7yg3rgnfvxSIaKWNdbdQrBRx9GG6ERto3RcHOiD0wOGcZ8klYChLMZ9EgSwbIORgeFuDj/rbgqP9xYT57TJ4Y6b/9PI9k1v9uqVH4vSsrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259422; c=relaxed/simple; bh=Fs0hqsceVE6tREsJFOaedH8nmI0CDFaCTGuwbMlpTHU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fK22Ky0npnKqCWV0HVaX1RI744zo7H0EBEfQRFPD3v+gn+6tLvYjhZvH8a+9dgyUknknTa/NdNy39JXoIbkfc/Hqnce9gfcy1WjEzFl+bj7uylJeqg89A18gkyhr9yUXsIsJnAEHk4zSBvMcHj8dbVodIt8dlEquSZdU9gheldM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hlzlNKQ3; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hlzlNKQ3" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-40ed1e78835so1960525e9.2 for ; Fri, 26 Jan 2024 00:57:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706259418; x=1706864218; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4cwlGhuyqhoddA6J3pLRTYguRcB5mi1DcrMGcpwmQIA=; b=hlzlNKQ3eoxsAve6qhHMiD90JiV7naUhKnZkL7tRmtaacAKjSlF1Tbu/blTFV/Dq54 x6I2hB+LowUcKsKZTxdtDqb2KgfeGWBVwv3GBb7y58iC3IfnOc2U25Zj7ngNkAEk/NGt Hukqv53Z9K0GwrWg/0ZWQPl2ES14CJTItUl1f8TWHvn3Kbt0JSiHHQUgRcBsaOm9vW8A g2GbtYtOol3dxOUgsP18hfb8xEm1dohY33nMZI1KwfCXI8Fi6EyoV7US5XUW+y6EHTpI rBY4MM2XKAQ3u7Ue5k0FwfETbCMxuBiQy0ZBxhmbvktWCzc3RTrqp/FCP++ganh52qJW C93Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706259418; x=1706864218; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4cwlGhuyqhoddA6J3pLRTYguRcB5mi1DcrMGcpwmQIA=; b=Hevx+/BwnDKqGs6y3CTBq1vgm7RhtFgMqY/IZF7A+7kO9QZ8FEaFQ+nPS8jvo8j5+W AbP3lQsKcNFXn2JH/4lLzlfWgiL60H6nNEc24vUudtoxo2+I3FK5U+U7KKmgtfrR2n80 ROGZjn8ooelkNtq95JSxHIm1kpjSnHF2/lb5S2uhb4QvT5Qw7PYx3hQsC9xeinLPxjAf YCR9Qj6Ab9dE7jCYB91P7w11foE2XFUZq9k7UVCUvisogORCPWgVQZU3EsuPX5VRhLQf j8edxqr0j+iCIzRs2JqVQNPQMRn9L86QQgy6vCDx8Hmh99xMyQWWCNGhwXo/TUXrUYHc MY1Q== X-Gm-Message-State: AOJu0YxCE/JJCRpQRSPQEJ1IxiFiEkYT+Gr606fuDjRNPmKNxoNUEHSp UvzfA6GPMS8lQCWq28xe0Yyj4Ui7gqNYbfYJpxdAAXKffC+pLnSuNRGt1CSSWLs= X-Google-Smtp-Source: AGHT+IFAdaWtnDOD8PLIKIlXxeLNO/Ya+2P7RC7p6rwfBjXFfy3hnxhIZgyklb6+mzikxAP38gufYw== X-Received: by 2002:a05:600c:43d4:b0:40e:863e:2f16 with SMTP id f20-20020a05600c43d400b0040e863e2f16mr613787wmn.128.1706259418564; Fri, 26 Jan 2024 00:56:58 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id q15-20020a170906b28f00b00a31710c0d32sm390522ejz.203.2024.01.26.00.56.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 00:56:58 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 26 Jan 2024 09:56:44 +0100 Subject: [PATCH v3 3/6] dt-bindings: PCI: qcom,pcie-sm8250: move SM8250 to dedicated schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-dt-bindings-pci-qcom-split-v3-3-f23cda4d74c0@linaro.org> References: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> In-Reply-To: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9618; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=Fs0hqsceVE6tREsJFOaedH8nmI0CDFaCTGuwbMlpTHU=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBls3PQg6VlMWZZ5x2CUW6tmGf4i7svqaIEPEWZc OcNtiWqTBSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbNz0AAKCRDBN2bmhouD 1yTgD/wLiRL1OwFMUgB64tiTgPCBfpSOAZgUwFU2xlYkTjIPJbKEDD1SsnYbAzV24Hq4DMgMD4L MYA4POjoNCl5gdJ5NNVo5iNedN9KHA3HlbcDkyPUkjVHd38Qvg6ta5QL1+uNtSgXKF9lHEnEpfG FDAi/0skKLwT9LytsjsX8qHIuxpn79xnnHnqNEvTnXgr1W4VeRjKtVRHdry0m2S4Srpij2A7QLw fWI1Z2iAtBdyJYLweiYt6xryCDHkJTqtfI/w+moFDUUqR8fxaGARPlowixbpc/2ktW/HG5mkhKC t6MIXHfOQk5GGrbDvI+miR2LhcYBlq4QhQZC/71ts6cFI4cw4Vfz6+HEGRLg5JN15gx1D88VG8g ZeIHXJQaXqbuemlPqQibBSojiI9JQk++DN6cpdEZbcuDyuTjTprdWlVz3lIwfva1WARkhJgfHIl HQv2dsvnOSveFR4qmHBt5ma+or33BBnY43M/fyVA6MJGWkc/0dA3/WD91WwDHJXJ5LFEA1LXXbg DIRs9bIyAgXerSuWkS1sLEtKxMeE8AiBvQcVJqCdSV8ocSHdB1Ls+kFqUjxgPofNdrbM6PkN6Rc HNblgTsaPcd2ly2Z1JbgjZp53Ir6NnDsPbfvUSVbQVFreSBExHAGPhKB6Y6kiHsrCBnufFdJN3n m/sJL3nSHX69AyA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8250 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-sm8250.yaml | 173 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 48 ------ 2 files changed, 173 insertions(+), 48 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml new file mode 100644 index 000000000000..4d060bce6f9d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8250 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + # Unfortunately the "optional" ref clock is used in the middle of the list + oneOf: + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8250"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + dma-coherent; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 791ddab8ddc7..14341d210063 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -36,7 +36,6 @@ properties: - qcom,pcie-sdm845 - qcom,pcie-sdx55 - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 @@ -215,7 +214,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdx55 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 then: properties: @@ -570,51 +568,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8250 - then: - oneOf: - # Unfortunately the "optional" ref clock is used in the middle of the list - - properties: - clocks: - minItems: 9 - maxItems: 9 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ref # REFERENCE clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - properties: - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -777,7 +730,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sdm845 - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 then: oneOf: From patchwork Fri Jan 26 08:56:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13532259 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BADCC14078E for ; Fri, 26 Jan 2024 08:57:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259424; cv=none; b=CihcedEDgBJf/xnWYMcJK8GvPPdvKnH/ZzeRKluRJ4s+RSgHFlxsx6u7raJFv9pK0bFW7vEYNi45Bkdkv7k/AvJGYT+RrKi/x84e38eqYfACbcLGF6jGzXsgJzgMZ4ws9VXISRMqtiiF77jGENgcGZHcOEXzJZ6yUB0k6JA3D/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259424; c=relaxed/simple; bh=L2tu3oVaNutiUYx1lhf/hq1yv4Gzm5YHggLrHFEaVTI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VO2Wc3TeI2dqLDAh7AIp/PJRFeRGlbi8m2UxQNUwUJv7ZqARCjyeVPLHwq1+voeoCENfURRjeB70JPgX6CgGx0mDtV+JfaHBw85OApsNpQsXCVwRwjwWpeSb6D8CbsTWBy7yPlD2ObRTbaQKBI5ROcBVD47wkwnUdrC+ugtFVzM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ycnxTktm; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ycnxTktm" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-337b8da1f49so171240f8f.0 for ; Fri, 26 Jan 2024 00:57:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706259420; x=1706864220; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yb0WcvqtQcLyXdbtPa/dVBnzAG+9fpalgiYlCkLzkns=; b=ycnxTktmRKgPPj5TAZ32nfLvK1Kiww6C9gEaG8i55AcGaz4JVq1JHKQMmU+0CMAJ0p kCB80j95kAV+g1x6SRrCPd0OlmsDN6mpDQoWCUNIT209bvhTI7n/7Ir0IGiT0H4YjSzp hS97ACRb1Vybv2lEDnnntyuG7Bfl/2uOgfb0kgsU3EpBOzcn9p8WKFobj9uHtbLQETg4 mWtQmX82f3/1BgGxf3E2w1uejutfjjkpm1H/V07XLhQG3wbRa8pNDSLJZG9ImqT+D0MW nPPSGy423g2CWIaF9/NAhOM0kzwB0vu82kCFtC4IecUq7fFvwOlnUxO59nOh4FWzX4CW wAzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706259420; x=1706864220; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yb0WcvqtQcLyXdbtPa/dVBnzAG+9fpalgiYlCkLzkns=; b=VPdA4LPLCvkTp5araEC6p0o+q2NydAXG7PmOhIZVFP4aDk1pm/qMScetD9lSVFdwpx hLucDNgpcpmfLMi4W79HOD3dr3DFPHGs4Hh+v/KIYRX862pz7pR3FR0NputkSiWYSOrG UbbErsmYZJm14gCIk1rTgwDidOgGP4ue7A0hKy+JXUvGHImKI0AcQqbtfKCL9PtXUOgh RScYEr9MkA0ni28uTwMtkXGJzOPYTxkQgQya1c+zJwo57zjAJXVgudEjODZol5yUjZjH H1ETIEeeAeiqFiepjwi6rDsClf7/R4BbxxvvQSCBMjujgBOSCDNYrkkG5+i4rNQgTq1C 48LQ== X-Gm-Message-State: AOJu0YwkhEizbhilAA9mLBcpUAygF3R6rK6eTsHc5rUPDgbjmnhILz8O OWLuvYFAUbxVx+i7TOBOYEhgvhAWZgrLmXfHA/Z3HkNIYXT5FyvbiUCFabnzsjE= X-Google-Smtp-Source: AGHT+IFXvKY7olw7KYjmnP4Ff66b4uPAlX1lK5/9TIk5oumoUXZuOdLj8CbaWC/jOtNQCMmALW7ywA== X-Received: by 2002:a05:600c:1f12:b0:40e:db62:9129 with SMTP id bd18-20020a05600c1f1200b0040edb629129mr229793wmb.271.1706259419990; Fri, 26 Jan 2024 00:56:59 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id q15-20020a170906b28f00b00a31710c0d32sm390522ejz.203.2024.01.26.00.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 00:56:59 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 26 Jan 2024 09:56:45 +0100 Subject: [PATCH v3 4/6] dt-bindings: PCI: qcom,pcie-sm8150: move SM8150 to dedicated schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-dt-bindings-pci-qcom-split-v3-4-f23cda4d74c0@linaro.org> References: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> In-Reply-To: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=7937; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=L2tu3oVaNutiUYx1lhf/hq1yv4Gzm5YHggLrHFEaVTI=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBls3PRn9rL81jv3m2XlYtmwskwYmtXrBa/iFCFC hAYAQaZaxCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbNz0QAKCRDBN2bmhouD 15w+D/9T3l4ySDrrXzZsnVYLZE/HhHiGox0wZEC1xtgipMToR/15hMkEI/Ujq0lACINSYiVBex6 Oc/eIXLD7oVE4KSi2V+D8/WJ90A8Jqy0jBkNljNXwYzs+0HkYslVh2BlL3rqPI+0tLmJ8CcxXP8 aJkOlEatOfUCy42nEyQxDPvEI/HTGySVKL/RUH67WMtF7Mh7r51JUtsTj9PKYV9gXEXY62OsTvY zP33JvG0VA7drEFGNbIPOyvLuRHtKjy2/8OGl42N5txEcaUnd/Q4kICEix5aDnkHFEbdoIeeiKD Pf+rvWteQQVmQAR/LJCaERjG1YVRUiYtUkeZYO8IFlffyV25fTwFZZYry8PnYpxlbmNh61L8UW1 YXf5zkT/iBE3N4M5JHaJbqMZE2v6ieUCBXZ6EFnOouijh6BbPU9xuW1LtK4LCnEfWmIDSMesedO wdDRcaU1TUXqucoGJuSpJQM5bxARCVJE2cHKWIqrYr9aciP1Hkx3Y3Py3wJVXs5tSauFbMQX8cY Wb/SdWK9iYteplPMuPGDqNxl78VDdBBYLdvFzxzvInhA6JwbOZcC4BSzlJcckc8sdFYfWcuKK4Y ZucJRNfjBiAKygPyLMfGJL03y3KXnfTF1u923f3UpWgHnvjx8xh+w3Il0njvxQIZb+Ag5zwuI7X Zl+c3U1VXzILXJQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8150 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 158 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ---- 2 files changed, 158 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml new file mode 100644 index 000000000000..9d569644fda9 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8150 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ref # REFERENCE clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@1c00000 { + compatible = "qcom,pcie-sm8150"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ref"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 14341d210063..47888b5b1a13 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -35,7 +35,6 @@ properties: - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - - qcom,pcie-sm8150 - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 @@ -541,33 +540,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8150 - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ref # REFERENCE clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -729,7 +701,6 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 - - qcom,pcie-sm8150 - qcom,pcie-sm8350 then: oneOf: From patchwork Fri Jan 26 08:56:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13532260 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 618EA14198F for ; Fri, 26 Jan 2024 08:57:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259425; cv=none; b=DD30fHFcR51HkeULSe6PMYa+jjaWm1n+wCkjDNnvOIHALeeMVyrcYisT66UYo29/8MZ0sO0rkDa8W3yyi/VxuNPt/HBNVRATmKMujjCsykf51rcneSi26UL7+cq9mkKdaV0+o3PpFWQv/hBF3NSYE90ZDhw3a7kkbxYhaka2MBk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259425; c=relaxed/simple; bh=DcOFAHWw57OZ+USGEw+XzihLlIieJcir1fqf4uIwPcY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aAVpuom3guGCk9LlpbNMTTaYwGPmWg5psvWLsksOI+qCUZSL6UZINziVm53Kwbp/+ZLittcrv7O6nhzEGRK6bbHSwXtVQv3g0gTFbnpA7iyTW+Kl3wsIMoQ6z56TuCwKgRzGr5c7x+Z3TK9Z3jAsH0mMko9NOlbdQqbt08dz7P4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=QtzAp0wF; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QtzAp0wF" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40eac352733so4798425e9.0 for ; Fri, 26 Jan 2024 00:57:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706259421; x=1706864221; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NiqsI0Dmx9Laa0Xbfs3XWKEz2D4BJKsaR8JMAPM6FUQ=; b=QtzAp0wFOkAh0TX3nc4nbSDlHpT2aMYeMZVrQyO9eXcyBO/yUuI98fhTgDjkaoihj+ dA0U//BCOKA1hSufqqZHXtGBK0yr0puTEy0e7LAO77pa5f0G8LVpnTFFu7PHMeA2g68u RQAqgunxVWWc/tUZxgfH/oKZs2R2FEsMlFuWGgzxeoQ8K9PIQfnw/ulvqSxAPc0SPHJx giam1d0RXRdZ8HmeueF92zz/LZF8nlyKnI7boI++s751/2C7WvDnYV/zC60gZJi+dER6 x3Y1awlUsOUBve0tozf/X565Wc5k3k/gezGcPfUq75KCDjsHncYlsI8VH0OSQoRTfmz3 l4Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706259421; x=1706864221; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NiqsI0Dmx9Laa0Xbfs3XWKEz2D4BJKsaR8JMAPM6FUQ=; b=EFjBkTSti9RCkEXGip6l9MeCAN0TMDDITl1+Wwtm2TzLkd+/0lmyA8DKyyTcTc0plo 3YGbalz5U4O3W8ncM669IXo1evsc7lIdt2zDIZx5r2lPcdEu6dMj0Cdguf1YdfHIFozD rm90Cb3pv0RzA9mnB5rWevZ46YSfCP96dJ4u/hXQ4+vCV56T+3tFi4gEBFP90mZbimdB 3wjT4krMrKYPeAYNMlZXNnTCy4dN+O7+JtZyNNZKTAbwOyXKfqpQWK3/gFiK65BE94+E /lCxH+S+YWyvT4NfmtZWi9y8NYaDhrqJzOUtifMzh5d0W+L9SVDPLo7oy+j1PDZWcY6O M4Ww== X-Gm-Message-State: AOJu0Yyn3aWByT4Ymgef2W+17nBcyUIpMgXp+R+rY4qNHliorR2dZWU5 ABt5VXHe3lKhH9qhmOi3e50UsX5+LmjYnUUCerWKUG9OVvkV3c/HpORZYuvJijs= X-Google-Smtp-Source: AGHT+IGu/OyLRplENoo4b3nG+aQ5WEj2ZdTj4NbJWvhaezABZYQmhTS/5hG3eo/PR176Zye3wwb6Uw== X-Received: by 2002:a7b:c846:0:b0:40e:ce9e:fd00 with SMTP id c6-20020a7bc846000000b0040ece9efd00mr576153wml.167.1706259421652; Fri, 26 Jan 2024 00:57:01 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id q15-20020a170906b28f00b00a31710c0d32sm390522ejz.203.2024.01.26.00.57.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 00:57:01 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 26 Jan 2024 09:56:46 +0100 Subject: [PATCH v3 5/6] dt-bindings: PCI: qcom,pcie-sm8350: move SM8350 to dedicated schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-dt-bindings-pci-qcom-split-v3-5-f23cda4d74c0@linaro.org> References: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> In-Reply-To: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=8894; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=DcOFAHWw57OZ+USGEw+XzihLlIieJcir1fqf4uIwPcY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBls3PSJftBHqe48kaAp0sLizKmDvNbpT1HPZXRM 6NGK5VeLTOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbNz0gAKCRDBN2bmhouD 119OD/98jQ1yLgbl0mMrMm2A5nXm9/hU892DS58iB0jWuzpz228mxI6AXZlY9P/RW9JwnIkj8BP 1oXWh4evym5TIoKFgp+PDR32d329gdR6Zb/ZVATnXAqQjd7eUHuvND1DR0atKBXxzHTuyqaIncV a2f3WCgztqlwAxNReP8pRdkg4VHClv4nCYy0rgwOCROg20Hf+R0Ib2ZmRIxRJ2FZLatNtBtwjgW bq4Y7MdR6Oprzy/ZgVUvcqBKePKNwvGAJO/lipROzb8IwOQv8RkcmU8q3M6qrNs+EA+/dsJHraR fj1DPgOrJ5KUKoJ7Jz1jdeVkVXOrzA2erifaC4mh4GzNjXGmznjAHYDJr8EcddJWQ3CfndWzuKj Aq+OkitujE45ctkPLRYbTPWMVmPFFw2RUAslYpfMzlkOz2+FEPUrqBhjEUHXENfNTdBOeAhhqDK QPBDTNXu9Z444MROKAO1OSQeOfG0bvsmj6DfkUuQI9FZoyzVOCulAgnybS2kHSh2Ot4AjOqZ92Y 3OSnX/dL5nZjFYc+myBycqK+CgC98gE7JDEgzjWGSqehJ/mCK58H4nX/TUYHLJGhiaiXGgQMW/Q SyP/+COuk6Hq1jlBZ0sXJjMu0kx3DpPnsjLS0ObD27deazYr3BE/YQg0rsWvHPkodX8krof+s59 2Jq7YGMLQ9lFrug== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8350 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-sm8350.yaml | 184 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 32 ---- 2 files changed, 184 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml new file mode 100644 index 000000000000..9eb6e457b07f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8350 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1", + "aggre0"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 47888b5b1a13..6e03a1bce5d4 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -35,7 +35,6 @@ properties: - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -213,7 +212,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdx55 - - qcom,pcie-sm8350 then: properties: reg: @@ -540,35 +538,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8350 - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -701,7 +670,6 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 - - qcom,pcie-sm8350 then: oneOf: - properties: From patchwork Fri Jan 26 08:56:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13532261 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 242B51420A5 for ; Fri, 26 Jan 2024 08:57:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259427; cv=none; b=oliqpErF+SV7INogst/rSDeIIv/cPimbdV2A9i+yrZFdRgbWDjNG//pxDTyF7LCV4AEZrIiI7t/4U17i4fi5IQ3S+7KyV4XA5VG8JIBDzbQ3V8HqRMDnfg36KC7gxf/q+8UhgVp5A5GPrkL4mBqWYni4cDierxJuZjlQ+mlynZw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706259427; c=relaxed/simple; bh=Kpi+e1zOQGsMvKNsg7T6zt51ptrCq+dQp4qRk2qgV5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TjO028q4WPUMfka3aFYHdTxqzSxrYbgtFuiU+/Myz693onmdjY6SS+Jx3SQZrCg/4kZr5TnHGNjEjgFdkglJGHECxDDGOLjHsQDAmf7tL2ggVA1CRDaEhNi2wM0n1rj4eXwk6uNEIQO5SLNchPbpQvFxff+OQ69KTkAyEM9Okhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WkxT78/r; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WkxT78/r" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-55cec718c30so105390a12.1 for ; Fri, 26 Jan 2024 00:57:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706259423; x=1706864223; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0J42QZRyE7hua2zyqMdnH79xAYGxt1x2MM5KxH2NKU8=; b=WkxT78/rfuB5UDWTKVAgj3rgyer1KsKmGx/w83GnbsgC7y+eHIHOpfzzqzH3N59e1T R5hG6jcZFeKta8WWJP2dDgUlSZ7VsFVv63W2JoPKt0HF0sIE45Ei+Azlaky4LcPH2zhN UuedgxTF8YyKLUlZaUa4ZjpOrccnUuBSjmUwt0l+kpKW7FOvThENaxJS7ObiDL7QxfSM dC6h/iBhK9Fa7PCGPMkLPodNYIViT7s5ZSOJ0DYr6FtHQZwz7My9PD/qucy832dUKdFQ iJ1sZ7Dy4x+bgI736Eju26WoRt8SvUWiqSK+/Ly7ouEtrVrQta0gWyLYPO46+BWHZEek 2w0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706259423; x=1706864223; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0J42QZRyE7hua2zyqMdnH79xAYGxt1x2MM5KxH2NKU8=; b=wHNb3Cp/GxZkVbGOkFwsIRs3e8RsVkrBgu3ED0zWftFHXZAnq24e5C7c6jSPCVI932 ZqYJTPja2OmUGzXh66ojawAmf72JbewbM4QnFUfB7jnbcYekPMsT6/b7dpEmTW29zDBW HwPQXDmghgZ8fOc4hc+hVL3l4XKDGd8SO9A98acXWWkSRpcSOnLodrb1/bES8rY5EzQa RX1itYP5RVkQqagyS4sE0ct0yc1n/wnQNKaB23ydM6YIhCjpEKGP0MkdC4UDyFZCCa7W QxBLLzjDbP5i4vuoHVcwv0UhVK1gCSkBrKGSZn91ct7Fq1a1w5gNBusNP9LMKUf+T1LQ Td2g== X-Gm-Message-State: AOJu0Yy6WXzDDZk92KcStX0UtlOhVc4ElYglX+8hv4Lq9U93KMg8QtZz BW+mTHKz+c7V/agcaZ79APQc+C2bfmkz5NweZxXRoUMtqWPFZp7vjEzD8oHpCGE= X-Google-Smtp-Source: AGHT+IEQt7oXP4BNEp/z5lF/C/bK7R7a6/fQ7BPln//N4qg4+gccF0swSyFD5xc68f6gK7hjOeH0WQ== X-Received: by 2002:a17:906:7b86:b0:a34:a1ec:52c0 with SMTP id s6-20020a1709067b8600b00a34a1ec52c0mr419534ejo.41.1706259423449; Fri, 26 Jan 2024 00:57:03 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id q15-20020a170906b28f00b00a31710c0d32sm390522ejz.203.2024.01.26.00.57.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 00:57:03 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 26 Jan 2024 09:56:47 +0100 Subject: [PATCH v3 6/6] dt-bindings: PCI: qcom,pcie-sc8280xp: move SC8280XP to dedicated schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-dt-bindings-pci-qcom-split-v3-6-f23cda4d74c0@linaro.org> References: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> In-Reply-To: <20240126-dt-bindings-pci-qcom-split-v3-0-f23cda4d74c0@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9872; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=Kpi+e1zOQGsMvKNsg7T6zt51ptrCq+dQp4qRk2qgV5Q=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBls3PTQFu//+S9LbCVBLz41HSxf1FRH5PTzVTmf Lx/9vylNE6JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbNz0wAKCRDBN2bmhouD 10iwEACKoHtW3TLROfNr/ilxZvuTE34vuo+AGuospVmusS7wcWasbZ5/5/rXQXN9LMWVRjjhgyz /fk8BShRrYHEmQa0ErjZGgpUTqnZ9oExnBMqKnjV0vyWMqXEu3WM8Cvw6bsOJoMP5RGm54VoonF /KpbI9/rC1MDHoxKWzIW1KAuslYeAP6UGjN6Uotb5N2eNc1so7BHh9ECDznHBLwzGHckZpCLLrB mhlfWBYvT0JP9LseW/kDeqRrBD7/ovLuX0j2iXLFn9R0KvRXD+eUdTNPEnDhBoPRlABbbRzLuOy Bw3g6e51zXYzi7M9MP/fG0WlBQzpE++dREwpFYBj9GIoNrSTq2RLta8qcQkmUwqc704NiffyGG/ BfipfYI+dsFEOxzhEQLB2GX+Im7vuUvHlF2t6AzjQ9OJmdkgPGgC29grZWJ9si2rQXiruLVNjvZ 4WneqzSUQD0kKpFj6qR5YGNCyC01D+nHakDtepElAd9rxrDJdnNKd23gG2TxyT9osbO7N/RA5CT Cu496uK2S1g3mXdmhfOmnXZIOypHBpL+cLVmdnGNE7RVp7Yj2r2WRHNX25bHBBVrJM5/oHCP04b GXM1cpXlv/ILFYoOobb1kKHm10aUxcb+0ThMvtto/Ie07EqUjw6F32UX/g0kB0/VV3bgB8RoaQI FuU2GrN1FItywWg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SC8280XP compatible PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except missing required compatible which is actually redundant. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../bindings/pci/qcom,pcie-sc8280xp.yaml | 180 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 54 ------- 2 files changed, 180 insertions(+), 54 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml new file mode 100644 index 000000000000..25c9f13ae977 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sa8540p + - qcom,pcie-sc8280xp + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr_4 # NoC aggregate 4 clock + - const: noc_aggr_south_sf # NoC aggregate South SF clock + - const: cnoc_qx # Configuration NoC QX clock + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + + vddpe-3v3-supply: + description: A phandle to the PCIe endpoint power supply + +required: + - interconnects + - interconnect-names + +allOf: + - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c20000 { + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x3c000000 0x0 0xf1d>, + <0x0 0x3c000f20 0x0 0xa8>, + <0x0 0x3c001000 0x0 0x1000>, + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <2>; + num-lanes = <4>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; + assigned-clock-rates = <19200000>; + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + dma-coherent; + + interrupts = , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie2a_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie2a_default>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_2A_GDSC>; + + resets = <&gcc GCC_PCIE_2A_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&vreg_nvme>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 6e03a1bce5d4..c8f36978a94c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -28,11 +28,9 @@ properties: - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - items: @@ -210,7 +208,6 @@ allOf: - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdx55 then: properties: @@ -538,36 +535,6 @@ allOf: items: - const: pci # PCIe core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8540p - - qcom,pcie-sc8280xp - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr_4 # NoC aggregate 4 clock - - const: noc_aggr_south_sf # NoC aggregate South SF clock - - const: cnoc_qx # Configuration NoC QX clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -623,9 +590,7 @@ allOf: compatible: contains: enum: - - qcom,pcie-sa8540p - qcom,pcie-sa8775p - - qcom,pcie-sc8280xp then: required: - interconnects @@ -692,24 +657,6 @@ allOf: - const: msi6 - const: msi7 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc8280xp - then: - properties: - interrupts: - minItems: 4 - maxItems: 4 - interrupt-names: - items: - - const: msi0 - - const: msi1 - - const: msi2 - - const: msi3 - - if: properties: compatible: @@ -724,7 +671,6 @@ allOf: - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p then: properties: interrupts: