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[34.91.112.229]) by smtp.gmail.com with ESMTPSA id vi1-20020a170907d40100b00a2f48a43c3esm1152235ejc.7.2024.01.26.16.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 16:37:04 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/5] clk: samsung: gs101: gpio_peric0_pclk needs to be kept on Date: Sat, 27 Jan 2024 00:35:50 +0000 Message-ID: <20240127003607.501086-2-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240127003607.501086-1-andre.draszik@linaro.org> References: <20240127003607.501086-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This pclk clock is required any time we access the pinctrl registers of this block. Since pinctrl-samsung doesn't support a clock at the moment, we just keep the kernel from disabling it at boot, until we have an update for pinctrl-samsung to handle this required clock, at which point we'll be able to drop the flag again. Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Reviewed-by: Peter Griffin --- drivers/clk/samsung/clk-gs101.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 4a0520e825b6..61bb0dcf84ee 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2848,7 +2848,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, - 21, 0, 0), + 21, CLK_IGNORE_UNUSED, 0), /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", From patchwork Sat Jan 27 00:35:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 13533849 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 508F0A55 for ; Sat, 27 Jan 2024 00:37:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706315829; cv=none; b=KwFd7xflp60Z+5/SbbpSS8WwMI8jeYhCAiWdOpG7PHggbpKry/a1ofWQ5cGv4QCM74lZ+WMjEEQZldtlO1xxHYxVSEJikI7BcT4EoWdLfQ+DFMw7vrSZCL19iLEvUVp7F7ai1cYW2SAYrIf6/LvDWzRqUtnvAE/wHSF9gouMA14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706315829; c=relaxed/simple; bh=e67JZ6JR8CeyU6VdIHYyK7Ki6SpejtvxhPnH0TB4kOc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IsGwsVI1nWs6EcHj8uOLQ9uv/erOw5KoDae1EjEueSmAo+30eTGR2N5j91Kup90urlAN3GV2M5/0IGFkXO1tFgpgnJOiTzB8+pNIc5UEnwhDQr2mAA4gM9NJE5m1m391EbfKJAVnMYQih9dnjWBxBKFN5/0ezHEFr+ec49uW6iI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=w0XYvZ0L; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="w0XYvZ0L" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40e76109cdeso19828205e9.0 for ; Fri, 26 Jan 2024 16:37:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706315825; x=1706920625; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sm+b1B1zFt2eVB9+ThV9mqMVXPNNXKvJvmEo2SUwft8=; b=w0XYvZ0LYRfwScdXDUjTnkBjz94KPFW+5aKpFOffAzqSZeBqTHBY0qnuPT1RB8R3+z HT2O8weHD4scF0NhXsCPLiFUp+YnBFAvZDHuQcFA8xmoHSOy0JCsjn8pYGtT7WUmVDO6 33pj/EDFs6LwfcsrRzXGx4JRJ4SlrMDIAf6b5KAxf2e32LImDo8iNrqkHJxbx0+sL2m6 bJdj1Apqlyofvnt9z33tqZKiDWvOy5PghHcjFEDfJZkhermdGzuz+E7BZnins2ihHzpA L+VDSScT5ycghJpY6weapl6AJhLHrOSWb6NK3sZMnt9dW4cXueqGligUgfLL7DRDqrz9 c79g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706315825; x=1706920625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sm+b1B1zFt2eVB9+ThV9mqMVXPNNXKvJvmEo2SUwft8=; b=uim666fD84H6Bn4cvU4t+IlbE9uOSDxKvkadPqYWcM0hautXjCg7GJ21B/pntdEVDq sFcq5/im/u5q4cVkLICgFPxEcBi5T/8QVBF5kM4H/bUPxqH3Byxl/nwlpx8oxDT47gc/ 1FzGz1cRgVnKGdQu7CD02JB2wQaLoKtOdm9PLykXMzt1zwlkc5PGnMCyixhgTCusUOyk MgokK28zmnBZSBuHiCJQ9IKz0mtagfY2EgK1x28mYNgaUsyJhL6a4Vfg3yMUnDHFlfJ2 uUV9tKG9Mp8qzOAjvM585wy6aOZFTf5yVOX4tYaDPCKrxDlQ4t4d08N8J6XYWxFeFE8V Yozg== X-Gm-Message-State: AOJu0Yz7IdzxMYn1M/6idLOBtb36JNQAz2gj05i22YDYTajLDwn4TFEv lIVyZmvRVWFww3doJ+DXe2jVLMWvkYMyD+zE1JXSsYYd646LTm1kJDqQXZ8c++Y= X-Google-Smtp-Source: AGHT+IGeFh5Dj5LZw+UG+J/Z91OUe5JueC+Wd93apWSOWisW8wFE95eSjirZGUDRp0E34HcX4tKyGQ== X-Received: by 2002:a05:600c:5123:b0:40d:484e:935 with SMTP id o35-20020a05600c512300b0040d484e0935mr455010wms.12.1706315825706; Fri, 26 Jan 2024 16:37:05 -0800 (PST) Received: from puffmais.c.googlers.com.com (229.112.91.34.bc.googleusercontent.com. [34.91.112.229]) by smtp.gmail.com with ESMTPSA id vi1-20020a170907d40100b00a2f48a43c3esm1152235ejc.7.2024.01.26.16.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 16:37:05 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/5] arm64: dts: exynos: gs101: fix usi8 default mode Date: Sat, 27 Jan 2024 00:35:51 +0000 Message-ID: <20240127003607.501086-3-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240127003607.501086-1-andre.draszik@linaro.org> References: <20240127003607.501086-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 While commit 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C configuration") states that the USI8 CONFIG is 0 at reset, the boot loader has configured it by the time Linux runs and it has a different value at this stage. Since we want board DTS files to explicitly select the mode, we should set it to none here so as to ensure things don't work by accident and to make it clear that board DTS actually need to set the mode based on the configuration. Fixes: 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C configuration") Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Reviewed-by: Peter Griffin --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index aaac04df5e65..bc251e565be6 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -384,6 +384,7 @@ usi8: usi@109700c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x101c>; + samsung,mode = ; status = "disabled"; hsi2c_8: i2c@10970000 { From patchwork Sat Jan 27 00:35:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 13533851 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9F211371 for ; Sat, 27 Jan 2024 00:37:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706315830; cv=none; b=UguxA5EPS2gcTO8MqKx9CvmG+K90EnKnnGKQRNcTSHvDHNmjash0ZI5bqI8xzInt6xkrEIhiV7vKYoNMl5JGSnk+CvUuopt1VO62YersZ+Cact8CqkIJt/vCPXb2dRdNcTv/mGOJQrOGyMtvOvPcwEm/JLTlP0SfymnmNIQsDrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706315830; c=relaxed/simple; bh=/GiPFN5+QIgnjdQBA8vewMsdqYN795L0TQdClULeVuM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Iu+aqsusMxl8k0xF3IHhrHPxeycBTpimT7x2qNL3fr8Uu0RIug1xVpWIAiqXqYmx+RtNXRh8iCZN7u55VyAtod9PkVh7Bx/Nu1jxrV2DB8e4EA9PjIvVvjNidMxq/PttqZbjfxyOHuOves4dvl76iYVQmF3E76J+5JWwrx/GFR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=lefWfPh9; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lefWfPh9" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-55a539d205aso1063289a12.3 for ; Fri, 26 Jan 2024 16:37:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706315826; x=1706920626; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FJ73thBf2vHveKg87OgpLBqSvGw1l2TtG/ztHfLjlvM=; b=lefWfPh9GJ/MjcuUN9BLLLcXibRBb96oAnzt1TY9nJ1kZ5oH/4K2PR12QnRGcCAdYb W7PvQrENEd0ZgVeDQS1lAbfrPK3EPpLorTp/0uuqjTVj6fJh+aq1OYykrXXoUVDKz0Ye YX3JsMziNduUB9xj5IirWfX4Ek2iTb32e2rkTnxnmOu/60HwuQkvMFa6wCQ0JGSDzHhN yd0GJ4078Bv1vmfkywqrd0sFlPeRl7RjDml3LwOk2PeBXz9TOQjDMaw7eX/5hK9TeDr9 WvTohVDWERztZwTFcH9/flZZ9iWXIAVdTA9YPOY4NwaXU9J0uQZDJKhfr8dhlF0ZqFqJ i5vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706315826; x=1706920626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FJ73thBf2vHveKg87OgpLBqSvGw1l2TtG/ztHfLjlvM=; b=PqJd9dPOes88Aq2H1ACw50U+x6tIOTsuU21T1H8jGUIIdFxVY1oA+G9BW/naaR6UrM oNQOEBFBcLdCfO8UtWMP+aH088gSducVsd0tgeEJZTsJVgRrgkL8haDQwf7hBlIP2oBc YsO08NusNYkDJGLK9FQLeP8m0Nh33+Qp1t3jgUnuJ0iyklgYV1RhYSjOWsrd/hnYSbUO w0/X3fTRc/x74EIZspga9+SL16Mf6T0qpwZSLRYBjrN9qgloyKe+UHtgTlcg6L/nPKqm SHYAfeEvlhIT1KDFPSVrdqgmSvLa2jmaRkR2yBmn86/dL+u9eHRkQryH+mF/qZpJd7p7 vC/g== X-Gm-Message-State: AOJu0YydL812IKw/tS+cqwI4kFkluueIla5vOK2oq777MEVh2drJFFUf lj06/EIp+axIkB7blBb7w3YkVrO9rG1hLfWmS2lAF8+8d2sfWnLQf00yZZHNXcw= X-Google-Smtp-Source: AGHT+IF62xxAOQKXenjs9SveeU52YIbIa7O0bn1bom9ZOgfi70BpL/1L08c0EOj83Fz3C5giIBjR4w== X-Received: by 2002:a17:906:8308:b0:a31:3745:33fb with SMTP id j8-20020a170906830800b00a31374533fbmr530874ejx.51.1706315826128; Fri, 26 Jan 2024 16:37:06 -0800 (PST) Received: from puffmais.c.googlers.com.com (229.112.91.34.bc.googleusercontent.com. [34.91.112.229]) by smtp.gmail.com with ESMTPSA id vi1-20020a170907d40100b00a2f48a43c3esm1152235ejc.7.2024.01.26.16.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 16:37:05 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/5] arm64: dts: exynos: gs101: use correct clocks for usi8 Date: Sat, 27 Jan 2024 00:35:52 +0000 Message-ID: <20240127003607.501086-4-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240127003607.501086-1-andre.draszik@linaro.org> References: <20240127003607.501086-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Wrong pclk clocks have been used in this usi8 instance here. For USI and I2C, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI8_USI_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and i2c drivers. Update the DTSI accordingly. Fixes: 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C configuration") Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Tested-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index bc251e565be6..e5b665be2d62 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -380,7 +380,7 @@ usi8: usi@109700c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x101c>; @@ -397,7 +397,7 @@ hsi2c_8: i2c@10970000 { pinctrl-names = "default"; pinctrl-0 = <&hsi2c8_bus>; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, - <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; status = "disabled"; }; From patchwork Sat Jan 27 00:35:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 13533852 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4577B17D9 for ; Sat, 27 Jan 2024 00:37:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706315830; cv=none; b=SVunMGzSQZomOJdPngSzEp4edH44kcNcGnaUhlVzeZgB+iT51PtlV4WbIGspHR53QPQQQmktvoNUPO0WDwSRskpXKaXb53OB94q8Rf0RqIt8bpLuJCqQjZ48JVHgiHt7l3Ne7NQItMRuzMBH2D0VuI02HtJhpPJagAidoP0lvPg= ARC-Message-Signature: i=1; a=rsa-sha256; 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[34.91.112.229]) by smtp.gmail.com with ESMTPSA id vi1-20020a170907d40100b00a2f48a43c3esm1152235ejc.7.2024.01.26.16.37.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 16:37:06 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/5] arm64: dts: exynos: gs101: use correct clocks for usi_uart Date: Sat, 27 Jan 2024 00:35:53 +0000 Message-ID: <20240127003607.501086-5-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240127003607.501086-1-andre.draszik@linaro.org> References: <20240127003607.501086-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Wrong pclk clocks have been used in this usi8 instance here. For USI and UART, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI0_UART_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and uart drivers. Update the DTSI accordingly. Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Tested-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e5b665be2d62..f93e937d2726 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -410,7 +410,7 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; @@ -422,7 +422,7 @@ serial_0: serial@10a00000 { reg = <0x10a00000 0xc0>; interrupts = ; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 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[34.91.112.229]) by smtp.gmail.com with ESMTPSA id vi1-20020a170907d40100b00a2f48a43c3esm1152235ejc.7.2024.01.26.16.37.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 16:37:06 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 5/5] clk: samsung: gs101: don't mark non-essential clocks as critical Date: Sat, 27 Jan 2024 00:35:54 +0000 Message-ID: <20240127003607.501086-6-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240127003607.501086-1-andre.draszik@linaro.org> References: <20240127003607.501086-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to peric0/uart_usi, with pclk being the bus clock. Without pclk running, any bus access will hang. Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") the gs101 DT ended up specifying an incorrect pclkk in the respective node and instead the two clocks here were marked as critical. We have fixed the gs101 DT and can therefore drop this incorrect work-around here, the uart driver will claim these clocks as needed. Note that this commit has the side-effect of causing earlycon to stop to work sometime into the boot for two reasons: * peric0_top1_ipclk_0 requires its parent gout_cmu_peric0_ip to be running, but because earlycon doesn't deal with clocks that parent will be disabled when none of the other drivers that actually deal with clocks correctly require it to be running and the real serial driver (which does deal with clocks) hasn't taken over yet * hand-over between earlycon and serial driver appears to be fragile and clocks get enabled and disabled a few times, which also causes register access to hang while earlycon is still active Nonetheless we shouldn't keep these clocks running unconditionally just for earlycon. Clocks should be disabled where possible. If earlycon is required in the future, e.g. for debug, this commit can simply be reverted (locally!). Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/clk/samsung/clk-gs101.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 61bb0dcf84ee..5c338ac9231c 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2982,20 +2982,18 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,