From patchwork Tue Jan 30 16:15:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20BAEC48285 for ; Tue, 30 Jan 2024 16:16:06 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.19.1706631361058182438 for ; Tue, 30 Jan 2024 08:16:01 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="192259975" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:00 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1967F4003EC2; Wed, 31 Jan 2024 01:15:58 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 1/9] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties Date: Tue, 30 Jan 2024 16:15:47 +0000 Message-Id: <20240130161555.85042-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14502 commit 56a3840486ae22c42176828e25d4073712837bfd upstream. From R01UH0914EJ0120 Rev.1.20 HW manual, for full duplex channels (SSI0/1/3) dma_rt interrupt has now being marked as reserved and similarly for half duplex channel (SSI2) dma_rx and dma_tx interrupts have now being marked as reserved (this applies to RZ/G2L and alike SoC's). This patch updates the binding doc to match the same. While at it also updated the example node. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230217185225.43310-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Mark Brown Signed-off-by: Lad Prabhakar --- .../bindings/sound/renesas,rz-ssi.yaml | 21 +++++++++++-------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml index 0d98403751324..5bd86a685cf72 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml @@ -22,14 +22,18 @@ properties: maxItems: 1 interrupts: - maxItems: 4 + minItems: 2 + maxItems: 3 interrupt-names: - items: - - const: int_req - - const: dma_rx - - const: dma_tx - - const: dma_rt + oneOf: + - items: + - const: int_req + - const: dma_rx + - const: dma_tx + - items: + - const: int_req + - const: dma_rt clocks: maxItems: 4 @@ -103,9 +107,8 @@ examples: reg = <0x10049c00 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, <&audio_clk1>, From patchwork Tue Jan 30 16:15:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D81FC46CD2 for ; Tue, 30 Jan 2024 16:16:06 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.19.1706631361058182438 for ; Tue, 30 Jan 2024 08:16:03 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="192259979" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:02 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 16EE04003EC2; Wed, 31 Jan 2024 01:16:00 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 2/9] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Date: Tue, 30 Jan 2024 16:15:48 +0000 Message-Id: <20240130161555.85042-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14503 commit 38c042b59af0248a8b13f01b1a09d890997c9f6e upstream. For half duplex channels we dont have separate interrupts for Tx and Rx instead we have single interrupt Rt (where the signal for Rx and Tx is muxed). To handle such a case install a handler in case we have a dma_rt interrupt specified in the DT for the PIO mode. Note, for backward compatibility we check if the Rx and Tx interrupts are present first instead of checking Rt interrupt. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20230217185225.43310-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Mark Brown Signed-off-by: Lad Prabhakar --- sound/soc/sh/rz-ssi.c | 63 ++++++++++++++++++++++++++++++------------- 1 file changed, 44 insertions(+), 19 deletions(-) diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c index 4901a660ffc52..ff5a650ac2b1a 100644 --- a/sound/soc/sh/rz-ssi.c +++ b/sound/soc/sh/rz-ssi.c @@ -109,6 +109,7 @@ struct rz_ssi_priv { int irq_int; int irq_tx; int irq_rx; + int irq_rt; spinlock_t lock; @@ -565,6 +566,17 @@ static irqreturn_t rz_ssi_interrupt(int irq, void *data) rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); } + if (irq == ssi->irq_rt) { + struct snd_pcm_substream *substream = strm->substream; + + if (rz_ssi_stream_is_play(ssi, substream)) { + strm->transfer(ssi, &ssi->playback); + } else { + strm->transfer(ssi, &ssi->capture); + rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); + } + } + return IRQ_HANDLED; } @@ -992,26 +1004,39 @@ static int rz_ssi_probe(struct platform_device *pdev) if (!rz_ssi_is_dma_enabled(ssi)) { /* Tx and Rx interrupts (pio only) */ ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); - if (ssi->irq_tx < 0) - return ssi->irq_tx; - - ret = devm_request_irq(&pdev->dev, ssi->irq_tx, - &rz_ssi_interrupt, 0, - dev_name(&pdev->dev), ssi); - if (ret < 0) - return dev_err_probe(&pdev->dev, ret, - "irq request error (dma_tx)\n"); - ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); - if (ssi->irq_rx < 0) - return ssi->irq_rx; - - ret = devm_request_irq(&pdev->dev, ssi->irq_rx, - &rz_ssi_interrupt, 0, - dev_name(&pdev->dev), ssi); - if (ret < 0) - return dev_err_probe(&pdev->dev, ret, - "irq request error (dma_rx)\n"); + if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { + ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); + if (ssi->irq_rt < 0) + return ssi->irq_rt; + + ret = devm_request_irq(&pdev->dev, ssi->irq_rt, + &rz_ssi_interrupt, 0, + dev_name(&pdev->dev), ssi); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "irq request error (dma_tx)\n"); + } else { + if (ssi->irq_tx < 0) + return ssi->irq_tx; + + if (ssi->irq_rx < 0) + return ssi->irq_rx; + + ret = devm_request_irq(&pdev->dev, ssi->irq_tx, + &rz_ssi_interrupt, 0, + dev_name(&pdev->dev), ssi); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "irq request error (dma_tx)\n"); + + ret = devm_request_irq(&pdev->dev, ssi->irq_rx, + &rz_ssi_interrupt, 0, + dev_name(&pdev->dev), ssi); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "irq request error (dma_rx)\n"); + } } ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); From patchwork Tue Jan 30 16:15:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D873C48286 for ; Tue, 30 Jan 2024 16:16:06 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.19.1706631361058182438 for ; Tue, 30 Jan 2024 08:16:05 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="192259984" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:04 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 134664004BD4; Wed, 31 Jan 2024 01:16:02 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 3/9] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels Date: Tue, 30 Jan 2024 16:15:49 +0000 Message-Id: <20240130161555.85042-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14504 commit c2b0dc0e83ef4a74cbe381fd0c84cea16cf067f0 upstream. From R01UH0936EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: cd0339ec25895c0b ("arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 stub node") Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index d2de7c615aed4..fa2dfd5eee415 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -249,9 +249,8 @@ ssi0: ssi@10049c00 { reg = <0 0x10049c00 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -270,9 +269,8 @@ ssi1: ssi@1004a000 { reg = <0 0x1004a000 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -290,10 +288,8 @@ ssi2: ssi@1004a400 { "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; interrupts = , - , - , ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + interrupt-names = "int_req", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -312,9 +308,8 @@ ssi3: ssi@1004a800 { reg = <0 0x1004a800 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; From patchwork Tue Jan 30 16:15:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14D89C47DA9 for ; Tue, 30 Jan 2024 16:16:16 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.23.1706631367024829960 for ; Tue, 30 Jan 2024 08:16:07 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="196170644" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:06 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 112754003EC2; Wed, 31 Jan 2024 01:16:04 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 4/9] arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels Date: Tue, 30 Jan 2024 16:15:50 +0000 Message-Id: <20240130161555.85042-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14505 commit 5da750ddd96454757a3b467e968e3fb70bb12bc8 upstream. From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 92a341315afc9 ("arm64: dts: renesas: r9a07g044: Add SSI support") Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 0495f1168a6c6..f7edace31807e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -249,9 +249,8 @@ ssi0: ssi@10049c00 { reg = <0 0x10049c00 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -270,9 +269,8 @@ ssi1: ssi@1004a000 { reg = <0 0x1004a000 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -290,10 +288,8 @@ ssi2: ssi@1004a400 { "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; interrupts = , - , - , ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + interrupt-names = "int_req", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -312,9 +308,8 @@ ssi3: ssi@1004a800 { reg = <0 0x1004a800 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; From patchwork Tue Jan 30 16:15:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D42CC48286 for ; Tue, 30 Jan 2024 16:16:16 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.19.1706631361058182438 for ; Tue, 30 Jan 2024 08:16:08 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="192259988" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:08 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1206C4004494; Wed, 31 Jan 2024 01:16:06 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 5/9] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS Date: Tue, 30 Jan 2024 16:15:51 +0000 Message-Id: <20240130161555.85042-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14506 It makes sense to have the configuration options in board dts, so move PMOD_SCI0_EN macro to r9a07g043u11-smarc.dts. This is in preparation of re-using the SoM and carrier board DTSIs for RZ/Five SMARC EVK. Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 4 ++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 121e55282d181..d882661c6dde3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -6,6 +6,10 @@ */ /dts-v1/; + +/* Please set this macro to 1 for enabling SCI0 on PMOD1 */ +#define PMOD_SCI0_EN 0 + #include "r9a07g043.dtsi" #include "rzg2ul-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index c6981bea40a46..44d5c82a9f18a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -15,9 +15,6 @@ #define SW_SW0_DEV_SEL 1 #define SW_ET0_EN_N 1 -/* Please set this macro to 1 for enabling SCI0 on PMOD1 */ -#define PMOD_SCI0_EN 0 - #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" From patchwork Tue Jan 30 16:15:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AD92C4828C for ; Tue, 30 Jan 2024 16:16:16 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.23.1706631367024829960 for ; Tue, 30 Jan 2024 08:16:10 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="196170650" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:10 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0F1084004BD4; Wed, 31 Jan 2024 01:16:08 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 6/9] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS Date: Tue, 30 Jan 2024 16:15:52 +0000 Message-Id: <20240130161555.85042-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14507 commit 53072ba67e534ddd208697d3465004738f1d4d61 upstream. Move including the rzg2ul-smarc-som.dtsi from the carrier board rzg2ul-smarc.dtsi to the actual RZ/G2UL SMARC EVK board dts r9a07g043u11-smarc.dts. Also move the SW_SW0_DEV_SEL and SW_ET0_EN_N macros to board dts as they are used by SoM and carrier board DTS/I. This is in preparation of re-using the SoM and carrier board DTSIs for RZ/Five SMARC EVK. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220915165256.352843-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [PL: manually applied the changes] Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 11 +++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index d882661c6dde3..990cb897083cb 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -10,7 +10,18 @@ /* Please set this macro to 1 for enabling SCI0 on PMOD1 */ #define PMOD_SCI0_EN 0 +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, SPI1) + * Please change below macros according to SW1 setting on the SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + #include "r9a07g043.dtsi" +#include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 44d5c82a9f18a..56c0752977d26 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -5,17 +5,6 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ -/* - * DIP-Switch SW1 setting - * 1 : High; 0: Low - * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) - * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) - * Please change below macros according to SW1 setting - */ -#define SW_SW0_DEV_SEL 1 -#define SW_ET0_EN_N 1 - -#include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" From patchwork Tue Jan 30 16:15:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 393E7C48285 for ; Tue, 30 Jan 2024 16:16:16 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.19.1706631361058182438 for ; Tue, 30 Jan 2024 08:16:13 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="192259993" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:12 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1103F4004494; Wed, 31 Jan 2024 01:16:10 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 7/9] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Date: Tue, 30 Jan 2024 16:15:53 +0000 Message-Id: <20240130161555.85042-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14508 commit 49669da644cf000eb79dbede55bd04acf3f2f0a0 upstream. Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so that we can share the common parts of the SoC DTSI with the RZ/Five (RISC-V) SoC and the RZ/G2UL (ARM64) SoC. This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL (ARM64) SoC specific parts. No functional changes (same DTB). Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20221025220629.79321-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 301 +++++++++--------- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 12 + .../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +- 3 files changed, 163 insertions(+), 152 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index ba48156febe18..1422760a090bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ -#include #include / { @@ -107,10 +106,10 @@ ssi0: ssi@10049c00 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, @@ -128,10 +127,10 @@ ssi1: ssi@1004a000 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a000 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, @@ -149,10 +148,10 @@ ssi2: ssi@1004a400 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, @@ -170,10 +169,10 @@ ssi3: ssi@1004a800 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a800 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, @@ -190,9 +189,9 @@ ssi3: ssi@1004a800 { spi0: spi@1004ac00 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004ac00 0 0x400>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; resets = <&cpg R9A07G043_RSPI0_RST>; @@ -208,9 +207,9 @@ spi0: spi@1004ac00 { spi1: spi@1004b000 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004b000 0 0x400>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; resets = <&cpg R9A07G043_RSPI1_RST>; @@ -226,9 +225,9 @@ spi1: spi@1004b000 { spi2: spi@1004b400 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004b400 0 0x400>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; resets = <&cpg R9A07G043_RSPI2_RST>; @@ -245,12 +244,12 @@ scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; @@ -264,12 +263,12 @@ scif1: serial@1004bc00 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004bc00 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; @@ -283,12 +282,12 @@ scif2: serial@1004c000 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c000 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; @@ -302,12 +301,12 @@ scif3: serial@1004c400 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c400 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; @@ -321,12 +320,12 @@ scif4: serial@1004c800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c800 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; @@ -339,10 +338,10 @@ scif4: serial@1004c800 { sci0: serial@1004d000 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; clock-names = "fck"; @@ -354,10 +353,10 @@ sci0: serial@1004d000 { sci1: serial@1004d400 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; clock-names = "fck"; @@ -369,14 +368,14 @@ sci1: serial@1004d400 { canfd: can@10050000 { compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "g_err", "g_recc", "ch0_err", "ch0_rec", "ch0_trx", "ch1_err", "ch1_rec", "ch1_trx"; @@ -405,14 +404,14 @@ i2c0: i2c@10058000 { #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; @@ -427,14 +426,14 @@ i2c1: i2c@10058400 { #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; @@ -449,14 +448,14 @@ i2c2: i2c@10058800 { #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058800 0 0x400>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; @@ -471,14 +470,14 @@ i2c3: i2c@10058c00 { #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; @@ -491,7 +490,7 @@ i2c3: i2c@10058c00 { adc: adc@10059000 { compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, <&cpg CPG_MOD R9A07G043_ADC_PCLK>; clock-names = "adclk", "pclk"; @@ -551,10 +550,10 @@ cpg: clock-controller@11010000 { sysc: system-controller@11020000 { compatible = "renesas,r9a07g043-sysc"; reg = <0 0x11020000 0 0x10000>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; status = "disabled"; @@ -578,23 +577,23 @@ dmac: dma-controller@11820000 { "renesas,rz-dmac"; reg = <0 0x11820000 0 0x10000>, <0 0x11830000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", @@ -625,8 +624,8 @@ sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - interrupts = , - ; + interrupts = , + ; clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, @@ -641,8 +640,8 @@ sdhi1: mmc@11c10000 { compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - interrupts = , - ; + interrupts = , + ; clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, @@ -657,9 +656,9 @@ eth0: ethernet@11c20000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; reg = <0 0x11c20000 0 0x10000>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "mux", "fil", "arp_ns"; phy-mode = "rgmii"; clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, @@ -677,9 +676,9 @@ eth1: ethernet@11c30000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; reg = <0 0x11c30000 0 0x10000>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "mux", "fil", "arp_ns"; phy-mode = "rgmii"; clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, @@ -707,7 +706,7 @@ phyrst: usbphy-ctrl@11c40000 { ohci0: usb@11c50000 { compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>, @@ -721,7 +720,7 @@ ohci0: usb@11c50000 { ohci1: usb@11c70000 { compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>, @@ -735,7 +734,7 @@ ohci1: usb@11c70000 { ehci0: usb@11c50100 { compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>, @@ -750,7 +749,7 @@ ehci0: usb@11c50100 { ehci1: usb@11c70100 { compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>, @@ -766,7 +765,7 @@ usb2_phy0: usb-phy@11c50200 { compatible = "renesas,usb2-phy-r9a07g043", "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>; @@ -779,7 +778,7 @@ usb2_phy1: usb-phy@11c70200 { compatible = "renesas,usb2-phy-r9a07g043", "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>; @@ -792,10 +791,10 @@ hsusb: usb@11c60000 { compatible = "renesas,usbhs-r9a07g043", "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; resets = <&phyrst 0>, @@ -814,8 +813,8 @@ wdt0: watchdog@12800800 { clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, <&cpg CPG_MOD R9A07G043_WDT0_CLK>; clock-names = "pclk", "oscclk"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A07G043_WDT0_PRESETN>; power-domains = <&cpg>; @@ -826,7 +825,7 @@ ostm0: timer@12801000 { compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; resets = <&cpg R9A07G043_OSTM0_PRESETZ>; power-domains = <&cpg>; @@ -837,7 +836,7 @@ ostm1: timer@12801400 { compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; resets = <&cpg R9A07G043_OSTM1_PRESETZ>; power-domains = <&cpg>; @@ -848,7 +847,7 @@ ostm2: timer@12801800 { compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; resets = <&cpg R9A07G043_OSTM2_PRESETZ>; power-domains = <&cpg>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi new file mode 100644 index 0000000000000..96f935bc2d4d1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include "r9a07g043.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 990cb897083cb..bfe0e9f128a31 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -20,7 +20,7 @@ #define SW_SW0_DEV_SEL 1 #define SW_ET0_EN_N 1 -#include "r9a07g043.dtsi" +#include "r9a07g043u.dtsi" #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc.dtsi" From patchwork Tue Jan 30 16:15:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14CC4C46CD2 for ; Tue, 30 Jan 2024 16:16:16 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.19.1706631361058182438 for ; Tue, 30 Jan 2024 08:16:15 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="192259998" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:14 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1288E4003EC2; Wed, 31 Jan 2024 01:16:12 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 8/9] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels Date: Tue, 30 Jan 2024 16:15:54 +0000 Message-Id: <20240130161555.85042-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14509 commit 2a5c9891392dca47f6865a2add1986876e40849c upstream. From R01UH0968EJ0100 Rev.1.00 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 559f2b0708c70 ("arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node") Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230217185225.43310-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 1422760a090bc..ca937f88406c2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -108,9 +108,8 @@ ssi0: ssi@10049c00 { reg = <0 0x10049c00 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -129,9 +128,8 @@ ssi1: ssi@1004a000 { reg = <0 0x1004a000 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -149,10 +147,8 @@ ssi2: ssi@1004a400 { "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; interrupts = , - , - , ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + interrupt-names = "int_req", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -171,9 +167,8 @@ ssi3: ssi@1004a800 { reg = <0 0x1004a800 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; From patchwork Tue Jan 30 16:15:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13537693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3136CC47DA9 for ; Tue, 30 Jan 2024 16:16:26 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.19.1706631361058182438 for ; Tue, 30 Jan 2024 08:16:17 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,230,1701097200"; d="scan'208";a="192260001" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 31 Jan 2024 01:16:16 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.7]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 26F084003EC2; Wed, 31 Jan 2024 01:16:14 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 9/9] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Date: Tue, 30 Jan 2024 16:15:55 +0000 Message-Id: <20240130161555.85042-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 30 Jan 2024 16:16:26 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14510 commit b9a0be2054964026aa58966ce9724b672f210835 upstream. Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC). Below are the changes due to which SoC specific parts are moved to r9a07g043u.dtsi: - RZ/G2UL has Cortex-A55 (ARM64) whereas RZ/Five has AX45MP (RISC-V), - RZ/G2UL has GICv3 as interrupt controller whereas RZ/Five has PLIC, - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing for SYSC block on RZ/Five, - RZ/G2UL has armv8-timer whereas RZ/Five has riscv-timer, - RZ/G2UL has PSCI whereas RZ/Five have OpenSBI. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 54 +------------------ arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 60 +++++++++++++++++++++ 2 files changed, 61 insertions(+), 53 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index ca937f88406c2..5f534db54d1c5 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2UL SoC + * Device Tree Source for the RZ/Five and RZ/G2UL SoCs * * Copyright (C) 2022 Renesas Electronics Corp. */ @@ -68,36 +68,8 @@ opp-1000000000 { }; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a55"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - next-level-cache = <&L3_CA55>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; - operating-points-v2 = <&cluster0_opp>; - }; - - L3_CA55: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-size = <0x40000>; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -545,12 +517,6 @@ cpg: clock-controller@11010000 { sysc: system-controller@11020000 { compatible = "renesas,r9a07g043-sysc"; reg = <0 0x11020000 0 0x10000>; - interrupts = , - , - , - ; - interrupt-names = "lpm_int", "ca55stbydone_int", - "cm33stbyr_int", "ca55_deny"; status = "disabled"; }; @@ -605,16 +571,6 @@ dmac: dma-controller@11820000 { dma-channels = <16>; }; - gic: interrupt-controller@11900000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; - interrupts = ; - }; - sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; @@ -880,12 +836,4 @@ target: trip-point { }; }; }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 96f935bc2d4d1..b8bf06b512351 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -10,3 +10,63 @@ #define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr #include "r9a07g043.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = ; + }; +}; + +&sysc { + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; +};