From patchwork Wed Jan 31 12:10:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13539389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC39EC47DB3 for ; Wed, 31 Jan 2024 12:11:25 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.673990.1048627 (Exim 4.92) (envelope-from ) id 1rV9Qz-0006qU-PU; Wed, 31 Jan 2024 12:11:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 673990.1048627; Wed, 31 Jan 2024 12:11:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rV9Qz-0006qJ-M7; Wed, 31 Jan 2024 12:11:17 +0000 Received: by outflank-mailman (input) for mailman id 673990; Wed, 31 Jan 2024 12:11:16 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rV9Qy-0006Ur-PA for xen-devel@lists.xenproject.org; Wed, 31 Jan 2024 12:11:16 +0000 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on20600.outbound.protection.outlook.com [2a01:111:f403:2412::600]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d3f7b16e-c031-11ee-98f5-efadbce2ee36; Wed, 31 Jan 2024 13:11:15 +0100 (CET) Received: from PA7P264CA0289.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:370::6) by PH7PR12MB7793.namprd12.prod.outlook.com (2603:10b6:510:270::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.34; Wed, 31 Jan 2024 12:11:10 +0000 Received: from SA2PEPF000015C8.namprd03.prod.outlook.com (2603:10a6:102:370:cafe::54) by PA7P264CA0289.outlook.office365.com (2603:10a6:102:370::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.32 via Frontend Transport; Wed, 31 Jan 2024 12:11:09 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SA2PEPF000015C8.mail.protection.outlook.com (10.167.241.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Wed, 31 Jan 2024 12:11:08 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 31 Jan 2024 06:11:04 -0600 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Wed, 31 Jan 2024 06:11:03 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d3f7b16e-c031-11ee-98f5-efadbce2ee36 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VIF5jzEZSC9rqRYnowSpYkC33zrExhFS7J6fJxQ0hPz3goYkjZpllFcMVGJro2Sr/yWIiksURzmJvXQCarUG0qwuWQ/seIz3v7rKw+V7nfVeJ2owygfbqIvtlVW2E4PnjYs0m8HAVnuq62Wnny6httsGWy5SbppgGRix0OEl4wRDxWXRFF7DJ4dj1kzXnyAQSWB0BVNnhl4I2f4eDDZv0lqq/f5dvWlZlSIeHt6IVLNPcKwTBb6R2qrnOd/TEFem3cmK/gPU4SLFqm9IOxv+u19ZfLEmVGep0DrsLIsh5BDTpa9zEpR07yOauY15T8HUoTAHs7bnhG+6Oz4Q/PPQrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fVnAE3Sk2Vh8GnJN0eIurwnYEGeWl1AfkF0U3da74B4=; b=BgWB6w8CVhsH+zNVZG+ht64a6M5i17Qn9AXqnAr9agSZW4KQVS86I8lZnO9NlGn6BLF9K8axBWJygIdJbIcjn8Rs0wf0Ez+uVlUrvIJ5HKOHQru+nDX1ymQXO+4NTJIvY2Cp202mtpWA4dqsxM1wt4vAoIaYC00OX0JO1oMGl+No5YRTOhHwyGGEMumBRHounplGsfytO5kzIfKwbL6ks5EhOeXLYfWw442kXvZOQA8TwujrK1xPZKftKh7AHXRPdlogU4wFSh55HOKuteXU3QJUnogu4G64c5KkkzWBnFGeuFyd4y6FHnCN4TtiYqzRanl1a3y99TN8O5mt6PcLJg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fVnAE3Sk2Vh8GnJN0eIurwnYEGeWl1AfkF0U3da74B4=; b=Gvc/bx5L2mj3tmhhh8sKBJF/IiSTzDcFcsqvUT10lZuYqrRlYtOx9nq6j/pGfDWfuOhFJ06C5afS+GKXnX8UojdMGZizzs98tx2Pax4VhsmXiXv1h9cIhPK+kdjGfWhVs8Ab+ptz7iuYc7rQKgtwKOxiajGO+PSKTIx0wr4JHaI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , Ayan Kumar Halder Subject: [XEN v4 1/3] xen/arm: Introduce CONFIG_PARTIAL_EMULATION and "partial-emulation" cmd option Date: Wed, 31 Jan 2024 12:10:47 +0000 Message-ID: <20240131121049.225044-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240131121049.225044-1-ayan.kumar.halder@amd.com> References: <20240131121049.225044-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|PH7PR12MB7793:EE_ X-MS-Office365-Filtering-Correlation-Id: e7fe2a37-613e-424b-7572-08dc2255b541 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HwoELydrYRFq+x9h7FaTjtBWWIUO4eRUuR4fOvupvxVVh4HjZR+xcWCLnIUomiVf22cXxNSTm9MUYuUmfnHucTrzL3ZMwHyKs0gqDXJRgKSO2bf7qYp/TTyhOYp5dGOYxbXgEof4VvSSm0RyXzPYrxs4iB/Jt2Fs05mjI6s4GukR4TZlMHIN9vo0wmPp2gKapFHt+/m3NKOTaorG1bY6bKIKdIKyR0HHjUvMv/ee2gjnqgqAJ7TZ7DmDPyo0DMku8stv7ZAxu145uNZSMNd59J3r0SrQ3gbkXcBLPc3PbFsdy4bV3JZiFihIdJgC+srGC3L8m0by1W3JBzXk7fs0k2AYI9zosyo7gEBYK738uNKodwKIgmNP9e7atNVqOsRpqckrU0DiHO3EBfr2dYT0NcYNUrV2+j/Z8WTTDtJeYW/CyXODkf98yFNN6sPiLLsZ4iEKLnYDN56rS9Vm43qJdEtlzWUwcL1X+lKtavZXuNczqGiz0WVuiTk/Ci6Dw8k07Zmq4oFzWmnA00TYw3bregodg4RPeqXYiv+p4ZEly1kbsSwmlH1Q8SJgV1/C6cHxfZeGI+F3ElYtzZOeN58YP0QExbbNYi2jgugOKLWWFLyeqTCLrNRZAwOMV553ZcCDMU37gaOUWsWekvWrZZQlAYEGNNKPYs7pP75ovE/ttAdrDO0RRPX36X1fkypICj9YDweZ3gR5ATY1JQyq+2fUz2mRYWnDpXd1SCBIFQZezL1118gtV/RLclcpkAFmSFw6mJOWlYiouBj1Hd6xQNe1YyJhNiejd78s8XB1Ve7ia6tYFkNeOKD15WruTFsTSG9J X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(376002)(346002)(39860400002)(230273577357003)(230173577357003)(230922051799003)(451199024)(64100799003)(1800799012)(82310400011)(186009)(40470700004)(46966006)(36840700001)(316002)(6916009)(356005)(2906002)(40460700003)(40480700001)(54906003)(36860700001)(8936002)(36756003)(8676002)(4326008)(47076005)(86362001)(5660300002)(70206006)(81166007)(103116003)(70586007)(82740400003)(83380400001)(26005)(426003)(336012)(1076003)(2616005)(6666004)(41300700001)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2024 12:11:08.7829 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7fe2a37-613e-424b-7572-08dc2255b541 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7793 There can be situations when the registers cannot be emulated to their full functionality. This can be due to the complexity involved. In such cases, one can emulate those registers as RAZ/WI for example. We call them as partial emulation. Some registers are non-optional and as such there is nothing preventing an OS from accessing them. Instead of injecting undefined exception (thus crashing a guest), one may want to prefer a partial emulation to let the guest running (in some cases accepting the fact that it might result in unwanted behavior). A suitable example of this (as seen in subsequent patches) is emulation of DBGDTRTX_EL0 (on Arm64) and DBGDTRTXINT(on Arm32). These non-optional registers can be emulated as RAZ/WI and they can be enclosed within CONFIG_PARTIAL_EMULATION. Further, "partial-emulation" command line option allows us to enable/disable partial emulation at run time. While CONFIG_PARTIAL_EMULATION enables support for partial emulation at compile time (i.e. adds code for partial emulation), this option may be enabled or disabled by Yocto or other build systems. However if the build system turns this option on, users can use scripts like Imagebuilder to generate uboot-script which will append "partial-emulation=false" to xen command line to turn off the partial emulation. Thus, it helps to avoid rebuilding xen. By default, "CONFIG_PARTIAL_EMULATION=y" and "partial-emulation=false". This is done so that Xen supports partial emulation. However, customers are fully aware when they enable partial emulation. It's important to note that enabling such support might result in unwanted/non-spec compliant behavior. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel --- Changes from v1 :- 1. New patch introduced in v2. v2 :- 1. Reordered the patches so that the config and command line option is introduced in the first patch. v3 :- 1. Defined a macro 'partial_emulation' to reduce if-defs. 2. Fixed style issues. docs/misc/xen-command-line.pandoc | 11 +++++++++++ xen/arch/arm/Kconfig | 9 +++++++++ xen/arch/arm/include/asm/traps.h | 6 ++++++ xen/arch/arm/traps.c | 9 +++++++++ 4 files changed, 35 insertions(+) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 8e65f8bd18..22c0d7c9f6 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1949,6 +1949,17 @@ This option is ignored in **pv-shim** mode. > Default: `on` +### partial-emulation (arm) +> `= ` + +> Default: `false` + +Flag to enable or disable partial emulation of system/coprocessor registers. +Only effective if CONFIG_PARTIAL_EMULATION is enabled. + +**WARNING: Enabling this option might result in unwanted/non-spec compliant +behavior.** + ### pci = List of [ serr=, perr= ] diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 50e9bfae1a..8d8f668e7f 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -225,6 +225,15 @@ config STATIC_EVTCHN This option enables establishing static event channel communication between domains on a dom0less system (domU-domU as well as domU-dom0). +config PARTIAL_EMULATION + bool "Enable partial emulation of system/coprocessor registers" + default y + help + This option enables partial emulation of registers to prevent guests + crashing when accessing registers which are not optional but have not been + emulated to its complete functionality. Enabling this might result in + unwanted/non-spec compliant behavior. + endmenu menu "ARM errata workaround via the alternative framework" diff --git a/xen/arch/arm/include/asm/traps.h b/xen/arch/arm/include/asm/traps.h index 883dae368e..9a60dbf70e 100644 --- a/xen/arch/arm/include/asm/traps.h +++ b/xen/arch/arm/include/asm/traps.h @@ -10,6 +10,12 @@ # include #endif +#ifdef CONFIG_PARTIAL_EMULATION +extern bool partial_emulation; +#else +#define partial_emulation false +#endif + /* * GUEST_BUG_ON is intended for checking that the guest state has not been * corrupted in hardware and/or that the hardware behaves as we diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 9c10e8f78c..d1c7a6c516 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -42,6 +42,15 @@ #include #include +/* + * partial_emulation: If true, partial emulation for system/coprocessor + * registers will be enabled. + */ +#ifdef CONFIG_PARTIAL_EMULATION +bool __ro_after_init partial_emulation = false; +boolean_param("partial-emulation", partial_emulation); +#endif + /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in * entry.S) and struct cpu_info (which lives at the bottom of a Xen From patchwork Wed Jan 31 12:10:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13539394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34CC2C47258 for ; Wed, 31 Jan 2024 12:14:40 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.673998.1048636 (Exim 4.92) (envelope-from ) id 1rV9U2-00083M-AZ; Wed, 31 Jan 2024 12:14:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 673998.1048636; Wed, 31 Jan 2024 12:14:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rV9U2-00083F-7u; Wed, 31 Jan 2024 12:14:26 +0000 Received: by outflank-mailman (input) for mailman id 673998; Wed, 31 Jan 2024 12:14:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rV9U0-000834-7y for xen-devel@lists.xenproject.org; Wed, 31 Jan 2024 12:14:24 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on20600.outbound.protection.outlook.com [2a01:111:f403:200a::600]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 441759fa-c032-11ee-8a43-1f161083a0e0; Wed, 31 Jan 2024 13:14:23 +0100 (CET) Received: from BYAPR07CA0028.namprd07.prod.outlook.com (2603:10b6:a02:bc::41) by CH0PR12MB8551.namprd12.prod.outlook.com (2603:10b6:610:186::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.34; Wed, 31 Jan 2024 12:14:19 +0000 Received: from SJ5PEPF000001D6.namprd05.prod.outlook.com (2603:10b6:a02:bc:cafe::23) by BYAPR07CA0028.outlook.office365.com (2603:10b6:a02:bc::41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.24 via Frontend Transport; Wed, 31 Jan 2024 12:14:19 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ5PEPF000001D6.mail.protection.outlook.com (10.167.242.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Wed, 31 Jan 2024 12:14:18 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 31 Jan 2024 06:14:17 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Wed, 31 Jan 2024 04:14:17 -0800 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Wed, 31 Jan 2024 06:14:16 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 441759fa-c032-11ee-8a43-1f161083a0e0 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=khbnwKU42Meo9RYKtHbiYZZEYD0rmS2YYxCEqJ3LRp0fdNJsxTKip7WJ6oHreCxtXanwk8GSWp2GTIQDQHV3PECdACXJ936KDQNfSGZ2o6pp0V9CPGxyjGrWMTlBhLXhHVspSPjUShc6tkNTUdNgHMyQT2kzmPhXB7Ho9CrR3F3RfUFo5WqiP5P3TLmz48XqjhTJrco8wicYORYLfg8cXRBoylvQ536AmJCfUCcbsNi2WLqWatV/fT1QJZHa7RVUWauIUWrTOtuP+HI89h2ldzSrCjiptZqzBmEnJTCDaG+grJLzheT9ql0yVL7USldfHIEaR7JCa63azuVl0fEQ0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fKVsyO8xIRiExnyh4ryfpCBXOBzr72XwASsT+kuql3k=; b=YZGmoEHBavFux0pKAY0A1lDBVyNzAyACYP476AN6rRvz+NEh4UTxwMPpA9l3MERpap7RrOVGTyToWe7GiqxzEnmIzCo6CAgg/xoyAkMPVcbAFjpiPGgR8efSshSNcFdZ+GeeygBTjNRO+Liung4/DkbW3Kj4QxP9IkHv07FS4z7UYO/YCgmkzZn30o25/FKtISZInAYlLI1b0VHmKItrZq+Xun1FuCI8Zusk87/fT6OIZEt6XImxC62TcUI5ERZUt9gz40At5rmFIWyTAeXhopFMKn/p9vYN2iXDcbOxxzo7sBL1ghkKDa0GG9qkIIwOOs3O2OJB81l+IByvJ0xCMg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fKVsyO8xIRiExnyh4ryfpCBXOBzr72XwASsT+kuql3k=; b=PHO6cn73u4XXCKOllRjdIFMXjbBoA+G2/O7KNpfGmERLR7o5AFJjUgEQIvRvg6+jEBmtVJhVW270G9ymP/Vvs3sef7icpegql/GgbYBpnez7PHLhG+6AW9Yk1xgw0/EJ814Bvcg0Pd66SQUa48MkBpcl4d9HHhrOGNNdXQXrrvU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , Ayan Kumar Halder Subject: [XEN v4 2/3] xen/arm: arm64: Add emulation of Debug Data Transfer Registers Date: Wed, 31 Jan 2024 12:10:48 +0000 Message-ID: <20240131121049.225044-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240131121049.225044-1-ayan.kumar.halder@amd.com> References: <20240131121049.225044-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D6:EE_|CH0PR12MB8551:EE_ X-MS-Office365-Filtering-Correlation-Id: ad937851-3f65-4330-8dbe-08dc22562672 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: i6EgjIQDpl29VgWpO5SNz8tRbuXyDKXaOcheGEHwR+Y2GHKYABO5SXyfUTBqBrCoeX6PrwYk9YlwAi4umnjmgDBpRnNQkQah/lsmeqJUSsJx3cG4lGMH8nAlFIqbT6M5yCjwCJq05LPC9z6NQB1L1hPwsIEx5Av5riL6PWjuw+n9SzElqtqAvNLVbf8OGOW7XZ8oXuUeSg17aENVwPyI0ztdFtG7n5kSs+dUzTyRgqEKbmTMlfBeIrdBjG5i1Sa+xQ/EIqxdLhJDvpCKKBlP4zoQPjBUV/EBQlI1zgEhWV15AqTVDSzRlzX3KgdmSrwDWn31zUHIFmVAgvmPXP52e3CXMFUrZBAxytClAZpYzZl/1GkXOJaTPeGvmSmvBl/jJHG7G3ISXFfI/MZsAyZCjQDtaGX8SYEKkqlwoQSEFSgwscBmdpRCSJ/cSI/Ho+FqcznQE94VRldJwHn5JHkXGvVQGIsH8QOjTaq5RKmXUW8jkf0imKWEurVTeVfAG46ANqTCY6wJa88nxJA37R/BK6pBlV/8x6IOXrHOW44PHnlWtXhJBG4wtVRablwMN6k5xKuTEVslGY6mGOIZ6NI19jywgeJtReqosA7pHsJfTAF/dQ0lkSPMxY3UdDJZESZlpcQYZUy9DjescWUjezZave7IsAv2NKzp/Jddoxy/hfh2oh8BpyTqnmHhcPdM0RPaNL7k3/uXTVvo+NwZx4Kgy7aaVdhcjnNDdTD2JpNaC7+vbU5/RmkdyOte2vT/zxHWchHWYdu5s+scsAMuwjTEJA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(346002)(376002)(136003)(230922051799003)(64100799003)(186009)(82310400011)(1800799012)(451199024)(46966006)(36840700001)(40470700004)(6916009)(316002)(70206006)(54906003)(478600001)(70586007)(6666004)(8936002)(8676002)(4326008)(1076003)(5660300002)(26005)(426003)(2616005)(336012)(2906002)(83380400001)(47076005)(81166007)(40460700003)(82740400003)(86362001)(40480700001)(41300700001)(36756003)(103116003)(36860700001)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2024 12:14:18.5934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad937851-3f65-4330-8dbe-08dc22562672 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8551 From: Michal Orzel Currently, if user enables HVC_DCC config option in Linux, it invokes access to debug data transfer registers (i.e. DBGDTRTX_EL0 on arm64, DBGDTRTXINT on arm32). As these registers are not emulated, Xen injects an undefined exception to the guest and Linux crashes. To prevent this crash, introduce a partial emulation of DBGDTR[TR]X_EL0 (these registers share the same encoding) as RAZ/WI and MDCCSR_EL0 as TXfull. Refer ARM DDI 0487J.a ID042523, D19.3.8, DBGDTRTX_EL0 "If TXfull is set to 1, set DTRRX and DTRTX to UNKNOWN". Thus, any OS is expected to read MDCCSR_EL0 and check for TXfull before using DBGDTRTX_EL0. Linux does it via hvc_dcc_init() ---> hvc_dcc_check(), and returns -ENODEV in case TXfull bit is still set after writing a test character. This way we prevent the guest from making use of HVC DCC as a console. Signed-off-by: Michal Orzel Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Signed-off-by: Michal Orzel Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel --- Changes from v1 :- 1. DBGDTR_EL0 does not emulate RXfull. This is to avoid giving the OS any indication that the RX buffer is full and is waiting to be read. 2. In Arm32, DBGOSLSR is emulated. Also DBGDTRTXINT is emulated at EL0 only. 3. Fixed the commit message and inline code comments. v2 :- 1. Split the patch into two (separate patches for arm64 and arm32). 2. Removed the "fail" label. 3. Fixed the commit message. v3 :- 1. "HSR_SYSREG_MDCCSR_EL0" emulation differs based on whether partial_emulation_enabled is true or not. 2. If partial_emulation_enabled is false, then access to HSR_SYSREG_DBGDTR_EL0, HSR_SYSREG_DBGDTRTX_EL0 would lead to undefined exception. xen/arch/arm/arm64/vsysreg.c | 28 ++++++++++++++++++++++++---- xen/arch/arm/include/asm/arm64/hsr.h | 3 +++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index b5d54c569b..94f0a6c384 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -159,9 +159,6 @@ void do_sysreg(struct cpu_user_regs *regs, * * Unhandled: * MDCCINT_EL1 - * DBGDTR_EL0 - * DBGDTRRX_EL0 - * DBGDTRTX_EL0 * OSDTRRX_EL1 * OSDTRTX_EL1 * OSECCR_EL1 @@ -173,10 +170,32 @@ void do_sysreg(struct cpu_user_regs *regs, return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); case HSR_SYSREG_MDCCSR_EL0: /* + * Xen doesn't expose a real (or emulated) Debug Communications Channel + * (DCC) to a domain. Yet the Arm ARM implies this is not an optional + * feature. So some domains may start to probe it. For instance, the + * HVC_DCC driver in Linux (since f377775dc083 and at least up to v6.7), + * will try to write some characters and check if the transmit buffer + * has emptied. + * + * By setting TX status bit (only if partial emulation is enabled) to + * indicate the transmit buffer is full, we would hint the OS that the + * DCC is probably not working. + * + * Bit 29: TX full + * * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate that * register as RAZ/WI above. So RO at both EL0 and EL1. */ - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 0, + partial_emulation ? (1U << 29) : 0); + + case HSR_SYSREG_DBGDTR_EL0: + /* DBGDTR[TR]X_EL0 share the same encoding */ + case HSR_SYSREG_DBGDTRTX_EL0: + if ( !partial_emulation ) + goto fail; + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0); + HSR_SYSREG_DBG_CASES(DBGBVR): HSR_SYSREG_DBG_CASES(DBGBCR): HSR_SYSREG_DBG_CASES(DBGWVR): @@ -394,6 +413,7 @@ void do_sysreg(struct cpu_user_regs *regs, * And all other unknown registers. */ default: + fail: { const struct hsr_sysreg sysreg = hsr.sysreg; diff --git a/xen/arch/arm/include/asm/arm64/hsr.h b/xen/arch/arm/include/asm/arm64/hsr.h index e691d41c17..1495ccddea 100644 --- a/xen/arch/arm/include/asm/arm64/hsr.h +++ b/xen/arch/arm/include/asm/arm64/hsr.h @@ -47,6 +47,9 @@ #define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) #define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4) #define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0) +#define HSR_SYSREG_DBGDTR_EL0 HSR_SYSREG(2,3,c0,c4,0) +#define HSR_SYSREG_DBGDTRTX_EL0 HSR_SYSREG(2,3,c0,c5,0) +#define HSR_SYSREG_DBGDTRRX_EL0 HSR_SYSREG(2,3,c0,c5,0) #define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4) #define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5) From patchwork Wed Jan 31 12:10:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13539395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E39F0C47DB3 for ; Wed, 31 Jan 2024 12:14:39 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.673999.1048647 (Exim 4.92) (envelope-from ) id 1rV9U6-0008JF-II; Wed, 31 Jan 2024 12:14:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 673999.1048647; Wed, 31 Jan 2024 12:14:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rV9U6-0008J8-FT; Wed, 31 Jan 2024 12:14:30 +0000 Received: by outflank-mailman (input) for mailman id 673999; Wed, 31 Jan 2024 12:14:29 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rV9U5-000834-F8 for xen-devel@lists.xenproject.org; Wed, 31 Jan 2024 12:14:29 +0000 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on20600.outbound.protection.outlook.com [2a01:111:f403:2009::600]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 482d427c-c032-11ee-8a43-1f161083a0e0; Wed, 31 Jan 2024 13:14:28 +0100 (CET) Received: from PA7P264CA0371.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:37c::12) by MN2PR12MB4080.namprd12.prod.outlook.com (2603:10b6:208:1d9::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.22; Wed, 31 Jan 2024 12:14:25 +0000 Received: from SN1PEPF000252A4.namprd05.prod.outlook.com (2603:10a6:102:37c:cafe::57) by PA7P264CA0371.outlook.office365.com (2603:10a6:102:37c::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.34 via Frontend Transport; Wed, 31 Jan 2024 12:14:24 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A4.mail.protection.outlook.com (10.167.242.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Wed, 31 Jan 2024 12:14:23 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 31 Jan 2024 06:14:23 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 31 Jan 2024 06:14:22 -0600 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Wed, 31 Jan 2024 06:14:21 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 482d427c-c032-11ee-8a43-1f161083a0e0 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=i4Vu+XK72uXA4D/ubeboL8vudYH23k0zoTjwNMAwhLBm+elh2hVjfrCYAbAJ/RhWF2aaCd2HtLTcILE90q+rV2US7WGdnNZyvMFq/wG66lDCNKGXhTeinLzELlvod/bGIP96ubCwnUjBtps8WUiXgGEpLqezvIRoxTxqfwBWVBiZBIhB4xej9etqqheTJLaqv/+89zjgd9GuP93cTnvVZ0jIFyWd4Z6xz0AVfvzlg0CWeZ13XMEzBPuV3yPf7VSSuwfCsgUrQjv2izDZg1on1J+y00TxDCp24tj2bBQ51wlu/41xXDndDLqOZvMo6ZOmmX9zKDCyEZK8FKuILrk9Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bWN5n85Dx3hu7zn/5LPwLV3qgP3PSpBmLZ4KywQ45kA=; b=KgWpVDxJMEO2YQa3VUqUaiRmim2WU6MYJCl4/vtVnBoB2qyECPo7u0SYoVxq9CfWW5PPM4IS3IjshJ5YVsrU/vkVWO2bOlOAktxCTRkHBS6iXF+AkvWRkLu3VGqc1FwS+JgCHEWuu6ezlr35iqk0evyvalx2T3S39QaIhxNlt0VShnUmzxKm5SEH50FNpe6u6vQdQnhj4ci/nU6wQ9PatSbEj5vIrJrP9MsY7tgbEkSGS/inJXaS4v+1qKRNfP9xYJiHbJzQdyztd1R9lQAnbopNnvkYgJD+pmiEYPtboGJfEHkiAJ+aUEouZhv4AZrPJ3ctr8yL1T0VKwga6u778g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bWN5n85Dx3hu7zn/5LPwLV3qgP3PSpBmLZ4KywQ45kA=; b=dVwUyM3aWq443cgKnZPjmkLVJF9zp/2oet7hnvgJMp6SqNOFscL3+ey2E1gDj5QHTGlgQLJCyV80+QFQo5blr5xZs5zULg4AqZKSu7I+YpWy2d/Wbj41ilsESMO+VK44nC2hPm/3bfJrrUbVDdpa8U9TfJoilU8+tFz/0d3jGH8= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , Ayan Kumar Halder Subject: [XEN v4 3/3] xen/arm: arm32: Add emulation of Debug Data Transfer Registers Date: Wed, 31 Jan 2024 12:10:49 +0000 Message-ID: <20240131121049.225044-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240131121049.225044-1-ayan.kumar.halder@amd.com> References: <20240131121049.225044-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|MN2PR12MB4080:EE_ X-MS-Office365-Filtering-Correlation-Id: 37afa499-6c6f-43a9-6e3e-08dc2256295d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GgKKE7MgDDokxtKY1pIa1Xe66vunda2GsUik9y+U1UwTusTRwiesDyNwA0dmpmETFSAZl0TGdqgd7Tiu1KUafmRfJE3sx2Yu5ATaYTiqikkk1PkPLUhlJQ13qT4NttNM/GaSWl7N7vLVfAeOJY+e5soup8YKUN1DPHd3PrMQ9Fe1eiyiP5TzIaYLtRwOXlIEvFwBD7I22s+++Cpbul72ELBh/XleXIlb0Kf+/g/c8EJjRflCSEarRFyjT1lNu8XGqkWcGOlT0UslELQLmemV61YYR8u+Y2K/8vgcYm3JdqrjKMKtin6hyiwoVOmHofrJVxBLeKOcodKbZBsoNpGx6Bo6BB4Gb/a9j8Xp+Clc5wronDz1+0ujf/m5gHKvSWOMbPfnrWntlTkf6zcFwdTJrpRwRfH62dMngha6KfiN0OpPHut/wGanWpcR9kxnmi7ddLWsBwVBPeIq4Zp3mqOmMEI8CYEiwjF4XKszJ0PXEueTnkpGee1J5RzPHxPXdKtOj9/M43PgyYtce27KRcNHCC/i9popsN5AGONzauemvI3jkdQIWulirzq2TRma8vNQXE9uW7b8JrFK/ii260r/5DIwbccU9lI2s/CDW5YOlpUlmQDClj3kj+/hDhr8ukqAtkQfHeZeyjSRuEizomA4a2nekKggXjn3dGO7EZ+IHhnkOh/DM9ZiYCsmUW52Kp3dMouInFRrrtUyv4fKha1jHZLnY7Q6p9J1wNd7MeMF3MtQegeN6Z171iRiiPouweg/A23SFxo5MPV3iQdnueaA5qkBtPi2EN/t9wlhb9Er+vcD7qXdjhOjsyxvr+zdNihj X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(346002)(376002)(136003)(230273577357003)(230173577357003)(230922051799003)(64100799003)(186009)(82310400011)(1800799012)(451199024)(46966006)(36840700001)(40470700004)(6916009)(316002)(70206006)(54906003)(478600001)(70586007)(6666004)(8936002)(8676002)(4326008)(1076003)(5660300002)(26005)(426003)(2616005)(336012)(2906002)(83380400001)(47076005)(81166007)(40460700003)(82740400003)(86362001)(40480700001)(41300700001)(36756003)(103116003)(36860700001)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2024 12:14:23.5507 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37afa499-6c6f-43a9-6e3e-08dc2256295d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4080 When user enables HVC_DCC config option in Linux, it invokes access to debug transfer register (i.e. DBGDTRTXINT). As this register is not emulated, Xen injects an undefined exception to the guest and Linux crashes. To prevent this crash, introduce a partial emulation of DBGDTRTXINT as RAZ/WI and TXfull should be set to 1. So that Linux will see that TXfull is set, and it will not access DBGDTRTXINT. As a pre-requisite, DBGOSLSR should be emulated in the same way as its AArch64 variant (ie OSLSR_EL1). This is to ensure that DBGOSLSR.OSLK is 0, thus MDSCR_EL1.TXfull is treated as UNK/SBZP. Only MDCCSR_EL0 can be emulated (which is DBGDSCRINT on arm32). DBGDSCRINT can be accessed at EL0 as DBGDSCREXT is emulated as RAZ (as DBGOSLSR.OSLK == 0). So, we tool the opportunity to fix the minimum EL for DBGDSCRINT. DBGDSCRINT.TXfull is set to 1. Refer ARM DDI 0487J.a ID042523, G8.3.19, DBGDTRTXint "If TXfull is set to 1, set DTRTX to UNKNOWN". So, DBGDTR[TR]XINT is emulated as RAZ/WI. Thus, any OS is expected to read DBGDSCRINT and check for TXfull before using DBGDTRTXINT. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel --- Changes from v1 :- 1. DBGDTR_EL0 does not emulate RXfull. This is to avoid giving the OS any indication that the RX buffer is full and is waiting to be read. 2. In Arm32, DBGOSLSR is emulated. Also DBGDTRTXINT is emulated at EL0 only. 3. Fixed the commit message and inline code comments. v2 :- 1. Split the patch into two (separate patches for arm64 and arm32). 2. Fixed in line comments and style related issues. 3. Updated commit message to mention DBGDSCRINT handling. v3 :- 1. The original emulation of DBGDSCRINT is retained when 'partial_emulation' is false. 2. If 'partial_emulation' is false, then access to DBGDTRTXINT will lead to undefined exception. xen/arch/arm/include/asm/cpregs.h | 2 ++ xen/arch/arm/vcpreg.c | 35 ++++++++++++++++++++++--------- 2 files changed, 27 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index 6b083de204..aec9e8f329 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -75,6 +75,8 @@ #define DBGDIDR p14,0,c0,c0,0 /* Debug ID Register */ #define DBGDSCRINT p14,0,c0,c1,0 /* Debug Status and Control Internal */ #define DBGDSCREXT p14,0,c0,c2,2 /* Debug Status and Control External */ +#define DBGDTRRXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, Receive */ +#define DBGDTRTXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, Transmit */ #define DBGVCR p14,0,c0,c7,0 /* Vector Catch */ #define DBGBVR0 p14,0,c0,c0,4 /* Breakpoint Value 0 */ #define DBGBCR0 p14,0,c0,c0,5 /* Breakpoint Control 0 */ diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index a2d0500704..87df4bd238 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -493,11 +493,12 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 * * Unhandled: - * DBGOSLSR * DBGPRCR */ case HSR_CPREG32(DBGOSLAR): return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(DBGOSLSR): + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 1, 1U << 3); case HSR_CPREG32(DBGOSDLR): return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); @@ -509,8 +510,6 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) * * Unhandled: * DBGDCCINT - * DBGDTRRXint - * DBGDTRTXint * DBGWFAR * DBGDTRTXext * DBGDTRRXext, @@ -550,10 +549,22 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) case HSR_CPREG32(DBGDSCRINT): /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. + * Xen doesn't expose a real (or emulated) Debug Communications + * Channel (DCC) to a domain. Yet the Arm ARM implies this is not an + * optional feature. So some domains may start to probe it. For + * instance, the HVC_DCC driver in Linux (since f377775dc083 and at + * least up to v6.7), will try to write some characters and check if + * the transmit buffer has emptied. By setting TX status bit to + * indicate the transmit buffer is full. This we would hint the OS + * that the DCC is probably not working. + * + * Bit 29: TX full + * + * Accessible by EL0 if DBGDSCRext.UDCCdis is set to 0, which we + * emulate as RAZ/WI in the next case. */ - return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 0, + partial_emulation ? (1U << 29) : 0); case HSR_CPREG32(DBGDSCREXT): /* @@ -562,6 +573,12 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + /* DBGDTR[TR]XINT share the same encoding */ + case HSR_CPREG32(DBGDTRTXINT): + if ( !partial_emulation ) + goto fail; + return handle_raz_wi(regs, regidx, cp32.read, hsr, 0); + case HSR_CPREG32(DBGVCR): case HSR_CPREG32(DBGBVR0): case HSR_CPREG32(DBGBCR0): @@ -591,6 +608,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) * And all other unknown registers. */ default: + fail: gdprintk(XENLOG_ERR, "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", cp32.read ? "mrc" : "mcr", @@ -659,10 +677,7 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 * * Unhandled: - * DBGDTRTXint - * DBGDTRRXint - * - * And all other unknown registers. + * All unknown registers. */ gdprintk(XENLOG_ERR, "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n",