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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2024 06:03:37.8071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3837c16e-da6f-423a-db98-08dc22eb884c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8705 Already public pci_doe() takes a protocol type argument. PCIe 6.0 defines three, define them in a header for use with pci_doe(). Signed-off-by: Alexey Kardashevskiy --- include/linux/pci-doe.h | 4 ++++ drivers/pci/doe.c | 2 -- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/linux/pci-doe.h b/include/linux/pci-doe.h index 1f14aed4354b..5c33f7dc978b 100644 --- a/include/linux/pci-doe.h +++ b/include/linux/pci-doe.h @@ -13,6 +13,10 @@ #ifndef LINUX_PCI_DOE_H #define LINUX_PCI_DOE_H +#define PCI_DOE_PROTOCOL_DISCOVERY 0 +#define PCI_DOE_PROTOCOL_CMA_SPDM 1 +#define PCI_DOE_PROTOCOL_SECURED_CMA_SPDM 2 + struct pci_doe_mb; struct pci_doe_mb *pci_find_doe_mailbox(struct pci_dev *pdev, u16 vendor, diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c index e3aab5edaf70..61f0531d2b1d 100644 --- a/drivers/pci/doe.c +++ b/drivers/pci/doe.c @@ -22,8 +22,6 @@ #include "pci.h" -#define PCI_DOE_PROTOCOL_DISCOVERY 0 - /* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */ #define PCI_DOE_TIMEOUT HZ #define PCI_DOE_POLL_INTERVAL (PCI_DOE_TIMEOUT / 128) From patchwork Thu Feb 1 06:02:26 2024 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2024 06:04:50.0879 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2bd4a0d7-3f19-42c4-092d-08dc22ebb362 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7526 PCIe spec v6.1 defines a "DOE Discovery Version" field in the DOE Discovery Request Data Object Contents (3rd DW) as: 15:8 DOE Discovery Version – must be 02h if the Capability Version in the Data Object Exchange Extended Capability is 02h or greater. Add support for the version on devices with the DOE v2 capability. Signed-off-by: Alexey Kardashevskiy --- include/uapi/linux/pci_regs.h | 1 + drivers/pci/doe.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index a39193213ff2..b9c681f14181 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1144,6 +1144,7 @@ #define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH 0x0003ffff #define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX 0x000000ff +#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_DISCOVER_VER 0x0000ff00 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID 0x0000ffff #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c index 61f0531d2b1d..f57def002175 100644 --- a/drivers/pci/doe.c +++ b/drivers/pci/doe.c @@ -381,11 +381,13 @@ static void pci_doe_task_complete(struct pci_doe_task *task) complete(task->private); } -static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid, +static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 capver, u8 *index, u16 *vid, u8 *protocol) { + u32 disver = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_DISCOVER_VER, + (capver >= 2) ? 2 : 0); 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Thu, 1 Feb 2024 00:04:49 -0600 From: Alexey Kardashevskiy To: CC: , Bjorn Helgaas , Jonathan Cameron , Lukas Wunner , Alexey Kardashevskiy Subject: [PATCH kernel 3/4] pci: Define TEE-IO bit in PCIe device capabilities Date: Thu, 1 Feb 2024 17:02:27 +1100 Message-ID: <20240201060228.3070928-4-aik@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240201060228.3070928-1-aik@amd.com> References: <20240201060228.3070928-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|IA0PR12MB8714:EE_ X-MS-Office365-Filtering-Correlation-Id: b0cdca7e-bac5-411a-c2d8-08dc22ebb78b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BuZ5C+uJR2mXpEnMAlYQx0L1Y2k42N076BYiMfY9I6Q9IuGdEVFh3cAMYFRO0UxPiakD9avxeShOmWA1GUIpLS4SroNBgHKePiMLeTZD93tv9D82l0ZTG/sioMdY8O6KuzmOuD2D2GQMfn7VheT9YNjXkVUFCHNuuarzYvUfE0q+97z+Xt9Xk7Y2LKxj2xzpksva93FLA+vj8RdqQi/ZS3gYy+7ZRHs7DoBCVDKbjSS0BFDleGNs7uoNbeALy+mYNBnGD6GY6wHb+BZc9FOO6+omaiAiqmL2/tGps1D6THj2k9wvY4C6vB0kHIcjQDDk0nZOOAFEU6+oixYnncDGVsNspMRYQJfowHU8hxuViR0lcZojG1pbHFQXnyVAvs9BrLyovniWkeneTzmOI126OztNLmU0dycValznT7ZSbQAjyfhT3wQKa4zZIag12wdM/jeDuK6c24cOfTrIHWY0RMg52Ckic7f60ytFjiqWjvjOBneiLE+7zeQ9pQynkz1W1jkLVDqIr57gz48dTedA2DvkbyJqkOYJWpo4v7O21XcEYU4pDpNNcHUI6t3Qhj+utawHIjuy5fi7FFoYLS5LEfTMj/bhl37xxMyagXbFb9urwp+j0jBLPy0wGgmB30/6P7DAfhNxeuD2eVwiKcSdpwyLGC5kI8gbTOBexDhOmii3II5alFio0ys2i/YUF9Rr91Zi2i20Eewseft2Zz1bW2mAZyua37wUKRuxhSk0zT6SSxD9DWZmABXCYUnNZwaeaPJ5R+GEIrFvKgTZs/gv2w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(376002)(39860400002)(136003)(230922051799003)(64100799003)(1800799012)(451199024)(186009)(82310400011)(40470700004)(46966006)(36840700001)(6916009)(54906003)(4326008)(70586007)(47076005)(70206006)(478600001)(8936002)(8676002)(6666004)(316002)(2616005)(336012)(1076003)(2906002)(4744005)(426003)(83380400001)(82740400003)(5660300002)(26005)(36860700001)(16526019)(81166007)(356005)(40460700003)(36756003)(40480700001)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2024 06:04:57.0722 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0cdca7e-bac5-411a-c2d8-08dc22ebb78b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8714 A new bit #30 from the PCI Express Device Capabilities Register is defined in PCIe 6.1 as "TEE Device Interface Security Protocol (TDISP)". Define the macro. Signed-off-by: Alexey Kardashevskiy --- include/uapi/linux/pci_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index b9c681f14181..e60b4df1f7d9 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -498,6 +498,7 @@ #define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */ #define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */ #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_TEE_IO 0x40000000 /* TEE-IO Supported (TDISP) */ #define PCI_EXP_DEVCTL 0x08 /* Device Control */ #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ From patchwork Thu Feb 1 06:02:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 13540680 X-Patchwork-Delegate: bhelgaas@google.com Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2041.outbound.protection.outlook.com [40.107.244.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F373284A20; 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Thu, 1 Feb 2024 00:05:38 -0600 From: Alexey Kardashevskiy To: CC: , Bjorn Helgaas , Jonathan Cameron , Lukas Wunner , Alexey Kardashevskiy Subject: [PATCH kernel 4/4] pci: Define Integrity and Data Encryption (IDE) extended capability Date: Thu, 1 Feb 2024 17:02:28 +1100 Message-ID: <20240201060228.3070928-5-aik@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240201060228.3070928-1-aik@amd.com> References: <20240201060228.3070928-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE38:EE_|DM4PR12MB7600:EE_ X-MS-Office365-Filtering-Correlation-Id: de7c4b6e-27b0-48a2-b157-08dc22ebd49e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ABrEfMDB8U6D/NW5dKrarHDUfewD0YIDSVMdTCdVLFX0dAgKY1/HJF9rzcvJa+85h2WOhVDysTjs9gH2a/IhZvkS/TLG5SMwc2nHQmHxLqXbbLWfDTZHQAglev9uZDCUzaO9r0S9o9IdSqgkQFoFucKkoJS4xlKZJ/D9GjSoMALVxPza0LUnOpsqBC8qhpRXJBiNMnOjUzcIpPz0i3T8jm9ILYc0y2LV4EvCcNpz/0WhUI8gSBF9X00kDsx7tO3NuQmAgHeYBygkPmpotW2zT8gX8B76R2mCFJk978XH1YKCB0gJlt5dqW1vKwKoDQccOuJx+rNfKfZou+D8hDMMDia8eQdSr0EGJLbPadB1aPf39TsYAaufWhp0EQwhopeHZhzz7mUqCzZwb+ilvz1RT468VyLxOOtGlqdg35OjAvyGu4SELScMGeqdOscGJ1TGT+0NAUMGK94c8oIQn15UIwK0KckrRQlSQUqUEo7nCE4swm86Xlrg2WSRayvRCz09rnaT1m7AYPSiY97AihwryEOeS0DZk6WCjl6/OrVUbS/FKYrsYbtiJ/oNMw82H7v9mZbG0jtoM0a/TjtjhxlRB7ImMLgXde1baCeJqY52R9SaXTNJEuAWWbdpE+aTrnlLAkFgiTlbILe2p44+lFObat+w/zU0uMxGwWmpVa7bwrtQR+fJqQO7KZV6LVaQ27TVEUtPvq1PpkHQQCxjwWqCxYxlTAbJQpi73KFFLzvcTeheqdq61YyNXs9UjPDswfM6wKZhiIyglYxOIWs9So0Q8A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(376002)(346002)(396003)(230922051799003)(64100799003)(451199024)(186009)(1800799012)(82310400011)(40470700004)(46966006)(36840700001)(40480700001)(40460700003)(426003)(478600001)(5660300002)(16526019)(70586007)(2906002)(26005)(6916009)(336012)(83380400001)(6666004)(70206006)(8676002)(54906003)(316002)(8936002)(4326008)(356005)(1076003)(2616005)(966005)(36860700001)(47076005)(81166007)(82740400003)(41300700001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2024 06:05:45.8502 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de7c4b6e-27b0-48a2-b157-08dc22ebd49e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE38.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7600 PCIe 6.0 introduces the "Integrity & Data Encryption (IDE)" feature which adds a new capability with id=0x30. Add the new id to the list of capabilities. Signed-off-by: Alexey Kardashevskiy --- This only adds an id. The rest is here: https://github.com/aik/pciutils/commit/ide Not sure how much of that we want in the Linux. --- include/uapi/linux/pci_regs.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index e60b4df1f7d9..b8d447b2c793 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -743,7 +743,8 @@ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE +#define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption (IDE) */ +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_IDE #define PCI_EXT_CAP_DSN_SIZEOF 12 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40