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Wed, 31 Jan 2024 22:40:45 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id y9-20020aa79e09000000b006ddc7af02c1sm10925764pfq.9.2024.01.31.22.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 22:40:45 -0800 (PST) From: Charlie Jenkins Date: Wed, 31 Jan 2024 22:40:22 -0800 Subject: [PATCH 1/2] riscv: lib: Introduce has_fast_misaligned_access function MIME-Version: 1.0 Message-Id: <20240131-disable_misaligned_probe_config-v1-1-98d155e9cda8@rivosinc.com> References: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> In-Reply-To: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706769643; l=1864; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Create has_fast_misaligned_access to avoid needing to explicitly check the fast_misaligned_access_speed_key static key. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/cpufeature.h | 6 ++++++ arch/riscv/lib/csum.c | 5 +---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 5a626ed2c47a..dfdcca229174 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -28,7 +28,9 @@ struct riscv_isainfo { DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS DECLARE_PER_CPU(long, misaligned_access_speed); +#endif /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; @@ -137,4 +139,8 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); +static __always_inline bool has_fast_misaligned_accesses(void) +{ + return static_branch_likely(&fast_misaligned_access_speed_key); +} #endif diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index af3df5274ccb..399fa09bf4cb 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -318,10 +318,7 @@ unsigned int do_csum(const unsigned char *buff, int len) * branches. The largest chunk of overlap was delegated into the * do_csum_common function. */ - if (static_branch_likely(&fast_misaligned_access_speed_key)) - return do_csum_no_alignment(buff, len); - - if (((unsigned long)buff & OFFSET_MASK) == 0) + if (has_fast_misaligned_accesses() || (((unsigned long)buff & OFFSET_MASK) == 0b101)) return do_csum_no_alignment(buff, len); return do_csum_with_alignment(buff, len); From patchwork Thu Feb 1 06:40:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13540702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7FBFBC47DDB for ; Thu, 1 Feb 2024 06:40:57 +0000 (UTC) DKIM-Signature: v=1; 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Wed, 31 Jan 2024 22:40:46 -0800 (PST) From: Charlie Jenkins Date: Wed, 31 Jan 2024 22:40:23 -0800 Subject: [PATCH 2/2] riscv: Disable misaligned access probe when CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS MIME-Version: 1.0 Message-Id: <20240131-disable_misaligned_probe_config-v1-2-98d155e9cda8@rivosinc.com> References: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> In-Reply-To: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706769643; l=3922; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=wzSLJadpkHjmp9X2BoqvKpkVX4rq2iE3DOomMnQVqdY=; b=DTn4IwM4ZIGuqtofPt6Obk2d6Ns8T0POg2dAYgBso9mTIalwSw7BMF2KHtVOxaqOzJGsrbvkF /jb1oVOA2joBeZ7x66cEr8DJ1S+QAdH1efsmP1wIb6hgiOKp5c/RKnH X-Developer-Key: i=charlie@rivosinc.com; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is selected, the cpus can be set to have fast misaligned access without needing to probe. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/cpufeature.h | 7 +++++++ arch/riscv/kernel/cpufeature.c | 4 ++++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ arch/riscv/kernel/traps_misaligned.c | 4 ++++ 4 files changed, 19 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index dfdcca229174..7d8d64783e38 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -137,10 +137,17 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); static __always_inline bool has_fast_misaligned_accesses(void) { return static_branch_likely(&fast_misaligned_access_speed_key); } +#else +static __always_inline bool has_fast_misaligned_accesses(void) +{ + return true; +} +#endif #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..d787846c0b68 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -43,10 +43,12 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS /* Performance information */ DEFINE_PER_CPU(long, misaligned_access_speed); static cpumask_t fast_misaligned_access; +#endif /** * riscv_isa_extension_base() - Get base extension word @@ -706,6 +708,7 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS static int check_unaligned_access(void *param) { int cpu = smp_processor_id(); @@ -946,6 +949,7 @@ static int check_unaligned_access_all_cpus(void) } arch_initcall(check_unaligned_access_all_cpus); +#endif /* CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS */ void riscv_user_isa_enable(void) { diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index a7c56b41efd2..3f1a6edfdb08 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -149,6 +149,7 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext) static u64 hwprobe_misaligned(const struct cpumask *cpus) { +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS int cpu; u64 perf = -1ULL; @@ -168,6 +169,9 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus) return RISCV_HWPROBE_MISALIGNED_UNKNOWN; return perf; +#else + return RISCV_HWPROBE_MISALIGNED_FAST; +#endif } static void hwprobe_one_pair(struct riscv_hwprobe *pair, diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 8ded225e8c5b..c24f79d769f6 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -413,7 +413,9 @@ int handle_misaligned_load(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED; +#endif if (!unaligned_enabled) return -1; @@ -596,6 +598,7 @@ int handle_misaligned_store(struct pt_regs *regs) return 0; } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS bool check_unaligned_access_emulated(int cpu) { long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu); @@ -640,6 +643,7 @@ void unaligned_emulation_finish(void) } unaligned_ctl = true; } +#endif bool unaligned_ctl_available(void) {