From patchwork Thu Feb 1 14:19:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541142 X-Patchwork-Delegate: geert@linux-m68k.org Received: from laurent.telenet-ops.be (laurent.telenet-ops.be [195.130.137.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97B025D48B for ; Thu, 1 Feb 2024 14:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797165; cv=none; b=i8Omz/UawBCvcTUR9+ADFzicVhmVNaCFaAI4FS+8/CQRsIsflaXug7qC7syW7oQpF5RSvJGXbjAFUyKVgbWzjLUs9XcL+3/BMT21f0tfjdiuzrzLO4LXILQDzaJfQKWEzn3fzuQeBlfcBJ59F2m8+PxNZZ5TlvGU6hT7t6/nds0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797165; c=relaxed/simple; bh=YJTGKYCbGRMvOO9KGyCz1lRYndgqRMLWq4L32TB2e84=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ITfkLPmkMpJsyIh9tKF0I9x52pqH0PJzHCVSbreWgMNedZYKzVQqO73b38cLa1VbgrB06mLPlcixCOa5CmRLFyQPh81XL66NGfRyH1kTeCM3scU+V2c15t55Q8YDeTRgwGs08a3x2UKnFYwNfxrSBMtlZukAfp/RsgK+fAI2+U8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by laurent.telenet-ops.be with bizsmtp id hqKM2B0074efzLr01qKM6R; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4Z-2m; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdJ-2M; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 1/5] arm64: dts: renesas: r8a779h0: Add L3 cache controller Date: Thu, 1 Feb 2024 15:19:16 +0100 Message-Id: <9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Duy Nguyen Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- Changes compared to the BSP: - Rename L3_CA76_0 label to L3_CA76, - Rename cache-controller-0 node to cache-controller. --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index eb555cbf51a41001..f47695158d991288 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -23,6 +23,14 @@ a76_0: cpu@0 { reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76>; + }; + + L3_CA76: cache-controller { + compatible = "cache"; + power-domains = <&sysc R8A779H0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; From patchwork Thu Feb 1 14:19:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541146 X-Patchwork-Delegate: geert@linux-m68k.org Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [195.130.132.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A4365D486 for ; Thu, 1 Feb 2024 14:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797166; cv=none; b=KCgdo6L2DkEiZCttqjPegkyqVWlVZKb547BoHmey9YWKExzyeV1cgDA076ORMqcsafZj0lc+P9daAoSh0CnXc5xAJmtoiEulN/1VVVMcpPaEO4xP2MF78NR2YjBOaGRKLzlVIpdMTczczDcCLbuslTGoXSzop+wnpjk/u1agdT4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797166; c=relaxed/simple; bh=ZoK5QqAiXUC/PFT86/uwfW9hJhdLikCmR8yZjtZhRLA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LU2BtTLp4/EpGyo6jvU2ayN+dfIjj9KODWydezLZRTWsYdScc1SfWXhaKrMjeiTq7Bareq98j015bh7sXDvoRBtsQjX3dx1tI7ENIqX2s1IK5P9DTZjeYoIJid5b3OmOrm/2JiABLNOkPuuck9AGEHKgV14ftkuC1slzdrAFqek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by xavier.telenet-ops.be with bizsmtp id hqKM2B0074efzLr01qKMiD; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4c-3P; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdM-30; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 2/5] arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores Date: Thu, 1 Feb 2024 15:19:17 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Duy Nguyen Complete the description of the Cortex-A76 CPU cores and L3 cache controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU topology and PSCI support for enabling CPU cores. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- Changes compared to the BSP: - Rename L3_CA76_0 label to L3_CA76, - Move psci node to preserve sort order (alphabetical), - Drop GIC_CPU_MASK_SIMPLE changes, as GICv3 PPI interrupt specifiers have no such masks. --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index f47695158d991288..88c5dcbc38d59dab 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -18,12 +18,57 @@ cpus { #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a76_0>; + }; + core1 { + cpu = <&a76_1>; + }; + core2 { + cpu = <&a76_2>; + }; + core3 { + cpu = <&a76_3>; + }; + }; + }; + a76_0: cpu@0 { compatible = "arm,cortex-a76"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76>; + enable-method = "psci"; + }; + + a76_1: cpu@100 { + compatible = "arm,cortex-a76"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + }; + + a76_2: cpu@200 { + compatible = "arm,cortex-a76"; + reg = <0x200>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + }; + + a76_3: cpu@300 { + compatible = "arm,cortex-a76"; + reg = <0x300>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; }; L3_CA76: cache-controller { @@ -53,6 +98,11 @@ pmu-a76 { interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif-clk { compatible = "fixed-clock"; From patchwork Thu Feb 1 14:19:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541143 X-Patchwork-Delegate: geert@linux-m68k.org Received: from laurent.telenet-ops.be (laurent.telenet-ops.be [195.130.137.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97ABD5D48A for ; Thu, 1 Feb 2024 14:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.137.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797165; cv=none; b=rjDlJKV2iortH+bX1qEG1uwZUx4PdhsJQuLYBmwflcYQKOA+LsHP4rjnABh91ZcDbTTO4owPusDsHwZM3KGtljWOdepStNNXUEKb2f2Gw+HC0xFmXU3Sf8kj5Aes3vBpv6uX27ExonctY/tIRZ2cg5LsySdLBjesoy8PCIP6ClI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797165; c=relaxed/simple; bh=OFrPToGeevujQS1JabxDYjkzzcy/ZA8B8JVFCIId3B4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I+yzEzDrQLOjy0dOVCPNbayQOubFA9PeOHtl3alILir6OSKqizci95B0ylSMGERgeuHVw+uCtKaZnUhk74A6zX0yt2S9F0snGTNnoFL6VD6Z3jjS7Pa84ifTIzl+ZATewlCDOyw1gcL7Z3tSmCcWBMnJJUdgyEcn4HK2Iup/ZJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.137.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by laurent.telenet-ops.be with bizsmtp id hqKM2B0084efzLr01qKM6S; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4i-4c; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdR-3k; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 3/5] arm64: dts: renesas: r8a779h0: Add CPUIdle support Date: Thu, 1 Feb 2024 15:19:18 +0100 Message-Id: <848d176bdbcaf3bc44e5dae555afa9c812a19fd1.1706796979.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Duy Nguyen Support CPUIdle for ARM Cortex-A76 on R-Car V4M. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 88c5dcbc38d59dab..b3255bba69e3e6da 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -42,6 +42,7 @@ a76_0: cpu@0 { power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_1: cpu@100 { @@ -51,6 +52,7 @@ a76_1: cpu@100 { power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_2: cpu@200 { @@ -60,6 +62,7 @@ a76_2: cpu@200 { power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_3: cpu@300 { @@ -69,6 +72,20 @@ a76_3: cpu@300 { power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; }; L3_CA76: cache-controller { From patchwork Thu Feb 1 14:19:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541144 X-Patchwork-Delegate: geert@linux-m68k.org Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [195.130.132.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A3F85D484 for ; Thu, 1 Feb 2024 14:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797166; cv=none; b=koOeOpLD2Lv8260j1ZAoLYd4Lt0981ESJnhUux20P4hMDlZWkqknj5oXC/yFu8Tup9JQRwQLeWEZx05lYt3HDcsv3NSGx+jjL8jbvtIEb749xL35pr6YVMiN3PxSwedOlVsApz07+QwisjNTVAuy3W/eQyeYbtnMpuQcfikUBOg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797166; c=relaxed/simple; bh=BQ5XINEvdzRZUIf76yiuqfyI/qE+NO/uTHHAN4hv/eQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XkZ3UIRlRcOJB3wUQERSA7MX+f7IaT+SX5hebzVflnWeqTkU32TVD6euxyGLLiBySgNiyUQWy9mMu87L7T1yE8hL86rPM4Om+6EeBfweysVqgXxVaseVE0UdX5DIIQJnX7jgLexBkKRuOD53APTpIrvVQ5DUHUqYGyWZ2rRC2nw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by xavier.telenet-ops.be with bizsmtp id hqKM2B0084efzLr01qKMiE; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4l-5P; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdV-4V; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 4/5] arm64: dts: renesas: r8a779h0: Add CPU core clocks Date: Thu, 1 Feb 2024 15:19:19 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Duy Nguyen Describe the clocks for the four Cortex-A76 CPU cores. CA76 CPU cores 0,1,2,3 are clocked by ZC0,ZC1,ZC2,ZC3. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index b3255bba69e3e6da..622775f6160f55bd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -43,6 +43,7 @@ a76_0: cpu@0 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; }; a76_1: cpu@100 { @@ -53,6 +54,7 @@ a76_1: cpu@100 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; }; a76_2: cpu@200 { @@ -63,6 +65,7 @@ a76_2: cpu@200 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; }; a76_3: cpu@300 { @@ -73,6 +76,7 @@ a76_3: cpu@300 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; }; idle-states { From patchwork Thu Feb 1 14:19:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541147 X-Patchwork-Delegate: geert@linux-m68k.org Received: from andre.telenet-ops.be (andre.telenet-ops.be [195.130.132.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B67C5D47C for ; Thu, 1 Feb 2024 14:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797166; cv=none; b=d470uqLsEvowa7eGwC/vjuP06cKuFVoYw5MPb0wQqPq0JhclGhnjcQZhB9SuOX7oY0WuDiHX/HRCoLxU0l0aeiiqPfDGKh+iuNbCxHhg5eCgTET5GJ0FJLbv3BQDN96btMjJVePryyXOoOca3+vg69aFbhyeTD9HxkvLeSBRzvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706797166; c=relaxed/simple; bh=DLIELGt0bbpiOhEQ1TDs4yiSw25rRIA23Ysdzrz3f/w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LefxMOoXfXOPL2L2E/JJrUuQQGtdpSWKEQSyqIk/kGPq4NdOR2X2mlNeRnDkYvHDQ+WSvFS9yW+dIwgD621u9lm9q8CPsVPndw1rbTwDSl6hKD5DFh60qgeXhebBGaiuMHVFtCj8KgpFqNnaxj48XM4+XoGAdvzskhoszNYF7t4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by andre.telenet-ops.be with bizsmtp id hqKM2B0054efzLr01qKMYG; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4r-6n; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdZ-5r; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 5/5] arm64: dts: renesas: r8a779h0: Add CA76 operating points Date: Thu, 1 Feb 2024 15:19:20 +0100 Message-Id: <736b5836ec2b54e8b36712866309dc1b7ee1fc48.1706796979.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Duy Nguyen Add operating points for running the Cortex-A76 CPU cores on R-Car V4M at various speeds, up to the Normal (1.0 GHz). Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 622775f6160f55bd..4e9e487ec51661fd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -14,6 +14,22 @@ / { #address-cells = <2>; #size-cells = <2>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -44,6 +60,7 @@ a76_0: cpu@0 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; + operating-points-v2 = <&cluster0_opp>; }; a76_1: cpu@100 { @@ -55,6 +72,7 @@ a76_1: cpu@100 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; + operating-points-v2 = <&cluster0_opp>; }; a76_2: cpu@200 { @@ -66,6 +84,7 @@ a76_2: cpu@200 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; + operating-points-v2 = <&cluster0_opp>; }; a76_3: cpu@300 { @@ -77,6 +96,7 @@ a76_3: cpu@300 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; + operating-points-v2 = <&cluster0_opp>; }; idle-states {