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The "Message Routing" is in the section 2.2.8, and the "INTx Mechanism Messages" is in the section 2.2.8.1 on the PCI Express Base Specification, Rev 6.1. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas Signed-off-by: Frank Li --- drivers/pci/pci.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2336a8d1edab2..ffd066c15f3bb 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,24 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* Message Routing (r[2:0]) See: PCIe r6.0, sec 2.2.8 */ +#define PCIE_MSG_TYPE_R_RC 0 +#define PCIE_MSG_TYPE_R_ADDR 1 +#define PCIE_MSG_TYPE_R_ID 2 +#define PCIE_MSG_TYPE_R_BC 3 +#define PCIE_MSG_TYPE_R_LOCAL 4 +#define PCIE_MSG_TYPE_R_GATHER 5 + +/* INTx Mechanism Messages See: PCIe r6.0, sec 2.2.8.1 */ +#define PCIE_MSG_CODE_ASSERT_INTA 0x20 +#define PCIE_MSG_CODE_ASSERT_INTB 0x21 +#define PCIE_MSG_CODE_ASSERT_INTC 0x22 +#define PCIE_MSG_CODE_ASSERT_INTD 0x23 +#define PCIE_MSG_CODE_DEASSERT_INTA 0x24 +#define PCIE_MSG_CODE_DEASSERT_INTB 0x25 +#define PCIE_MSG_CODE_DEASSERT_INTC 0x26 +#define PCIE_MSG_CODE_DEASSERT_INTD 0x27 + extern const unsigned char pcie_link_speed[]; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?vzdfNw9abXWaKGcDmAWSwDOZfSvi?= =?utf-8?q?+JpL4y00V8pviYIBNDtZGLRyxdVWCe630dR1uM5cPrOTSzKfME/vd2CXnPWA09lRO?= =?utf-8?q?QVDZlLh3D9ALxGYgw9GqYqbJjjsE7bOQjvv0dXr6EY+hfj4j3e2FWzJxF8RoNhUB4?= =?utf-8?q?BOSwKtdDUDBiSH6r57MvbyBuwqR5WyfE0Z6GLrlKA5Q1yr2tGAWedBznzpClqibSh?= =?utf-8?q?id7szqxnL0+YmsF+C195uOVQ5FC6i9zWnig18cGaj1iLp6/sOFc1vk52sBiGp0a92?= =?utf-8?q?bwghY3N33c9MYfbngomd/cAqbFWgMlsGj0PV0dqA/0r0/0xH/XPzJIVzEv/b1VwLl?= =?utf-8?q?uymuNo0re72LM/auqVcNy6aGh0nC/cFMMrveiNL1/REUDf+QwdaetOaGqaLT7ewz8?= =?utf-8?q?VOwR4OQSehL2xwm+ELpGc+WEKmeycOCM5AkUvmflDYUXxenhBLkfEmb0P9wD5XmIE?= =?utf-8?q?gsbBoHrk0ttQeU128ly+3ReF8IfCDDdlYIq8Qb7jCUZyRKO/1NepegXDXJQ0604do?= =?utf-8?q?fEjQ73H+l68k30dFmFJJgWXjg2jMG54vEGwKYOcWaX7R1sLeJpuio/IndzYgdMrZH?= =?utf-8?q?ULK/zFkaxC3Fc4DLXuv/HfoVrwv0BPmFvyC7u7GEGg+onDBAJ6onZikqLt0PtR22/?= =?utf-8?q?mcXlFEp8XaG//QhwkgcCYNV2BJ0WS13NmPcOlxTquXIvzAsKPoAOr5L+n2IWPTWqv?= =?utf-8?q?aYvLl02uC/5U/OxHf400Zd5PAlyVWcxlyjI9359Ce10bnXgvnqvdNDL+13C8oyBSP?= =?utf-8?q?P69c/veJah1Oq/3x+7oAZERA/Q4b6gYXql1k5+gpnXeqsUb0v+Lrf2DQIQNYausTq?= =?utf-8?q?ssQcoaAFz/Qb0VHkmYuZc5NBDpOyrNCi6SAcda0WqfhkiTeFrk8jfmHcAdKFXRosL?= =?utf-8?q?7nWh1XJHnOgHWwy0byirmCrhZqz7+CWVhBRcJKzpQR/NAKLKQ0pxh+0pllp6DFc71?= =?utf-8?q?8v9fSqy++wGzLvAXk/qITy9nQUOtbdYukzciXobbZFNc9IAEIRsln94ieHR7K3JfW?= =?utf-8?q?HKylthEdioo2Ws2L5i+oA6/GGFeR5HU4Lx4aLLtC71Fefi0SXCjCwYRwbrnRLP61b?= =?utf-8?q?JEH7i6QdC9Uvy/l7SDOPb1sFqGApNV2KDLmw9tsWUHNnyXyfXEuBMha4Lh9nh8XSu?= =?utf-8?q?mkJI+1sUqfZFK24QebwovVtrKJQkeA3uWnP8zHr800r7bQPJI67u72lW1PBSBdORj?= =?utf-8?q?q42kGICb2bStdP8cbe5/qsj0ffCDb7e5VnrZDlIQZTfMz+k4o6v/eD1JUNwoIWqiA?= =?utf-8?q?Et8w7cgbwzDfBE2AUNZQn8dOY4voWb8NTyTTZYHOeKR3+8sz+c9Ch+B7uhkQPllTi?= =?utf-8?q?JdWNtmyMsRbGvl6FAPnuamBzO66KjTT66J82xd3f41+BoiD/D13D6TE7kV3RP3o6B?= =?utf-8?q?x9nj87jsj7joCAdERh355wlzQzeXPRyHzLGn4STQ8dABalLDzQC+CLQN/1UPqZRom?= =?utf-8?q?YqXobsLKL/1Vnxr9SYSj5HbbBQw/qaoqDNtLgoepHk9tVyiKnvqwU3KoPzjXT06P2?= =?utf-8?q?waBHbcfYNRBG?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6438c80-dc10-4938-4591-08dc240146da X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2024 15:11:48.2959 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8SNz2wmhP97LVU3gVKyYrEzBLBy/+Fkl0akUjXPI74C9M86zsvcZcY04kYEsiDkGq3U5j9O61PXAtoAX3NMywA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8425 From: Yoshihiro Shimoda This is a preparation before adding the Msg-type outbound iATU mapping. The respective update will require two more arguments added to __dw_pcie_prog_outbound_atu(). That will make the already complicated function prototype even more hard to comprehend accepting _eight_ arguments. In order to prevent that and keep the code more-or-less readable all the outbound iATU-related arguments are moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer to which shall be passed to dw_pcie_prog_outbound_atu(). The structure is supposed to be locally defined and populated with the outbound iATU settings implied by the caller context. As a result of the denoted change there is no longer need in having the two distinctive methods for the Host and End-point outbound iATU setups since the corresponding code can directly call the dw_pcie_prog_outbound_atu() method with the config-structure populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware-ep.c | 21 +++++---- drivers/pci/controller/dwc/pcie-designware-host.c | 52 ++++++++++++++++------- drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++++------------- drivers/pci/controller/dwc/pcie-designware.h | 15 +++++-- 4 files changed, 77 insertions(+), 60 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 5befed2dc02b7..27956b2a73be7 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -159,9 +159,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, return 0; } -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, - phys_addr_t phys_addr, - u64 pci_addr, size_t size) +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, + struct dw_pcie_ob_atu_cfg *atu) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); u32 free_win; @@ -173,13 +172,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, return -EINVAL; } - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM, - phys_addr, pci_addr, size); + atu->index = free_win; + ret = dw_pcie_prog_outbound_atu(pci, atu); if (ret) return ret; set_bit(free_win, ep->ob_window_map); - ep->outbound_addr[free_win] = phys_addr; + ep->outbound_addr[free_win] = atu->cpu_addr; return 0; } @@ -279,8 +278,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, int ret; struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size); + struct dw_pcie_ob_atu_cfg atu = { 0 }; + + atu.func_no = func_no; + atu.type = PCIE_ATU_TYPE_MEM; + atu.cpu_addr = addr; + atu.pci_addr = pci_addr; + atu.size = size; + ret = dw_pcie_ep_outbound_atu(ep, &atu); if (ret) { dev_err(pci->dev, "Failed to enable address\n"); return ret; diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d5fc31f8345f7..267687ab33cbc 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, { struct dw_pcie_rp *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = { 0 }; int type, ret; u32 busdev; @@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, else type = PCIE_ATU_TYPE_CFG1; - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, - pp->cfg0_size); + atu.type = type; + atu.cpu_addr = pp->cfg0_base; + atu.pci_addr = busdev; + atu.size = pp->cfg0_size; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) return NULL; @@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, { struct dw_pcie_rp *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = { 0 }; int ret; ret = pci_generic_config_read(bus, devfn, where, size, val); @@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, return ret; if (pp->cfg0_io_shared) { - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, - pp->io_base, pp->io_bus_addr, - pp->io_size); + atu.type = PCIE_ATU_TYPE_IO; + atu.cpu_addr = pp->io_base; + atu.pci_addr = pp->io_bus_addr; + atu.size = pp->io_size; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) return PCIBIOS_SET_FAILED; } @@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, { struct dw_pcie_rp *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = { 0 }; int ret; ret = pci_generic_config_write(bus, devfn, where, size, val); @@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, return ret; if (pp->cfg0_io_shared) { - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, - pp->io_base, pp->io_bus_addr, - pp->io_size); + atu.type = PCIE_ATU_TYPE_IO; + atu.cpu_addr = pp->io_base; + atu.pci_addr = pp->io_bus_addr; + atu.size = pp->io_size; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) return PCIBIOS_SET_FAILED; } @@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = { static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = { 0 }; struct resource_entry *entry; int i, ret; @@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (pci->num_ob_windows <= ++i) break; - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM, - entry->res->start, - entry->res->start - entry->offset, - resource_size(entry->res)); + atu.index = i; + atu.type = PCIE_ATU_TYPE_MEM; + atu.cpu_addr = entry->res->start; + atu.pci_addr = entry->res->start - entry->offset; + atu.size = resource_size(entry->res); + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) { dev_err(pci->dev, "Failed to set MEM range %pr\n", entry->res); @@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (pp->io_size) { if (pci->num_ob_windows > ++i) { - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO, - pp->io_base, - pp->io_bus_addr, - pp->io_size); + atu.index = i; + atu.type = PCIE_ATU_TYPE_IO; + atu.cpu_addr = pp->io_base; + atu.pci_addr = pp->io_bus_addr; + atu.size = pp->io_size; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) { dev_err(pci->dev, "Failed to set IO range %pr\n", entry->res); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 250cf7f40b858..df2575ec5f44c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -465,56 +465,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val) return val | PCIE_ATU_TD; } -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, - int index, int type, u64 cpu_addr, - u64 pci_addr, u64 size) +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, + const struct dw_pcie_ob_atu_cfg *atu) { + u64 cpu_addr = atu->cpu_addr; u32 retries, val; u64 limit_addr; if (pci->ops && pci->ops->cpu_addr_fixup) cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); - limit_addr = cpu_addr + size - 1; + limit_addr = cpu_addr + atu->size - 1; if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || !IS_ALIGNED(cpu_addr, pci->region_align) || - !IS_ALIGNED(pci_addr, pci->region_align) || !size) { + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { return -EINVAL; } - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE, + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, lower_32_bits(cpu_addr)); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE, + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, upper_32_bits(cpu_addr)); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT, + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, lower_32_bits(limit_addr)); if (dw_pcie_ver_is_ge(pci, 460A)) - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT, + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, upper_32_bits(limit_addr)); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET, - lower_32_bits(pci_addr)); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET, - upper_32_bits(pci_addr)); + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, + lower_32_bits(atu->pci_addr)); + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, + upper_32_bits(atu->pci_addr)); - val = type | PCIE_ATU_FUNC_NUM(func_no); + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && dw_pcie_ver_is_ge(pci, 460A)) val |= PCIE_ATU_INCREASE_REGION_SIZE; if (dw_pcie_ver_is(pci, 490A)) val = dw_pcie_enable_ecrc(val); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val); + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); /* * Make sure ATU enable takes effect before any subsequent config * and I/O accesses. */ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2); + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); if (val & PCIE_ATU_ENABLE) return 0; @@ -526,21 +526,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, return -ETIMEDOUT; } -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, - u64 cpu_addr, u64 pci_addr, u64 size) -{ - return __dw_pcie_prog_outbound_atu(pci, 0, index, type, - cpu_addr, pci_addr, size); -} - -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u64 pci_addr, - u64 size) -{ - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type, - cpu_addr, pci_addr, size); -} - static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) { return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae48374627..d21db82e586d5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -299,6 +299,15 @@ enum dw_pcie_ltssm { DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, }; +struct dw_pcie_ob_atu_cfg { + int index; + int type; + u8 func_no; + u64 cpu_addr; + u64 pci_addr; + u64 size; +}; + struct dw_pcie_host_ops { int (*init)(struct dw_pcie_rp *pp); void (*deinit)(struct dw_pcie_rp *pp); @@ -434,10 +443,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, - u64 cpu_addr, u64 pci_addr, u64 size); -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u64 pci_addr, u64 size); +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, + const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u64 size); int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, From patchwork Fri Feb 2 15:11:25 2024 Content-Type: text/plain; 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PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of MsgD. So, this implementation supports the data-less messages only for now. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++-- drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index df2575ec5f44c..ba909fade9db1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, upper_32_bits(atu->pci_addr)); - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && dw_pcie_ver_is_ge(pci, 460A)) val |= PCIE_ATU_INCREASE_REGION_SIZE; @@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val = dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); + val = PCIE_ATU_ENABLE; + if (atu->type == PCIE_ATU_TYPE_MSG) { + /* The data-less messages only for now */ + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; + } + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); /* * Make sure ATU enable takes effect before any subsequent config diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index d21db82e586d5..703b50bc5e0f1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -148,11 +148,13 @@ #define PCIE_ATU_TYPE_IO 0x2 #define PCIE_ATU_TYPE_CFG0 0x4 #define PCIE_ATU_TYPE_CFG1 0x5 +#define PCIE_ATU_TYPE_MSG 0x10 #define PCIE_ATU_TD BIT(8) #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20) #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 #define PCIE_ATU_UPPER_BASE 0x00C @@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg { int index; 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Fri, 2 Feb 2024 15:11:55 +0000 From: Frank Li Date: Fri, 02 Feb 2024 10:11:26 -0500 Subject: [PATCH v3 4/6] PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro Message-Id: <20240202-pme_msg-v3-4-ff2af57a02ad@nxp.com> References: <20240202-pme_msg-v3-0-ff2af57a02ad@nxp.com> In-Reply-To: <20240202-pme_msg-v3-0-ff2af57a02ad@nxp.com> To: Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , imx@lists.linux.dev Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-c87ef X-Developer-Signature: v=1; a=ed25519-sha256; t=1706886696; l=608; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=ze2L3Nl6ITdmvSqJ46+wd69F0Sc18FLzWocNjgTx/8s=; b=xlDvb9xvDjSEKHo89z84k0VDggPn/A4dlj/anQGCt1jr/oF4yq0trB1uzBZg/oYW01NcRcxi0 nOh0m+ApYo0BGbAMaxkpSGzhDFofkvy6R/qNNdH6AWITHqmg0hJd5Wu X-Developer-Key: i=Frank.Li@nxp.com; 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Signed-off-by: Frank Li --- drivers/pci/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index ffd066c15f3bb..989681a0d6057 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -40,6 +40,8 @@ #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 +#define PCIE_MSG_CODE_PME_TURN_OFF 0x19 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; From patchwork Fri Feb 2 15:11:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13543004 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2078.outbound.protection.outlook.com [40.107.8.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 175A71474BD; Fri, 2 Feb 2024 15:12:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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So all platforms can use common method to send out PME_Turn_Off message by using one outbound iATU. Signed-off-by: Frank Li --- Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 022055edbf9e6..25a5420a9ce1e 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -101,6 +101,10 @@ properties: Outbound iATU-capable memory-region which will be used to access the peripheral PCIe devices configuration space. const: config + - description: + Outbound iATU-capable memory-region which will be used to send + PCIe message (such as PME_Turn_Off) to peripheral. + const: msg - description: Vendor-specific CSR names. Consider using the generic names above for new bindings. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?spuEeFVxUkKrDG2b/Xh2fdoU2iyf?= =?utf-8?q?Nqr/iwtRodFa5GooEVXpx5Cz/lBEKCHVOuijsuvsZmzplK6iugz1gvS6QW4CeDtyL?= =?utf-8?q?vouRoypLzZ+Dz9udYsJ+CjARwzfwyps8JzxpZsc0+gkliy/ppXDFAvkVhdb/WpiUx?= =?utf-8?q?rtZsT9ipqWGVgMaiJchStGnRvBKpNaYxxZPMs9Tu9YzFUr4uhfjnNEhQZ4nIlTush?= =?utf-8?q?ii0Q8qmitkdlsHY+8l5jA1xSCL9Hkc8D7vY0kBo0X42Jqq+O2R/HBPuG/FQIAL262?= =?utf-8?q?ekqHSyzlcpi90o5pYNYsEbIYFE4hUc74Agbm1i+vQGqW51+TYeJ0WoB43n6UO8dkZ?= =?utf-8?q?pc6L55QvOUHt+s/Nb23k/cQyrZ+vMIOqqpXTivopSeYzu8d9/C8x32WcQFUNQ/7kj?= =?utf-8?q?jGVTnlEDz0EKvOPcyyNC/wy9Nil6L80wnQJoO86Co9Pb5zUNCZX3Dl+tcnWWh0TCz?= =?utf-8?q?arhz5m0MP5Bh7Ez35JjPnlZtFGimuTi4Rv794lA7ud2bwDq3TRSeoyOz4sptJ1LaU?= =?utf-8?q?5JC79EBlbP4UAfgz7fe24nAh4HAsDLH9lM5CyBG/CB14U+ts6qx0IBCxEM3+PEroa?= =?utf-8?q?X00r5yLmEJBoD2Pl0kPszCFKxowv7UT5l6YAV4T5aKn6j9OKMT+wv3AQ060U/O/dX?= =?utf-8?q?JMPnPiU4kKIiQMjpod/aCw859adLJLvzSiuBnt2l0KlY59+mTpwjFbN1HO9PGQBTu?= =?utf-8?q?Omy9dkdZpbG5X4GFtfvRMTxn7moZzl8wYQVYM9XDcEXJ2yhI+cc8LNmhf0RnwpjSy?= =?utf-8?q?552CAq/H2kDWSefp1VWoZ+SEKQVTygZ1fu+091vyfEPo3GKDrHLZ5LrQKmSMN7lpP?= =?utf-8?q?JiH0VOSHhPvfC1sSk1/vnIM6hnAe0bmYE4Z6e1rLQMlKdjYr+1dzxkhmWKn5JUnvT?= =?utf-8?q?tNvOB+P26VsQM+w3sc3zuZPHmgJrd98M7kWJPTHlCeNZb2JT54kwgrksKMi529qVc?= =?utf-8?q?DjlKpxjh/oyuM4xojqkAgJ6LUJ7HDbmHlFbpR+UxS5zIABSdGDJ8KST70ddFquIdn?= =?utf-8?q?5X9JIkvXGk/c0rxMGV8Wbjpm5y+YgIgWKmK0RAPrF6aHpIDunIREC2DXhNmIR6/Ml?= =?utf-8?q?UNF44MaHIpKwssgne83S81AEoqE/WjhckBs9ZfnEq9qXlliGc+84hL4KNiRAhcRIp?= =?utf-8?q?CQ5AYpsdpebdsNWkQLFutXmO5uVr25jxVi8gIshFQ1WEWRxUz6JLv0xf7lG0NG5OF?= =?utf-8?q?FlK/JBcY0P5jxmpk95Y28+KngHp1fnYcOfgV+oWB3ky5bHUDucxRjWK1BMUIrrbSq?= =?utf-8?q?jVMT6vxv13DCe9QbVbuh1f9xt6r/cfiiv9J2vEQzQY7KSdjwSROh+pmT8MTL3+t4y?= =?utf-8?q?kxKBEfxYkg+ldM9zfmxzL4JTX6c6ZMkvmt0aYN7ju8bf19JS2Yj5rQBStmI1q8K6W?= =?utf-8?q?MQ2PNbQ5NxscQvGQXL49xD5hCVIkFl70OsCVu26CTM7HVhBjCJ3wH8lWH9FQJuclk?= =?utf-8?q?xQ4xF2mbys8a3TW0h0FgglK3PnYWa7DHk7cjC0W69FGZvhbk311PfpDKjtaGS7huq?= =?utf-8?q?UDuX6eNuPg7m?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 804cd913-c5a9-42dc-e3f8-08dc24014f4f X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2024 15:12:02.4675 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /oilQct4DrKkMOrjH6qS+W58ipshh2PJQmETUqdEfXgwOdVhmLOwvNms8LCK3UWwxwRGbWe7rK871vF12t2a0w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8425 Set outbound ATU map memory write to send PCI message. So one MMIO write can trigger a PCI message, such as PME_Turn_Off. Add common dwc_pme_turn_off() function. Call dwc_pme_turn_off() to send out PME_Turn_Off message in general dw_pcie_suspend_noirq() if there are not platform callback pme_turn_off() exist. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++++++++++-- drivers/pci/controller/dwc/pcie-designware.c | 8 ++++ drivers/pci/controller/dwc/pcie-designware.h | 3 ++ 3 files changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 267687ab33cbc..c177f1076ecea 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -728,6 +728,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", pci->num_ob_windows); + pci->msg_atu_index = i; + i = 0; resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { if (resource_type(entry->res) != IORESOURCE_MEM) @@ -833,11 +835,50 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); +/* Using message outbound ATU to send out PME_Turn_Off message for dwc PCIe controller */ +static int dw_pcie_pme_turn_off(struct dw_pcie *pci) +{ + struct dw_pcie_ob_atu_cfg atu = { 0 }; + void __iomem *m; + int ret = 0; + + if (pci->num_ob_windows <= pci->msg_atu_index) + return -EINVAL; + + atu.code = PCIE_MSG_CODE_PME_TURN_OFF; + atu.routing = PCIE_MSG_TYPE_R_BC; + atu.type = PCIE_ATU_TYPE_MSG; + atu.size = pci->msg_io_size; + + if (!atu.size) { + dev_dbg(pci->dev, + "atu memory map windows is zero, please check 'msg' reg in dts\n"); + return -ENOMEM; + } + + atu.cpu_addr = pci->msg_io_base; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + m = ioremap(atu.cpu_addr, PAGE_SIZE); + if (!m) + return -ENOMEM; + + /* A dummy write is converted to a Msg TLP */ + writel(0, m); + + iounmap(m); + + return ret; +} + int dw_pcie_suspend_noirq(struct dw_pcie *pci) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; - int ret; + int ret = 0; /* * If L1SS is supported, then do not put the link into L2 as some @@ -849,10 +890,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) return 0; - if (!pci->pp.ops->pme_turn_off) - return 0; + if (pci->pp.ops->pme_turn_off) + pci->pp.ops->pme_turn_off(&pci->pp); + else + ret = dw_pcie_pme_turn_off(pci); - pci->pp.ops->pme_turn_off(&pci->pp); + if (ret) + return ret; ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, PCIE_PME_TO_L2_TIMEOUT_US/10, diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index ba909fade9db1..eb24362009bb6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -155,6 +155,14 @@ int dw_pcie_get_resources(struct dw_pcie *pci) } } + if (!pci->msg_io_base) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg"); + if (res) { + pci->msg_io_base = res->start; + pci->msg_io_size = res->end - res->start + 1; + } + } + /* LLDD is supposed to manually switch the clocks and resets state */ if (dw_pcie_cap_is(pci, REQ_RES)) { ret = dw_pcie_get_clocks(pci); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 703b50bc5e0f1..866ab44df9fd1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -424,6 +424,9 @@ struct dw_pcie { struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; bool suspended; + int msg_atu_index; + phys_addr_t msg_io_base; + size_t msg_io_size; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)