From patchwork Mon Feb 5 15:32:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 599DEC48298 for ; Mon, 5 Feb 2024 15:33:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676195.1052153 (Exim 4.92) (envelope-from ) id 1rX0xh-0007IJ-23; Mon, 05 Feb 2024 15:32:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676195.1052153; Mon, 05 Feb 2024 15:32:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xg-0007IB-VQ; Mon, 05 Feb 2024 15:32:44 +0000 Received: by outflank-mailman (input) for mailman id 676195; Mon, 05 Feb 2024 15:32:43 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xf-0007Hv-Cn for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:43 +0000 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [2a00:1450:4864:20::12f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id cd757792-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:32:42 +0100 (CET) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-5115744dfe5so5542e87.2 for ; Mon, 05 Feb 2024 07:32:42 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id s1-20020a056512314100b005114d401157sm474445lfi.2.2024.02.05.07.32.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 07:32:41 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: cd757792-c43b-11ee-8a46-1f161083a0e0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707147161; x=1707751961; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QPaE7lsiNetODMb4yDxZSXp3uI/1BFAvrBNl/vZuK+E=; b=bKqRZn5jdJN6+wt/o+/lL9ABu/9YZy27WMS/LlSgHnuGLpYtAb+4LXisR1YH8HCqFm 3iHEKjEhk3L922sC8EXf0UcHwFHf6y07i4KMxUSz3ge7BOvv7GmLbWpvWCBwZOAA9DgW 8BTic73wpqNu2w+Tyfd6J/Mi4Wk6F4B904d7pEPP1GidqzXyv3bZGe/JCd/jVO9jvuTP 9PSy3jMfMgB+FGhFIn+rCrkUIPsxzy6npB2iFjleBFfncHv2xSUid1VqGCMMLeVzBJXe xugkHkJgeC6jezInvU0lgQ1JPOh/ExoVBgYV1S6RyN2px/YXnzc92jwkb9nlxxMyQDz9 d29g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707147161; x=1707751961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QPaE7lsiNetODMb4yDxZSXp3uI/1BFAvrBNl/vZuK+E=; b=N7TQRdE4KK4TUzKGbp13ZB18D4U/mwFYW0Cuz3hU8vaKdAq0J1uZNeGAFfikY9FGiP w+vROJLeC99X5AFmCe/94Kn1kigl6bn5shYAXg04+oGV00sGZroysV9e2qo/1uWWliJh YnLBUv5B4NDX6g+FfCHMsAQTIuRY89zSNvFqnWf2EoWS9Jk8bkkYOtkEMn1sCgMqY2si rUgoH7cpSW/rLG0mg6WPtGI2AlM+Mm5n0Ie69DbscHhJI4zPipxx13x+VTmV2nE+nL8P 5l0i27PQRb1t5/y5nIKJw7sqxOEMenumtHCr8U4N0kd2adkqOKW4J781UOH2+iTlea8t WT1w== X-Gm-Message-State: AOJu0YweoOJUqjm3oG4HijURvzUtehpchwicuaXMPsxQ4gh7F//WUf4J zk8WJj3+4Z5kTs1kvGF2j/RrPvRP8iErSlFN52n8LphSh09HKbfw8d93pTh6 X-Google-Smtp-Source: AGHT+IHj7ev+GqSUfsoELsOVw/8nhp+7AMv61Oet/v+xMIOQqrZa4qZ6u5PeQKgFzTMP5CzOqPrZJg== X-Received: by 2002:a05:6512:31ca:b0:50e:a789:dd3b with SMTP id j10-20020a05651231ca00b0050ea789dd3bmr7231537lfe.1.1707147161488; Mon, 05 Feb 2024 07:32:41 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCVFa5DpX6sTlNLEgC5k0Lz+lvWZArIUVNAnFr7qgtcW4FKjWwsmyqFiHuoWMgkZQKQ9J3KupSVv0hL+HxfDn3obLPaUicS1IvBaiTsUf+Z/Gaz5dsL9rbP6HxAtvRUcLtlOn7Tka/BJpOXnFMmzS7S6snhK++tJVvjM482qCQO4LattImaKbC0nxKKMQkD2m/lNa4jaFhoI1CgijKO88ksdYEL1 From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Doug Goldstein , Stefano Stabellini , Alistair Francis , Bob Eshleman , Connor Davis Subject: [PATCH v4 01/30] xen/riscv: disable unnecessary configs Date: Mon, 5 Feb 2024 16:32:08 +0100 Message-ID: <3a6ac88525e645e57c0dd44324fadc7ce499369e.1707146506.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 This patch disables unnecessary configs for two cases: 1. By utilizing EXTRA_FIXED_RANDCONFIG and risc-fixed-randconfig.yaml file for randconfig builds (GitLab CI jobs). 2. By using tiny64_defconfig for non-randconfig builds. Signed-off-by: Oleksii Kurochko --- Changes in V4: - Nothing changed. Only rebase --- Changes in V3: - Remove EXTRA_FIXED_RANDCONFIG for non-randconfig jobs. For non-randconfig jobs, it is sufficient to disable configs by using the defconfig. - Remove double blank lines in build.yaml file before archlinux-current-gcc-riscv64-debug --- Changes in V2: - update the commit message. - remove xen/arch/riscv/Kconfig changes. --- .../gitlab-ci/riscv-fixed-randconfig.yaml | 27 +++++++++++++++++++ xen/arch/riscv/configs/tiny64_defconfig | 17 ++++++++++++ 2 files changed, 44 insertions(+) diff --git a/automation/gitlab-ci/riscv-fixed-randconfig.yaml b/automation/gitlab-ci/riscv-fixed-randconfig.yaml index f1282b40c9..344f39c2d8 100644 --- a/automation/gitlab-ci/riscv-fixed-randconfig.yaml +++ b/automation/gitlab-ci/riscv-fixed-randconfig.yaml @@ -5,3 +5,30 @@ CONFIG_EXPERT=y CONFIG_GRANT_TABLE=n CONFIG_MEM_ACCESS=n + CONFIG_COVERAGE=n + CONFIG_SCHED_CREDIT=n + CONFIG_SCHED_CREDIT2=n + CONFIG_SCHED_RTDS=n + CONFIG_SCHED_NULL=n + CONFIG_SCHED_ARINC653=n + CONFIG_TRACEBUFFER=n + CONFIG_HYPFS=n + CONFIG_SPECULATIVE_HARDEN_ARRAY=n + CONFIG_ARGO=n + CONFIG_HYPFS_CONFIG=n + CONFIG_CORE_PARKING=n + CONFIG_DEBUG_TRACE=n + CONFIG_IOREQ_SERVER=n + CONFIG_CRASH_DEBUG=n + CONFIG_KEXEC=n + CONFIG_LIVEPATCH=n + CONFIG_NUMA=n + CONFIG_PERF_COUNTERS=n + CONFIG_HAS_PMAP=n + CONFIG_TRACEBUFFER=n + CONFIG_XENOPROF=n + CONFIG_COMPAT=n + CONFIG_COVERAGE=n + CONFIG_UBSAN=n + CONFIG_NEEDS_LIBELF=n + CONFIG_XSM=n diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig index 09defe236b..35915255e6 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -7,6 +7,23 @@ # CONFIG_GRANT_TABLE is not set # CONFIG_SPECULATIVE_HARDEN_ARRAY is not set # CONFIG_MEM_ACCESS is not set +# CONFIG_ARGO is not set +# CONFIG_HYPFS_CONFIG is not set +# CONFIG_CORE_PARKING is not set +# CONFIG_DEBUG_TRACE is not set +# CONFIG_IOREQ_SERVER is not set +# CONFIG_CRASH_DEBUG is not setz +# CONFIG_KEXEC is not set +# CONFIG_LIVEPATCH is not set +# CONFIG_NUMA is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_HAS_PMAP is not set +# CONFIG_TRACEBUFFER is not set +# CONFIG_XENOPROF is not set +# CONFIG_COMPAT is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NEEDS_LIBELF is not set CONFIG_RISCV_64=y CONFIG_DEBUG=y From patchwork Mon Feb 5 15:32:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33A06C4829E for ; Mon, 5 Feb 2024 15:33:02 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676196.1052162 (Exim 4.92) (envelope-from ) id 1rX0xi-0007WZ-99; Mon, 05 Feb 2024 15:32:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676196.1052162; Mon, 05 Feb 2024 15:32:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xi-0007WS-6I; Mon, 05 Feb 2024 15:32:46 +0000 Received: by outflank-mailman (input) for mailman id 676196; Mon, 05 Feb 2024 15:32:44 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xg-0007Hv-1q for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:44 +0000 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [2a00:1450:4864:20::12a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id cdf39f89-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:32:43 +0100 (CET) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-5114fa38434so1247127e87.0 for ; Mon, 05 Feb 2024 07:32:43 -0800 (PST) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- As [PATCH v6 0/9] Introduce generic headers (https://lore.kernel.org/xen-devel/cover.1703072575.git.oleksii.kurochko@gmail.com/) is not stable, the list in asm/Makefile can be changed, but the changes will be easy. --- Changes in V4: - removed numa.h from asm/include/Makefile because of the patch: [PATCH v2] NUMA: no need for asm/numa.h when !NUMA - updated the commit message --- Changes in V3: - remove monitor.h from the RISC-V asm/Makefile list. - add Acked-by: Jan Beulich --- Changes in V2: - New commit introduced in V2. --- xen/arch/riscv/include/asm/Makefile | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 xen/arch/riscv/include/asm/Makefile diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/asm/Makefile new file mode 100644 index 0000000000..ced02e26ed --- /dev/null +++ b/xen/arch/riscv/include/asm/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +generic-y += altp2m.h +generic-y += device.h +generic-y += div64.h +generic-y += hardirq.h +generic-y += hypercall.h +generic-y += iocap.h +generic-y += paging.h +generic-y += percpu.h +generic-y += random.h +generic-y += softirq.h +generic-y += vm_event.h From patchwork Mon Feb 5 15:32:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CD4DC4828D for ; Mon, 5 Feb 2024 15:33:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676198.1052174 (Exim 4.92) (envelope-from ) id 1rX0xi-0007fM-TM; Mon, 05 Feb 2024 15:32:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676198.1052174; Mon, 05 Feb 2024 15:32:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xi-0007e8-Ns; Mon, 05 Feb 2024 15:32:46 +0000 Received: by outflank-mailman (input) for mailman id 676198; Mon, 05 Feb 2024 15:32:45 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xh-0007Hv-NS for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:45 +0000 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [2a00:1450:4864:20::12c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id cf13b1bf-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:32:45 +0100 (CET) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-51124d86022so7009478e87.0 for ; Mon, 05 Feb 2024 07:32:45 -0800 (PST) Received: from fedora.. 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Code related to PPC was changed based on the comment: https://lore.kernel.org/xen-devel/c2f3280e-2208-496b-a0b5-fda1a2076b3a@raptorengineering.com/ Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V4: - Updated the commit message --- Changes in V3: - update the commit message. - For PPC and RISC-V nothing to include in public/hvm/save.h, so just comment was added. --- Changes in V2: - remove copyright an the top of hvm/save.h as the header write now is a newly introduced empty header. --- xen/include/public/hvm/save.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/public/hvm/save.h b/xen/include/public/hvm/save.h index 5561495b27..72e16ab5bc 100644 --- a/xen/include/public/hvm/save.h +++ b/xen/include/public/hvm/save.h @@ -89,8 +89,8 @@ DECLARE_HVM_SAVE_TYPE(END, 0, struct hvm_save_end); #include "../arch-x86/hvm/save.h" #elif defined(__arm__) || defined(__aarch64__) #include "../arch-arm/hvm/save.h" -#elif defined(__powerpc64__) -#include "../arch-ppc.h" +#elif defined(__powerpc64__) || defined(__riscv) +/* no specific header to include */ #else #error "unsupported architecture" #endif From patchwork Mon Feb 5 15:32:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 318FDC48297 for ; Mon, 5 Feb 2024 15:33:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676199.1052192 (Exim 4.92) (envelope-from ) id 1rX0xl-0008Fv-B8; Mon, 05 Feb 2024 15:32:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676199.1052192; Mon, 05 Feb 2024 15:32:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xl-0008Fh-85; Mon, 05 Feb 2024 15:32:49 +0000 Received: by outflank-mailman (input) for mailman id 676199; Mon, 05 Feb 2024 15:32:47 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xj-0007I6-Np for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:47 +0000 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [2a00:1450:4864:20::22d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id cf9f5f23-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:32:46 +0100 (CET) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2cf206e4d56so62538941fa.3 for ; Mon, 05 Feb 2024 07:32:46 -0800 (PST) Received: from fedora.. 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Only rebase --- Changes in V3: - add SPDX and footer - update declaration of cpu_nr_siblings() to return unsigned int instead of int. - add Acked-by: Jan Beulich --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/cpufeature.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 xen/arch/riscv/include/asm/cpufeature.h diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/include/asm/cpufeature.h new file mode 100644 index 0000000000..c08b7d67ad --- /dev/null +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_CPUFEATURE_H +#define __ASM_RISCV_CPUFEATURE_H + +#ifndef __ASSEMBLY__ + +static inline unsigned int cpu_nr_siblings(unsigned int cpu) +{ + return 1; +} + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_RISCV_CPUFEATURE_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75C75C4829A for ; Mon, 5 Feb 2024 15:33:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676200.1052199 (Exim 4.92) (envelope-from ) id 1rX0xl-0008Jd-Ms; Mon, 05 Feb 2024 15:32:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676200.1052199; Mon, 05 Feb 2024 15:32:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xl-0008Il-Gm; Mon, 05 Feb 2024 15:32:49 +0000 Received: by outflank-mailman (input) for mailman id 676200; Mon, 05 Feb 2024 15:32:48 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xk-0007I6-OC for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:48 +0000 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [2a00:1450:4864:20::134]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d028054a-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:32:47 +0100 (CET) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-51121637524so6822970e87.1 for ; Mon, 05 Feb 2024 07:32:47 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/guest_atomics.h | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest_atomics.h diff --git a/xen/arch/riscv/include/asm/guest_atomics.h b/xen/arch/riscv/include/asm/guest_atomics.h new file mode 100644 index 0000000000..de54914454 --- /dev/null +++ b/xen/arch/riscv/include/asm/guest_atomics.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_GUEST_ATOMICS_H +#define __ASM_RISCV_GUEST_ATOMICS_H + +#include + +#define guest_testop(name) \ +static inline int guest_##name(struct domain *d, int nr, volatile void *p) \ +{ \ + BUG_ON("unimplemented"); \ + \ + return 0; \ +} + +#define guest_bitop(name) \ +static inline void guest_##name(struct domain *d, int nr, volatile void *p) \ +{ \ + BUG_ON("unimplemented"); \ +} + +guest_bitop(set_bit) +guest_bitop(clear_bit) +guest_bitop(change_bit) + +#undef guest_bitop + +guest_testop(test_and_set_bit) +guest_testop(test_and_clear_bit) +guest_testop(test_and_change_bit) + +#undef guest_testop + +#define guest_test_bit(d, nr, p) ((void)(d), test_bit(nr, p)) + +#endif /* __ASM_RISCV_GUEST_ATOMICS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C1A7C4829F for ; Mon, 5 Feb 2024 15:33:03 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676201.1052213 (Exim 4.92) (envelope-from ) id 1rX0xn-0000Ir-0J; Mon, 05 Feb 2024 15:32:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676201.1052213; Mon, 05 Feb 2024 15:32:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xm-0000Ih-Rg; Mon, 05 Feb 2024 15:32:50 +0000 Received: by outflank-mailman (input) for mailman id 676201; Mon, 05 Feb 2024 15:32:49 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xl-0007I6-Oa for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:49 +0000 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [2a00:1450:4864:20::133]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d0af2684-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:32:47 +0100 (CET) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-51124db6cf0so3952831e87.0 for ; Mon, 05 Feb 2024 07:32:47 -0800 (PST) Received: from fedora.. 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As is ifdef-ed by CONFIG_HAS_PASSTHROUGH it should be also ifdef-ed field "struct arch_iommu arch" in struct domain_iommu as definition of arch_iommu is located in . These amount of changes are enough to avoid generation of empty asm/iommu.h for now. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V4: - Update the commit message. --- Changes in V3: - new patch. --- xen/include/xen/iommu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index a21f25df9f..7aa6a77209 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -337,7 +337,9 @@ extern int iommu_add_extra_reserved_device_memory(unsigned long start, extern int iommu_get_extra_reserved_device_memory(iommu_grdm_t *func, void *ctxt); +#ifdef CONFIG_HAS_PASSTHROUGH #include +#endif #ifndef iommu_call # define iommu_call(ops, fn, args...) ((ops)->fn(args)) @@ -345,7 +347,9 @@ extern int iommu_get_extra_reserved_device_memory(iommu_grdm_t *func, #endif struct domain_iommu { +#ifdef CONFIG_HAS_PASSTHROUGH struct arch_iommu arch; +#endif /* iommu_ops */ const struct iommu_ops *platform_ops; From patchwork Mon Feb 5 15:32:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DC3AC4829B for ; Mon, 5 Feb 2024 15:33:02 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676203.1052228 (Exim 4.92) (envelope-from ) id 1rX0xo-0000fF-TB; Mon, 05 Feb 2024 15:32:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676203.1052228; Mon, 05 Feb 2024 15:32:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xo-0000e6-In; Mon, 05 Feb 2024 15:32:52 +0000 Received: by outflank-mailman (input) for mailman id 676203; Mon, 05 Feb 2024 15:32:51 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xn-0007I6-6m for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:51 +0000 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [2a00:1450:4864:20::133]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d1b5319b-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:32:49 +0100 (CET) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-51124d86022so7009589e87.0 for ; Mon, 05 Feb 2024 07:32:49 -0800 (PST) Received: from fedora.. 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Arm's nospec.h was taken as a base with updated guards: _ASM_ARM_NOSPEC_H -> _ASM_GENERIC_NOSPEC_H Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V4: - Rebase the patch. It was conflics in asm/include/Makefile because it doesn't contain numa.h in it because of the patch: [PATCH v2] NUMA: no need for asm/numa.h when !NUMA - Properly move/rename the Arm's nospec.h with only guards update in the header from _ASM_ARM_NOSPEC_H to _ASM_GENERIC_NOSPEC_H. - Acked-by: Jan Beulich --- Changes in V3: - new patch. --- xen/arch/arm/include/asm/Makefile | 1 + xen/arch/ppc/include/asm/Makefile | 1 + xen/arch/ppc/include/asm/nospec.h | 15 --------------- xen/arch/riscv/include/asm/Makefile | 1 + .../include/asm => include/asm-generic}/nospec.h | 6 +++--- 5 files changed, 6 insertions(+), 18 deletions(-) delete mode 100644 xen/arch/ppc/include/asm/nospec.h rename xen/{arch/arm/include/asm => include/asm-generic}/nospec.h (79%) diff --git a/xen/arch/arm/include/asm/Makefile b/xen/arch/arm/include/asm/Makefile index 4a4036c951..41f73bf968 100644 --- a/xen/arch/arm/include/asm/Makefile +++ b/xen/arch/arm/include/asm/Makefile @@ -3,6 +3,7 @@ generic-y += altp2m.h generic-y += device.h generic-y += hardirq.h generic-y += iocap.h +generic-y += nospec.h generic-y += paging.h generic-y += percpu.h generic-y += random.h diff --git a/xen/arch/ppc/include/asm/Makefile b/xen/arch/ppc/include/asm/Makefile index ced02e26ed..2e8623bb10 100644 --- a/xen/arch/ppc/include/asm/Makefile +++ b/xen/arch/ppc/include/asm/Makefile @@ -5,6 +5,7 @@ generic-y += div64.h generic-y += hardirq.h generic-y += hypercall.h generic-y += iocap.h +generic-y += nospec.h generic-y += paging.h generic-y += percpu.h generic-y += random.h diff --git a/xen/arch/ppc/include/asm/nospec.h b/xen/arch/ppc/include/asm/nospec.h deleted file mode 100644 index b97322e48d..0000000000 --- a/xen/arch/ppc/include/asm/nospec.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* From arch/arm/include/asm/nospec.h. */ -#ifndef __ASM_PPC_NOSPEC_H__ -#define __ASM_PPC_NOSPEC_H__ - -static inline bool evaluate_nospec(bool condition) -{ - return condition; -} - -static inline void block_speculation(void) -{ -} - -#endif /* __ASM_PPC_NOSPEC_H__ */ diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/asm/Makefile index ced02e26ed..2e8623bb10 100644 --- a/xen/arch/riscv/include/asm/Makefile +++ b/xen/arch/riscv/include/asm/Makefile @@ -5,6 +5,7 @@ generic-y += div64.h generic-y += hardirq.h generic-y += hypercall.h generic-y += iocap.h +generic-y += nospec.h generic-y += paging.h generic-y += percpu.h generic-y += random.h diff --git a/xen/arch/arm/include/asm/nospec.h b/xen/include/asm-generic/nospec.h similarity index 79% rename from xen/arch/arm/include/asm/nospec.h rename to xen/include/asm-generic/nospec.h index 51c7aea4f4..65fd745db2 100644 --- a/xen/arch/arm/include/asm/nospec.h +++ b/xen/include/asm-generic/nospec.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. */ -#ifndef _ASM_ARM_NOSPEC_H -#define _ASM_ARM_NOSPEC_H +#ifndef _ASM_GENERIC_NOSPEC_H +#define _ASM_GENERIC_NOSPEC_H static inline bool evaluate_nospec(bool condition) { @@ -13,7 +13,7 @@ static inline void block_speculation(void) { } -#endif /* _ASM_ARM_NOSPEC_H */ +#endif /* _ASM_GENERIC_NOSPEC_H */ /* * Local variables: From patchwork Mon Feb 5 15:32:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27FC4C4829D for ; Mon, 5 Feb 2024 15:33:02 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676202.1052223 (Exim 4.92) (envelope-from ) id 1rX0xo-0000a4-BP; Mon, 05 Feb 2024 15:32:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676202.1052223; Mon, 05 Feb 2024 15:32:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xo-0000ZX-6s; Mon, 05 Feb 2024 15:32:52 +0000 Received: by outflank-mailman (input) for mailman id 676202; Mon, 05 Feb 2024 15:32:51 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xm-0007Hv-Uc for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:50 +0000 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [2a00:1450:4864:20::131]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d21fed8e-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:32:50 +0100 (CET) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-510faac8c57so2310580e87.1 for ; Mon, 05 Feb 2024 07:32:50 -0800 (PST) Received: from fedora.. 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Only rebase --- Changes in V3: - add SPDX - add Acked-by: Jan Beulich --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/setup.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 xen/arch/riscv/include/asm/setup.h diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/asm/setup.h new file mode 100644 index 0000000000..7613a5dbd0 --- /dev/null +++ b/xen/arch/riscv/include/asm/setup.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_RISCV_SETUP_H__ +#define __ASM_RISCV_SETUP_H__ + +#define max_init_domid (0) + +#endif /* __ASM_RISCV_SETUP_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A56AC48297 for ; Mon, 5 Feb 2024 15:33:07 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676205.1052252 (Exim 4.92) (envelope-from ) id 1rX0xs-0001UB-Qf; Mon, 05 Feb 2024 15:32:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676205.1052252; Mon, 05 Feb 2024 15:32:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xs-0001TJ-I6; Mon, 05 Feb 2024 15:32:56 +0000 Received: by outflank-mailman (input) for mailman id 676205; Mon, 05 Feb 2024 15:32:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xq-0007I6-V0 for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:55 +0000 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [2a00:1450:4864:20::133]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d336bf53-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:32:52 +0100 (CET) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-5111c7d40deso7533965e87.1 for ; Mon, 05 Feb 2024 07:32:52 -0800 (PST) Received: from fedora.. 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Additionaly, the following bit ops are introduced: * __ffs * ffsl * fls * flsl * ffs * ffz * find_first_bit_set * hweight64 * test_bit Some of the introduced bit operations are included in asm-generic, as they exhibit similarity across multiple architectures. Signed-off-by: Oleksii Kurochko --- Changes in V4: - updated the commit message: dropped the message about what was taken from linux/include/asm-generic/bitops/find.h as related changes now are located in xen/bitops.h. Also these changes were removed from riscv/bitops.h - switch tabs to spaces. - update return type of __ffs function, format __ffs according to Xen code style. Move the function to respective asm-generic header. - format ffsl() according to Xen code style, update the type of num: int -> unsigned to be align with return type of the function. Move the function to respective asm-generic header. - add new line for the files: asm-generic/bitops-bits.h asm-generic/ffz.h asm-generic/find-first-bit-set.h asm-generic/fls.h asm-generic/flsl.h asm-generic/test-bit.h - rename asm-generic/find-first-bit-set.h to asm-generic/find-first-set-bit.h to be aligned with the function name implemented inside. - introduce generic___test_and*() operation for non-atomic bitops. - rename current __test_and_*() -> test_and_*() as their implementation are atomic aware. - define __test_and_*() to generic___test_and_*(). - introduce test_and_change_bit(). - update asm-generic/bitops/bitops-bits.h to give possoibility to change BITOP_*() macros by architecture. Also, it was introduced bitops_uint_t type to make generic___test_and_*() generic. - "include asm-generic/bitops/bitops-bits.h" to files which use its definitions. - add comment why generic ffz is defined as __ffs(). - update the commit message. - swtich ffsl() to generic_ffsl(). --- Changes in V3: - update the commit message - Introduce the following asm-generic bitops headers: create mode 100644 xen/arch/riscv/include/asm/bitops.h create mode 100644 xen/include/asm-generic/bitops/bitops-bits.h create mode 100644 xen/include/asm-generic/bitops/ffs.h create mode 100644 xen/include/asm-generic/bitops/ffz.h create mode 100644 xen/include/asm-generic/bitops/find-first-bit-set.h create mode 100644 xen/include/asm-generic/bitops/fls.h create mode 100644 xen/include/asm-generic/bitops/flsl.h create mode 100644 xen/include/asm-generic/bitops/hweight.h create mode 100644 xen/include/asm-generic/bitops/test-bit.h - switch some bitops functions to asm-generic's versions. - re-sync some macros with Linux kernel version mentioned in the commit message. - Xen code style fixes. --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/bitops.h | 164 ++++++++++++++++++ xen/arch/riscv/include/asm/config.h | 2 + xen/include/asm-generic/bitops/__ffs.h | 47 +++++ xen/include/asm-generic/bitops/bitops-bits.h | 21 +++ xen/include/asm-generic/bitops/ffs.h | 9 + xen/include/asm-generic/bitops/ffsl.h | 16 ++ xen/include/asm-generic/bitops/ffz.h | 18 ++ .../asm-generic/bitops/find-first-set-bit.h | 17 ++ xen/include/asm-generic/bitops/fls.h | 18 ++ xen/include/asm-generic/bitops/flsl.h | 10 ++ .../asm-generic/bitops/generic-non-atomic.h | 89 ++++++++++ xen/include/asm-generic/bitops/hweight.h | 13 ++ xen/include/asm-generic/bitops/test-bit.h | 18 ++ 13 files changed, 442 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bitops.h create mode 100644 xen/include/asm-generic/bitops/__ffs.h create mode 100644 xen/include/asm-generic/bitops/bitops-bits.h create mode 100644 xen/include/asm-generic/bitops/ffs.h create mode 100644 xen/include/asm-generic/bitops/ffsl.h create mode 100644 xen/include/asm-generic/bitops/ffz.h create mode 100644 xen/include/asm-generic/bitops/find-first-set-bit.h create mode 100644 xen/include/asm-generic/bitops/fls.h create mode 100644 xen/include/asm-generic/bitops/flsl.h create mode 100644 xen/include/asm-generic/bitops/generic-non-atomic.h create mode 100644 xen/include/asm-generic/bitops/hweight.h create mode 100644 xen/include/asm-generic/bitops/test-bit.h diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/asm/bitops.h new file mode 100644 index 0000000000..1225298d35 --- /dev/null +++ b/xen/arch/riscv/include/asm/bitops.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012 Regents of the University of California */ + +#ifndef _ASM_RISCV_BITOPS_H +#define _ASM_RISCV_BITOPS_H + +#include + +#include + +/* Based on linux/arch/include/linux/bits.h */ + +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) + +#define __set_bit(n,p) set_bit(n,p) +#define __clear_bit(n,p) clear_bit(n,p) + +/* Based on linux/arch/include/asm/bitops.h */ + +#if ( BITS_PER_LONG == 64 ) +#define __AMO(op) "amo" #op ".d" +#elif ( BITS_PER_LONG == 32 ) +#define __AMO(op) "amo" #op ".w" +#else +#error "Unexpected BITS_PER_LONG" +#endif + +#define __test_and_op_bit_ord(op, mod, nr, addr, ord) \ +({ \ + unsigned long __res, __mask; \ + __mask = BIT_MASK(nr); \ + __asm__ __volatile__ ( \ + __AMO(op) #ord " %0, %2, %1" \ + : "=r" (__res), "+A" (addr[BIT_WORD(nr)]) \ + : "r" (mod(__mask)) \ + : "memory"); \ + ((__res & __mask) != 0); \ +}) + +#define __op_bit_ord(op, mod, nr, addr, ord) \ + __asm__ __volatile__ ( \ + __AMO(op) #ord " zero, %1, %0" \ + : "+A" (addr[BIT_WORD(nr)]) \ + : "r" (mod(BIT_MASK(nr))) \ + : "memory"); + +#define __test_and_op_bit(op, mod, nr, addr) \ + __test_and_op_bit_ord(op, mod, nr, addr, .aqrl) +#define __op_bit(op, mod, nr, addr) \ + __op_bit_ord(op, mod, nr, addr, ) + +/* Bitmask modifiers */ +#define __NOP(x) (x) +#define __NOT(x) (~(x)) + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation may be reordered on other architectures than x86. + */ +static inline int test_and_set_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + return __test_and_op_bit(or, __NOP, nr, addr); +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation can be reordered on other architectures other than x86. + */ +static inline int test_and_clear_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + return __test_and_op_bit(and, __NOT, nr, addr); +} + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + __op_bit(or, __NOP, nr, addr); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + */ +static inline void clear_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + __op_bit(and, __NOT, nr, addr); +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + return __test_and_op_bit(xor, __NOP, nr, addr); +} + +#undef __test_and_op_bit +#undef __op_bit +#undef __NOP +#undef __NOT +#undef __AMO + +#include + +#define __test_and_set_bit generic___test_and_set_bit +#define __test_and_clear_bit generic___test_and_clear_bit +#define __test_and_change_bit generic___test_and_change_bit + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _ASM_RISCV_BITOPS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index a80cdd4f85..56387ac159 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -50,6 +50,8 @@ # error "Unsupported RISCV variant" #endif +#define BITS_PER_BYTE 8 + #define BYTES_PER_LONG (1 << LONG_BYTEORDER) #define BITS_PER_LONG (BYTES_PER_LONG << 3) #define POINTER_ALIGN BYTES_PER_LONG diff --git a/xen/include/asm-generic/bitops/__ffs.h b/xen/include/asm-generic/bitops/__ffs.h new file mode 100644 index 0000000000..fecb4484d9 --- /dev/null +++ b/xen/include/asm-generic/bitops/__ffs.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS___FFS_H_ +#define _ASM_GENERIC_BITOPS___FFS_H_ + +/** + * ffs - find first bit in word. + * @word: The word to search + * + * Returns 0 if no bit exists, otherwise returns 1-indexed bit location. + */ +static inline unsigned int __ffs(unsigned long word) +{ + unsigned int num = 0; + +#if BITS_PER_LONG == 64 + if ( (word & 0xffffffff) == 0 ) + { + num += 32; + word >>= 32; + } +#endif + if ( (word & 0xffff) == 0 ) + { + num += 16; + word >>= 16; + } + if ( (word & 0xff) == 0 ) + { + num += 8; + word >>= 8; + } + if ( (word & 0xf) == 0 ) + { + num += 4; + word >>= 4; + } + if ( (word & 0x3) == 0 ) + { + num += 2; + word >>= 2; + } + if ( (word & 0x1) == 0 ) + num += 1; + return num; +} + +#endif /* _ASM_GENERIC_BITOPS___FFS_H_ */ diff --git a/xen/include/asm-generic/bitops/bitops-bits.h b/xen/include/asm-generic/bitops/bitops-bits.h new file mode 100644 index 0000000000..4ece2affd6 --- /dev/null +++ b/xen/include/asm-generic/bitops/bitops-bits.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_BITS_H_ +#define _ASM_GENERIC_BITOPS_BITS_H_ + +#ifndef BITOP_BITS_PER_WORD +#define BITOP_BITS_PER_WORD 32 +#endif + +#ifndef BITOP_MASK +#define BITOP_MASK(nr) (1U << ((nr) % BITOP_BITS_PER_WORD)) +#endif + +#ifndef BITOP_WORD +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) +#endif + +#ifndef BITOP_TYPE +typedef uint32_t bitops_uint_t; +#endif + +#endif /* _ASM_GENERIC_BITOPS_BITS_H_ */ diff --git a/xen/include/asm-generic/bitops/ffs.h b/xen/include/asm-generic/bitops/ffs.h new file mode 100644 index 0000000000..3f75fded14 --- /dev/null +++ b/xen/include/asm-generic/bitops/ffs.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ + +#include + +#define ffs(x) ({ unsigned int t_ = (x); fls(ISOLATE_LSB(t_)); }) + +#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/xen/include/asm-generic/bitops/ffsl.h b/xen/include/asm-generic/bitops/ffsl.h new file mode 100644 index 0000000000..d0996808f5 --- /dev/null +++ b/xen/include/asm-generic/bitops/ffsl.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FFSL_H_ +#define _ASM_GENERIC_BITOPS_FFSL_H_ + +/** + * ffsl - find first bit in long. + * @word: The word to search + * + * Returns 0 if no bit exists, otherwise returns 1-indexed bit location. + */ +static inline unsigned int ffsl(unsigned long word) +{ + return generic_ffsl(word); +} + +#endif /* _ASM_GENERIC_BITOPS_FFSL_H_ */ diff --git a/xen/include/asm-generic/bitops/ffz.h b/xen/include/asm-generic/bitops/ffz.h new file mode 100644 index 0000000000..5932fe6695 --- /dev/null +++ b/xen/include/asm-generic/bitops/ffz.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FFZ_H_ +#define _ASM_GENERIC_BITOPS_FFZ_H_ + +/* + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + * + * ffz() is defined as __ffs() and not as ffs() as it is defined in such + * a way in Linux kernel (6.4.0 ) from where this header was taken, so this + * header is supposed to be aligned with Linux kernel version. + * Also, most architectures are defined in the same way in Xen. + */ +#define ffz(x) __ffs(~(x)) + +#endif /* _ASM_GENERIC_BITOPS_FFZ_H_ */ diff --git a/xen/include/asm-generic/bitops/find-first-set-bit.h b/xen/include/asm-generic/bitops/find-first-set-bit.h new file mode 100644 index 0000000000..7d28b8a89b --- /dev/null +++ b/xen/include/asm-generic/bitops/find-first-set-bit.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FIND_FIRST_SET_BIT_H_ +#define _ASM_GENERIC_BITOPS_FIND_FIRST_SET_BIT_H_ + +/** + * find_first_set_bit - find the first set bit in @word + * @word: the word to search + * + * Returns the bit-number of the first set bit (first bit being 0). + * The input must *not* be zero. + */ +static inline unsigned int find_first_set_bit(unsigned long word) +{ + return ffsl(word) - 1; +} + +#endif /* _ASM_GENERIC_BITOPS_FIND_FIRST_SET_BIT_H_ */ diff --git a/xen/include/asm-generic/bitops/fls.h b/xen/include/asm-generic/bitops/fls.h new file mode 100644 index 0000000000..369a4c790c --- /dev/null +++ b/xen/include/asm-generic/bitops/fls.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FLS_H_ +#define _ASM_GENERIC_BITOPS_FLS_H_ + +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ + +static inline int fls(unsigned int x) +{ + return generic_fls(x); +} + +#endif /* _ASM_GENERIC_BITOPS_FLS_H_ */ diff --git a/xen/include/asm-generic/bitops/flsl.h b/xen/include/asm-generic/bitops/flsl.h new file mode 100644 index 0000000000..d0a2e9c729 --- /dev/null +++ b/xen/include/asm-generic/bitops/flsl.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_FLSL_H_ +#define _ASM_GENERIC_BITOPS_FLSL_H_ + +static inline int flsl(unsigned long x) +{ + return generic_flsl(x); +} + +#endif /* _ASM_GENERIC_BITOPS_FLSL_H_ */ diff --git a/xen/include/asm-generic/bitops/generic-non-atomic.h b/xen/include/asm-generic/bitops/generic-non-atomic.h new file mode 100644 index 0000000000..07efca245e --- /dev/null +++ b/xen/include/asm-generic/bitops/generic-non-atomic.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * The file is based on Linux ( 6.4.0 ) header: + * include/asm-generic/bitops/generic-non-atomic.h + * + * Only functions that can be reused in Xen were left; others were removed. + * + * Also, the following changes were done: + * - it was updated the message inside #ifndef ... #endif. + * - __always_inline -> always_inline to be align with definition in + * xen/compiler.h. + * - update function prototypes from + * generic___test_and_*(unsigned long nr nr, volatile unsigned long *addr) to + * generic___test_and_*(unsigned long nr, volatile void *addr) to be + * consistent with other related macros/defines. + * - convert identations from tabs to spaces. + * - inside generic__test_and_* use 'bitops_uint_t' instead of 'unsigned long' + * to be generic. + */ + +#ifndef __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H +#define __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H + +#include + +#include + +#ifndef _LINUX_BITOPS_H +#error only can be included directly +#endif + +/* + * Generic definitions for bit operations, should not be used in regular code + * directly. + */ + +/** + * generic___test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic___test_and_set_bit(unsigned long nr, volatile void *addr) +{ + bitops_uint_t mask = BIT_MASK(nr); + bitops_uint_t *p = ((bitops_uint_t *)addr) + BIT_WORD(nr); + bitops_uint_t old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +/** + * generic___test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic___test_and_clear_bit(bitops_uint_t nr, volatile void *addr) +{ + bitops_uint_t mask = BIT_MASK(nr); + bitops_uint_t *p = ((bitops_uint_t *)addr) + BIT_WORD(nr); + bitops_uint_t old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +/* WARNING: non atomic and it can be reordered! */ +static always_inline bool +generic___test_and_change_bit(unsigned long nr, volatile void *addr) +{ + bitops_uint_t mask = BIT_MASK(nr); + bitops_uint_t *p = ((bitops_uint_t *)addr) + BIT_WORD(nr); + bitops_uint_t old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +#endif /* __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H */ diff --git a/xen/include/asm-generic/bitops/hweight.h b/xen/include/asm-generic/bitops/hweight.h new file mode 100644 index 0000000000..0d7577054e --- /dev/null +++ b/xen/include/asm-generic/bitops/hweight.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_HWEIGHT_H_ +#define _ASM_GENERIC_BITOPS_HWEIGHT_H_ + +/* + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ +#define hweight64(x) generic_hweight64(x) + +#endif /* _ASM_GENERIC_BITOPS_HWEIGHT_H_ */ diff --git a/xen/include/asm-generic/bitops/test-bit.h b/xen/include/asm-generic/bitops/test-bit.h new file mode 100644 index 0000000000..6fb414d808 --- /dev/null +++ b/xen/include/asm-generic/bitops/test-bit.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS_TESTBIT_H_ +#define _ASM_GENERIC_BITOPS_TESTBIT_H_ + +#include + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile void *addr) +{ + const volatile bitops_uint_t *p = addr; + return 1 & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD - 1))); +} + +#endif /* _ASM_GENERIC_BITOPS_TESTBIT_H_ */ From patchwork Mon Feb 5 15:32:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75CADC4829C for ; Mon, 5 Feb 2024 15:33:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676204.1052243 (Exim 4.92) (envelope-from ) id 1rX0xr-0001E8-Dx; Mon, 05 Feb 2024 15:32:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676204.1052243; Mon, 05 Feb 2024 15:32:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xr-0001Dm-8X; Mon, 05 Feb 2024 15:32:55 +0000 Received: by outflank-mailman (input) for mailman id 676204; Mon, 05 Feb 2024 15:32:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xp-0007I6-Up for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:53 +0000 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [2a00:1450:4864:20::131]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d356a980-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:32:52 +0100 (CET) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-511490772f6so1897755e87.2 for ; Mon, 05 Feb 2024 07:32:52 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/flushtlb.h | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 xen/arch/riscv/include/asm/flushtlb.h diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include/asm/flushtlb.h new file mode 100644 index 0000000000..7ce32bea0b --- /dev/null +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_FLUSHTLB_H__ +#define __ASM_RISCV_FLUSHTLB_H__ + +#include +#include + +/* + * Filter the given set of CPUs, removing those that definitely flushed their + * TLB since @page_timestamp. + */ +/* XXX lazy implementation just doesn't clear anything.... */ +static inline void tlbflush_filter(cpumask_t *mask, uint32_t page_timestamp) {} + +#define tlbflush_current_time() (0) + +static inline void page_set_tlbflush_timestamp(struct page_info *page) +{ + BUG_ON("unimplemented"); +} + +/* Flush specified CPUs' TLBs */ +void arch_flush_tlb_mask(const cpumask_t *mask); + +#endif /* __ASM_RISCV_FLUSHTLB_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 468A8C48298 for ; Mon, 5 Feb 2024 15:33:12 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676207.1052269 (Exim 4.92) (envelope-from ) id 1rX0xv-0001yC-7m; Mon, 05 Feb 2024 15:32:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676207.1052269; Mon, 05 Feb 2024 15:32:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xu-0001wZ-TE; Mon, 05 Feb 2024 15:32:58 +0000 Received: by outflank-mailman (input) for mailman id 676207; Mon, 05 Feb 2024 15:32:56 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xr-0007I6-V7 for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:55 +0000 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [2a00:1450:4864:20::129]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d440b2ba-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:32:53 +0100 (CET) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-51147d0abd1so1854784e87.1 for ; Mon, 05 Feb 2024 07:32:53 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/smp.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 xen/arch/riscv/include/asm/smp.h diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/smp.h new file mode 100644 index 0000000000..b1ea91b1eb --- /dev/null +++ b/xen/arch/riscv/include/asm/smp.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_SMP_H +#define __ASM_RISCV_SMP_H + +#include +#include + +DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); +DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); + +/* + * Do we, for platform reasons, need to actually keep CPUs online when we + * would otherwise prefer them to be off? + */ +#define park_offline_cpus false + +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65FC9C48297 for ; Mon, 5 Feb 2024 15:33:12 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676206.1052262 (Exim 4.92) (envelope-from ) id 1rX0xu-0001rG-Fo; Mon, 05 Feb 2024 15:32:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676206.1052262; Mon, 05 Feb 2024 15:32:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xu-0001pe-9z; Mon, 05 Feb 2024 15:32:58 +0000 Received: by outflank-mailman (input) for mailman id 676206; Mon, 05 Feb 2024 15:32:55 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xr-0007Hv-Hn for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:55 +0000 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [2a00:1450:4864:20::12f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d4d97775-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:32:54 +0100 (CET) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-511413e52d4so2567629e87.1 for ; Mon, 05 Feb 2024 07:32:54 -0800 (PST) Received: from fedora.. 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Addionally, were updated: * add emulation of {cmp}xchg for 1/2 byte types * replace tabs with spaces * replace __* varialbed with *__ * introduce generic version of xchg_* and cmpxchg_*. Signed-off-by: Oleksii Kurochko --- Changes in V4: - Code style fixes. - enforce in __xchg_*() has the same type for new and *ptr, also "\n" was removed at the end of asm instruction. - dependency from https://lore.kernel.org/xen-devel/cover.1706259490.git.federico.serafini@bugseng.com/ - switch from ASSERT_UNREACHABLE to STATIC_ASSERT_UNREACHABLE(). - drop xchg32(ptr, x) and xchg64(ptr, x) as they aren't used. - drop cmpxcg{32,64}_{local} as they aren't used. - introduce generic version of xchg_* and cmpxchg_*. - update the commit message. --- Changes in V3: - update the commit message - add emulation of {cmp}xchg_... for 1 and 2 bytes types --- Changes in V2: - update the comment at the top of the header. - change xen/lib.h to xen/bug.h. - sort inclusion of headers properly. --- xen/arch/riscv/include/asm/cmpxchg.h | 237 +++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) create mode 100644 xen/arch/riscv/include/asm/cmpxchg.h diff --git a/xen/arch/riscv/include/asm/cmpxchg.h b/xen/arch/riscv/include/asm/cmpxchg.h new file mode 100644 index 0000000000..b751a50cbf --- /dev/null +++ b/xen/arch/riscv/include/asm/cmpxchg.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) 2014 Regents of the University of California */ + +#ifndef _ASM_RISCV_CMPXCHG_H +#define _ASM_RISCV_CMPXCHG_H + +#include +#include + +#include +#include +#include + +#define ALIGN_DOWN(addr, size) ((addr) & (~((size) - 1))) + +#define __amoswap_generic(ptr, new, ret, sfx, release_barrier, acquire_barrier) \ +({ \ + asm volatile( \ + release_barrier \ + " amoswap" sfx " %0, %2, %1\n" \ + acquire_barrier \ + : "=r" (ret), "+A" (*ptr) \ + : "r" (new) \ + : "memory" ); \ +}) + +#define emulate_xchg_1_2(ptr, new, ret, release_barrier, acquire_barrier) \ +({ \ + uint32_t *ptr_32b_aligned = (uint32_t *)ALIGN_DOWN((unsigned long)ptr, 4); \ + uint8_t mask_l = ((unsigned long)(ptr) & (0x8 - sizeof(*ptr))) * BITS_PER_BYTE; \ + uint8_t mask_size = sizeof(*ptr) * BITS_PER_BYTE; \ + uint8_t mask_h = mask_l + mask_size - 1; \ + unsigned long mask = GENMASK(mask_h, mask_l); \ + unsigned long new_ = (unsigned long)(new) << mask_l; \ + unsigned long ret_; \ + unsigned long rc; \ + \ + asm volatile( \ + release_barrier \ + "0: lr.d %0, %2\n" \ + " and %1, %0, %z4\n" \ + " or %1, %1, %z3\n" \ + " sc.d %1, %1, %2\n" \ + " bnez %1, 0b\n" \ + acquire_barrier \ + : "=&r" (ret_), "=&r" (rc), "+A" (*ptr_32b_aligned) \ + : "rJ" (new_), "rJ" (~mask) \ + : "memory"); \ + \ + ret = (__typeof__(*(ptr)))((ret_ & mask) >> mask_l); \ +}) + +#define __xchg_generic(ptr, new, size, sfx, release_barrier, acquire_barrier) \ +({ \ + __typeof__(ptr) ptr__ = (ptr); \ + __typeof__(*(ptr)) new__ = (new); \ + __typeof__(*(ptr)) ret__; \ + switch (size) \ + { \ + case 1: \ + case 2: \ + emulate_xchg_1_2(ptr__, new__, ret__, release_barrier, acquire_barrier); \ + break; \ + case 4: \ + __amoswap_generic(ptr__, new__, ret__,\ + ".w" sfx, release_barrier, acquire_barrier); \ + break; \ + case 8: \ + __amoswap_generic(ptr__, new__, ret__,\ + ".d" sfx, release_barrier, acquire_barrier); \ + break; \ + default: \ + STATIC_ASSERT_UNREACHABLE(); \ + } \ + ret__; \ +}) + +#define xchg_relaxed(ptr, x) \ +({ \ + __typeof__(*(ptr)) x_ = (x); \ + (__typeof__(*(ptr)))__xchg_generic(ptr, x_, sizeof(*(ptr)), "", "", ""); \ +}) + +#define xchg_acquire(ptr, x) \ +({ \ + __typeof__(*(ptr)) x_ = (x); \ + (__typeof__(*(ptr)))__xchg_generic(ptr, x_, sizeof(*(ptr)), \ + "", "", RISCV_ACQUIRE_BARRIER); \ +}) + +#define xchg_release(ptr, x) \ +({ \ + __typeof__(*(ptr)) x_ = (x); \ + (__typeof__(*(ptr)))__xchg_generic(ptr, x_, sizeof(*(ptr)),\ + "", RISCV_RELEASE_BARRIER, ""); \ +}) + +#define xchg(ptr,x) \ +({ \ + __typeof__(*(ptr)) ret__; \ + ret__ = (__typeof__(*(ptr))) \ + __xchg_generic(ptr, (unsigned long)(x), sizeof(*(ptr)), \ + ".aqrl", "", ""); \ + ret__; \ +}) + +#define __generic_cmpxchg(ptr, old, new, ret, lr_sfx, sc_sfx, release_barrier, acquire_barrier) \ + ({ \ + register unsigned int rc; \ + asm volatile( \ + release_barrier \ + "0: lr" lr_sfx " %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc" sc_sfx " %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + acquire_barrier \ + "1:\n" \ + : "=&r" (ret), "=&r" (rc), "+A" (*ptr) \ + : "rJ" (old), "rJ" (new) \ + : "memory"); \ + }) + +#define emulate_cmpxchg_1_2(ptr, old, new, ret, sc_sfx, release_barrier, acquire_barrier) \ +({ \ + uint32_t *ptr_32b_aligned = (uint32_t *)ALIGN_DOWN((unsigned long)ptr, 4); \ + uint8_t mask_l = ((unsigned long)(ptr) & (0x8 - sizeof(*ptr))) * BITS_PER_BYTE; \ + uint8_t mask_size = sizeof(*ptr) * BITS_PER_BYTE; \ + uint8_t mask_h = mask_l + mask_size - 1; \ + unsigned long mask = GENMASK(mask_h, mask_l); \ + unsigned long old_ = (unsigned long)(old) << mask_l; \ + unsigned long new_ = (unsigned long)(new) << mask_l; \ + unsigned long ret_; \ + unsigned long rc; \ + \ + __asm__ __volatile__ ( \ + release_barrier \ + "0: lr.d %0, %2\n" \ + " and %1, %0, %z5\n" \ + " bne %1, %z3, 1f\n" \ + " and %1, %0, %z6\n" \ + " or %1, %1, %z4\n" \ + " sc.d" sc_sfx " %1, %1, %2\n" \ + " bnez %1, 0b\n" \ + acquire_barrier \ + "1:\n" \ + : "=&r" (ret_), "=&r" (rc), "+A" (*ptr_32b_aligned) \ + : "rJ" (old_), "rJ" (new_), \ + "rJ" (mask), "rJ" (~mask) \ + : "memory"); \ + \ + ret = (__typeof__(*(ptr)))((ret_ & mask) >> mask_l); \ +}) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ +#define __cmpxchg_generic(ptr, old, new, size, sc_sfx, release_barrier, acquire_barrier) \ +({ \ + __typeof__(ptr) ptr__ = (ptr); \ + __typeof__(*(ptr)) old__ = (__typeof__(*(ptr)))(old); \ + __typeof__(*(ptr)) new__ = (__typeof__(*(ptr)))(new); \ + __typeof__(*(ptr)) ret__; \ + switch (size) \ + { \ + case 1: \ + case 2: \ + emulate_cmpxchg_1_2(ptr, old, new, ret__,\ + sc_sfx, release_barrier, acquire_barrier); \ + break; \ + case 4: \ + __generic_cmpxchg(ptr__, old__, new__, ret__, \ + ".w", ".w"sc_sfx, release_barrier, acquire_barrier); \ + break; \ + case 8: \ + __generic_cmpxchg(ptr__, old__, new__, ret__, \ + ".d", ".d"sc_sfx, release_barrier, acquire_barrier); \ + break; \ + default: \ + STATIC_ASSERT_UNREACHABLE(); \ + } \ + ret__; \ +}) + +#define cmpxchg_relaxed(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) o_ = (o); \ + __typeof__(*(ptr)) n_ = (n); \ + (__typeof__(*(ptr)))__cmpxchg_generic(ptr, \ + o_, n_, sizeof(*(ptr)), "", "", ""); \ +}) + +#define cmpxchg_acquire(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) o_ = (o); \ + __typeof__(*(ptr)) n_ = (n); \ + (__typeof__(*(ptr)))__cmpxchg_generic(ptr, o_, n_, sizeof(*(ptr)), \ + "", "", RISCV_ACQUIRE_BARRIER); \ +}) + +#define cmpxchg_release(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) o_ = (o); \ + __typeof__(*(ptr)) n_ = (n); \ + (__typeof__(*(ptr)))__cmpxchg_release(ptr, o_, n_, sizeof(*(ptr)), \ + "", RISCV_RELEASE_BARRIER, ""); \ +}) + +#define cmpxchg(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) ret__; \ + ret__ = (__typeof__(*(ptr))) \ + __cmpxchg_generic(ptr, (unsigned long)(o), (unsigned long)(n), \ + sizeof(*(ptr)), ".rl", "", " fence rw, rw\n"); \ + ret__; \ +}) + +#define __cmpxchg(ptr, o, n, s) \ +({ \ + __typeof__(*(ptr)) ret__; \ + ret__ = (__typeof__(*(ptr))) \ + __cmpxchg_generic(ptr, (unsigned long)(o), (unsigned long)(n), \ + s, ".rl", "", " fence rw, rw\n"); \ + ret__; \ +}) + +#endif /* _ASM_RISCV_CMPXCHG_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DCB9C4828D for ; Mon, 5 Feb 2024 15:33:11 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676208.1052275 (Exim 4.92) (envelope-from ) id 1rX0xw-00028M-4F; Mon, 05 Feb 2024 15:33:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676208.1052275; Mon, 05 Feb 2024 15:32:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xv-00025T-GQ; Mon, 05 Feb 2024 15:32:59 +0000 Received: by outflank-mailman (input) for mailman id 676208; Mon, 05 Feb 2024 15:32:56 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xs-0007Hv-PD for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:32:56 +0000 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [2a00:1450:4864:20::12a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d5a2f590-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:32:56 +0100 (CET) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-5114cd44fdbso2336153e87.2 for ; Mon, 05 Feb 2024 07:32:56 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id s1-20020a056512314100b005114d401157sm474445lfi.2.2024.02.05.07.32.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 07:32:54 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d5a2f590-c43b-11ee-8a46-1f161083a0e0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707147175; x=1707751975; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B4eMIfLBmdHylf/GKrqfYgIxqeR1GAXR1e29mkuHIvw=; b=cQ+NA4PHsJf5bqkwI78v1ycIS5JBE7gHtCZpEErSuB7pKrl1e7xklco5xsnkNvoiQX HZP0NDi1Q2PVT8kBEBlzZSmlDVrXPkiWE1hwmkvpUmaj5ylcbvV9RGQ9BcuK979goBNv p5PVBY4XOSU8fgnjx0uFQnBGdWpsoFrRfmuBuyYeuuPoAwwsb6aJZ58iGm/TC6z8c3OY 6zOI85JA7AzVBERHQyEPniZpGiFCtEOdw2Cnzco4Tl+T56iFK1X616hkVhyKCWN9p8d/ 6tkyV0Jjlu6PNXKz5UXqkQINr8KGoSv6sblb8Gkjjqu6lQ7GwYZcvjf4N9T3uthzDFPu hutg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707147175; x=1707751975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B4eMIfLBmdHylf/GKrqfYgIxqeR1GAXR1e29mkuHIvw=; b=c4uOBxiGPI7RWLIfqlU2l8AnZi8d5HCf9O6da4y5Mo+2wS9bp3QkSp7XGyuBZAsRMy yYV8lOdWJnJNxuqGTHswtwkbpiQ3qKrLsqfB1wmAmcs5eeYo/lzUJ/+oZX9iV62sceL2 FZceXeUv9rg0ITJj7LaAoBB3CqSz4QgAKPoffHSkb9RZAxcjtNEkOAlU8iopoK4vOjV0 RslzG+8OiPUM9FxJY+aT7qeJ9GVvze13B5y5t5L1DMjyErtXYWRzxKqosBERYNUhZMD/ DwLPD9ZGwCktqGVPAJYujqwL/c4BdelPakzzXVjQh7jopN7AisswSA2m8kBUDvzWHeaX NjQA== X-Gm-Message-State: AOJu0Yx+mvGIqryRZVuwSotww7l/KA5hK3AAK+J3zKJsjjXlDNwkPJFL /CLTZGvwSH1Gb8XtOKVVvkqYgQkxEGTTFYxeE7dpF+WljBUvc/HGcyMD1Hda X-Google-Smtp-Source: AGHT+IHKPIhVNBwsZykURNlJGS0BKoSDbw+LWo4E8hC3aDGWQ/scYCbvIN6O3HIhuXb0gQjbpOIhgw== X-Received: by 2002:ac2:54ac:0:b0:511:4db9:d6c7 with SMTP id w12-20020ac254ac000000b005114db9d6c7mr2300376lfk.67.1707147175099; Mon, 05 Feb 2024 07:32:55 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCUGBoM+qWiIPUT4iMVMfMFxU84N5INAS2iE0GVSc9JZRRztDCVbMucN6Dc8Zv1lBz5vA1x1rWvtHSN9lJLyvudlTkGQtTnkSvYX1G+USD+8kqyyfFC8ag4l2moRAJ5YTe2EnwlBZystJA0krJJ1G05rhN7ewmAEBq/yXRZ+pvPuI813ILZzGrym7EBeuhYBdAgp5kvZoVIy4lF9LXLF3xITlLkrBmVfvrXg6viw5SvN5dUINKrY1svWO8fROCKg0IMNUNbXk/rk4xDsdgCE/jrASYJ1BwXw865RvG6cvMyOZoaAg39VjOXKmKR1pr6A+vLdukP7 From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v4 13/30] xen/riscv: introduce io.h Date: Mon, 5 Feb 2024 16:32:20 +0100 Message-ID: <64afc021f680e55d486f8429c02513bc9bf4b9ea.1707146506.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 The header taken form Linux 6.4.0-rc1 and is based on arch/riscv/include/asm/mmio.h. Addionally, to the header was added definions of ioremap_*(). Signed-off-by: Oleksii Kurochko --- Changes in V4: - delete inner parentheses in macros. - s/u/uint. --- Changes in V3: - re-sync with linux kernel - update the commit message --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/io.h | 142 ++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 xen/arch/riscv/include/asm/io.h diff --git a/xen/arch/riscv/include/asm/io.h b/xen/arch/riscv/include/asm/io.h new file mode 100644 index 0000000000..1e61a40522 --- /dev/null +++ b/xen/arch/riscv/include/asm/io.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h + * which was based on arch/arm/include/io.h + * + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2014 Regents of the University of California + */ + + +#ifndef _ASM_RISCV_IO_H +#define _ASM_RISCV_IO_H + +#include + +/* + * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't + * change the properties of memory regions. This should be fixed by the + * upcoming platform spec. + */ +#define ioremap_nocache(addr, size) ioremap(addr, size) +#define ioremap_wc(addr, size) ioremap(addr, size) +#define ioremap_wt(addr, size) ioremap(addr, size) + +/* Generic IO read/write. These perform native-endian accesses. */ +#define __raw_writeb __raw_writeb +static inline void __raw_writeb(uint8_t val, volatile void __iomem *addr) +{ + asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writew __raw_writew +static inline void __raw_writew(uint16_t val, volatile void __iomem *addr) +{ + asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writel __raw_writel +static inline void __raw_writel(uint32_t val, volatile void __iomem *addr) +{ + asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#ifdef CONFIG_64BIT +#define __raw_writeq __raw_writeq +static inline void __raw_writeq(u64 val, volatile void __iomem *addr) +{ + asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); +} +#endif + +#define __raw_readb __raw_readb +static inline uint8_t __raw_readb(const volatile void __iomem *addr) +{ + uint8_t val; + + asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#define __raw_readw __raw_readw +static inline uint16_t __raw_readw(const volatile void __iomem *addr) +{ + uint16_t val; + + asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#define __raw_readl __raw_readl +static inline uint32_t __raw_readl(const volatile void __iomem *addr) +{ + uint32_t val; + + asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#ifdef CONFIG_64BIT +#define __raw_readq __raw_readq +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + u64 val; + + asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} +#endif + +/* + * Unordered I/O memory access primitives. These are even more relaxed than + * the relaxed versions, as they don't even order accesses between successive + * operations to the I/O regions. + */ +#define readb_cpu(c) ({ uint8_t __r = __raw_readb(c); __r; }) +#define readw_cpu(c) ({ uint16_t __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) +#define readl_cpu(c) ({ uint32_t __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) + +#define writeb_cpu(v,c) ((void)__raw_writeb(v,c)) +#define writew_cpu(v,c) ((void)__raw_writew((__force uint16_t)cpu_to_le16(v),c)) +#define writel_cpu(v,c) ((void)__raw_writel((__force uint32_t)cpu_to_le32(v),c)) + +#ifdef CONFIG_64BIT +#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) +#define writeq_cpu(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),c)) +#endif + +/* + * I/O memory access primitives. Reads are ordered relative to any + * following Normal memory access. Writes are ordered relative to any prior + * Normal memory access. The memory barriers here are necessary as RISC-V + * doesn't define any ordering between the memory space and the I/O space. + */ +#define __io_br() do {} while (0) +#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory"); +#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); +#define __io_aw() do { } while (0) + +#define readb(c) ({ uint8_t __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) +#define readw(c) ({ uint16_t __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) +#define readl(c) ({ uint32_t __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) + +#define writeb(v,c) ({ __io_bw(); writeb_cpu(v,c); __io_aw(); }) +#define writew(v,c) ({ __io_bw(); writew_cpu(v,c); __io_aw(); }) +#define writel(v,c) ({ __io_bw(); writel_cpu(v,c); __io_aw(); }) + +#ifdef CONFIG_64BIT +#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) +#define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); }) +#endif + +#endif /* _ASM_RISCV_IO_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9832AC4829A for ; Mon, 5 Feb 2024 15:33:26 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676214.1052323 (Exim 4.92) (envelope-from ) id 1rX0y5-00047i-7P; Mon, 05 Feb 2024 15:33:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676214.1052323; Mon, 05 Feb 2024 15:33:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y4-00040L-6l; Mon, 05 Feb 2024 15:33:08 +0000 Received: by outflank-mailman (input) for mailman id 676214; Mon, 05 Feb 2024 15:33:04 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y0-0007Hv-3e for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:04 +0000 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [2a00:1450:4864:20::12c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d99e9ed1-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:33:02 +0100 (CET) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-511570b2f49so135907e87.1 for ; Mon, 05 Feb 2024 07:33:02 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id s1-20020a056512314100b005114d401157sm474445lfi.2.2024.02.05.07.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 07:32:55 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d99e9ed1-c43b-11ee-8a46-1f161083a0e0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707147182; x=1707751982; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2DAJ7IaJfHQvUHlz0u6Dc8IIe22blASYjWQPSCDm2uk=; b=KbmjpN73Af4yHM7urjg9RVCIeenEEE4rlz0iVgAMIbdMvcpwpJSukT/KHByIsaKQYW lf2qCAyyw0K8lnozw7H4bQmwU/3fPpO5JBGW623OWNvHe4j3RCehMblwi+q7LlZE6Jdm noAxlbTSAASpoCtTagJQZT7nrDz/8OVF4eqD3B4UHYruplJgB1EepdgKlLOIoi0xCMsj b1I689aP9hs9XWgZD+ZaRyQ9dTrR0yJ3hYpb5CXosJlE5F32cHWg4YNNs4MtaNy1LNGx j6uadJ9lo0SiBjthH1+qxFECi5Vj9nDJjw+ERWInoESDoXStZcK5Hmhmrcpl2c/8UR18 T4Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707147182; x=1707751982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2DAJ7IaJfHQvUHlz0u6Dc8IIe22blASYjWQPSCDm2uk=; b=kjW4zKzQIXey7VF6B0cwUkcn/X3NoH0eujJJf+MY8M82kWl7NmjItavIBdHBoPg++K IY9Zx4fUo7uugRYAKXUYURbjA3kkmj2CYb2MPdGifM6Hxc91Za2KMO/DZ16001Jil5TQ SwoVsRNhBkfi0HUW35mmHSqgTtj9bvDvpWoVEw568vp3E1zACvuZBYnze9ml8C/eiklX CwviOTDKpugXRNZTXsstBw4rCCXQPJy0F0AulbiJ42qwgo49xmh3iuUutWDKXXcviCqD 0iyoxuWLy0VFS7NwtDkwsaCxAAwfUo4R8BEeahBGN3VToZgd56BIJiK8fnabHQdv6ymc 0lyQ== X-Gm-Message-State: AOJu0Yzxn3bnKFaOs0YyJk7gm9K6SZV9/87rvd/dYhuyy2Xd0NXDAMFo rn/E4w+ibMfoofdDHBWnle9O5+Cyq9x6jeZONE3iNglqxv5DQSyCR4PmJ7du X-Google-Smtp-Source: AGHT+IFtbI9+CWD1Auxa9moJtSAklOkWsFFpBqwrVQEwf1r4zBMEyVFFRDmDo5gEKvONDfOdYqMwxg== X-Received: by 2002:a05:6512:2812:b0:511:463c:32c1 with SMTP id cf18-20020a056512281200b00511463c32c1mr2648458lfb.19.1707147176431; Mon, 05 Feb 2024 07:32:56 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCXjRqVStwX6pbmwqKFDtpxYXWQ2xqzbjeMcJjPMa8k5/uxF5sgYQ/3Nae4aUgMYqxDzYs87+I+3QjPQZ0dPS3MWDTuJSioRFJodZWLLfVT9fN5+euwV5j+LTMZQLdW1d+/1iBHjyVf9bG/1BxO8VtO1Zi++2TAz33rK0TmqIBhx/9V0EgNftyVnyHoyT+oh+fG+NQEPl6MkcX5dwUZyGod4ucetAsajapedUjFQcJpMMXyArBeKVmO66rp6UFno95+B55wrF/5hcDbAgsil5rrpGdiNOnzGaz4/FTBSh9CzhBXjj8AC3oiN6jk9mEbhNbxnEObsdgvl From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Bobby Eshleman , Alistair Francis , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Oleksii Kurochko Subject: [PATCH v4 14/30] xen/riscv: introduce atomic.h Date: Mon, 5 Feb 2024 16:32:21 +0100 Message-ID: <6554f2479e19ed3eae6de842ac1568c31d236461.1707146506.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 From: Bobby Eshleman Additionally, this patch introduces macros in fence.h, which are utilized in atomic.h. atomic##prefix##_*xchg_*(atomic##prefix##_t *v, c_t n) were updated to use __*xchg_generic(). Signed-off-by: Oleksii Kurochko --- Changes in V4: - do changes related to the updates of [PATCH v3 13/34] xen/riscv: introduce cmpxchg.h - drop casts in read_atomic_size(), write_atomic(), add_sized() - tabs -> spaces - drop #ifdef CONFIG_SMP ... #endif in fence.ha as it is simpler to handle NR_CPUS=1 the same as NR_CPUS>1 with accepting less than ideal performance. --- Changes in V3: - update the commit message - add SPDX for fence.h - code style fixes - Remove /* TODO: ... */ for add_sized macros. It looks correct to me. - re-order the patch - merge to this patch fence.h --- Changes in V2: - Change an author of commit. I got this header from Bobby's old repo. --- xen/arch/riscv/include/asm/atomic.h | 395 ++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/fence.h | 8 + 2 files changed, 403 insertions(+) create mode 100644 xen/arch/riscv/include/asm/atomic.h create mode 100644 xen/arch/riscv/include/asm/fence.h diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/asm/atomic.h new file mode 100644 index 0000000000..267d3c0803 --- /dev/null +++ b/xen/arch/riscv/include/asm/atomic.h @@ -0,0 +1,395 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Taken and modified from Linux. + * + * atomic##prefix##_*xchg_*(atomic##prefix##_t *v, c_t n) were updated to use + * __*xchg_generic() + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2021 Vates SAS + */ + +#ifndef _ASM_RISCV_ATOMIC_H +#define _ASM_RISCV_ATOMIC_H + +#include +#include +#include +#include +#include + +void __bad_atomic_size(void); + +static always_inline void read_atomic_size(const volatile void *p, + void *res, + unsigned int size) +{ + switch ( size ) + { + case 1: *(uint8_t *)res = readb(p); break; + case 2: *(uint16_t *)res = readw(p); break; + case 4: *(uint32_t *)res = readl(p); break; + case 8: *(uint32_t *)res = readq(p); break; + default: __bad_atomic_size(); break; + } +} + +#define read_atomic(p) ({ \ + union { typeof(*p) val; char c[0]; } x_; \ + read_atomic_size(p, x_.c, sizeof(*p)); \ + x_.val; \ +}) + +#define write_atomic(p, x) \ +({ \ + typeof(*p) x__ = (x); \ + switch ( sizeof(*p) ) \ + { \ + case 1: writeb((uint8_t)x__, p); break; \ + case 2: writew((uint16_t)x__, p); break; \ + case 4: writel((uint32_t)x__, p); break; \ + case 8: writeq((uint64_t)x__, p); break; \ + default: __bad_atomic_size(); break; \ + } \ + x__; \ +}) + +#define add_sized(p, x) \ +({ \ + typeof(*(p)) x__ = (x); \ + switch ( sizeof(*(p)) ) \ + { \ + case 1: writeb(read_atomic(p) + x__, p); break; \ + case 2: writew(read_atomic(p) + x__, p); break; \ + case 4: writel(read_atomic(p) + x__, p); break; \ + default: __bad_atomic_size(); break; \ + } \ +}) + +/* + * __unqual_scalar_typeof(x) - Declare an unqualified scalar type, leaving + * non-scalar types unchanged. + * + * Prefer C11 _Generic for better compile-times and simpler code. Note: 'char' + * is not type-compatible with 'signed char', and we define a separate case. + */ +#define __scalar_type_to_expr_cases(type) \ + unsigned type: (unsigned type)0, \ + signed type: (signed type)0 + +#define __unqual_scalar_typeof(x) typeof( \ + _Generic((x), \ + char: (char)0, \ + __scalar_type_to_expr_cases(char), \ + __scalar_type_to_expr_cases(short), \ + __scalar_type_to_expr_cases(int), \ + __scalar_type_to_expr_cases(long), \ + __scalar_type_to_expr_cases(long long), \ + default: (x))) + +#define READ_ONCE(x) (*(const volatile __unqual_scalar_typeof(x) *)&(x)) +#define WRITE_ONCE(x, val) \ + do { \ + *(volatile typeof(x) *)&(x) = (val); \ + } while (0) + +#define __atomic_acquire_fence() \ + __asm__ __volatile__( RISCV_ACQUIRE_BARRIER "" ::: "memory" ) + +#define __atomic_release_fence() \ + __asm__ __volatile__( RISCV_RELEASE_BARRIER "" ::: "memory" ); + +static inline int atomic_read(const atomic_t *v) +{ + return READ_ONCE(v->counter); +} + +static inline int _atomic_read(atomic_t v) +{ + return v.counter; +} + +static inline void atomic_set(atomic_t *v, int i) +{ + WRITE_ONCE(v->counter, i); +} + +static inline void _atomic_set(atomic_t *v, int i) +{ + v->counter = i; +} + +static inline int atomic_sub_and_test(int i, atomic_t *v) +{ + return atomic_sub_return(i, v) == 0; +} + +static inline void atomic_inc(atomic_t *v) +{ + atomic_add(1, v); +} + +static inline int atomic_inc_return(atomic_t *v) +{ + return atomic_add_return(1, v); +} + +static inline void atomic_dec(atomic_t *v) +{ + atomic_sub(1, v); +} + +static inline int atomic_dec_return(atomic_t *v) +{ + return atomic_sub_return(1, v); +} + +static inline int atomic_dec_and_test(atomic_t *v) +{ + return atomic_sub_return(1, v) == 0; +} + +static inline int atomic_add_negative(int i, atomic_t *v) +{ + return atomic_add_return(i, v) < 0; +} + +static inline int atomic_inc_and_test(atomic_t *v) +{ + return atomic_add_return(1, v) == 0; +} + +/* + * First, the atomic ops that have no ordering constraints and therefor don't + * have the AQ or RL bits set. These don't return anything, so there's only + * one version to worry about. + */ +#define ATOMIC_OP(op, asm_op, I, asm_type, c_type, prefix) \ +static inline \ +void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " zero, %1, %0" \ + : "+A" (v->counter) \ + : "r" (I) \ + : "memory" ); \ +} \ + +#define ATOMIC_OPS(op, asm_op, I) \ + ATOMIC_OP (op, asm_op, I, w, int, ) + +ATOMIC_OPS(add, add, i) +ATOMIC_OPS(sub, add, -i) +ATOMIC_OPS(and, and, i) +ATOMIC_OPS( or, or, i) +ATOMIC_OPS(xor, xor, i) + +#undef ATOMIC_OP +#undef ATOMIC_OPS + +/* + * Atomic ops that have ordered, relaxed, acquire, and release variants. + * There's two flavors of these: the arithmatic ops have both fetch and return + * versions, while the logical ops only have fetch versions. + */ +#define ATOMIC_FETCH_OP(op, asm_op, I, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_fetch_##op##_relaxed(c_type i, \ + atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " %1, %2, %0" \ + : "+A" (v->counter), "=r" (ret) \ + : "r" (I) \ + : "memory" ); \ + return ret; \ +} \ +static inline \ +c_type atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \ + : "+A" (v->counter), "=r" (ret) \ + : "r" (I) \ + : "memory" ); \ + return ret; \ +} + +#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_##op##_return_relaxed(c_type i, \ + atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op##_relaxed(i, v) c_op I; \ +} \ +static inline \ +c_type atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op(i, v) c_op I; \ +} + +#define ATOMIC_OPS(op, asm_op, c_op, I) \ + ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, ) + +ATOMIC_OPS(add, add, +, i) +ATOMIC_OPS(sub, add, +, -i) + +#define atomic_add_return_relaxed atomic_add_return_relaxed +#define atomic_sub_return_relaxed atomic_sub_return_relaxed +#define atomic_add_return atomic_add_return +#define atomic_sub_return atomic_sub_return + +#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed +#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed +#define atomic_fetch_add atomic_fetch_add +#define atomic_fetch_sub atomic_fetch_sub + +#undef ATOMIC_OPS + +#define ATOMIC_OPS(op, asm_op, I) \ + ATOMIC_FETCH_OP(op, asm_op, I, w, int, ) + +ATOMIC_OPS(and, and, i) +ATOMIC_OPS( or, or, i) +ATOMIC_OPS(xor, xor, i) + +#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed +#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed +#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed +#define atomic_fetch_and atomic_fetch_and +#define atomic_fetch_or atomic_fetch_or +#define atomic_fetch_xor atomic_fetch_xor + +#undef ATOMIC_OPS + +#undef ATOMIC_FETCH_OP +#undef ATOMIC_OP_RETURN + +/* This is required to provide a full barrier on success. */ +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0: lr.w %[p], %[c]\n" + " beq %[p], %[u], 1f\n" + " add %[rc], %[p], %[a]\n" + " sc.w.rl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + " fence rw, rw\n" + "1:\n" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [a]"r" (a), [u]"r" (u) + : "memory"); + return prev; +} +#define atomic_fetch_add_unless atomic_fetch_add_unless + +/* + * atomic_{cmp,}xchg is required to have exactly the same ordering semantics as + * {cmp,}xchg and the operations that return, so they need a full barrier. + */ +#define ATOMIC_OP(c_t, prefix, size) \ +static inline \ +c_t atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_generic(&(v->counter), n, size, "", "", ""); \ +} \ +static inline \ +c_t atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_generic(&(v->counter), n, size, \ + "", "", RISCV_ACQUIRE_BARRIER); \ +} \ +static inline \ +c_t atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_generic(&(v->counter), n, size, \ + "", RISCV_RELEASE_BARRIER, ""); \ +} \ +static inline \ +c_t atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_generic(&(v->counter), n, size, \ + ".aqrl", "", ""); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_relaxed(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_generic(&(v->counter), o, n, size, \ + "", "", ""); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_generic(&(v->counter), o, n, size, \ + "", "", RISCV_ACQUIRE_BARRIER); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_generic(&(v->counter), o, n, size, \ + "", RISCV_RELEASE_BARRIER, ""); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ +{ \ + return __cmpxchg_generic(&(v->counter), o, n, size, \ + ".rl", "", " fence rw, rw\n"); \ +} + +#define ATOMIC_OPS() \ + ATOMIC_OP(int, , 4) + +ATOMIC_OPS() + +#define atomic_xchg_relaxed atomic_xchg_relaxed +#define atomic_xchg_acquire atomic_xchg_acquire +#define atomic_xchg_release atomic_xchg_release +#define atomic_xchg atomic_xchg +#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed +#define atomic_cmpxchg_acquire atomic_cmpxchg_acquire +#define atomic_cmpxchg_release atomic_cmpxchg_release +#define atomic_cmpxchg atomic_cmpxchg + +#undef ATOMIC_OPS +#undef ATOMIC_OP + +static inline int atomic_sub_if_positive(atomic_t *v, int offset) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0: lr.w %[p], %[c]\n" + " sub %[rc], %[p], %[o]\n" + " bltz %[rc], 1f\n" + " sc.w.rl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + " fence rw, rw\n" + "1:\n" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [o]"r" (offset) + : "memory" ); + return prev - offset; +} + +#define atomic_dec_if_positive(v) atomic_sub_if_positive(v, 1) + +#endif /* _ASM_RISCV_ATOMIC_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/riscv/include/asm/fence.h b/xen/arch/riscv/include/asm/fence.h new file mode 100644 index 0000000000..ff3f23dbd7 --- /dev/null +++ b/xen/arch/riscv/include/asm/fence.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _ASM_RISCV_FENCE_H +#define _ASM_RISCV_FENCE_H + +#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" +#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" + +#endif /* _ASM_RISCV_FENCE_H */ From patchwork Mon Feb 5 15:32:22 2024 Content-Type: text/plain; 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RISC-V has only 2 free for use bits in PTE, not 4 as Arm. - update the comment after p2m_ram_rw: s/guest/domain/ as this also applies for dom0. - return INVALID_MFN in gfn_to_mfn() instead of mfn(0). - drop PPC changes. --- Changes in V3: - add SPDX - drop unneeded for now p2m types. - return false in all functions implemented with BUG() inside. - update the commit message --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/p2m.h | 102 +++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 xen/arch/riscv/include/asm/p2m.h diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h new file mode 100644 index 0000000000..8ad020974f --- /dev/null +++ b/xen/arch/riscv/include/asm/p2m.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_P2M_H__ +#define __ASM_RISCV_P2M_H__ + +#include + +#define paddr_bits PADDR_BITS + +/* + * List of possible type for each page in the p2m entry. + * The number of available bit per page in the pte for this purpose is 2 bits. + * So it's possible to only have 4 fields. If we run out of value in the + * future, it's possible to use higher value for pseudo-type and don't store + * them in the p2m entry. + */ +typedef enum { + p2m_invalid = 0, /* Nothing mapped here */ + p2m_ram_rw, /* Normal read/write domain RAM */ +} p2m_type_t; + +#include + +static inline int get_page_and_type(struct page_info *page, + struct domain *domain, + unsigned long type) +{ + BUG_ON("unimplemented"); + return -EINVAL; +} + +/* Look up a GFN and take a reference count on the backing page. */ +typedef unsigned int p2m_query_t; +#define P2M_ALLOC (1u<<0) /* Populate PoD and paged-out entries */ +#define P2M_UNSHARE (1u<<1) /* Break CoW sharing */ + +static inline struct page_info *get_page_from_gfn( + struct domain *d, unsigned long gfn, p2m_type_t *t, p2m_query_t q) +{ + BUG_ON("unimplemented"); + return NULL; +} + +static inline void memory_type_changed(struct domain *d) +{ + BUG_ON("unimplemented"); +} + + +static inline int guest_physmap_mark_populate_on_demand(struct domain *d, unsigned long gfn, + unsigned int order) +{ + return -EOPNOTSUPP; +} + +static inline int guest_physmap_add_entry(struct domain *d, + gfn_t gfn, + mfn_t mfn, + unsigned long page_order, + p2m_type_t t) +{ + BUG_ON("unimplemented"); + return -EINVAL; +} + +/* Untyped version for RAM only, for compatibility */ +static inline int __must_check +guest_physmap_add_page(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order) +{ + return guest_physmap_add_entry(d, gfn, mfn, page_order, p2m_ram_rw); +} + +static inline mfn_t gfn_to_mfn(struct domain *d, gfn_t gfn) +{ + BUG_ON("unimplemented"); + return INVALID_MFN; +} + +static inline bool arch_acquire_resource_check(struct domain *d) +{ + /* + * The reference counting of foreign entries in set_foreign_p2m_entry() + * is supported on RISCV. + */ + return true; +} + +static inline void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +{ + /* Not supported on RISCV. */ +} + +#endif /* __ASM_RISCV_P2M_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2759CC48298 for ; Mon, 5 Feb 2024 15:33:25 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676211.1052303 (Exim 4.92) (envelope-from ) id 1rX0y1-0003Dg-93; Mon, 05 Feb 2024 15:33:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676211.1052303; Mon, 05 Feb 2024 15:33:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y0-0003BP-HJ; Mon, 05 Feb 2024 15:33:04 +0000 Received: by outflank-mailman (input) for mailman id 676211; Mon, 05 Feb 2024 15:33:01 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xx-0007I6-GU for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:01 +0000 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [2a00:1450:4864:20::22a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d7da89d9-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:32:59 +0100 (CET) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2cf4d2175b2so51938751fa.0 for ; Mon, 05 Feb 2024 07:32:59 -0800 (PST) Received: from fedora.. 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Mon, 05 Feb 2024 07:33:00 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCVv0V2Sn1riFTcccMtaw4DrDISuAWzeSjJbFZLS60Bt1zzm5rHHNZZ5719o0GuJ3Zloh8JRFR0HWBsQljxCnJIG4dy4pcTfVNMkTQlozDoJRy+gAQtiuH0Yyu7MVjp1B+qAAk609pFnX4azd5lmdlumMjsLfqM3KFxVu41h95BXd3MpBtNtCWdCiL1Bpv2LylLvLH2rcDmnBclr9a0YkFLuukm6VwYXwke3MkV+2VMm2Q/gTtx+6goiKCCWRmdVMWQ2dnUbDxYKNzFloaLeXv8/PM+fSDzFGJ3wqHLedvq9nwNTljLZyK+OXWtWIvV/2JWgbGzr From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v4 18/30] xen/riscv: introduce time.h Date: Mon, 5 Feb 2024 16:32:25 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V4: - s/BUG()/BUG_ON("unimplemented") --- Changes in V3: - Acked-by: Jan Beulich - add SPDX - Add new line --- Changes in V2: - change xen/lib.h to xen/bug.h - remove inclusion of as it's not needed. --- xen/arch/riscv/include/asm/time.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 xen/arch/riscv/include/asm/time.h diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm/time.h new file mode 100644 index 0000000000..2e359fa046 --- /dev/null +++ b/xen/arch/riscv/include/asm/time.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_TIME_H__ +#define __ASM_RISCV_TIME_H__ + +#include +#include + +struct vcpu; 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Only rebase. --- xen/arch/riscv/include/asm/event.h | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 xen/arch/riscv/include/asm/event.h diff --git a/xen/arch/riscv/include/asm/event.h b/xen/arch/riscv/include/asm/event.h new file mode 100644 index 0000000000..b6a76c0f5d --- /dev/null +++ b/xen/arch/riscv/include/asm/event.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_EVENT_H__ +#define __ASM_RISCV_EVENT_H__ + +#include + +void vcpu_mark_events_pending(struct vcpu *v); + +static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) +{ + BUG_ON("unimplemented"); + return 0; +} + +static inline int local_events_need_delivery(void) +{ + BUG_ON("unimplemented"); + return 0; +} + +static inline void local_event_delivery_enable(void) +{ + BUG_ON("unimplemented"); +} + +/* No arch specific virq definition now. Default to global. */ +static inline bool arch_virq_is_global(unsigned int virq) +{ + return true; +} + +#endif +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC36EC4828D for ; Mon, 5 Feb 2024 15:33:24 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676213.1052317 (Exim 4.92) (envelope-from ) id 1rX0y3-0003oz-LM; Mon, 05 Feb 2024 15:33:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676213.1052317; Mon, 05 Feb 2024 15:33:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y2-0003kK-TB; Mon, 05 Feb 2024 15:33:06 +0000 Received: by outflank-mailman (input) for mailman id 676213; Mon, 05 Feb 2024 15:33:03 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0xz-0007Hv-3M for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:03 +0000 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [2a00:1450:4864:20::132]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d94cedc5-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:33:02 +0100 (CET) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-5114fa38434so1247558e87.0 for ; Mon, 05 Feb 2024 07:33:02 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id s1-20020a056512314100b005114d401157sm474445lfi.2.2024.02.05.07.33.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 07:33:01 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d94cedc5-c43b-11ee-8a46-1f161083a0e0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707147182; x=1707751982; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0gARUjv581cUW1g1ZCe6+dI3h9g3+PYO7UcATFZv3k0=; b=g22vWrY8+fK2ayS8ZcnJ+I8FXx9GbFTAsuqgW7pHhNR3jjusQZSTwuuLhGbLvhqVVk BecYFd4JPXe634r33P02NvFLEA3q/3acujM5FHzEat+NIde1I7L2316k5AjSh121mOFG N5UJUSqppO1uRoZLalb9JsidOMvE6QYNuKMpph9vvAGPZxwfKB+C6MDpNYUAruDdIMoV LVY9TSESl8xZ6eS7Y4QqfjTz/Id3eptsXm722C+k4Usmop8eZsef1mGbzeQAhBfY8Bqe Fb47rl4Rr7abKexipprAGGC73FLK/2Tc8JdworLOtsJ4G7RqxDm7Oe9CEnsz0sggxo16 +dfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707147182; x=1707751982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0gARUjv581cUW1g1ZCe6+dI3h9g3+PYO7UcATFZv3k0=; b=Rg/hTMx9olmzxDx7/d03+muXi2+Av/9deLg1QgWpuIm5R2qe5mL7CRWsjDqiMqZrug eHSrYj5ITcv682oui52/3bw5zbL3JgArIkTveY8j+UHBeWfT1HaqVsHjGO/dpnph/37G yTFW9VReOcJNvJbkU5xxoV0ZWD/nNq/88WR57ors+7eWzddRUSaoGTJd4NaFZ0wFPwEP YRx8TumyLLftUZQTJ+8fI6lEO+xb9uUjCpJw9Bh5GMdAhb+wyRGUOr08AXlawplauKoS /ebdHiMqEqMFENzKjpbtgrqrv5zOICqlO6DikTl7Zbvm2SC2z2LhGKe05FLvzNdkHVRp 3r6w== X-Gm-Message-State: AOJu0YwG1mQHfNQBck9fWspna26LdmlKofruibGejCS2gUOTnBJPgpf3 /yzNqCUyHdWO57JmpaVlFwbZsOT2YWTITVkQrT67kzRaRnAsIT5BIr7RQis2 X-Google-Smtp-Source: AGHT+IFKTLFETIdqzqjZRLukSGR3tjSLZkxLYn00YvDSQ8zxBRdVKq45GMT3uiVnqoV8z0pF1UOhFA== X-Received: by 2002:a05:6512:2c0a:b0:511:4758:c99e with SMTP id dx10-20020a0565122c0a00b005114758c99emr4788620lfb.25.1707147181786; Mon, 05 Feb 2024 07:33:01 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCXbhFD80mHCSO8eudoZxHaF6IND71BLdMe16lXGKwf8DfEF7jmIIt2zP8H0uJwmhBjRP44zwK/ByhIxkMwptkJuvGzkZW5vYiesQZYQKBL0QYa6idXKfQDYeet7YMLIE1WFYtTJ4MhPNQwmOMe4PFEFNOwS1jtXaB8SOW1Df363y/CuJtQntPczNwXwf/nLbLSP3+k77xHP3FZ9YORNTm/9oUbzTre6SwvEaTG0diBZvukPAWSAWdBMTH2e+JJZ6XeyEw== From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu , Alistair Francis , Bob Eshleman , Connor Davis Subject: [PATCH v4 20/30] xen/riscv: introduce monitor.h Date: Mon, 5 Feb 2024 16:32:27 +0100 Message-ID: <846a0c47e1808b01d5650a72d3366c3c0f2764c1.1707146506.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Taking into account conversion in [PATCH v6 0/9] Introduce generic headers (https://lore.kernel.org/xen-devel/cover.1703072575.git.oleksii.kurochko@gmail.com/) this patch can be changed --- Changes in V4: - Nothing changed. Only rebase. --- Changes in V3: - new patch. --- xen/arch/riscv/include/asm/monitor.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 xen/arch/riscv/include/asm/monitor.h diff --git a/xen/arch/riscv/include/asm/monitor.h b/xen/arch/riscv/include/asm/monitor.h new file mode 100644 index 0000000000..f4fe2c0690 --- /dev/null +++ b/xen/arch/riscv/include/asm/monitor.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_MONITOR_H__ +#define __ASM_RISCV_MONITOR_H__ + +#include + +#include + +struct domain; + +static inline uint32_t arch_monitor_get_capabilities(struct domain *d) +{ + BUG_ON("unimplemented"); + return 0; +} + +#endif /* __ASM_RISCV_MONITOR_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Feb 5 15:32:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13C1AC4828D for ; Mon, 5 Feb 2024 15:37:56 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676260.1052380 (Exim 4.92) (envelope-from ) id 1rX12a-0002dQ-Nv; Mon, 05 Feb 2024 15:37:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676260.1052380; Mon, 05 Feb 2024 15:37:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX12a-0002dJ-JZ; Mon, 05 Feb 2024 15:37:48 +0000 Received: by outflank-mailman (input) for mailman id 676260; Mon, 05 Feb 2024 15:37:47 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y1-0007Hv-3r for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:05 +0000 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [2a00:1450:4864:20::12f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d9e34def-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:33:03 +0100 (CET) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-5112bd13a4fso4071568e87.0 for ; Mon, 05 Feb 2024 07:33:03 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id s1-20020a056512314100b005114d401157sm474445lfi.2.2024.02.05.07.33.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 07:33:02 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d9e34def-c43b-11ee-8a46-1f161083a0e0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707147183; x=1707751983; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nSkC4h9RHu0ZPi8yVkfyYrb9TlPun8CaqbFwSR6X+nY=; b=lgAOSssgK0izZvo/eByOYxCZOcyQuLl1LphlcFgDfrw4bTM0CMdT+7oaC8UE0pqGMZ o6DoafnVO+RZsMiDEiq4bWPyGNGENGVrVu+1AIwfmRmlX0Kz3Wb6cym2z2sZdQIxM+8D lZggEUd3deN3Nc68HFWj2E9A0ljMhOu67U0XkogkDk/zmMXOXfeeElMG9YZzufBLHIX+ zqUn4B6M2z1yKPQBr3SHlMuThthRLG8mLjjcf5KlkjBAzWFwnUlHdheGtQKwJKF9di5b +NrHefe3dpHsopNA8xgc86q8axLgXHel3zeXB7TIfSLbDdU75b0SrE4cEd8oQi9pPdei NWGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707147183; x=1707751983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nSkC4h9RHu0ZPi8yVkfyYrb9TlPun8CaqbFwSR6X+nY=; b=OHtEHmKiDBhJQyBoDiTg2aykeOmnjtmO1wJE9ZPaUtVuoYC5O4IiDghheR4itjBq2M 2gvn2rQ2I6GTkpdox2FgeEbMnudhsatWamhk8fb2QsWpiBnAzSU2XBb5j2rU6m8905Tq p7uJTl1N4DdZkAUzivMNgZOH9t10V5QMUiptVvELLDngoKrI82ClCpmCf/ujH/4bO24k OmXeVI7WUgJDvND9QMmNPEnrFMkmVR1iuwmCVCuysovSKhPs3unAIJswNOlhAfWFEfYl +kJ8LJ74zDgWvPbtTc97c+ep5zuJwWSbgYVw9V4542MGfK5HfQuWNMytrwPLdsN99uvq RK7Q== X-Gm-Message-State: AOJu0Ywz/VL81NFVqYzOkItZKlgP1Z8im6UkeaKy2jL5/40NOJBL51Zy zCwIDHSJX2ezPTtGhRIzheaRnAbXeehb+Qs7BS0uvfirUCqm0TZppYE2RrCZ X-Google-Smtp-Source: AGHT+IGTlPwspuKMw53Na5DdBtJmFPAAq5A3ih9VNf0oCvaDXAg4cGvieTC4z72KOBq4nEL9xYpnWw== X-Received: by 2002:a19:4f57:0:b0:511:4646:54f3 with SMTP id a23-20020a194f57000000b00511464654f3mr14586lfk.10.1707147182714; Mon, 05 Feb 2024 07:33:02 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCVGXvLe4XJsrxfdoixZ0NqlGgka//FC5/RH2AS+rnUaVAp3xJu/mcmHp12yRfb30V2wK5zQgc9x03U4B4wHAUQfJrYvTTGmFUrhsHMWJN7LP2wJGa3ZsD9Uc2WJ7tRri/tJXigsrxgosYLy+fSoMDCwQXBuuCSyh4EyDim9bZ4DtIWfxwXzfRQlVW9TSfdfHK07mcmqdIVNtUkTz7GLtliRrzbh7WUkclVrm0plT50H1FanZgtI20Pep8E6Gi/vJvYTjMQbr+e63Eeu9bskPRfnFW2u1FyIke69s7aw/kArt41+sFXcurvgvorUa7hEqy8AFf5+ From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v4 21/30] xen/riscv: add definition of __read_mostly Date: Mon, 5 Feb 2024 16:32:28 +0100 Message-ID: <5aff6b7d13b17e4ce5807f589c0be20f2e9e0bc0.1707146506.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 The definition of __read_mostly should be removed in: https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse.com/ The patch introduces it in arch-specific header to not block enabling of full Xen build for RISC-V. Signed-off-by: Oleksii Kurochko --- - [PATCH] move __read_mostly to xen/cache.h [2] Right now, the patch series doesn't have a direct dependency on [2] and it provides __read_mostly in the patch: [PATCH v3 26/34] xen/riscv: add definition of __read_mostly However, it will be dropped as soon as [2] is merged or at least when the final version of the patch [2] is provided. [2] https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse.com/ --- Changes in V4: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/riscv/include/asm/cache.h b/xen/arch/riscv/include/asm/cache.h index 69573eb051..94bd94db53 100644 --- a/xen/arch/riscv/include/asm/cache.h +++ b/xen/arch/riscv/include/asm/cache.h @@ -3,4 +3,6 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#define __read_mostly __section(".data.read_mostly") + #endif /* _ASM_RISCV_CACHE_H */ From patchwork Mon Feb 5 15:32:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15464C4828D for ; Mon, 5 Feb 2024 15:42:47 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676312.1052429 (Exim 4.92) (envelope-from ) id 1rX17H-0007ai-Bl; Mon, 05 Feb 2024 15:42:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676312.1052429; Mon, 05 Feb 2024 15:42:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX17H-0007ab-96; Mon, 05 Feb 2024 15:42:39 +0000 Received: by outflank-mailman (input) for mailman id 676312; Mon, 05 Feb 2024 15:42:37 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y2-0007Hv-45 for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:06 +0000 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [2a00:1450:4864:20::132]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id da8776ec-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:33:04 +0100 (CET) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-5111e5e4e2bso7067914e87.3 for ; Mon, 05 Feb 2024 07:33:04 -0800 (PST) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V4: - move "#define VPN_BITS (9)" inside CONFIG_RISCV_64 as for SV32 it should be defined differently. - drop SLOTN_ENTRY_SIZE and introduce DIRECTMAP_SIZE. It is not needed for now, but will be needed in the future. - update memory layout table and some related macros. --- Changes in V3: - drop OFFSET_BITS, and use PAGE_SHIFT instead. - code style fixes. - add comment how macros are useful. - move all memory related layout definitions close to comment with memory layout description. - make memory layout description generic for any MMU mode. --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/config.h | 105 ++++++++++++++++++++-------- 1 file changed, 77 insertions(+), 28 deletions(-) diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index 56387ac159..479da15782 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -6,6 +6,16 @@ #include #include +#include + +#ifdef CONFIG_RISCV_64 +#define CONFIG_PAGING_LEVELS 3 +#define RV_STAGE1_MODE SATP_MODE_SV39 +#else +#define CONFIG_PAGING_LEVELS 2 +#define RV_STAGE1_MODE SATP_MODE_SV32 +#endif + /* * RISC-V64 Layout: * @@ -23,25 +33,78 @@ * It means that: * top VA bits are simply ignored for the purpose of translating to PA. * + * Amount of slots for Frametable were calculated base on + * sizeof(struct page_info) = 48. If the 'struct page_info' is changed, + * the table below must be updated. + * * ============================================================================ - * Start addr | End addr | Size | Slot |area description - * ============================================================================ - * FFFFFFFFC0800000 | FFFFFFFFFFFFFFFF |1016 MB | L2 511 | Unused - * FFFFFFFFC0600000 | FFFFFFFFC0800000 | 2 MB | L2 511 | Fixmap - * FFFFFFFFC0200000 | FFFFFFFFC0600000 | 4 MB | L2 511 | FDT - * FFFFFFFFC0000000 | FFFFFFFFC0200000 | 2 MB | L2 511 | Xen - * ... | 1 GB | L2 510 | Unused - * 0000003200000000 | 0000007F80000000 | 309 GB | L2 200-509 | Direct map - * ... | 1 GB | L2 199 | Unused - * 0000003100000000 | 00000031C0000000 | 3 GB | L2 196-198 | Frametable - * ... | 1 GB | L2 195 | Unused - * 0000003080000000 | 00000030C0000000 | 1 GB | L2 194 | VMAP - * ... | 194 GB | L2 0 - 193 | Unused + * Start addr | End addr | Slot | area description * ============================================================================ - * + * ..... L2 511 Unused + * 0xffffffffc0600000 0xffffffffc0800000 L2 511 Fixmap + * 0xffffffffc0200000 0xffffffffc0600000 L2 511 FDT + * 0xffffffffc0000000 0xffffffffc0200000 L2 511 Xen + * ..... L2 510 Unused + * 0x3200000000 0x7f40000000 L2 200-509 Direct map + * ..... L2 199 Unused + * 0x30c0000000 0x31c0000000 L2 195-198 Frametable + * ..... L2 194 Unused + * 0x3040000000 0x3080000000 L2 193 VMAP + * ..... L2 0-192 Unused +#elif RV_STAGE1_MODE == SATP_MODE_SV48 + * Memory layout is the same as for SV39 in terms of slots, so only start and + * end addresses should be shifted by 9 #endif */ +#define HYP_PT_ROOT_LEVEL (CONFIG_PAGING_LEVELS - 1) + +#ifdef CONFIG_RISCV_64 + +#define VPN_BITS (9) + +#define SLOTN_ENTRY_BITS (HYP_PT_ROOT_LEVEL * VPN_BITS + PAGE_SHIFT) +#define SLOTN(slot) (_AT(vaddr_t, slot) << SLOTN_ENTRY_BITS) + +#if RV_STAGE1_MODE == SATP_MODE_SV39 +#define XEN_VIRT_START 0xFFFFFFFFC0000000 +#elif RV_STAGE1_MODE == SATP_MODE_SV48 +#define XEN_VIRT_START 0xFFFFFF8000000000 +#else +#error "unsupported RV_STAGE1_MODE" +#endif + +#define DIRECTMAP_SLOT_END 509 +#define DIRECTMAP_SLOT_START 200 +#define DIRECTMAP_VIRT_START SLOTN(DIRECTMAP_SLOT_START) +#define DIRECTMAP_SIZE (SLOTN(DIRECTMAP_SLOT_END) - SLOTN(DIRECTMAP_SLOT_START)) + +#define FRAMETABLE_SCALE_FACTOR (PAGE_SIZE/sizeof(struct page_info)) +#define FRAMETABLE_SIZE_IN_SLOTS (((DIRECTMAP_SIZE / SLOTN(1)) / FRAMETABLE_SCALE_FACTOR) + 1) + +/* + * We have to skip Unused slot between DIRECTMAP and FRAMETABLE (look at mem. + * layout), so -1 is needed + */ +#define FRAMETABLE_SLOT_START (DIRECTMAP_SLOT_START - FRAMETABLE_SIZE_IN_SLOTS - 1) +#define FRAMETABLE_SIZE (FRAMETABLE_SIZE_IN_SLOTS * SLOTN(1)) +#define FRAMETABLE_VIRT_START SLOTN(FRAMETABLE_SLOT_START) +#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) +#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE - 1) + +/* + * We have to skip Unused slot between Frametable and VMAP (look at mem. + * layout), so an additional -1 is needed */ +#define VMAP_SLOT_START (FRAMETABLE_SLOT_START - 1 - 1) +#define VMAP_VIRT_START SLOTN(VMAP_SLOT_START) +#define VMAP_VIRT_SIZE GB(1) + +#else +#error "RV32 isn't supported" +#endif + +#define HYPERVISOR_VIRT_START XEN_VIRT_START + #if defined(CONFIG_RISCV_64) # define LONG_BYTEORDER 3 # define ELFSIZE 64 @@ -75,24 +138,10 @@ #define CODE_FILL /* empty */ #endif -#ifdef CONFIG_RISCV_64 -#define XEN_VIRT_START 0xFFFFFFFFC0000000 /* (_AC(-1, UL) + 1 - GB(1)) */ -#else -#error "RV32 isn't supported" -#endif - #define SMP_CACHE_BYTES (1 << 6) #define STACK_SIZE PAGE_SIZE -#ifdef CONFIG_RISCV_64 -#define CONFIG_PAGING_LEVELS 3 -#define RV_STAGE1_MODE SATP_MODE_SV39 -#else -#define CONFIG_PAGING_LEVELS 2 -#define RV_STAGE1_MODE SATP_MODE_SV32 -#endif - #define IDENT_AREA_SIZE 64 #endif /* __RISCV_CONFIG_H__ */ From patchwork Mon Feb 5 15:32:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2F72C48295 for ; Mon, 5 Feb 2024 15:41:20 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676289.1052419 (Exim 4.92) (envelope-from ) id 1rX15s-0006lH-3B; Mon, 05 Feb 2024 15:41:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676289.1052419; Mon, 05 Feb 2024 15:41:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX15r-0006lA-VW; Mon, 05 Feb 2024 15:41:11 +0000 Received: by outflank-mailman (input) for mailman id 676289; Mon, 05 Feb 2024 15:41:10 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y2-0007I6-S0 for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:06 +0000 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [2a00:1450:4864:20::12b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id db09ce0c-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:33:05 +0100 (CET) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-51032058f17so5125718e87.3 for ; Mon, 05 Feb 2024 07:33:05 -0800 (PST) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V4: - BUG() was changed to BUG_ON("unimplemented"); - Change "xen/bug.h" to "xen/lib.h" as BUG_ON is defined in xen/lib.h. - Add Acked-by: Jan Beulich --- Changes in V3: - add SPDX - drop a forward declaration of struct vcpu; - update guest_cpu_user_regs() macros - replace get_processor_id with smp_processor_id - update the commit message - code style fixes --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/current.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/asm/current.h index d84f15dc50..aedb6dc732 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -3,6 +3,21 @@ #ifndef __ASM_CURRENT_H #define __ASM_CURRENT_H +#include +#include +#include + +#ifndef __ASSEMBLY__ + +/* Which VCPU is "current" on this PCPU. */ +DECLARE_PER_CPU(struct vcpu *, curr_vcpu); + +#define current this_cpu(curr_vcpu) +#define set_current(vcpu) do { current = (vcpu); } while (0) +#define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu) + +#define guest_cpu_user_regs() ({ BUG_ON("unimplemented"); NULL; }) + #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ "mv sp, %0\n" \ @@ -10,4 +25,8 @@ unreachable(); \ } while ( false ) +#define get_per_cpu_offset() __per_cpu_offset[smp_processor_id()] + +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_CURRENT_H */ From patchwork Mon Feb 5 15:32:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8C17C4828D for ; Mon, 5 Feb 2024 15:48:19 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676336.1052469 (Exim 4.92) (envelope-from ) id 1rX1Cf-0002T5-Nf; Mon, 05 Feb 2024 15:48:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676336.1052469; Mon, 05 Feb 2024 15:48:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX1Cf-0002Sy-KZ; Mon, 05 Feb 2024 15:48:13 +0000 Received: by outflank-mailman (input) for mailman id 676336; Mon, 05 Feb 2024 15:48:12 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y4-0007I6-SS for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:08 +0000 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [2a00:1450:4864:20::134]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id dbd8ab44-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:33:06 +0100 (CET) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-51124d43943so7188941e87.2 for ; Mon, 05 Feb 2024 07:33:06 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/page.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm/page.h index 95074e29b3..c831e16417 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -6,6 +6,7 @@ #ifndef __ASSEMBLY__ #include +#include #include #include @@ -32,6 +33,10 @@ #define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITABLE) #define PTE_TABLE (PTE_VALID) +#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITABLE) + +#define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW + /* Calculate the offsets into the pagetables for a given VA */ #define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl)) @@ -62,6 +67,20 @@ static inline bool pte_is_valid(pte_t p) return p.pte & PTE_VALID; } +static inline void invalidate_icache(void) +{ + BUG_ON("unimplemented"); +} + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +#define copy_page(dp, sp) memcpy(dp, sp, PAGE_SIZE) + +/* TODO: Flush the dcache for an entire page. */ +static inline void flush_page_to_ram(unsigned long mfn, bool sync_icache) +{ + BUG_ON("unimplemented"); +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PAGE_H */ From patchwork Mon Feb 5 15:32:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82145C48295 for ; Mon, 5 Feb 2024 15:37:56 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676261.1052381 (Exim 4.92) (envelope-from ) id 1rX12a-0002g5-Tk; Mon, 05 Feb 2024 15:37:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676261.1052381; Mon, 05 Feb 2024 15:37:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX12a-0002fR-QF; Mon, 05 Feb 2024 15:37:48 +0000 Received: by outflank-mailman (input) for mailman id 676261; Mon, 05 Feb 2024 15:37:47 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y5-0007I6-SU for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:09 +0000 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [2a00:1450:4864:20::12e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id dc634284-c43b-11ee-98f5-efadbce2ee36; Mon, 05 Feb 2024 16:33:07 +0100 (CET) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-51032e62171so7141623e87.3 for ; Mon, 05 Feb 2024 07:33:07 -0800 (PST) Received: from fedora.. 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In the future, it can be checked if the extension is supported by system __riscv_isa_extension_available() ( https://gitlab.com/xen-project/people/olkur/xen/-/commit/737998e89ed305eb92059300c374dfa53d2143fa ) - update cpu_relax() function to check if __riscv_zihintpause is supported by a toolchain - add conditional _zihintpause to -march if it is supported by a toolchain Changes in V3: - update the commit subject - rename get_processor_id to smp_processor_id - code style fixes - update the cpu_relax instruction: use pause instruction instead of div %0, %0, zero --- Changes in V2: - Nothing changed. Only rebase. --- docs/misc/riscv/booting.txt | 8 ++++++++ xen/arch/riscv/Kconfig | 7 +++++++ xen/arch/riscv/arch.mk | 1 + xen/arch/riscv/include/asm/processor.h | 23 +++++++++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 docs/misc/riscv/booting.txt diff --git a/docs/misc/riscv/booting.txt b/docs/misc/riscv/booting.txt new file mode 100644 index 0000000000..38fad74956 --- /dev/null +++ b/docs/misc/riscv/booting.txt @@ -0,0 +1,8 @@ +System requirements +=================== + +The following extensions are expected to be supported by a system on which +Xen is run: +- Zihintpause: + On a system that doesn't have this extension, cpu_relax() should be + implemented properly. Otherwise, an illegal instruction exception will arise. diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index f382b36f6c..383ce06771 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -45,6 +45,13 @@ config RISCV_ISA_C If unsure, say Y. +config TOOLCHAIN_HAS_ZIHINTPAUSE + bool + default y + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zihintpause) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zihintpause) + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23600 + endmenu source "common/Kconfig" diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8403f96b6f..a4b53adaf7 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -7,6 +7,7 @@ CFLAGS-$(CONFIG_RISCV_64) += -mabi=lp64 riscv-march-$(CONFIG_RISCV_ISA_RV64G) := rv64g riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause # Note that -mcmodel=medany is used so that Xen can be mapped # into the upper half _or_ the lower half of the address space. diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h index 6db681d805..289dc35ea0 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -12,6 +12,9 @@ #ifndef __ASSEMBLY__ +/* TODO: need to be implemeted */ +#define smp_processor_id() 0 + /* On stack VCPU state */ struct cpu_user_regs { @@ -53,6 +56,26 @@ struct cpu_user_regs unsigned long pregs; }; +/* TODO: need to implement */ +#define cpu_to_core(cpu) (0) +#define cpu_to_socket(cpu) (0) + +static inline void cpu_relax(void) +{ +#ifdef __riscv_zihintpause + /* + * Reduce instruction retirement. + * This assumes the PC changes. + */ + __asm__ __volatile__ ("pause"); +#else + /* Encoding of the pause instruction */ + __asm__ __volatile__ (".insn 0x100000F"); +#endif + + barrier(); +} + static inline void wfi(void) { __asm__ __volatile__ ("wfi"); From patchwork Mon Feb 5 15:32:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0726C4828D for ; Mon, 5 Feb 2024 15:39:15 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676274.1052409 (Exim 4.92) (envelope-from ) id 1rX13r-0004Ll-GO; Mon, 05 Feb 2024 15:39:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676274.1052409; Mon, 05 Feb 2024 15:39:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX13r-0004LY-Dj; Mon, 05 Feb 2024 15:39:07 +0000 Received: by outflank-mailman (input) for mailman id 676274; Mon, 05 Feb 2024 15:39:05 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y5-0007Hv-D1 for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:09 +0000 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [2a00:1450:4864:20::136]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id dcf60bb0-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:33:08 +0100 (CET) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-511570b2f49so136041e87.1 for ; Mon, 05 Feb 2024 07:33:08 -0800 (PST) Received: from fedora.. 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Mon, 05 Feb 2024 07:33:07 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCXqqlMbaSt5dGe6wWB/Mq9M7T+par/wtcW9fLFZQD0jxwZqidUCJuT7gLsc0f9m5J5Z0qt6rISb/JSAYl79PL/E4plmr7tdNgMVghLgHOXCYjfvDZ0bdqIx95KTjKCM+RAwLlhFo6A+wMdgkkOr9903rCCkn+jtVV1XbIjhy7f1WnAvKXn7+YJ5KXvJlyzFWETuCl8er+K94UNkv7F/SimG+ceohExy49hPvZqnjGBC16yPsKA0c/AtgMp81TG2Bm/0KBZwr2OlfR49KakGMAxSkT+e9iG5N2xCvKREBtmkgIHjxHUyt9KPsUnmAtF+3YfvHxxO From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v4 26/30] xen/riscv: add minimal stuff to mm.h to build full Xen Date: Mon, 5 Feb 2024 16:32:33 +0100 Message-ID: <369fe9e80d11c5e499810a6819fc1c282ce60628.1707146506.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V4: - update an argument name of PFN_ORDERN macros. - drop pad at the end of 'struct page_info'. - Change message -> subject in "Changes in V3" - delete duplicated macros from riscv/mm.h - fix identation in struct page_info - align comment for PGC_ macros - update definitions of domain_set_alloc_bitsize() and domain_clamp_alloc_bitsize() - drop unnessary comments. - s/BUG/BUG_ON("...") - define __virt_to_maddr, __maddr_to_virt as stubs - add inclusion of xen/mm-frame.h for mfn_x and others - include "xen/mm.h" instead of "asm/mm.h" to fix compilation issues: In file included from arch/riscv/setup.c:7: ./arch/riscv/include/asm/mm.h:60:28: error: field 'list' has incomplete type 60 | struct page_list_entry list; | ^~~~ ./arch/riscv/include/asm/mm.h:81:43: error: 'MAX_ORDER' undeclared here (not in a function) 81 | unsigned long first_dirty:MAX_ORDER + 1; | ^~~~~~~~~ ./arch/riscv/include/asm/mm.h:81:31: error: bit-field 'first_dirty' width not an integer constant 81 | unsigned long first_dirty:MAX_ORDER + 1; - Define __virt_to_mfn() and __mfn_to_virt() using maddr_to_mfn() and mfn_to_maddr(). --- Changes in V3: - update the commit title - introduce DIRECTMAP_VIRT_START. - drop changes related pfn_to_paddr() and paddr_to_pfn as they were remvoe in [PATCH v2 32/39] xen/riscv: add minimal stuff to asm/page.h to build full Xen - code style fixes. - drop get_page_nr and put_page_nr as they don't need for time being - drop CONFIG_STATIC_MEMORY related things - code style fixes --- Changes in V2: - define stub for arch_get_dma_bitsize(void) --- xen/arch/riscv/include/asm/mm.h | 246 ++++++++++++++++++++++++++++++++ xen/arch/riscv/mm.c | 2 +- xen/arch/riscv/setup.c | 2 +- 3 files changed, 248 insertions(+), 2 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h index 07c7a0abba..0254babcc1 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -3,11 +3,252 @@ #ifndef _ASM_RISCV_MM_H #define _ASM_RISCV_MM_H +#include +#include +#include +#include +#include + #include #define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) #define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa)) +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn)) +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga)) +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn)) +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma)) +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)va)) +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va)) + +static inline unsigned long __virt_to_maddr(unsigned long va) +{ + BUG_ON("unimplemented"); + return 0; +} + +static inline void *__maddr_to_virt(unsigned long ma) +{ + BUG_ON("unimplemented"); + return NULL; +} + +#define virt_to_maddr(va) __virt_to_maddr((unsigned long)(va)) +#define maddr_to_virt(pa) __maddr_to_virt((unsigned long)(pa)) + +/* Convert between Xen-heap virtual addresses and machine frame numbers. */ +#define __virt_to_mfn(va) mfn_x(maddr_to_mfn(virt_to_maddr(va))) +#define __mfn_to_virt(mfn) maddr_to_virt(mfn_to_maddr(_mfn(mfn))) + +/* Convert between Xen-heap virtual addresses and page-info structures. */ +static inline struct page_info *virt_to_page(const void *v) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* + * We define non-underscored wrappers for above conversion functions. + * These are overriden in various source files while underscored version + * remain intact. + */ +#define virt_to_mfn(va) __virt_to_mfn(va) +#define mfn_to_virt(mfn) __mfn_to_virt(mfn) + +struct page_info +{ + /* Each frame can be threaded onto a doubly-linked list. */ + struct page_list_entry list; + + /* Reference count and various PGC_xxx flags and fields. */ + unsigned long count_info; + + /* Context-dependent fields follow... */ + union { + /* Page is in use: ((count_info & PGC_count_mask) != 0). */ + struct { + /* Type reference count and various PGT_xxx flags and fields. */ + unsigned long type_info; + } inuse; + /* Page is on a free list: ((count_info & PGC_count_mask) == 0). */ + union { + struct { + /* + * Index of the first *possibly* unscrubbed page in the buddy. + * One more bit than maximum possible order to accommodate + * INVALID_DIRTY_IDX. + */ +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + unsigned long first_dirty:MAX_ORDER + 1; + + /* Do TLBs need flushing for safety before next page use? */ + bool need_tlbflush:1; + +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + unsigned long scrub_state:2; + }; + + unsigned long val; + } free; + } u; + + union { + /* Page is in use, but not as a shadow. */ + struct { + /* Owner of this page (zero if page is anonymous). */ + struct domain *domain; + } inuse; + + /* Page is on a free list. */ + struct { + /* Order-size of the free chunk this page is the head of. */ + unsigned int order; + } free; + } v; + + union { + /* + * Timestamp from 'TLB clock', used to avoid extra safety flushes. + * Only valid for: a) free pages, and b) pages with zero type count + */ + uint32_t tlbflush_timestamp; + }; +}; + +#define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) + +/* PDX of the first page in the frame table. */ +extern unsigned long frametable_base_pdx; + +/* Convert between machine frame numbers and page-info structures. */ +#define mfn_to_page(mfn) \ + (frame_table + (mfn_to_pdx(mfn) - frametable_base_pdx)) +#define page_to_mfn(pg) \ + pdx_to_mfn((unsigned long)((pg) - frame_table) + frametable_base_pdx) + +static inline void *page_to_virt(const struct page_info *pg) +{ + return mfn_to_virt(mfn_x(page_to_mfn(pg))); +} + +/* + * Common code requires get_page_type and put_page_type. + * We don't care about typecounts so we just do the minimum to make it + * happy. + */ +static inline int get_page_type(struct page_info *page, unsigned long type) +{ + return 1; +} + +static inline void put_page_type(struct page_info *page) +{ +} + +static inline void put_page_and_type(struct page_info *page) +{ + put_page_type(page); + put_page(page); +} + +/* + * RISC-V does not have an M2P, but common code expects a handful of + * M2P-related defines and functions. Provide dummy versions of these. + */ +#define INVALID_M2P_ENTRY (~0UL) +#define SHARED_M2P_ENTRY (~0UL - 1UL) +#define SHARED_M2P(_e) ((_e) == SHARED_M2P_ENTRY) + +#define set_gpfn_from_mfn(mfn, pfn) do { (void)(mfn), (void)(pfn); } while (0) +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define PDX_GROUP_SHIFT (16 + 5) + +static inline unsigned long domain_get_maximum_gpfn(struct domain *d) +{ + BUG_ON("unimplemented"); + return 0; +} + +static inline long arch_memory_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); + return 0; +} + +/* + * On RISCV, all the RAM is currently direct mapped in Xen. + * Hence return always true. + */ +static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr) +{ + return true; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x ## UL << PG_shift(idx)) + +#define PGT_none PG_mask(0, 1) /* no special uses of this page */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ + + /* Count of uses of this frame as its current type. */ +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL << PGT_count_width) - 1) + +/* + * Page needs to be scrubbed. Since this bit can only be set on a page that is + * free (i.e. in PGC_state_free) we can reuse PGC_allocated bit. + */ +#define _PGC_need_scrub _PGC_allocated +#define PGC_need_scrub PGC_allocated + +/* Cleared when the owning guest 'frees' this page. */ +#define _PGC_allocated PG_shift(1) +#define PGC_allocated PG_mask(1, 1) +/* Page is Xen heap? */ +#define _PGC_xen_heap PG_shift(2) +#define PGC_xen_heap PG_mask(1, 2) +/* Page is broken? */ +#define _PGC_broken PG_shift(7) +#define PGC_broken PG_mask(1, 7) +/* Mutually-exclusive page states: { inuse, offlining, offlined, free }. */ +#define PGC_state PG_mask(3, 9) +#define PGC_state_inuse PG_mask(0, 9) +#define PGC_state_offlining PG_mask(1, 9) +#define PGC_state_offlined PG_mask(2, 9) +#define PGC_state_free PG_mask(3, 9) +#define page_state_is(pg, st) (((pg)->count_info&PGC_state) == PGC_state_##st) + +/* Count of references to this frame. */ +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL << PGC_count_width) - 1) + +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +#define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) +#define is_xen_heap_mfn(mfn) \ + (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) + +#define is_xen_fixed_mfn(mfn) \ + ((mfn_to_maddr(mfn) >= virt_to_maddr((vaddr_t)_start)) && \ + (mfn_to_maddr(mfn) <= virt_to_maddr((vaddr_t)_end - 1))) + +#define page_get_owner(_p) (_p)->v.inuse.domain +#define page_set_owner(_p,_d) ((_p)->v.inuse.domain = (_d)) + +/* TODO: implement */ +#define mfn_valid(mfn) ({ (void)(mfn); 0; }) + +#define domain_set_alloc_bitsize(d) ((void)(d)) +#define domain_clamp_alloc_bitsize(d, b) ((void)(d), (b)) + +#define PFN_ORDER(pfn) ((pfn)->v.free.order) + extern unsigned char cpu0_boot_stack[]; void setup_initial_pagetables(void); @@ -20,4 +261,9 @@ unsigned long calc_phys_offset(void); void turn_on_mmu(unsigned long ra); +static inline unsigned int arch_get_dma_bitsize(void) +{ + return 32; /* TODO */ +} + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 053f043a3d..fe3a43be20 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -5,12 +5,12 @@ #include #include #include +#include #include #include #include #include -#include #include #include diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 6593f601c1..98a94c4c48 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,9 +2,9 @@ #include #include +#include #include -#include /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] From patchwork Mon Feb 5 15:32:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B62B0C4828D for ; Mon, 5 Feb 2024 15:46:11 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676323.1052438 (Exim 4.92) (envelope-from ) id 1rX1AV-0000JP-QJ; Mon, 05 Feb 2024 15:45:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 676323.1052438; Mon, 05 Feb 2024 15:45:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX1AV-0000JI-NH; Mon, 05 Feb 2024 15:45:59 +0000 Received: by outflank-mailman (input) for mailman id 676323; Mon, 05 Feb 2024 15:45:59 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rX0y6-0007Hv-E1 for xen-devel@lists.xenproject.org; Mon, 05 Feb 2024 15:33:10 +0000 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [2a00:1450:4864:20::132]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ddca2410-c43b-11ee-8a46-1f161083a0e0; Mon, 05 Feb 2024 16:33:09 +0100 (CET) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-511490772f6so1898306e87.2 for ; Mon, 05 Feb 2024 07:33:09 -0800 (PST) Received: from fedora.. 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+struct vcpu; + +void vm_event_fill_regs(struct vm_event_st *req) +{ + BUG_ON("unimplemented"); +} + +void vm_event_set_registers(struct vcpu *v, struct vm_event_st *rsp) +{ + BUG_ON("unimplemented"); +} + +void vm_event_monitor_next_interrupt(struct vcpu *v) +{ + /* Not supported on RISCV. */ +} From patchwork Mon Feb 5 15:32:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31FF5C48295 for ; Mon, 5 Feb 2024 15:49:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.676344.1052499 (Exim 4.92) (envelope-from ) id 1rX1E0-0004Zg-KD; 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It is defibed in asm-generic/vm_event.h. - move vm_event_*() functions from stubs.c to riscv/vm_event.c. - s/BUG/BUG_ON("unimplemented") in stubs.c - back irq_actor_none() and irq_actor_none() as common/irq.c isn't compiled at this moment, so this function are needed to avoid compilation error. - defined max_page to avoid compilation error, it will be removed as soon as common/page_alloc.c will be compiled. --- Changes in V3: - code style fixes. - update attribute for frametable_base_pdx and frametable_virt_end to __ro_after_init. insteaf of read_mostly. - use BUG() instead of assert_failed/WARN for newly introduced stubs. - drop "#include " in stubs.c and use forward declaration instead. - drop ack_node() and end_node() as they aren't used now. --- Changes in V2: - define udelay stub - remove 'select HAS_PDX' from RISC-V Kconfig because of https://lore.kernel.org/xen-devel/20231006144405.1078260-1-andrew.cooper3@citrix.com/ --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/early_printk.c | 1 - xen/arch/riscv/mm.c | 50 ++++ xen/arch/riscv/setup.c | 8 + xen/arch/riscv/stubs.c | 438 ++++++++++++++++++++++++++++++++++ xen/arch/riscv/traps.c | 25 ++ 6 files changed, 522 insertions(+), 1 deletion(-) create mode 100644 xen/arch/riscv/stubs.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 1ed1a8369b..60afbc0ad9 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,7 @@ obj-y += mm.o obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o obj-y += setup.o +obj-y += stubs.o obj-y += traps.o obj-y += vm_event.o diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c index 60742a042d..6d0911659d 100644 --- a/xen/arch/riscv/early_printk.c +++ b/xen/arch/riscv/early_printk.c @@ -207,4 +207,3 @@ void printk(const char *format, ...) } #endif - diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index fe3a43be20..2c3fb7d72e 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -14,6 +15,9 @@ #include #include +unsigned long __ro_after_init frametable_base_pdx; +unsigned long __ro_after_init frametable_virt_end; + struct mmu_desc { unsigned int num_levels; unsigned int pgtbl_count; @@ -294,3 +298,49 @@ unsigned long __init calc_phys_offset(void) phys_offset = load_start - XEN_VIRT_START; return phys_offset; } + +void put_page(struct page_info *page) +{ + BUG_ON("unimplemented"); +} + +unsigned long get_upper_mfn_bound(void) +{ + /* No memory hotplug yet, so current memory limit is the final one. */ + return max_page - 1; +} + +void arch_dump_shared_mem_info(void) +{ + BUG_ON("unimplemented"); +} + +int populate_pt_range(unsigned long virt, unsigned long nr_mfns) +{ + BUG_ON("unimplemented"); + return -1; +} + +int xenmem_add_to_physmap_one(struct domain *d, unsigned int space, + union add_to_physmap_extra extra, + unsigned long idx, gfn_t gfn) +{ + BUG_ON("unimplemented"); + + return 0; +} + +int destroy_xen_mappings(unsigned long s, unsigned long e) +{ + BUG_ON("unimplemented"); + return -1; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + BUG_ON("unimplemented"); + return -1; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 98a94c4c48..8bb5bdb2ae 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include + #include +void arch_get_xen_caps(xen_capabilities_info_t *info) +{ + BUG_ON("unimplemented"); +} + /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c new file mode 100644 index 0000000000..529f1dbe52 --- /dev/null +++ b/xen/arch/riscv/stubs.c @@ -0,0 +1,438 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include + +#include + +/* smpboot.c */ + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +/* ID of the PCPU we're running on */ +DEFINE_PER_CPU(unsigned int, cpu_id); +/* XXX these seem awfully x86ish... */ +/* representing HT siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); +/* representing HT and core siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); + +nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; + +/* + * max_page is defined in page_alloc.c which isn't complied for now. + * definition of max_page will be remove as soon as page_alloc is built. + */ +unsigned long __read_mostly max_page; + +/* time.c */ + +unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ + +s_time_t get_s_time(void) +{ + BUG_ON("unimplemented"); +} + +int reprogram_timer(s_time_t timeout) +{ + BUG_ON("unimplemented"); +} + +void send_timer_event(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) +{ + BUG_ON("unimplemented"); +} + +/* shutdown.c */ + +void machine_restart(unsigned int delay_millisecs) +{ + BUG_ON("unimplemented"); +} + +void machine_halt(void) +{ + BUG_ON("unimplemented"); +} + +/* domctl.c */ + +long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, + XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) +{ + BUG_ON("unimplemented"); +} + +void arch_get_domain_info(const struct domain *d, + struct xen_domctl_getdomaininfo *info) +{ + BUG_ON("unimplemented"); +} + +void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +/* monitor.c */ + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop) +{ + BUG_ON("unimplemented"); +} + +/* smp.c */ + +void arch_flush_tlb_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_call_function_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +/* irq.c */ + +struct pirq *alloc_pirq_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) +{ + BUG_ON("unimplemented"); +} + +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) +{ + BUG_ON("unimplemented"); +} + +void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +hw_irq_controller no_irq_type = { + .typename = "none", + .startup = irq_startup_none, + .shutdown = irq_shutdown_none, + .enable = irq_enable_none, + .disable = irq_disable_none, +}; + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +void smp_send_state_dump(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* domain.c */ + +DEFINE_PER_CPU(struct vcpu *, curr_vcpu); +unsigned long __per_cpu_offset[NR_CPUS]; + +void context_switch(struct vcpu *prev, struct vcpu *next) +{ + BUG_ON("unimplemented"); +} + +void continue_running(struct vcpu *same) +{ + BUG_ON("unimplemented"); +} + +void sync_local_execstate(void) +{ + BUG_ON("unimplemented"); +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void startup_cpu_idle_loop(void) +{ + BUG_ON("unimplemented"); +} + +void free_domain_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void dump_pageframe_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void free_vcpu_struct(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_create(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_switch_to_aarch64_mode(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_teardown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_destroy(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_shutdown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_pause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_unpause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_soft_reset(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_creation_finished(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +int arch_initialise_vcpu(struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_reset(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int domain_relinquish_resources(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_domain_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_vcpu_info(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_mark_events_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_block_unless_event_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_kick(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +struct domain *alloc_domain_struct(void) +{ + BUG_ON("unimplemented"); +} + +struct vcpu *alloc_vcpu_struct(const struct domain *d) +{ + BUG_ON("unimplemented"); +} + +unsigned long +hypercall_create_continuation(unsigned int op, const char *format, ...) +{ + BUG_ON("unimplemented"); +} + +int __init parse_arch_dom0_param(const char *s, const char *e) +{ + BUG_ON("unimplemented"); +} + +/* guestcopy.c */ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +unsigned long raw_copy_from_guest(void *to, const void __user *from, + unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* sysctl.c */ + +long arch_do_sysctl(struct xen_sysctl *sysctl, + XEN_GUEST_HANDLE_PARAM(xen_sysctl_t) u_sysctl) +{ + BUG_ON("unimplemented"); +} + +void arch_do_physinfo(struct xen_sysctl_physinfo *pi) +{ + BUG_ON("unimplemented"); +} + +/* p2m.c */ + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + BUG_ON("unimplemented"); +} + +int unmap_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int map_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int set_foreign_p2m_entry(struct domain *d, const struct domain *fd, + unsigned long gfn, mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + BUG_ON("unimplemented"); +} + +/* delay.c */ + +void udelay(unsigned long usecs) +{ + BUG_ON("unimplemented"); +} + +/* guest_access.h */ + +static inline unsigned long raw_clear_guest(void *to, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* smpboot.c */ + +int __cpu_up(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +void __cpu_disable(void) +{ + BUG_ON("unimplemented"); +} + +void __cpu_die(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* + * The following functions are defined in common/irq.c, which will be built in + * the next commit, so these changes will be removed there. + */ + +void cf_check irq_actor_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +unsigned int cf_check irq_startup_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); + + return 0; +} diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..ca56df75d8 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,6 +4,10 @@ * * RISC-V Trap handlers */ + +#include +#include + #include #include @@ -11,3 +15,24 @@ void do_trap(struct cpu_user_regs *cpu_regs) { die(); } + +void vcpu_show_execution_state(struct vcpu *v) +{ + assert_failed("need to be implented"); +} + +void show_execution_state(const struct cpu_user_regs *regs) +{ + printk("implement show_execution_state(regs)\n"); +} + +void arch_hypercall_tasklet_result(struct vcpu *v, long res) +{ + assert_failed("need to be implented"); +} + +enum mc_disposition arch_do_multicall_call(struct mc_state *state) +{ + assert_failed("need to be implented"); + return mc_continue; +} From patchwork Mon Feb 5 15:32:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13545742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FED7C48295 for ; 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Only rebase. --- xen/arch/riscv/Makefile | 16 +++- xen/arch/riscv/arch.mk | 4 - xen/arch/riscv/early_printk.c | 167 ---------------------------------- xen/arch/riscv/stubs.c | 23 ----- 4 files changed, 15 insertions(+), 195 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 60afbc0ad9..81b77b13d6 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -12,10 +12,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=sysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=sysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=sysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index a4b53adaf7..4363776f34 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -14,7 +14,3 @@ riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause # -mcmodel=medlow would force Xen into the lower half. CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany - -# TODO: Drop override when more of the build is working -override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o -override ALL_LIBS-y = diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c index 6d0911659d..610c814f54 100644 --- a/xen/arch/riscv/early_printk.c +++ b/xen/arch/riscv/early_printk.c @@ -40,170 +40,3 @@ void early_printk(const char *str) str++; } } - -/* - * The following #if 1 ... #endif should be removed after printk - * and related stuff are ready. - */ -#if 1 - -#include -#include - -/** - * strlen - Find the length of a string - * @s: The string to be sized - */ -size_t (strlen)(const char * s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} - -/** - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *(memcpy)(void *dest, const void *src, size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} - -int vsnprintf(char* str, size_t size, const char* format, va_list args) -{ - size_t i = 0; /* Current position in the output string */ - size_t written = 0; /* Total number of characters written */ - char* dest = str; - - while ( format[i] != '\0' && written < size - 1 ) - { - if ( format[i] == '%' ) - { - i++; - - if ( format[i] == '\0' ) - break; - - if ( format[i] == '%' ) - { - if ( written < size - 1 ) - { - dest[written] = '%'; - written++; - } - i++; - continue; - } - - /* - * Handle format specifiers. - * For simplicity, only %s and %d are implemented here. - */ - - if ( format[i] == 's' ) - { - char* arg = va_arg(args, char*); - size_t arglen = strlen(arg); - - size_t remaining = size - written - 1; - - if ( arglen > remaining ) - arglen = remaining; - - memcpy(dest + written, arg, arglen); - - written += arglen; - i++; - } - else if ( format[i] == 'd' ) - { - int arg = va_arg(args, int); - - /* Convert the integer to string representation */ - char numstr[32]; /* Assumes a maximum of 32 digits */ - int numlen = 0; - int num = arg; - size_t remaining; - - if ( arg < 0 ) - { - if ( written < size - 1 ) - { - dest[written] = '-'; - written++; - } - - num = -arg; - } - - do - { - numstr[numlen] = '0' + num % 10; - num = num / 10; - numlen++; - } while ( num > 0 ); - - /* Reverse the string */ - for (int j = 0; j < numlen / 2; j++) - { - char tmp = numstr[j]; - numstr[j] = numstr[numlen - 1 - j]; - numstr[numlen - 1 - j] = tmp; - } - - remaining = size - written - 1; - - if ( numlen > remaining ) - numlen = remaining; - - memcpy(dest + written, numstr, numlen); - - written += numlen; - i++; - } - } - else - { - if ( written < size - 1 ) - { - dest[written] = format[i]; - written++; - } - i++; - } - } - - if ( size > 0 ) - dest[written] = '\0'; - - return written; -} - -void printk(const char *format, ...) -{ - static char buf[1024]; - - va_list args; - va_start(args, format); - - (void)vsnprintf(buf, sizeof(buf), format, args); - - early_printk(buf); - - va_end(args); -} - -#endif diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 529f1dbe52..bda35fc347 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -24,12 +24,6 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; -/* - * max_page is defined in page_alloc.c which isn't complied for now. - * definition of max_page will be remove as soon as page_alloc is built. - */ -unsigned long __read_mostly max_page; - /* time.c */ unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ @@ -419,20 +413,3 @@ void __cpu_die(unsigned int cpu) { BUG_ON("unimplemented"); } - -/* - * The following functions are defined in common/irq.c, which will be built in - * the next commit, so these changes will be removed there. - */ - -void cf_check irq_actor_none(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); -} - -unsigned int cf_check irq_startup_none(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id s1-20020a056512314100b005114d401157sm474445lfi.2.2024.02.05.07.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 07:33:12 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e00f2f61-c43b-11ee-8a46-1f161083a0e0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1707147192; x=1707751992; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mHfOArS8uJvdUvmhNcbyjrkgkF05plzKh9QEvVv6hbw=; b=bLoNxZCoOZz11OEsjc8LJGnXFcSvDYbnpuvISuu5kV9G0XNkROTmOrbuHslvbCwB7/ 8yVGHvX0G+dJo08hoBkFIG0o1DKW1BPelVWjxsD3uXOYDomSGtgx+xp7wqHleKW54VXr X5r4rs72J/UtLVnM798rieJxK8DvLFqxq4kngMI4Cx2A7Rl6rK2EXodEB9Gj7xtme7YI E8vVeSD5yM2a9fs7KqvZ6Pr8W7og01EKKvWcanRqWt85LmV3XKXw7N/G64JCzErxfqob kXJ0NLJvUqcXIFj8GJcJVefjXJIZehML3pg5+sb7X5e6UAnODOEx604l9oOA3PPVcKNU VBmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707147192; x=1707751992; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mHfOArS8uJvdUvmhNcbyjrkgkF05plzKh9QEvVv6hbw=; b=OC26O00Xke4vbFjyJf4o1Us3ZZyaXZ59+y4CuGfQSYEj7ZULrQUxe5yVKAR2aXg3aY JpuvAmrPs5i7XyfFKaM3+rldBmXD/+D6thhrMcksj/rCO55Hojt4DLmzdW3pJ02dY33p OrbGLZYUCUfosYQKYsAo9qm26OBO55iQtGhI65gb9k4qyO5dHnxSIa2zqeSxah87KN6I qCaynFosp/WQoOn/4PpcXavE6EJ6ChnYKhBByCpn6X10KGEt+IdfCXU7g8YJH5ripIXk pqghPCg2R9sqNI0eCE9oyCz3Vg3fkVMyza9TqGRP4VbH0i3wiQh6i6pHuq2lO4upvUUS MQmQ== X-Gm-Message-State: AOJu0YzqTIU167HfXgwYy+CUW4MFRSjvvrAEc2QwGKijGrwNtH4BjJBG NBNcWxNNkl64+as2AC/yYFJCMuVnnp/Yh1Ue4jJy0CqUy1yTtZMiFBgVBsQl X-Google-Smtp-Source: AGHT+IFBvdM1BK0z6wUkWhrRiZ3w2wNb0SO1kX6dmGbvkfVIsOwXcHO3jk/3iF64lOET80/d5b1U7A== X-Received: by 2002:a05:6512:3d1d:b0:511:47ed:d744 with SMTP id d29-20020a0565123d1d00b0051147edd744mr4893576lfv.12.1707147192622; Mon, 05 Feb 2024 07:33:12 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCXFoXbLJwXhoXwmg9HQ+lqPXk8ylmx6jbLjT+zM89gRYK/F0wv/tsMO4LoKFT5RIGEPAjMnZtD9g8xotGFo6TZrZ7UmGcGLygewAGSL5QM9fTZN1n8ffiiEhq1ZH2XVuRwtsb9xjdRLQTjItvvEuW6JbI7lAfj4eugYX4XgbSMr/lBK6App7anZC0zPg96h0B7Xd5vLLt39uhriz3C3sqzNSUnrzA4uWJYcKw== From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v4 30/30] xen/README: add compiler and binutils versions for RISC-V64 Date: Mon, 5 Feb 2024 16:32:37 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V4: - Update version of GCC (12.2) and GNU Binutils (2.39) to the version which are in Xen's contrainter for RISC-V --- Changes in V3: - new patch --- README | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README b/README index c8a108449e..9a898125e1 100644 --- a/README +++ b/README @@ -48,6 +48,9 @@ provided by your OS distributor: - For ARM 64-bit: - GCC 5.1 or later - GNU Binutils 2.24 or later + - For RISC-V 64-bit: + - GCC 12.2 or later + - GNU Binutils 2.39 or later * POSIX compatible awk * Development install of zlib (e.g., zlib-dev) * Development install of Python 2.7 or later (e.g., python-dev)