From patchwork Wed Feb 7 00:36:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Ogletree X-Patchwork-Id: 13547947 Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CD7E53A0; Wed, 7 Feb 2024 00:37:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.149.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266222; cv=none; b=u7VGO7ofzafZa5kSV1tqMbAb1Tk6+GYgSSDTNloEN0sDKJRAzxhWsuzfnuSyzpviLtRw4xgkTOeoRHuqE8UFFy2a0Swy2x5iohOwuXggOaX38L7rsN7pO5BIbueRGo77uMdw8n0wBtGdH6YCKAxBrJYwXG2LZgeuR2LS5XYF9+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266222; c=relaxed/simple; bh=vXVEHro+kh+YU7oYUQETQGKSqdh5tFmUoTsCCOespAA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oG5JnLeJ5dQO67MtBWmu3qsyqP6qTMjOJZdvqYXygAbztvnFpkoc8fx/EXlrBOoFcp5R+RLCFbVZRBaAV1rGSUkGMVHhxkaXUcbp6CfJNfNTpl8VXNLRLcMh3t/jFWKs1dYV606b7LR+r216XmRkml/1xA+/vRignnDgsoQ6eTA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com; spf=pass smtp.mailfrom=opensource.cirrus.com; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b=RKHlu0GC; arc=none smtp.client-ip=67.231.149.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="RKHlu0GC" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4166x9cg021815; Tue, 6 Feb 2024 18:36:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= PODMain02222019; bh=bgXhbPQ0oVIzVPug/8JX+JbGbjZVzrHLQ1/b0crdZ48=; b= RKHlu0GCNN9+nicvfRsAWS8c1oBi4gWo74QqAe1g3uLM8AZoEvvyW31VVFW0Z7Nm Y3AvWKakHBS01mCb7Ji6MCIkn9RH9gMv3IUf7+fjKTmwNMLrWNRC9zlKYkvtpEYC dfg8WNclntbqAcIs6T0Ya+s7GoFSXDbENzMAgii4eP8stmAKrdtLjqywyQC064wR mauiw8SH2kgKQnDYclSfauokcEH8M10lGb9pQxtW4esq5e1fr2Z3+W6NPdI861m5 hlb8Aj/S2b1Jpjj9bAc+VQknz9pPvzFZcqpv45lTghmd0W2nVVm030HlIc9PXo0Q t6gc5QCSk6fFXkOhHwKdzw== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3w1ks2cbg7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 18:36:45 -0600 (CST) Received: from ediex01.ad.cirrus.com (198.61.84.80) by ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 7 Feb 2024 00:36:42 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40 via Frontend Transport; Wed, 7 Feb 2024 00:36:42 +0000 Received: from aus-sw-rshr002.ad.cirrus.com (aus-sw-rshr002.ad.cirrus.com [141.131.145.53]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTP id 353FC820246; Wed, 7 Feb 2024 00:36:41 +0000 (UTC) From: James Ogletree To: , , , , , , CC: , , , , James Ogletree Subject: [PATCH v6 1/5] firmware: cs_dsp: Add write sequencer interface Date: Wed, 7 Feb 2024 00:36:08 +0000 Message-ID: <20240207003612.4187370-2-jogletre@opensource.cirrus.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> References: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: LSdHx7hfL6XUvv3S9TNWJwa4S7TkRjmA X-Proofpoint-ORIG-GUID: LSdHx7hfL6XUvv3S9TNWJwa4S7TkRjmA X-Proofpoint-Spam-Reason: safe A write sequencer is a sequence of register addresses and values executed by some Cirrus DSPs following power state transitions. Add support for Cirrus drivers to update or add to a write sequencer present in firmware. Signed-off-by: James Ogletree --- drivers/firmware/cirrus/cs_dsp.c | 263 +++++++++++++++++++++++++ include/linux/firmware/cirrus/cs_dsp.h | 29 +++ 2 files changed, 292 insertions(+) diff --git a/drivers/firmware/cirrus/cs_dsp.c b/drivers/firmware/cirrus/cs_dsp.c index 79d4254d1f9b..bf6aab16ddc4 100644 --- a/drivers/firmware/cirrus/cs_dsp.c +++ b/drivers/firmware/cirrus/cs_dsp.c @@ -275,6 +275,12 @@ #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff #define HALO_MPU_VIO_ERR_SRC_SHIFT 0 +/* + * Write Sequence + */ +#define WSEQ_OP_MAX_WORDS 3 +#define WSEQ_END_OF_SCRIPT 0xFFFFFF + struct cs_dsp_ops { bool (*validate_version)(struct cs_dsp *dsp, unsigned int version); unsigned int (*parse_sizes)(struct cs_dsp *dsp, @@ -3339,6 +3345,263 @@ int cs_dsp_chunk_read(struct cs_dsp_chunk *ch, int nbits) } EXPORT_SYMBOL_NS_GPL(cs_dsp_chunk_read, FW_CS_DSP); + +struct cs_dsp_wseq_op { + struct list_head list; + u32 address; + u32 data; + u16 offset; + u8 operation; +}; + +static int cs_dsp_populate_wseq(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq) +{ + struct cs_dsp_wseq_op *op = NULL; + struct cs_dsp_chunk ch; + u8 *words; + int ret; + + if (!wseq->ctl) { + cs_dsp_err(dsp, "No control for write sequence\n"); + return -EINVAL; + } + + words = kzalloc(wseq->ctl->len, GFP_KERNEL); + if (!words) + return -ENOMEM; + + ret = cs_dsp_coeff_read_ctrl(wseq->ctl, 0, words, wseq->ctl->len); + if (ret) { + cs_dsp_err(dsp, "Failed to read %s: %d\n", wseq->name, ret); + goto err_free; + } + + INIT_LIST_HEAD(&wseq->ops); + + ch = cs_dsp_chunk(words, wseq->ctl->len); + + while (!cs_dsp_chunk_end(&ch)) { + op = devm_kzalloc(dsp->dev, sizeof(*op), GFP_KERNEL); + if (!op) { + ret = -ENOMEM; + goto err_free; + } + + op->offset = cs_dsp_chunk_bytes(&ch); + op->operation = cs_dsp_chunk_read(&ch, 8); + + switch (op->operation) { + case CS_DSP_WSEQ_END: + op->data = WSEQ_END_OF_SCRIPT; + break; + case CS_DSP_WSEQ_UNLOCK: + op->data = cs_dsp_chunk_read(&ch, 16); + break; + case CS_DSP_WSEQ_ADDR8: + op->address = cs_dsp_chunk_read(&ch, 8); + op->data = cs_dsp_chunk_read(&ch, 32); + break; + case CS_DSP_WSEQ_H16: + case CS_DSP_WSEQ_L16: + op->address = cs_dsp_chunk_read(&ch, 24); + op->data = cs_dsp_chunk_read(&ch, 16); + break; + case CS_DSP_WSEQ_FULL: + op->address = cs_dsp_chunk_read(&ch, 32); + op->data = cs_dsp_chunk_read(&ch, 32); + break; + default: + ret = -EINVAL; + cs_dsp_err(dsp, "Unsupported op: %X\n", op->operation); + goto err_free; + } + + list_add(&op->list, &wseq->ops); + + if (op->operation == CS_DSP_WSEQ_END) + break; + } + + if (op && op->operation != CS_DSP_WSEQ_END) { + cs_dsp_err(dsp, "Write sequence missing end terminator\n"); + ret = -ENOENT; + } + +err_free: + kfree(words); + + return ret; +} + +/** + * cs_dsp_wseq_init() - Initialize write sequences contained within the loaded DSP firmware + * @dsp: Pointer to DSP structure + * @wseqs: List of write sequences to initialize + * @num_wseqs: Number of write sequences to initialize + * + * Return: Zero for success, a negative number on error. + */ +int cs_dsp_wseq_init(struct cs_dsp *dsp, struct cs_dsp_wseq *wseqs, unsigned int num_wseqs) +{ + int i, ret = 0; + + mutex_lock(&dsp->pwr_lock); + + for (i = 0; i < num_wseqs; i++) { + ret = cs_dsp_populate_wseq(dsp, &wseqs[i]); + if (ret) + break; + } + + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(cs_dsp_wseq_init); + +static struct cs_dsp_wseq_op *cs_dsp_wseq_find_op(u32 addr, u8 op_code, + struct list_head *wseq_ops) +{ + struct cs_dsp_wseq_op *op; + + list_for_each_entry(op, wseq_ops, list) { + if (op->operation == op_code && op->address == addr) + return op; + } + + return NULL; +} + +/** + * cs_dsp_wseq_write() - Add or update an entry in a write sequence + * @dsp: Pointer to a DSP structure + * @wseq: Write sequence to write to + * @addr: Address of the register to be written to + * @data: Data to be written + * @op_code: The type of operation of the new entry + * @update: If true, searches for the first entry in the write sequence with + * the same address and op_code, and replaces it. If false, creates a new entry + * at the tail. + * + * This function formats register address and value pairs into the format + * required for write sequence entries, and either updates or adds the + * new entry into the write sequence. + * + * Return: Zero for success, a negative number on error. + */ +int cs_dsp_wseq_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, + u32 addr, u32 data, u8 op_code, bool update) +{ + struct cs_dsp_wseq_op *op_end, *op_new = NULL; + u32 words[WSEQ_OP_MAX_WORDS]; + struct cs_dsp_chunk ch; + int new_op_size, ret; + + if (update) + op_new = cs_dsp_wseq_find_op(addr, op_code, &wseq->ops); + + /* If entry to update is not found, treat it as a new operation */ + if (!op_new) { + op_end = cs_dsp_wseq_find_op(0, CS_DSP_WSEQ_END, &wseq->ops); + if (!op_end) { + cs_dsp_err(dsp, "Missing write sequence list terminator\n"); + return -EINVAL; + } + + op_new = devm_kzalloc(dsp->dev, sizeof(*op_new), GFP_KERNEL); + if (!op_new) + return -ENOMEM; + + op_new->operation = op_code; + op_new->address = addr; + op_new->offset = op_end->offset; + update = false; + } + + op_new->data = data; + + ch = cs_dsp_chunk(words, sizeof(words)); + cs_dsp_chunk_write(&ch, 8, op_new->operation); + switch (op_code) { + case CS_DSP_WSEQ_FULL: + cs_dsp_chunk_write(&ch, 32, op_new->address); + cs_dsp_chunk_write(&ch, 32, op_new->data); + break; + case CS_DSP_WSEQ_L16: + case CS_DSP_WSEQ_H16: + cs_dsp_chunk_write(&ch, 24, op_new->address); + cs_dsp_chunk_write(&ch, 16, op_new->data); + break; + default: + ret = -EINVAL; + cs_dsp_err(dsp, "Op code not supported: %X\n", op_code); + goto op_new_free; + } + + new_op_size = cs_dsp_chunk_bytes(&ch); + + if (!update) { + if (wseq->ctl->len - op_end->offset < new_op_size) { + cs_dsp_err(dsp, "Not enough memory in write sequence for entry\n"); + ret = -ENOMEM; + goto op_new_free; + } + + op_end->offset += new_op_size; + + ret = cs_dsp_coeff_write_ctrl(wseq->ctl, op_end->offset / sizeof(u32), + &op_end->data, sizeof(u32)); + if (ret) + goto op_new_free; + + list_add(&op_new->list, &wseq->ops); + } + + ret = cs_dsp_coeff_write_ctrl(wseq->ctl, op_new->offset / sizeof(u32), + words, new_op_size); + if (ret) + goto op_new_free; + + return 0; + +op_new_free: + devm_kfree(dsp->dev, op_new); + + return ret; +} +EXPORT_SYMBOL_GPL(cs_dsp_wseq_write); + +/** + * cs_dsp_wseq_multi_write() - Add or update multiple entries in the write sequence + * @dsp: Pointer to a DSP structure + * @wseq: Write sequence to write to + * @reg_seq: List of address-data pairs + * @num_regs: Number of address-data pairs + * @op_code: The types of operations of the new entries + * @update: If true, searches for the first entry in the write sequence with the same + * address and op code, and replaces it. If false, creates a new entry at the tail. + * + * This function calls cs_dsp_wseq_write() for multiple address-data pairs. + * + * Return: Zero for success, a negative number on error. + */ +int cs_dsp_wseq_multi_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, + const struct reg_sequence *reg_seq, int num_regs, + u8 op_code, bool update) +{ + int ret, i; + + for (i = 0; i < num_regs; i++) { + ret = cs_dsp_wseq_write(dsp, wseq, reg_seq[i].reg, + reg_seq[i].def, update, op_code); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cs_dsp_wseq_multi_write); + MODULE_DESCRIPTION("Cirrus Logic DSP Support"); MODULE_AUTHOR("Simon Trimmer "); MODULE_LICENSE("GPL v2"); diff --git a/include/linux/firmware/cirrus/cs_dsp.h b/include/linux/firmware/cirrus/cs_dsp.h index 29cd11d5a3cf..8190f12d3620 100644 --- a/include/linux/firmware/cirrus/cs_dsp.h +++ b/include/linux/firmware/cirrus/cs_dsp.h @@ -42,6 +42,16 @@ #define CS_DSP_ACKED_CTL_MIN_VALUE 0 #define CS_DSP_ACKED_CTL_MAX_VALUE 0xFFFFFF +/* + * Write sequence operation codes + */ +#define CS_DSP_WSEQ_FULL 0x00 +#define CS_DSP_WSEQ_ADDR8 0x02 +#define CS_DSP_WSEQ_L16 0x04 +#define CS_DSP_WSEQ_H16 0x05 +#define CS_DSP_WSEQ_UNLOCK 0xFD +#define CS_DSP_WSEQ_END 0xFF + /** * struct cs_dsp_region - Describes a logical memory region in DSP address space * @type: Memory region type @@ -255,6 +265,25 @@ struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp, const char *cs_dsp_mem_region_name(unsigned int type); +/** + * struct cs_dsp_wseq - Describes a write sequence + * @name: Name of cs_dsp control + * @ctl: Write sequence cs_dsp control + * @ops: Operations contained within this write sequence + */ +struct cs_dsp_wseq { + const char *name; + struct cs_dsp_coeff_ctl *ctl; + struct list_head ops; +}; + +int cs_dsp_wseq_init(struct cs_dsp *dsp, struct cs_dsp_wseq *wseqs, unsigned int num_wseqs); +int cs_dsp_wseq_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, u32 addr, u32 data, + u8 op_code, bool update); +int cs_dsp_wseq_multi_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, + const struct reg_sequence *reg_seq, int num_regs, + u8 op_code, bool update); + /** * struct cs_dsp_chunk - Describes a buffer holding data formatted for the DSP * @data: Pointer to underlying buffer memory From patchwork Wed Feb 7 00:36:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Ogletree X-Patchwork-Id: 13547946 Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D976F7F9; Wed, 7 Feb 2024 00:36:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.152.168 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266217; cv=none; b=YU1xIpz9QF3KhlAg+Ot6r/ETFe/75spSK+wpsmUD3XMUb/mqxRphi6Cwn6/c0sgKbHr/xMNVGlbpP00xiVYI45VbpsPMFspazqHWPnGl91R4OMmTxjCKpTQaGUC8t2mVczkIJs9WlbQJDckssyNmAIrvEdKIgQJ4x2WpRPhhRto= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266217; c=relaxed/simple; bh=wTxDmVzfPdXcHQSwlW4KF2mssI4Lscw01gT+paiaLMk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bWcV0oaP8AkTWRBjGEyJhZZdFIov+0Uh+YabRGgXdhuDaISHHAsYKr5WInXGsFmIWef5cgyLB7Sg4+xdsja8jsT4wjYlDDFyxovlI+S5x9EpNAi014u414R3s3a0VClyt3KahMovSuM3EPBaPiqempG1nRUJjgyUTCAkpoLUQFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com; spf=pass smtp.mailfrom=opensource.cirrus.com; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b=fgQShG/3; arc=none smtp.client-ip=67.231.152.168 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="fgQShG/3" Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 416Ng0Rw017380; Tue, 6 Feb 2024 18:36:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= PODMain02222019; bh=47IHhsRme6l9Ja8GxBg5XecVkHApII8gwWqYXN4mq3Y=; b= fgQShG/3qdDIGN4vMt12CJcCzoEgmuGuWG8LcrGuDPYM4oZp1vgDmuAb3aTa4+v7 KInrsHFjfkuC6phiiTYWd67O9Y6PcKSU8IVR601tZOuA9/kjaPXeke6WQ0TsFCyh 7UUK12zPSXxbwL1jsa0yiV1qD07iv9sR+uVdCPRDSmJrK3CX6pYy3GOloiK/ZO5q HUW3q7qpXoLCBEqCqJqrk0Nk07RoWcNnArJF43C3vUlQraa3hcv309OnQAYVZEB/ sUwNqtcdrSreLuVQi/Jk2W9fiKrkbxhyTzs0Aya8e7NhbgHS6ioJJSiMnaD3i/Pm G9tqfEQHgv94hHHg6XAj1w== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3w1jsnm8yr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 18:36:49 -0600 (CST) Received: from ediex02.ad.cirrus.com (198.61.84.81) by ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 7 Feb 2024 00:36:48 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by anon-ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server id 15.2.1118.40 via Frontend Transport; Wed, 7 Feb 2024 00:36:48 +0000 Received: from aus-sw-rshr002.ad.cirrus.com (aus-sw-rshr002.ad.cirrus.com [141.131.145.53]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTP id 3FC9F820246; Wed, 7 Feb 2024 00:36:46 +0000 (UTC) From: James Ogletree To: , , , , , , CC: , , , , James Ogletree , Krzysztof Kozlowski Subject: [PATCH v6 2/5] dt-bindings: input: cirrus,cs40l50: Add initial DT binding Date: Wed, 7 Feb 2024 00:36:09 +0000 Message-ID: <20240207003612.4187370-3-jogletre@opensource.cirrus.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> References: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: qMtWqgrcxIqeOypNsYUQ9ZqehdVNfRjQ X-Proofpoint-ORIG-GUID: qMtWqgrcxIqeOypNsYUQ9ZqehdVNfRjQ X-Proofpoint-Spam-Reason: safe The CS40L50 is a haptic driver with waveform memory, integrated DSP, and closed-loop algorithms. Add a YAML DT binding document for this device. Reviewed-by: Krzysztof Kozlowski Signed-off-by: James Ogletree --- .../bindings/input/cirrus,cs40l50.yaml | 70 +++++++++++++++++++ MAINTAINERS | 8 +++ 2 files changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml diff --git a/Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml b/Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml new file mode 100644 index 000000000000..6a5bdafed56b --- /dev/null +++ b/Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/cirrus,cs40l50.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS40L50 Advanced Haptic Driver + +maintainers: + - James Ogletree + +description: + CS40L50 is a haptic driver with waveform memory, + integrated DSP, and closed-loop algorithms. + +properties: + compatible: + enum: + - cirrus,cs40l50 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + va-supply: + description: Power supply for internal analog circuits. + + vp-supply: + description: Power supply for always-on circuits. + + vio-supply: + description: Power supply for digital input/output. + + vamp-supply: + description: Power supply for the Class D amplifier. + +required: + - compatible + - reg + - interrupts + - reset-gpios + - vp-supply + - vio-supply + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + haptic-driver@34 { + compatible = "cirrus,cs40l50"; + reg = <0x34>; + interrupt-parent = <&gpio>; + interrupts = <113 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio 112 GPIO_ACTIVE_LOW>; + vp-supply = <&vreg>; + vio-supply = <&vreg>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index dd5de540ec0b..b71017a187f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4933,6 +4933,14 @@ F: sound/pci/hda/cs* F: sound/pci/hda/hda_cs_dsp_ctl.* F: sound/soc/codecs/cs* +CIRRUS LOGIC HAPTIC DRIVERS +M: James Ogletree +M: Fred Treven +M: Ben Bright +L: patches@opensource.cirrus.com +S: Supported +F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml + CIRRUS LOGIC DSP FIRMWARE DRIVER M: Simon Trimmer M: Charles Keepax From patchwork Wed Feb 7 00:36:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Ogletree X-Patchwork-Id: 13547948 Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CD485382; Wed, 7 Feb 2024 00:37:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.149.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266222; cv=none; b=Hd3WPW+e0G0NGNxKXVjyZs1clHHIjoxH9K5aZsHoXqfEP3megavdlnv6soc5vHBv4RWXBv/XYnX5XeV5ImOhHDP8C1olXJoVEZPBlw/kaOWZaEedYTIMZVcKkZZtjBR0u3nGS/xZjSZP6/2D5x3Bf/lqdGtELjzHFGLTpN97AHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266222; c=relaxed/simple; bh=+3XGplTgclxOyWy1gnP9oJnTdiPMdH0/Nkf0/AWQFvE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rdf4L+SEVCau4AxqIoxR2DWGasaZOJu4zM/Z1LpnORaD7ZeOpf50hbQyGQwzW8jfoWXZ+EpqN3+mki5/h5YIYeIeH+1g0o1G7B/XzsefDWkSOYseTaXQUpGJtDKTSwiNaNIEgaur+Nsq2SOo1cBAjr9rztEmr+Zj7WFlvstXdOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com; spf=pass smtp.mailfrom=opensource.cirrus.com; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b=LIowJD15; arc=none smtp.client-ip=67.231.149.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="LIowJD15" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4166x9ch021815; Tue, 6 Feb 2024 18:36:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= PODMain02222019; bh=wwSJeCQjME0gCDZnyBcLJ4o0I/8DT61PqlfA8TKK9H0=; b= LIowJD15LtgfNnlaF1Q2A2YdeWTtg4MiQ3AUs24PH+vfJlnxplKD9b8DU1xQkHTO zTAyPnOK76pk4+l5G9IRdrI6CqyHXpmPm1igPhP3TYYbnlxvfVmF4iWqk2cYW6TT G1X+KNuFhAbhTsHj8hdjrXHhBKwmO9m8+q/WQu25uEjTKpCfClBatKSDLMum2CT1 gI6EPERLLT+zr6jCqQ1zckx2rrgyoXseWHRxnw04v9RuApnOzpoHPm2cXYnumjqW kxyqo0UJ236SpAsLuDKzpUclYS7SdRtH7Tn89/WGf9XW8FjMTZVOSjfcS7lzeuX0 2RqMk6ASh1ZWLBmA3fhLtA== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3w1ks2cbge-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 18:36:52 -0600 (CST) Received: from ediex02.ad.cirrus.com (198.61.84.81) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 7 Feb 2024 00:36:50 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by anon-ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server id 15.2.1118.40 via Frontend Transport; Wed, 7 Feb 2024 00:36:50 +0000 Received: from aus-sw-rshr002.ad.cirrus.com (aus-sw-rshr002.ad.cirrus.com [141.131.145.53]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTP id 4C26C820246; Wed, 7 Feb 2024 00:36:48 +0000 (UTC) From: James Ogletree To: , , , , , , CC: , , , , James Ogletree Subject: [PATCH v6 3/5] mfd: cs40l50: Add support for CS40L50 core driver Date: Wed, 7 Feb 2024 00:36:10 +0000 Message-ID: <20240207003612.4187370-4-jogletre@opensource.cirrus.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> References: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: uBvNmOzx8Ne4hIX5YL78Ixo8e6eIQLNz X-Proofpoint-ORIG-GUID: uBvNmOzx8Ne4hIX5YL78Ixo8e6eIQLNz X-Proofpoint-Spam-Reason: safe Introduce support for Cirrus Logic Device CS40L50: a haptic driver with waveform memory, integrated DSP, and closed-loop algorithms. The MFD component registers and initializes the device. Signed-off-by: James Ogletree --- MAINTAINERS | 2 + drivers/mfd/Kconfig | 30 ++ drivers/mfd/Makefile | 3 + drivers/mfd/cs40l50-core.c | 537 ++++++++++++++++++++++++++++++++++++ drivers/mfd/cs40l50-i2c.c | 69 +++++ drivers/mfd/cs40l50-spi.c | 69 +++++ include/linux/mfd/cs40l50.h | 134 +++++++++ 7 files changed, 844 insertions(+) create mode 100644 drivers/mfd/cs40l50-core.c create mode 100644 drivers/mfd/cs40l50-i2c.c create mode 100644 drivers/mfd/cs40l50-spi.c create mode 100644 include/linux/mfd/cs40l50.h diff --git a/MAINTAINERS b/MAINTAINERS index b71017a187f8..69a9e0a3b968 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4940,6 +4940,8 @@ M: Ben Bright L: patches@opensource.cirrus.com S: Supported F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml +F: drivers/mfd/cs40l* +F: include/linux/mfd/cs40l* CIRRUS LOGIC DSP FIRMWARE DRIVER M: Simon Trimmer diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 90ce58fd629e..5efab06a9a50 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -237,6 +237,36 @@ config MFD_CROS_EC_DEV To compile this driver as a module, choose M here: the module will be called cros-ec-dev. +config MFD_CS40L50_CORE + tristate + select MFD_CORE + select FW_CS_DSP + select REGMAP_IRQ + +config MFD_CS40L50_I2C + tristate "Cirrus Logic CS40L50 (I2C)" + select REGMAP_I2C + select MFD_CS40L50_CORE + depends on I2C + help + Select this to support the Cirrus Logic CS40L50 Haptic + Driver over I2C. + + This driver can be built as a module. If built as a module it will be + called "cs40l50-i2c". + +config MFD_CS40L50_SPI + tristate "Cirrus Logic CS40L50 (SPI)" + select REGMAP_SPI + select MFD_CS40L50_CORE + depends on SPI + help + Select this to support the Cirrus Logic CS40L50 Haptic + Driver over SPI. + + This driver can be built as a module. If built as a module it will be + called "cs40l50-spi". + config MFD_CS42L43 tristate select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index c66f07edcd0e..a7a0e50d83c3 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -13,6 +13,9 @@ obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o obj-$(CONFIG_MFD_BD9571MWV) += bd9571mwv.o obj-$(CONFIG_MFD_CROS_EC_DEV) += cros_ec_dev.o +obj-$(CONFIG_MFD_CS40L50_CORE) += cs40l50-core.o +obj-$(CONFIG_MFD_CS40L50_I2C) += cs40l50-i2c.o +obj-$(CONFIG_MFD_CS40L50_SPI) += cs40l50-spi.o obj-$(CONFIG_MFD_CS42L43) += cs42l43.o obj-$(CONFIG_MFD_CS42L43_I2C) += cs42l43-i2c.o obj-$(CONFIG_MFD_CS42L43_SDW) += cs42l43-sdw.o diff --git a/drivers/mfd/cs40l50-core.c b/drivers/mfd/cs40l50-core.c new file mode 100644 index 000000000000..22c16a273b7c --- /dev/null +++ b/drivers/mfd/cs40l50-core.c @@ -0,0 +1,537 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CS40L50 Advanced Haptic Driver with waveform memory, + * integrated DSP, and closed-loop algorithms + * + * Copyright 2024 Cirrus Logic, Inc. + * + * Author: James Ogletree + */ + +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell cs40l50_devs[] = { + { .name = "cs40l50-codec", }, + { .name = "cs40l50-vibra", }, +}; + +const struct regmap_config cs40l50_regmap = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, +}; +EXPORT_SYMBOL_GPL(cs40l50_regmap); + +static const char * const cs40l50_supplies[] = { + "vp", "vio", +}; + +static const struct regmap_irq cs40l50_reg_irqs[] = { + REGMAP_IRQ_REG(CS40L50_DSP_QUEUE_IRQ, CS40L50_IRQ1_INT_2_OFFSET, + CS40L50_DSP_QUEUE_MASK), + REGMAP_IRQ_REG(CS40L50_AMP_SHORT_IRQ, CS40L50_IRQ1_INT_1_OFFSET, + CS40L50_AMP_SHORT_MASK), + REGMAP_IRQ_REG(CS40L50_TEMP_ERR_IRQ, CS40L50_IRQ1_INT_8_OFFSET, + CS40L50_TEMP_ERR_MASK), + REGMAP_IRQ_REG(CS40L50_BST_UVP_IRQ, CS40L50_IRQ1_INT_9_OFFSET, + CS40L50_BST_UVP_MASK), + REGMAP_IRQ_REG(CS40L50_BST_SHORT_IRQ, CS40L50_IRQ1_INT_9_OFFSET, + CS40L50_BST_SHORT_MASK), + REGMAP_IRQ_REG(CS40L50_BST_ILIMIT_IRQ, CS40L50_IRQ1_INT_9_OFFSET, + CS40L50_BST_ILIMIT_MASK), + REGMAP_IRQ_REG(CS40L50_UVLO_VDDBATT_IRQ, CS40L50_IRQ1_INT_10_OFFSET, + CS40L50_UVLO_VDDBATT_MASK), + REGMAP_IRQ_REG(CS40L50_GLOBAL_ERROR_IRQ, CS40L50_IRQ1_INT_18_OFFSET, + CS40L50_GLOBAL_ERROR_MASK), +}; + +static struct regmap_irq_chip cs40l50_irq_chip = { + .name = "CS40L50 IRQ Controller", + + .status_base = CS40L50_IRQ1_INT_1, + .mask_base = CS40L50_IRQ1_MASK_1, + .ack_base = CS40L50_IRQ1_INT_1, + .num_regs = 22, + + .irqs = cs40l50_reg_irqs, + .num_irqs = ARRAY_SIZE(cs40l50_reg_irqs), + + .runtime_pm = true, +}; + +int cs40l50_dsp_write(struct device *dev, struct regmap *regmap, u32 val) +{ + int err, i; + u32 ack; + + /* Device NAKs if exiting hibernation, so optionally retry here */ + for (i = 0; i < CS40L50_DSP_TIMEOUT_COUNT; i++) { + err = regmap_write(regmap, CS40L50_DSP_QUEUE, val); + if (!err) + break; + + usleep_range(CS40L50_DSP_POLL_US, CS40L50_DSP_POLL_US + 100); + } + + /* If we never wrote, don't bother checking for ACK */ + if (i == CS40L50_DSP_TIMEOUT_COUNT) { + dev_err(dev, "Timed out writing %#X to DSP: %d\n", val, err); + return err; + } + + err = regmap_read_poll_timeout(regmap, CS40L50_DSP_QUEUE, ack, !ack, + CS40L50_DSP_POLL_US, + CS40L50_DSP_POLL_US * CS40L50_DSP_TIMEOUT_COUNT); + if (err) + dev_err(dev, "DSP did not ack %#X: %d\n", val, err); + + return err; +} +EXPORT_SYMBOL_GPL(cs40l50_dsp_write); + +static const struct cs_dsp_region cs40l50_dsp_regions[] = { + { .type = WMFW_HALO_PM_PACKED, .base = CS40L50_PMEM_0 }, + { .type = WMFW_HALO_XM_PACKED, .base = CS40L50_XMEM_PACKED_0 }, + { .type = WMFW_HALO_YM_PACKED, .base = CS40L50_YMEM_PACKED_0 }, + { .type = WMFW_ADSP2_XM, .base = CS40L50_XMEM_UNPACKED24_0 }, + { .type = WMFW_ADSP2_YM, .base = CS40L50_YMEM_UNPACKED24_0 }, +}; + +static void cs40l50_dsp_remove(void *data) +{ + cs_dsp_remove((struct cs_dsp *)data); +} + +static const struct cs_dsp_client_ops cs40l50_client_ops; + +static int cs40l50_dsp_init(struct cs40l50 *cs40l50) +{ + int err; + + cs40l50->dsp.num = 1; + cs40l50->dsp.type = WMFW_HALO; + cs40l50->dsp.dev = cs40l50->dev; + cs40l50->dsp.regmap = cs40l50->regmap; + cs40l50->dsp.base = CS40L50_CORE_BASE; + cs40l50->dsp.base_sysinfo = CS40L50_SYS_INFO_ID; + cs40l50->dsp.mem = cs40l50_dsp_regions; + cs40l50->dsp.num_mems = ARRAY_SIZE(cs40l50_dsp_regions); + cs40l50->dsp.no_core_startstop = true; + cs40l50->dsp.client_ops = &cs40l50_client_ops; + + err = cs_dsp_halo_init(&cs40l50->dsp); + if (err) + return err; + + return devm_add_action_or_reset(cs40l50->dev, cs40l50_dsp_remove, + &cs40l50->dsp); +} + +struct cs40l50_irq { + const char *name; + int virq; +}; + +static struct cs40l50_irq cs40l50_irqs[] = { + { "DSP", }, + { "Global", }, + { "Boost UVLO", }, + { "Boost current limit", }, + { "Boost short", }, + { "Boost undervolt", }, + { "Overtemp", }, + { "Amp short", }, +}; + +static const struct reg_sequence cs40l50_err_rls[] = { + { CS40L50_ERR_RLS, CS40L50_GLOBAL_ERR_RLS_SET }, + { CS40L50_ERR_RLS, CS40L50_GLOBAL_ERR_RLS_CLEAR }, +}; + +static irqreturn_t cs40l50_hw_err(int irq, void *data) +{ + struct cs40l50 *cs40l50 = data; + int err = 0, i; + + mutex_lock(&cs40l50->lock); + + /* Log hardware interrupt and execute error release sequence */ + for (i = 1; i < ARRAY_SIZE(cs40l50_irqs); i++) { + if (cs40l50_irqs[i].virq == irq) { + dev_err(cs40l50->dev, "%s error\n", cs40l50_irqs[i].name); + err = regmap_multi_reg_write(cs40l50->regmap, cs40l50_err_rls, + ARRAY_SIZE(cs40l50_err_rls)); + goto exit; + } + } +exit: + mutex_unlock(&cs40l50->lock); + return IRQ_RETVAL(!err); +} + +static irqreturn_t cs40l50_dsp_queue(int irq, void *data) +{ + struct cs40l50 *cs40l50 = data; + u32 rd_ptr, val, wt_ptr; + int err = 0; + + mutex_lock(&cs40l50->lock); + + /* Read from DSP queue and update read pointer */ + while (!err) { + err = regmap_read(cs40l50->regmap, CS40L50_DSP_QUEUE_WT, &wt_ptr); + if (err) + goto exit; + + err = regmap_read(cs40l50->regmap, CS40L50_DSP_QUEUE_RD, &rd_ptr); + if (err) + goto exit; + + /* Check if queue is empty */ + if (wt_ptr == rd_ptr) + goto exit; + + err = regmap_read(cs40l50->regmap, rd_ptr, &val); + if (err) + goto exit; + + dev_dbg(cs40l50->dev, "DSP payload: %#X", val); + + rd_ptr += sizeof(u32); + + if (rd_ptr > CS40L50_DSP_QUEUE_END) + rd_ptr = CS40L50_DSP_QUEUE_BASE; + + err = regmap_write(cs40l50->regmap, CS40L50_DSP_QUEUE_RD, rd_ptr); + if (err) + goto exit; + } +exit: + mutex_unlock(&cs40l50->lock); + + return IRQ_RETVAL(!err); +} + +static int cs40l50_irq_init(struct cs40l50 *cs40l50) +{ + struct device *dev = cs40l50->dev; + int err, i, virq; + + err = devm_regmap_add_irq_chip(dev, cs40l50->regmap, cs40l50->irq, + IRQF_ONESHOT | IRQF_SHARED, 0, + &cs40l50_irq_chip, &cs40l50->irq_data); + if (err) { + dev_err(dev, "Failed adding IRQ chip\n"); + return err; + } + + for (i = 0; i < ARRAY_SIZE(cs40l50_irqs); i++) { + virq = regmap_irq_get_virq(cs40l50->irq_data, i); + if (virq < 0) { + dev_err(dev, "Failed getting %s\n", cs40l50_irqs[i].name); + return virq; + } + + cs40l50_irqs[i].virq = virq; + + /* Handle DSP and non-DSP interrupts separately */ + err = devm_request_threaded_irq(dev, virq, NULL, + i ? cs40l50_hw_err : cs40l50_dsp_queue, + IRQF_ONESHOT | IRQF_SHARED, + cs40l50_irqs[i].name, cs40l50); + if (err) { + dev_err(dev, "Failed requesting %s IRQ\n", cs40l50_irqs[i].name); + return err; + } + } + + return 0; +} + +static const struct reg_sequence cs40l50_stop_core[] = { + { CS40L50_CCM_CORE_CONTROL, CS40L50_CLOCK_DISABLE}, + { CS40L50_RAM_INIT, CS40L50_RAM_INIT_FLAG}, + { CS40L50_PWRMGT_CTL, CS40L50_MEM_RDY_HW}, +}; + +static const struct reg_sequence cs40l50_internal_vamp_config[] = { + { CS40L50_BST_LPMODE_SEL, CS40L50_DCM_LOW_POWER }, + { CS40L50_BLOCK_ENABLES2, CS40L50_OVERTEMP_WARN }, +}; + +static const struct reg_sequence cs40l50_irq_mask_override[] = { + { CS40L50_IRQ1_MASK_2, CS40L50_IRQ_MASK_2_OVERRIDE }, + { CS40L50_IRQ1_MASK_20, CS40L50_IRQ_MASK_20_OVERRIDE }, +}; + +static void cs40l50_dsp_power_down(void *data) +{ + cs_dsp_power_down((struct cs_dsp *)data); +} + +static int cs40l50_power_up_dsp(struct cs40l50 *cs40l50) +{ + int err; + + mutex_lock(&cs40l50->lock); + + /* Stop and resume core to load patch file */ + err = regmap_multi_reg_write(cs40l50->regmap, cs40l50_stop_core, + ARRAY_SIZE(cs40l50_stop_core)); + if (err) + goto err_mutex; + + err = cs_dsp_power_up(&cs40l50->dsp, cs40l50->patch, "cs40l50.wmfw", + cs40l50->bin, "cs40l50.bin", "cs40l50"); + if (err) + goto err_mutex; + + err = devm_add_action_or_reset(cs40l50->dev, cs40l50_dsp_power_down, + &cs40l50->dsp); + if (err) + goto err_mutex; + + err = regmap_write(cs40l50->regmap, CS40L50_CCM_CORE_CONTROL, + CS40L50_CLOCK_ENABLE); + +err_mutex: + mutex_unlock(&cs40l50->lock); + + return err; +} + +static struct cs_dsp_wseq cs40l50_wseqs[] = { + { "PM_PWR_ON_SEQ" }, +}; + +static int cs40l50_configure_dsp(struct cs40l50 *cs40l50) +{ + u32 nwaves; + int err, i; + + if (cs40l50->bin) { + /* Log number of effects if wavetable was loaded */ + err = regmap_read(cs40l50->regmap, CS40L50_NUM_WAVES, &nwaves); + if (err) + return err; + + dev_info(cs40l50->dev, "Loaded with %u effects\n", nwaves); + } + + for (i = 0; i < ARRAY_SIZE(cs40l50_wseqs); i++) { + mutex_lock(&cs40l50->dsp.pwr_lock); + cs40l50_wseqs[i].ctl = cs_dsp_get_ctl(&cs40l50->dsp, + cs40l50_wseqs[i].name, + WMFW_ADSP2_XM, + CS40L50_PM_ALGO_ID); + mutex_unlock(&cs40l50->dsp.pwr_lock); + if (!cs40l50_wseqs[i].ctl) { + dev_err(cs40l50->dev, "No control: %s\n", cs40l50_wseqs[i].name); + return -ENOENT; + } + } + + err = cs_dsp_wseq_init(&cs40l50->dsp, cs40l50_wseqs, + ARRAY_SIZE(cs40l50_wseqs)); + if (err) { + dev_err(cs40l50->dev, "Failed to initialize write sequences\n"); + return err; + } + + /* Use internal V_AMP supply */ + err = regmap_multi_reg_write(cs40l50->regmap, cs40l50_internal_vamp_config, + ARRAY_SIZE(cs40l50_internal_vamp_config)); + if (err) + return err; + + err = cs_dsp_wseq_multi_write(&cs40l50->dsp, &cs40l50_wseqs[0], + cs40l50_internal_vamp_config, CS_DSP_WSEQ_FULL, + ARRAY_SIZE(cs40l50_internal_vamp_config), false); + if (err) + return err; + + /* Override firmware defaults for IRQ masks */ + err = regmap_multi_reg_write(cs40l50->regmap, cs40l50_irq_mask_override, + ARRAY_SIZE(cs40l50_irq_mask_override)); + if (err) + return err; + + return cs_dsp_wseq_multi_write(&cs40l50->dsp, &cs40l50_wseqs[0], + cs40l50_irq_mask_override, CS_DSP_WSEQ_FULL, + ARRAY_SIZE(cs40l50_irq_mask_override), false); +} + +static void cs40l50_start_dsp(const struct firmware *bin, void *context) +{ + struct cs40l50 *cs40l50 = context; + int err; + + /* Wavetable is optional; power up DSP regardless */ + cs40l50->bin = bin; + + err = cs40l50_power_up_dsp(cs40l50); + if (err) { + dev_err(cs40l50->dev, "Failed to power up DSP: %d\n", err); + goto err_fw; + } + + err = cs40l50_configure_dsp(cs40l50); + if (err) + dev_err(cs40l50->dev, "Failed to configure DSP: %d\n", err); + + err = devm_mfd_add_devices(cs40l50->dev, PLATFORM_DEVID_NONE, cs40l50_devs, + ARRAY_SIZE(cs40l50_devs), NULL, 0, NULL); + if (err) + dev_err(cs40l50->dev, "Failed to add sub devices: %d\n", err); + +err_fw: + release_firmware(cs40l50->bin); + release_firmware(cs40l50->patch); +} + +static void cs40l50_request_patch(const struct firmware *patch, void *context) +{ + struct cs40l50 *cs40l50 = context; + + if (!patch) { + dev_err(cs40l50->dev, "Failed to request patch file\n"); + return; + } + + cs40l50->patch = patch; + + if (request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, CS40L50_WT, + cs40l50->dev, GFP_KERNEL, cs40l50, + cs40l50_start_dsp)) { + dev_err(cs40l50->dev, "Failed to request %s\n", CS40L50_WT); + release_firmware(cs40l50->patch); + } +} + +static int cs40l50_get_model(struct cs40l50 *cs40l50) +{ + int err; + + err = regmap_read(cs40l50->regmap, CS40L50_DEVID, &cs40l50->devid); + if (err) + return err; + + if (cs40l50->devid != CS40L50_DEVID_A) + return -EINVAL; + + err = regmap_read(cs40l50->regmap, CS40L50_REVID, &cs40l50->revid); + if (err) + return err; + + if (cs40l50->revid < CS40L50_REVID_B0) + return -EINVAL; + + dev_info(cs40l50->dev, "Cirrus Logic CS40L50 rev. %02X\n", cs40l50->revid); + + return 0; +} + +static int cs40l50_pm_runtime_setup(struct device *dev) +{ + int err; + + pm_runtime_set_autosuspend_delay(dev, CS40L50_AUTOSUSPEND_MS); + pm_runtime_use_autosuspend(dev); + pm_runtime_get_noresume(dev); + err = pm_runtime_set_active(dev); + if (err) + return err; + + return devm_pm_runtime_enable(dev); +} + +int cs40l50_probe(struct cs40l50 *cs40l50) +{ + struct device *dev = cs40l50->dev; + int err; + + mutex_init(&cs40l50->lock); + + cs40l50->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(cs40l50->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(cs40l50->reset_gpio), + "Failed getting reset GPIO\n"); + + err = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(cs40l50_supplies), + cs40l50_supplies); + if (err) + return dev_err_probe(dev, err, "Failed getting supplies\n"); + + /* Ensure minimum reset pulse width */ + usleep_range(CS40L50_RESET_PULSE_US, CS40L50_RESET_PULSE_US + 100); + + gpiod_set_value_cansleep(cs40l50->reset_gpio, 0); + + /* Wait for control port to be ready */ + usleep_range(CS40L50_CP_READY_US, CS40L50_CP_READY_US + 100); + + err = cs40l50_dsp_init(cs40l50); + if (err) + return dev_err_probe(dev, err, "Failed to initialize DSP\n"); + + err = cs40l50_pm_runtime_setup(dev); + if (err) + return dev_err_probe(dev, err, "Failed to initialize runtime PM\n"); + + err = cs40l50_get_model(cs40l50); + if (err) + return dev_err_probe(dev, err, "Failed to get part number\n"); + + err = cs40l50_irq_init(cs40l50); + if (err) + return dev_err_probe(dev, err, "Failed to request IRQs\n"); + + err = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, CS40L50_FW, + dev, GFP_KERNEL, cs40l50, cs40l50_request_patch); + if (err) + return dev_err_probe(dev, err, "Failed to request %s\n", CS40L50_FW); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; +} +EXPORT_SYMBOL_GPL(cs40l50_probe); + +int cs40l50_remove(struct cs40l50 *cs40l50) +{ + gpiod_set_value_cansleep(cs40l50->reset_gpio, 1); + + return 0; +} +EXPORT_SYMBOL_GPL(cs40l50_remove); + +static int cs40l50_runtime_suspend(struct device *dev) +{ + struct cs40l50 *cs40l50 = dev_get_drvdata(dev); + + return regmap_write(cs40l50->regmap, CS40L50_DSP_QUEUE, CS40L50_ALLOW_HIBER); +} + +static int cs40l50_runtime_resume(struct device *dev) +{ + struct cs40l50 *cs40l50 = dev_get_drvdata(dev); + + return cs40l50_dsp_write(dev, cs40l50->regmap, CS40L50_PREVENT_HIBER); +} + +EXPORT_GPL_DEV_PM_OPS(cs40l50_pm_ops) = { + RUNTIME_PM_OPS(cs40l50_runtime_suspend, cs40l50_runtime_resume, NULL) +}; + +MODULE_DESCRIPTION("CS40L50 Advanced Haptic Driver"); +MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(FW_CS_DSP); diff --git a/drivers/mfd/cs40l50-i2c.c b/drivers/mfd/cs40l50-i2c.c new file mode 100644 index 000000000000..e18938dbddaa --- /dev/null +++ b/drivers/mfd/cs40l50-i2c.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CS40L50 Advanced Haptic Driver with waveform memory, + * integrated DSP, and closed-loop algorithms + * + * Copyright 2024 Cirrus Logic, Inc. + * + * Author: James Ogletree + */ + +#include +#include + +static int cs40l50_i2c_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct cs40l50 *cs40l50; + + cs40l50 = devm_kzalloc(dev, sizeof(*cs40l50), GFP_KERNEL); + if (!cs40l50) + return -ENOMEM; + + i2c_set_clientdata(client, cs40l50); + + cs40l50->regmap = devm_regmap_init_i2c(client, &cs40l50_regmap); + if (IS_ERR(cs40l50->regmap)) + return dev_err_probe(cs40l50->dev, PTR_ERR(cs40l50->regmap), + "Failed to initialize register map\n"); + + cs40l50->dev = dev; + cs40l50->irq = client->irq; + + return cs40l50_probe(cs40l50); +} + +static void cs40l50_i2c_remove(struct i2c_client *client) +{ + struct cs40l50 *cs40l50 = i2c_get_clientdata(client); + + cs40l50_remove(cs40l50); +} + +static const struct i2c_device_id cs40l50_id_i2c[] = { + {"cs40l50"}, + {} +}; +MODULE_DEVICE_TABLE(i2c, cs40l50_id_i2c); + +static const struct of_device_id cs40l50_of_match[] = { + { .compatible = "cirrus,cs40l50" }, + {} +}; +MODULE_DEVICE_TABLE(of, cs40l50_of_match); + +static struct i2c_driver cs40l50_i2c_driver = { + .driver = { + .name = "cs40l50", + .of_match_table = cs40l50_of_match, + .pm = pm_ptr(&cs40l50_pm_ops), + }, + .id_table = cs40l50_id_i2c, + .probe = cs40l50_i2c_probe, + .remove = cs40l50_i2c_remove, +}; +module_i2c_driver(cs40l50_i2c_driver); + +MODULE_DESCRIPTION("CS40L50 I2C Driver"); +MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. "); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/cs40l50-spi.c b/drivers/mfd/cs40l50-spi.c new file mode 100644 index 000000000000..9e18bb74eae0 --- /dev/null +++ b/drivers/mfd/cs40l50-spi.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CS40L50 Advanced Haptic Driver with waveform memory, + * integrated DSP, and closed-loop algorithms + * + * Copyright 2024 Cirrus Logic, Inc. + * + * Author: James Ogletree + */ + +#include +#include + +static int cs40l50_spi_probe(struct spi_device *spi) +{ + struct cs40l50 *cs40l50; + struct device *dev = &spi->dev; + + cs40l50 = devm_kzalloc(dev, sizeof(*cs40l50), GFP_KERNEL); + if (!cs40l50) + return -ENOMEM; + + spi_set_drvdata(spi, cs40l50); + + cs40l50->regmap = devm_regmap_init_spi(spi, &cs40l50_regmap); + if (IS_ERR(cs40l50->regmap)) + return dev_err_probe(cs40l50->dev, PTR_ERR(cs40l50->regmap), + "Failed to initialize register map\n"); + + cs40l50->dev = dev; + cs40l50->irq = spi->irq; + + return cs40l50_probe(cs40l50); +} + +static void cs40l50_spi_remove(struct spi_device *spi) +{ + struct cs40l50 *cs40l50 = spi_get_drvdata(spi); + + cs40l50_remove(cs40l50); +} + +static const struct spi_device_id cs40l50_id_spi[] = { + {"cs40l50"}, + {} +}; +MODULE_DEVICE_TABLE(spi, cs40l50_id_spi); + +static const struct of_device_id cs40l50_of_match[] = { + { .compatible = "cirrus,cs40l50" }, + {} +}; +MODULE_DEVICE_TABLE(of, cs40l50_of_match); + +static struct spi_driver cs40l50_spi_driver = { + .driver = { + .name = "cs40l50", + .of_match_table = cs40l50_of_match, + .pm = pm_ptr(&cs40l50_pm_ops), + }, + .id_table = cs40l50_id_spi, + .probe = cs40l50_spi_probe, + .remove = cs40l50_spi_remove, +}; +module_spi_driver(cs40l50_spi_driver); + +MODULE_DESCRIPTION("CS40L50 SPI Driver"); +MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/cs40l50.h b/include/linux/mfd/cs40l50.h new file mode 100644 index 000000000000..0e6240df6d1c --- /dev/null +++ b/include/linux/mfd/cs40l50.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * CS40L50 Advanced Haptic Driver with waveform memory, + * integrated DSP, and closed-loop algorithms + * + * Copyright 2024 Cirrus Logic, Inc. + * + * Author: James Ogletree + */ + +#ifndef __CS40L50_H__ +#define __CS40L50_H__ + +#include +#include +#include +#include + +/* Power Supply Configuration */ +#define CS40L50_BLOCK_ENABLES2 0x201C +#define CS40L50_ERR_RLS 0x2034 +#define CS40L50_PWRMGT_CTL 0x2900 +#define CS40L50_BST_LPMODE_SEL 0x3810 +#define CS40L50_DCM_LOW_POWER 0x1 +#define CS40L50_OVERTEMP_WARN 0x4000010 + +/* Interrupts */ +#define CS40L50_IRQ1_INT_1 0xE010 +#define CS40L50_IRQ1_BASE CS40L50_IRQ1_INT_1 +#define CS40L50_IRQ1_INT_2 0xE014 +#define CS40L50_IRQ1_INT_8 0xE02C +#define CS40L50_IRQ1_INT_9 0xE030 +#define CS40L50_IRQ1_INT_10 0xE034 +#define CS40L50_IRQ1_INT_18 0xE054 +#define CS40L50_IRQ1_MASK_1 0xE090 +#define CS40L50_IRQ1_MASK_2 0xE094 +#define CS40L50_IRQ1_MASK_20 0xE0DC +#define CS40L50_IRQ1_INT_1_OFFSET (CS40L50_IRQ1_INT_1 - CS40L50_IRQ1_BASE) +#define CS40L50_IRQ1_INT_2_OFFSET (CS40L50_IRQ1_INT_2 - CS40L50_IRQ1_BASE) +#define CS40L50_IRQ1_INT_8_OFFSET (CS40L50_IRQ1_INT_8 - CS40L50_IRQ1_BASE) +#define CS40L50_IRQ1_INT_9_OFFSET (CS40L50_IRQ1_INT_9 - CS40L50_IRQ1_BASE) +#define CS40L50_IRQ1_INT_10_OFFSET (CS40L50_IRQ1_INT_10 - CS40L50_IRQ1_BASE) +#define CS40L50_IRQ1_INT_18_OFFSET (CS40L50_IRQ1_INT_18 - CS40L50_IRQ1_BASE) +#define CS40L50_IRQ_MASK_2_OVERRIDE 0xFFDF7FFF +#define CS40L50_IRQ_MASK_20_OVERRIDE 0x15C01000 +#define CS40L50_AMP_SHORT_MASK BIT(31) +#define CS40L50_DSP_QUEUE_MASK BIT(21) +#define CS40L50_TEMP_ERR_MASK BIT(31) +#define CS40L50_BST_UVP_MASK BIT(6) +#define CS40L50_BST_SHORT_MASK BIT(7) +#define CS40L50_BST_ILIMIT_MASK BIT(18) +#define CS40L50_UVLO_VDDBATT_MASK BIT(16) +#define CS40L50_GLOBAL_ERROR_MASK BIT(15) + +enum cs40l50_irq_list { + CS40L50_DSP_QUEUE_IRQ, + CS40L50_GLOBAL_ERROR_IRQ, + CS40L50_UVLO_VDDBATT_IRQ, + CS40L50_BST_ILIMIT_IRQ, + CS40L50_BST_SHORT_IRQ, + CS40L50_BST_UVP_IRQ, + CS40L50_TEMP_ERR_IRQ, + CS40L50_AMP_SHORT_IRQ, +}; + +/* DSP */ +#define CS40L50_XMEM_PACKED_0 0x2000000 +#define CS40L50_XMEM_UNPACKED24_0 0x2800000 +#define CS40L50_SYS_INFO_ID 0x25E0000 +#define CS40L50_RAM_INIT 0x28021DC +#define CS40L50_DSP_QUEUE_WT 0x28042C8 +#define CS40L50_DSP_QUEUE_RD 0x28042CC +#define CS40L50_NUM_WAVES 0x2805C18 +#define CS40L50_CORE_BASE 0x2B80000 +#define CS40L50_CCM_CORE_CONTROL 0x2BC1000 +#define CS40L50_YMEM_PACKED_0 0x2C00000 +#define CS40L50_YMEM_UNPACKED24_0 0x3400000 +#define CS40L50_PMEM_0 0x3800000 +#define CS40L50_MEM_RDY_HW 0x2 +#define CS40L50_RAM_INIT_FLAG 0x1 +#define CS40L50_CLOCK_DISABLE 0x80 +#define CS40L50_CLOCK_ENABLE 0x281 +#define CS40L50_DSP_POLL_US 1000 +#define CS40L50_DSP_TIMEOUT_COUNT 100 +#define CS40L50_RESET_PULSE_US 2200 +#define CS40L50_CP_READY_US 3100 +#define CS40L50_AUTOSUSPEND_MS 2000 +#define CS40L50_PM_ALGO_ID 0x9F206 +#define CS40L50_GLOBAL_ERR_RLS_SET BIT(11) +#define CS40L50_GLOBAL_ERR_RLS_CLEAR 0 + +/* DSP Commands */ +#define CS40L50_DSP_QUEUE_BASE 0x11004 +#define CS40L50_DSP_QUEUE_END 0x1101C +#define CS40L50_DSP_QUEUE 0x11020 +#define CS40L50_PREVENT_HIBER 0x2000003 +#define CS40L50_ALLOW_HIBER 0x2000004 +#define CS40L50_START_I2S 0x3000002 +#define CS40L50_OWT_PUSH 0x3000008 +#define CS40L50_STOP_PLAYBACK 0x5000000 +#define CS40L50_OWT_DELETE 0xD000000 + +/* Firmware files */ +#define CS40L50_FW "cs40l50.wmfw" +#define CS40L50_WT "cs40l50.bin" + +/* Device */ +#define CS40L50_DEVID 0x0 +#define CS40L50_REVID 0x4 +#define CS40L50_DEVID_A 0x40A50 +#define CS40L50_REVID_B0 0xB0 + +struct cs40l50 { + struct device *dev; + struct regmap *regmap; + struct mutex lock; + struct cs_dsp dsp; + struct gpio_desc *reset_gpio; + struct regmap_irq_chip_data *irq_data; + const struct firmware *patch; + const struct firmware *bin; + int irq; + u32 devid; + u32 revid; +}; + +int cs40l50_dsp_write(struct device *dev, struct regmap *regmap, u32 val); +int cs40l50_probe(struct cs40l50 *cs40l50); +int cs40l50_remove(struct cs40l50 *cs40l50); + +extern const struct regmap_config cs40l50_regmap; +extern const struct dev_pm_ops cs40l50_pm_ops; + +#endif /* __CS40L50_H__ */ From patchwork Wed Feb 7 00:36:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Ogletree X-Patchwork-Id: 13547949 Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37AB67F9; Wed, 7 Feb 2024 00:37:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.149.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266224; cv=none; b=sbRtdFwOE07XqOa4QvJURj8wv3Od/IprtJjcZzpeiVP2I+G4p7aIJi2Ret2cYFEPc4dJYmoCM7xobo87gizsbm9+XLmMlDnA5iOwGG/rZE/xEY+rliPiXoK9oSe6ctQY3bX2iNT9vPcoM52+ELBRSLEjLnEodcyqP2vGCPTWrmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266224; c=relaxed/simple; bh=7y/4ViLPRGYrOSjsVVRy5ZBw28bs66ApuJPZ44shogQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BOxEv+CTSQLdNbj7NdMEvDx7rINUsLqgdsYO1ynfceJ926NiHkF5+NaxWeXop4z5uxTe6/LuuRV0Iyp+LSLflZPtyh8QE/r8h4AmxTczIheEtEo4Emy9k/khRy10uJ37a5xZTRyoXYC7C5aJQz8gesNdfvPWQ7VL89rsyJwETso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com; spf=pass smtp.mailfrom=opensource.cirrus.com; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b=RqIZr1pi; arc=none smtp.client-ip=67.231.149.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="RqIZr1pi" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 416AS7SJ031521; Tue, 6 Feb 2024 18:36:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= PODMain02222019; bh=r8SgbSU5Bb16oL6hwjfXq9bAlM6A6aG75rHFr3z9GMk=; b= RqIZr1pi9Jaf81mKDNVOPjfi05wi4uz7Lizs6GxlIqqZe0q0d10QoQ/ppESa0vst b4BifBn1wWx7u8WgG55gVj/u+J0DmBshxrJa15CKSYbqUsgYH4LSUdePX877RdYf DsFn7AFzn8VPNTttBj4c+yHzKKufr1sYmZolnvLUmw4ebs/udERp0/v2l11dxwzu u3OveVj2UKXbfQLeS+o5pbQTi21ldORRDRZ3u8Dqr45i2WWbCvXbjFFOsljg6ToP dL0vSigx5mRSeysD34XlzDDap1aZR/j7fhMgvCSMQ+hYI0vcRYmkpqkayHPb16ai ZNazu1Bc5ytXqjIS955VTA== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3w1ks2cbgh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 18:36:54 -0600 (CST) Received: from ediex01.ad.cirrus.com (198.61.84.80) by ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 7 Feb 2024 00:36:51 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40 via Frontend Transport; Wed, 7 Feb 2024 00:36:51 +0000 Received: from aus-sw-rshr002.ad.cirrus.com (aus-sw-rshr002.ad.cirrus.com [141.131.145.53]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTP id 3DE8A820247; Wed, 7 Feb 2024 00:36:50 +0000 (UTC) From: James Ogletree To: , , , , , , CC: , , , , James Ogletree Subject: [PATCH v6 4/5] Input: cs40l50 - Add support for the CS40L50 haptic driver Date: Wed, 7 Feb 2024 00:36:11 +0000 Message-ID: <20240207003612.4187370-5-jogletre@opensource.cirrus.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> References: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: W3k3SO7VX5shIGXYiVyVeRVvIPn7OGNq X-Proofpoint-ORIG-GUID: W3k3SO7VX5shIGXYiVyVeRVvIPn7OGNq X-Proofpoint-Spam-Reason: safe Introduce support for Cirrus Logic Device CS40L50: a haptic driver with waveform memory, integrated DSP, and closed-loop algorithms. The input driver provides the interface for control of haptic effects through the device. Signed-off-by: James Ogletree --- v6: Please advise if playback stop is still misused with respect to not specifying an effect, and if so what the best solution would be. The device can only play one effect at a time, but setting max effects for the EVIOCGEFFECTS ioctl to 1 would restrict the number of uploads to 1 as well. Is there an alternative solution here? And please correct my wrong assumptions if there are any. MAINTAINERS | 1 + drivers/input/misc/Kconfig | 10 + drivers/input/misc/Makefile | 1 + drivers/input/misc/cs40l50-vibra.c | 571 +++++++++++++++++++++++++++++ 4 files changed, 583 insertions(+) create mode 100644 drivers/input/misc/cs40l50-vibra.c diff --git a/MAINTAINERS b/MAINTAINERS index 69a9e0a3b968..24cfb4f017bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4940,6 +4940,7 @@ M: Ben Bright L: patches@opensource.cirrus.com S: Supported F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml +F: drivers/input/misc/cs40l* F: drivers/mfd/cs40l* F: include/linux/mfd/cs40l* diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 6ba984d7f0b1..ee45dbb0636e 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -140,6 +140,16 @@ config INPUT_BMA150 To compile this driver as a module, choose M here: the module will be called bma150. +config INPUT_CS40L50_VIBRA + tristate "CS40L50 Haptic Driver support" + depends on MFD_CS40L50_CORE + help + Say Y here to enable support for Cirrus Logic's CS40L50 + haptic driver. + + To compile this driver as a module, choose M here: the + module will be called cs40l50-vibra. + config INPUT_E3X0_BUTTON tristate "NI Ettus Research USRP E3xx Button support." default n diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 04296a4abe8e..88279de6d3d5 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_INPUT_CMA3000) += cma3000_d0x.o obj-$(CONFIG_INPUT_CMA3000_I2C) += cma3000_d0x_i2c.o obj-$(CONFIG_INPUT_COBALT_BTNS) += cobalt_btns.o obj-$(CONFIG_INPUT_CPCAP_PWRBUTTON) += cpcap-pwrbutton.o +obj-$(CONFIG_INPUT_CS40L50_VIBRA) += cs40l50-vibra.o obj-$(CONFIG_INPUT_DA7280_HAPTICS) += da7280.o obj-$(CONFIG_INPUT_DA9052_ONKEY) += da9052_onkey.o obj-$(CONFIG_INPUT_DA9055_ONKEY) += da9055_onkey.o diff --git a/drivers/input/misc/cs40l50-vibra.c b/drivers/input/misc/cs40l50-vibra.c new file mode 100644 index 000000000000..9089b90c31a9 --- /dev/null +++ b/drivers/input/misc/cs40l50-vibra.c @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CS40L50 Advanced Haptic Driver with waveform memory, + * integrated DSP, and closed-loop algorithms + * + * Copyright 2024 Cirrus Logic, Inc. + * + * Author: James Ogletree + */ + +#include +#include +#include +#include +#include + +/* Wavetables */ +#define CS40L50_RAM_INDEX_START 0x1000000 +#define CS40L50_RAM_INDEX_END 0x100007F +#define CS40L50_RTH_INDEX_START 0x1400000 +#define CS40L50_RTH_INDEX_END 0x1400001 +#define CS40L50_ROM_INDEX_START 0x1800000 +#define CS40L50_ROM_INDEX_END 0x180001A +#define CS40L50_TYPE_PCM 8 +#define CS40L50_TYPE_PWLE 12 +#define CS40L50_PCM_ID 0x0 +#define CS40L50_OWT_CUSTOM_DATA_SIZE 2 + +/* DSP */ +#define CS40L50_GPIO_BASE 0x2804140 +#define CS40L50_OWT_BASE 0x2805C34 +#define CS40L50_OWT_SIZE 0x2805C38 +#define CS40L50_OWT_NEXT 0x2805C3C + +/* GPIO */ +#define CS40L50_GPIO_NUM_MASK GENMASK(14, 12) +#define CS40L50_GPIO_EDGE_MASK BIT(15) +#define CS40L50_GPIO_MAPPING_NONE 0 +#define CS40L50_GPIO_DISABLE 0x1FF + +enum vibra_bank_type { + WVFRM_BANK_RAM, + WVFRM_BANK_ROM, + WVFRM_BANK_OWT, + WVFRM_BANK_NUM, +}; + +/* Describes an area in DSP memory populated by effects */ +struct vibra_bank { + enum vibra_bank_type bank; + u32 base_index; + u32 max_index; +}; + +struct vibra_effect { + enum vibra_bank_type bank; + struct list_head list; + u32 gpio_reg; + u32 index; + int id; +}; + +/* Describes haptic interface of loaded DSP firmware */ +struct vibra_dsp { + struct vibra_bank *banks; + u32 gpio_base_reg; + u32 owt_offset_reg; + u32 owt_size_reg; + u32 owt_base_reg; + int (*write)(struct device *dev, struct regmap *regmap, u32 val); + u32 push_owt_cmd; + u32 delete_owt_cmd; + u32 stop_cmd; +}; + +/* Describes configuration and state of haptic operations */ +struct vibra_info { + struct device *dev; + struct regmap *regmap; + struct input_dev *input; + struct mutex lock; + struct workqueue_struct *vibe_wq; + struct list_head effect_head; + struct vibra_dsp dsp; +}; + +struct vibra_work { + struct vibra_info *info; + struct ff_effect *effect; + struct work_struct work; + s16 *custom_data; + int count; + int error; +}; + +static struct vibra_bank cs40l50_banks[] = { + { + .bank = WVFRM_BANK_RAM, + .base_index = CS40L50_RAM_INDEX_START, + .max_index = CS40L50_RAM_INDEX_END, + }, + { + .bank = WVFRM_BANK_ROM, + .base_index = CS40L50_ROM_INDEX_START, + .max_index = CS40L50_ROM_INDEX_END, + }, + { + .bank = WVFRM_BANK_OWT, + .base_index = CS40L50_RTH_INDEX_START, + .max_index = CS40L50_RTH_INDEX_END, + }, +}; + +static struct vibra_dsp cs40l50_dsp = { + .banks = cs40l50_banks, + .gpio_base_reg = CS40L50_GPIO_BASE, + .owt_base_reg = CS40L50_OWT_BASE, + .owt_offset_reg = CS40L50_OWT_NEXT, + .owt_size_reg = CS40L50_OWT_SIZE, + + .push_owt_cmd = CS40L50_OWT_PUSH, + .delete_owt_cmd = CS40L50_OWT_DELETE, + .stop_cmd = CS40L50_STOP_PLAYBACK, + + .write = cs40l50_dsp_write, +}; + +static struct vibra_effect *vibra_find_effect(int id, struct list_head *effect_head) +{ + struct vibra_effect *effect; + + list_for_each_entry(effect, effect_head, list) + if (effect->id == id) + return effect; + + return NULL; +} + +static int vibra_effect_bank_set(struct vibra_work *work_data, + struct vibra_effect *effect) +{ + unsigned int len = work_data->effect->u.periodic.custom_len; + s16 bank = work_data->custom_data[0] & 0xffffu; + + if (bank >= WVFRM_BANK_NUM) { + dev_err(work_data->info->dev, "Invalid waveform bank: %d\n", bank); + return -EINVAL; + } + + effect->bank = len > CS40L50_OWT_CUSTOM_DATA_SIZE ? WVFRM_BANK_OWT : bank; + + return 0; +} + +static int vibra_effect_gpio_mapping_set(struct vibra_work *work_data, + struct vibra_effect *effect) +{ + u16 button = work_data->effect->trigger.button; + struct vibra_info *info = work_data->info; + u32 gpio_num, gpio_edge; + + if (button) { + gpio_num = FIELD_GET(CS40L50_GPIO_NUM_MASK, button); + gpio_edge = FIELD_GET(CS40L50_GPIO_EDGE_MASK, button); + effect->gpio_reg = info->dsp.gpio_base_reg + (gpio_num * 8) - gpio_edge; + + return regmap_write(info->regmap, effect->gpio_reg, button); + } + + effect->gpio_reg = CS40L50_GPIO_MAPPING_NONE; + + return 0; +} + +static int vibra_effect_index_set(struct vibra_work *work_data, + struct vibra_effect *effect) +{ + struct vibra_info *info = work_data->info; + struct vibra_effect *owt_effect; + u32 base_index, max_index; + + base_index = info->dsp.banks[effect->bank].base_index; + max_index = info->dsp.banks[effect->bank].max_index; + + effect->index = base_index; + + switch (effect->bank) { + case WVFRM_BANK_OWT: + list_for_each_entry(owt_effect, &info->effect_head, list) + if (owt_effect->bank == WVFRM_BANK_OWT) + effect->index++; + break; + case WVFRM_BANK_ROM: + case WVFRM_BANK_RAM: + effect->index += work_data->custom_data[1] & 0xffffu; + break; + default: + dev_err(info->dev, "Bank not supported: %d\n", effect->bank); + return -EINVAL; + } + + if (effect->index > max_index || effect->index < base_index) { + dev_err(info->dev, "Index out of bounds: %u\n", effect->index); + return -ENOSPC; + } + + return 0; +} + +/* Describes a header for an OWT effect */ +struct owt_header { + u32 type; + u32 data_words; + u32 offset; +} __packed; + +static int vibra_upload_owt(struct vibra_work *work_data, struct vibra_effect *effect) +{ + struct ff_periodic_effect add_effect = work_data->effect->u.periodic; + u32 len = 2 * add_effect.custom_len, wt_offset, wt_size; + struct vibra_info *info = work_data->info; + struct owt_header header; + u8 *out_data; + int error; + + error = regmap_read(info->regmap, info->dsp.owt_size_reg, &wt_size); + if (error) + return error; + + if ((wt_size * sizeof(u32)) < sizeof(header) + len) { + dev_err(info->dev, "No space in OWT bank for effect\n"); + return -ENOSPC; + } + + out_data = kzalloc(sizeof(header) + len, GFP_KERNEL); + if (!out_data) + return -ENOMEM; + + header.type = add_effect.custom_data[0] == CS40L50_PCM_ID ? CS40L50_TYPE_PCM : + CS40L50_TYPE_PWLE; + header.offset = sizeof(header) / sizeof(u32); + header.data_words = len / sizeof(u32); + + memcpy(out_data, &header, sizeof(header)); + memcpy(out_data + sizeof(header), add_effect.custom_data, len); + + error = regmap_read(info->regmap, info->dsp.owt_offset_reg, &wt_offset); + if (error) + return error; + + error = regmap_bulk_write(info->regmap, info->dsp.owt_base_reg + + (wt_offset * sizeof(u32)), out_data, + sizeof(header) + len); + if (error) + goto err_free; + + error = info->dsp.write(info->dev, info->regmap, info->dsp.push_owt_cmd); +err_free: + kfree(out_data); + + return error; +} + +static void vibra_add_worker(struct work_struct *work) +{ + struct vibra_work *work_data = container_of(work, struct vibra_work, work); + struct vibra_info *info = work_data->info; + struct vibra_effect *effect; + bool is_new = false; + int error; + + error = pm_runtime_resume_and_get(info->dev); + if (error < 0) + goto exit; + + mutex_lock(&info->lock); + + effect = vibra_find_effect(work_data->effect->id, &info->effect_head); + if (!effect) { + effect = kzalloc(sizeof(*effect), GFP_KERNEL); + if (!effect) { + error = -ENOMEM; + goto err_mutex; + } + + effect->id = work_data->effect->id; + is_new = true; + } + + error = vibra_effect_bank_set(work_data, effect); + if (error) + goto err_free; + + error = vibra_effect_index_set(work_data, effect); + if (error) + goto err_free; + + error = vibra_effect_gpio_mapping_set(work_data, effect); + if (error) + goto err_free; + + if (effect->bank == WVFRM_BANK_OWT) + error = vibra_upload_owt(work_data, effect); +err_free: + if (is_new) { + if (error) + kfree(effect); + else + list_add(&effect->list, &info->effect_head); + } +err_mutex: + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); +exit: + work_data->error = error; +} + +static int vibra_add(struct input_dev *dev, struct ff_effect *effect, + struct ff_effect *old) +{ + struct ff_periodic_effect *periodic = &effect->u.periodic; + struct vibra_info *info = input_get_drvdata(dev); + struct vibra_work work_data = { info, effect, }; + u32 len = effect->u.periodic.custom_len; + + if (effect->type != FF_PERIODIC || periodic->waveform != FF_CUSTOM) { + dev_err(info->dev, "Type (%#X) or waveform (%#X) unsupported\n", + effect->type, periodic->waveform); + return -EINVAL; + } + + work_data.custom_data = kcalloc(len, sizeof(s16), GFP_KERNEL); + if (!work_data.custom_data) + return -ENOMEM; + + if (copy_from_user(work_data.custom_data, effect->u.periodic.custom_data, + sizeof(s16) * len)) { + work_data.error = -EFAULT; + goto out_free; + } + + INIT_WORK(&work_data.work, vibra_add_worker); + + /* Push to the workqueue to serialize with playbacks */ + queue_work(info->vibe_wq, &work_data.work); + flush_work(&work_data.work); +out_free: + kfree(work_data.custom_data); + + return work_data.error; +} + +static void vibra_start_worker(struct work_struct *work) +{ + struct vibra_work *work_data = container_of(work, struct vibra_work, work); + struct vibra_info *info = work_data->info; + struct vibra_effect *start_effect; + + if (pm_runtime_resume_and_get(info->dev) < 0) + goto error; + + mutex_lock(&info->lock); + + start_effect = vibra_find_effect(work_data->effect->id, &info->effect_head); + if (start_effect) { + while (--work_data->count >= 0) { + info->dsp.write(info->dev, info->regmap, start_effect->index); + usleep_range(work_data->effect->replay.length, + work_data->effect->replay.length + 100); + } + } + + mutex_unlock(&info->lock); + + if (!start_effect) + dev_err(info->dev, "Effect to play not found\n"); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); +error: + kfree(work_data); +} + +static void vibra_stop_worker(struct work_struct *work) +{ + struct vibra_work *work_data = container_of(work, struct vibra_work, work); + struct vibra_info *info = work_data->info; + + if (pm_runtime_resume_and_get(info->dev) < 0) + return; + + mutex_lock(&info->lock); + + info->dsp.write(info->dev, info->regmap, info->dsp.stop_cmd); + + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + + kfree(work_data); +} + +static int vibra_playback(struct input_dev *dev, int effect_id, int val) +{ + struct vibra_info *info = input_get_drvdata(dev); + struct vibra_work *work_data; + + work_data = kzalloc(sizeof(*work_data), GFP_ATOMIC); + if (!work_data) + return -ENOMEM; + + work_data->info = info; + + if (val > 0) { + work_data->effect = &dev->ff->effects[effect_id]; + work_data->count = val; + INIT_WORK(&work_data->work, vibra_start_worker); + } else { + /* Stop the amplifier as device can only drive one effect */ + INIT_WORK(&work_data->work, vibra_stop_worker); + } + + queue_work(info->vibe_wq, &work_data->work); + + return 0; +} + +static void vibra_erase_worker(struct work_struct *work) +{ + struct vibra_work *work_data = container_of(work, struct vibra_work, work); + struct vibra_effect *owt_effect, *erase_effect; + struct vibra_info *info = work_data->info; + int error; + + error = pm_runtime_resume_and_get(info->dev); + if (error < 0) + goto exit; + + mutex_lock(&info->lock); + + erase_effect = vibra_find_effect(work_data->effect->id, &info->effect_head); + if (!erase_effect) { + dev_err(info->dev, "Effect to erase not found\n"); + error = -EINVAL; + goto error; + } + + if (erase_effect->gpio_reg != CS40L50_GPIO_MAPPING_NONE) { + error = regmap_write(info->regmap, erase_effect->gpio_reg, + CS40L50_GPIO_DISABLE); + if (error) + goto error; + } + + if (erase_effect->bank == WVFRM_BANK_OWT) { + error = info->dsp.write(info->dev, info->regmap, + info->dsp.delete_owt_cmd | + erase_effect->index); + if (error) + goto error; + + list_for_each_entry(owt_effect, &info->effect_head, list) + if (owt_effect->bank == WVFRM_BANK_OWT && + owt_effect->index > erase_effect->index) + owt_effect->index--; + } + + list_del(&erase_effect->list); + kfree(erase_effect); +error: + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); +exit: + work_data->error = error; +} + +static int vibra_erase(struct input_dev *dev, int effect_id) +{ + struct vibra_info *info = input_get_drvdata(dev); + struct vibra_work work_data = { info, &dev->ff->effects[effect_id], }; + + INIT_WORK(&work_data.work, vibra_erase_worker); + + /* Push to workqueue to serialize with playbacks */ + queue_work(info->vibe_wq, &work_data.work); + flush_work(&work_data.work); + + return work_data.error; +} + +static void vibra_remove_wq(void *data) +{ + struct vibra_info *info = data; + + flush_workqueue(info->vibe_wq); + destroy_workqueue(info->vibe_wq); +} + +static int cs40l50_vibra_probe(struct platform_device *pdev) +{ + struct cs40l50 *cs40l50 = dev_get_drvdata(pdev->dev.parent); + struct vibra_info *info; + int error; + + info = devm_kzalloc(pdev->dev.parent, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + mutex_init(&info->lock); + + info->dev = cs40l50->dev; + info->regmap = cs40l50->regmap; + info->dsp = cs40l50_dsp; + + info->input = devm_input_allocate_device(info->dev); + if (!info->input) + return -ENOMEM; + info->input->id.product = cs40l50->devid & 0xFFFF; + info->input->id.version = cs40l50->revid; + info->input->name = "cs40l50_vibra"; + + input_set_drvdata(info->input, info); + input_set_capability(info->input, EV_FF, FF_PERIODIC); + input_set_capability(info->input, EV_FF, FF_CUSTOM); + + error = input_ff_create(info->input, FF_MAX_EFFECTS); + if (error) { + dev_err(info->dev, "Failed to create input device\n"); + return error; + } + + info->input->ff->upload = vibra_add; + info->input->ff->playback = vibra_playback; + info->input->ff->erase = vibra_erase; + + INIT_LIST_HEAD(&info->effect_head); + + info->vibe_wq = alloc_ordered_workqueue("vibe_wq", WQ_HIGHPRI); + if (!info->vibe_wq) + return -ENOMEM; + + error = devm_add_action_or_reset(info->dev, vibra_remove_wq, info); + if (error) + return error; + + return input_register_device(info->input); +} + +static const struct platform_device_id vibra_id_match[] = { + { "cs40l50-vibra", }, + {} +}; +MODULE_DEVICE_TABLE(platform, vibra_id_match); + +static struct platform_driver cs40l50_vibra_driver = { + .probe = cs40l50_vibra_probe, + .id_table = vibra_id_match, + .driver = { + .name = "cs40l50-vibra", + }, +}; +module_platform_driver(cs40l50_vibra_driver); + +MODULE_DESCRIPTION("CS40L50 Advanced Haptic Driver"); +MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. "); +MODULE_LICENSE("GPL"); From patchwork Wed Feb 7 00:36:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Ogletree X-Patchwork-Id: 13547950 Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADA528F48; Wed, 7 Feb 2024 00:37:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.149.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266224; cv=none; b=bMG/G7N0v9HONpvzsqTl4U7ipX00xePlwXp81r7vjetgQgUuKLxTnIHQcRn5bbx0DveWrSSRM8D0Ylzt/gZ6IEIoMGu8VBNIlgnYnF6VY/z9rFz7h2ESdeIYTNj63sUbiTp496yQEEz7CEJRPY5+4pcYrLT5zTkr2UpwH393oBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707266224; c=relaxed/simple; bh=Q77eP9BlgsHS3+Rd+GFZpg0wZysfS2mudbPFQY4pBbw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b9LUG9z7qkWhSgSB3wCaGwBCvW9OWwysidBrQoNEvaOaKgID84PSPukgims+fcDbdKFzlJj8WyxGQRG+EI1FWzBPiaDXZp3ugdAJmmuxxek+tXCNubExzgd4hBISENiRrYDDoNUwcrOoDn0gy+ihpO0NVXhl+HIAAbRnPxcwoHI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com; spf=pass smtp.mailfrom=opensource.cirrus.com; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b=Wz+eB2F1; arc=none smtp.client-ip=67.231.149.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="Wz+eB2F1" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 416AS7SK031521; Tue, 6 Feb 2024 18:36:56 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= PODMain02222019; bh=CQ39LmvJ5XiLh4OsF067Tkk6ZcmreIjE1P0+wrkk23k=; b= Wz+eB2F1wjy+jkFFhcyHpv691TTTFZ5uA33l9Es3jeREaxMtvIg/BMvP8ouXFk8n 5ojuINWHAsl+MZ/KFc2b2g5dT+5es7HoxT5CjOs0jqQjM4HS7L1ZN35WIbwlfB5o BDOnQHHUoy7ouNa07lpr8hDLkVcHfGo9FmTVW9KJkeHXDnM44omWq0Zch0uUs/VJ xDe8ml1ApQd66298kADlUbGPa7UqsGMqpvmmxVWk2bR3AoMQkmP/b2jl7emlkxJL iHvVBykONQGh6qdINhYSE7G3x9QE2mainZNQJgkT2Vxic94k6hEkyIUNY921RT2D k0Ym8B4j5d4pbQFrPw2Gjg== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3w1ks2cbgh-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 18:36:56 -0600 (CST) Received: from ediex02.ad.cirrus.com (198.61.84.81) by ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 7 Feb 2024 00:36:53 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by anon-ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server id 15.2.1118.40 via Frontend Transport; Wed, 7 Feb 2024 00:36:53 +0000 Received: from aus-sw-rshr002.ad.cirrus.com (aus-sw-rshr002.ad.cirrus.com [141.131.145.53]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTP id 2E1D9820248; Wed, 7 Feb 2024 00:36:52 +0000 (UTC) From: James Ogletree To: , , , , , , CC: , , , , James Ogletree Subject: [PATCH v6 5/5] ASoC: cs40l50: Support I2S streaming to CS40L50 Date: Wed, 7 Feb 2024 00:36:12 +0000 Message-ID: <20240207003612.4187370-6-jogletre@opensource.cirrus.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> References: <20240207003612.4187370-1-jogletre@opensource.cirrus.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: n_E4LKI5l3YF56kFSirbhbcljxaj2U6q X-Proofpoint-ORIG-GUID: n_E4LKI5l3YF56kFSirbhbcljxaj2U6q X-Proofpoint-Spam-Reason: safe Introduce support for Cirrus Logic Device CS40L50: a haptic driver with waveform memory, integrated DSP, and closed-loop algorithms. The ASoC driver enables I2S streaming to the device. Signed-off-by: James Ogletree --- MAINTAINERS | 1 + sound/soc/codecs/Kconfig | 11 ++ sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs40l50-codec.c | 311 +++++++++++++++++++++++++++++++ 4 files changed, 325 insertions(+) create mode 100644 sound/soc/codecs/cs40l50-codec.c diff --git a/MAINTAINERS b/MAINTAINERS index 24cfb4f017bb..fca2454a7a38 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4943,6 +4943,7 @@ F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml F: drivers/input/misc/cs40l* F: drivers/mfd/cs40l* F: include/linux/mfd/cs40l* +F: sound/soc/codecs/cs40l* CIRRUS LOGIC DSP FIRMWARE DRIVER M: Simon Trimmer diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index f1e1dbc509f6..1a81bedfdbe3 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -73,6 +73,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_CS35L56_I2C imply SND_SOC_CS35L56_SPI imply SND_SOC_CS35L56_SDW + imply SND_SOC_CS40L50 imply SND_SOC_CS42L42 imply SND_SOC_CS42L42_SDW imply SND_SOC_CS42L43 @@ -800,6 +801,16 @@ config SND_SOC_CS35L56_SDW help Enable support for Cirrus Logic CS35L56 boosted amplifier with SoundWire control +config SND_SOC_CS40L50 + tristate "Cirrus Logic CS40L50 CODEC" + depends on MFD_CS40L50_CORE + help + This option enables support for I2S streaming to Cirrus Logic CS40L50. + + CS40L50 is a haptic driver with waveform memory, an integrated + DSP, and closed-loop algorithms. If built as a module, it will be + called snd-soc-cs40l50. + config SND_SOC_CS42L42_CORE tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index a87e56938ce5..7e31f000774a 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -74,6 +74,7 @@ snd-soc-cs35l56-shared-objs := cs35l56-shared.o snd-soc-cs35l56-i2c-objs := cs35l56-i2c.o snd-soc-cs35l56-spi-objs := cs35l56-spi.o snd-soc-cs35l56-sdw-objs := cs35l56-sdw.o +snd-soc-cs40l50-objs := cs40l50-codec.o snd-soc-cs42l42-objs := cs42l42.o snd-soc-cs42l42-i2c-objs := cs42l42-i2c.o snd-soc-cs42l42-sdw-objs := cs42l42-sdw.o @@ -460,6 +461,7 @@ obj-$(CONFIG_SND_SOC_CS35L56_SHARED) += snd-soc-cs35l56-shared.o obj-$(CONFIG_SND_SOC_CS35L56_I2C) += snd-soc-cs35l56-i2c.o obj-$(CONFIG_SND_SOC_CS35L56_SPI) += snd-soc-cs35l56-spi.o obj-$(CONFIG_SND_SOC_CS35L56_SDW) += snd-soc-cs35l56-sdw.o +obj-$(CONFIG_SND_SOC_CS40L50) += snd-soc-cs40l50.o obj-$(CONFIG_SND_SOC_CS42L42_CORE) += snd-soc-cs42l42.o obj-$(CONFIG_SND_SOC_CS42L42) += snd-soc-cs42l42-i2c.o obj-$(CONFIG_SND_SOC_CS42L42_SDW) += snd-soc-cs42l42-sdw.o diff --git a/sound/soc/codecs/cs40l50-codec.c b/sound/soc/codecs/cs40l50-codec.c new file mode 100644 index 000000000000..3632069d6091 --- /dev/null +++ b/sound/soc/codecs/cs40l50-codec.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CS40L50 Advanced Haptic Driver with waveform memory, + * integrated DSP, and closed-loop algorithms + * + * Copyright 2024 Cirrus Logic, Inc. + * + * Author: James Ogletree + */ + +#include +#include +#include +#include +#include + +#define CS40L50_REFCLK_INPUT 0x2C04 +#define CS40L50_ASP_CONTROL2 0x4808 +#define CS40L50_ASP_DATA_CONTROL5 0x4840 + +/* PLL Config */ +#define CS40L50_PLL_CLK_CFG_32768 0x00 +#define CS40L50_PLL_CLK_CFG_1536000 0x1B +#define CS40L50_PLL_CLK_CFG_3072000 0x21 +#define CS40L50_PLL_CLK_CFG_6144000 0x28 +#define CS40L50_PLL_CLK_CFG_9600000 0x30 +#define CS40L50_PLL_CLK_CFG_12288000 0x33 +#define CS40L50_PLL_CLK_FRQ_32768 32768 +#define CS40L50_PLL_CLK_FRQ_1536000 1536000 +#define CS40L50_PLL_CLK_FRQ_3072000 3072000 +#define CS40L50_PLL_CLK_FRQ_6144000 6144000 +#define CS40L50_PLL_CLK_FRQ_9600000 9600000 +#define CS40L50_PLL_CLK_FRQ_12288000 12288000 +#define CS40L50_PLL_REFCLK_BCLK 0x0 +#define CS40L50_PLL_REFCLK_MCLK 0x5 +#define CS40L50_PLL_REFCLK_LOOP_MASK BIT(11) +#define CS40L50_PLL_REFCLK_OPEN_LOOP 1 +#define CS40L50_PLL_REFCLK_CLOSED_LOOP 0 +#define CS40L50_PLL_REFCLK_LOOP_SHIFT 11 +#define CS40L50_PLL_REFCLK_FREQ_MASK GENMASK(10, 5) +#define CS40L50_PLL_REFCLK_FREQ_SHIFT 5 +#define CS40L50_PLL_REFCLK_SEL_MASK GENMASK(2, 0) + +/* ASP Config */ +#define CS40L50_ASP_RX_WIDTH_SHIFT 24 +#define CS40L50_ASP_RX_WIDTH_MASK GENMASK(31, 24) +#define CS40L50_ASP_RX_WL_MASK GENMASK(5, 0) +#define CS40L50_ASP_FSYNC_INV_MASK BIT(2) +#define CS40L50_ASP_BCLK_INV_MASK BIT(6) +#define CS40L50_ASP_FMT_MASK GENMASK(10, 8) +#define CS40L50_ASP_FMT_I2S 0x2 +#define CS40L50_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) + +struct cs40l50_pll_sysclk_config { + unsigned int freq; + unsigned int clk_cfg; +}; + +struct cs40l50_codec { + struct device *dev; + struct regmap *regmap; + unsigned int sysclk_rate; + unsigned int daifmt; +}; + +static const struct cs40l50_pll_sysclk_config cs40l50_pll_sysclk[] = { + {CS40L50_PLL_CLK_FRQ_32768, CS40L50_PLL_CLK_CFG_32768}, + {CS40L50_PLL_CLK_FRQ_1536000, CS40L50_PLL_CLK_CFG_1536000}, + {CS40L50_PLL_CLK_FRQ_3072000, CS40L50_PLL_CLK_CFG_3072000}, + {CS40L50_PLL_CLK_FRQ_6144000, CS40L50_PLL_CLK_CFG_6144000}, + {CS40L50_PLL_CLK_FRQ_9600000, CS40L50_PLL_CLK_CFG_9600000}, + {CS40L50_PLL_CLK_FRQ_12288000, CS40L50_PLL_CLK_CFG_12288000}, +}; + +static int cs40l50_get_clk_config(unsigned int freq, unsigned int *clk_cfg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs40l50_pll_sysclk); i++) { + if (cs40l50_pll_sysclk[i].freq == freq) { + *clk_cfg = cs40l50_pll_sysclk[i].clk_cfg; + return 0; + } + } + + return -EINVAL; +} + +static int cs40l50_swap_ext_clk(struct cs40l50_codec *codec, unsigned int clk_src) +{ + unsigned int clk_cfg; + int ret; + + switch (clk_src) { + case CS40L50_PLL_REFCLK_BCLK: + ret = cs40l50_get_clk_config(codec->sysclk_rate, &clk_cfg); + if (ret) + return ret; + break; + case CS40L50_PLL_REFCLK_MCLK: + clk_cfg = CS40L50_PLL_CLK_CFG_32768; + break; + default: + return -EINVAL; + } + + ret = regmap_update_bits(codec->regmap, CS40L50_REFCLK_INPUT, + CS40L50_PLL_REFCLK_LOOP_MASK, + CS40L50_PLL_REFCLK_OPEN_LOOP << + CS40L50_PLL_REFCLK_LOOP_SHIFT); + if (ret) + return ret; + + ret = regmap_update_bits(codec->regmap, CS40L50_REFCLK_INPUT, + CS40L50_PLL_REFCLK_FREQ_MASK | + CS40L50_PLL_REFCLK_SEL_MASK, + (clk_cfg << CS40L50_PLL_REFCLK_FREQ_SHIFT) | clk_src); + if (ret) + return ret; + + return regmap_update_bits(codec->regmap, CS40L50_REFCLK_INPUT, + CS40L50_PLL_REFCLK_LOOP_MASK, + CS40L50_PLL_REFCLK_CLOSED_LOOP << + CS40L50_PLL_REFCLK_LOOP_SHIFT); +} + +static int cs40l50_clk_en(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(comp); + int ret; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + ret = cs40l50_dsp_write(codec->dev, codec->regmap, CS40L50_STOP_PLAYBACK); + if (ret) + return ret; + + ret = cs40l50_dsp_write(codec->dev, codec->regmap, CS40L50_START_I2S); + if (ret) + return ret; + + ret = cs40l50_swap_ext_clk(codec, CS40L50_PLL_REFCLK_BCLK); + if (ret) + return ret; + break; + case SND_SOC_DAPM_PRE_PMD: + ret = cs40l50_swap_ext_clk(codec, CS40L50_PLL_REFCLK_MCLK); + if (ret) + return ret; + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct snd_soc_dapm_widget cs40l50_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY_S("ASP PLL", 0, SND_SOC_NOPM, 0, 0, cs40l50_clk_en, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_OUTPUT("OUT"), +}; + +static const struct snd_soc_dapm_route cs40l50_dapm_routes[] = { + { "ASP Playback", NULL, "ASP PLL" }, + { "ASPRX1", NULL, "ASP Playback" }, + { "ASPRX2", NULL, "ASP Playback" }, + + { "OUT", NULL, "ASPRX1" }, + { "OUT", NULL, "ASPRX2" }, +}; + +static int cs40l50_component_set_sysclk(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir) +{ + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(component); + + codec->sysclk_rate = freq; + + return 0; +} + +static int cs40l50_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(codec_dai->component); + + if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) + return -EINVAL; + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + codec->daifmt = 0; + break; + case SND_SOC_DAIFMT_NB_IF: + codec->daifmt = CS40L50_ASP_FSYNC_INV_MASK; + break; + case SND_SOC_DAIFMT_IB_NF: + codec->daifmt = CS40L50_ASP_BCLK_INV_MASK; + break; + case SND_SOC_DAIFMT_IB_IF: + codec->daifmt = CS40L50_ASP_FSYNC_INV_MASK | CS40L50_ASP_BCLK_INV_MASK; + break; + default: + dev_err(codec->dev, "Invalid clock invert\n"); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + codec->daifmt |= FIELD_PREP(CS40L50_ASP_FMT_MASK, CS40L50_ASP_FMT_I2S); + break; + default: + dev_err(codec->dev, "Unsupported DAI format\n"); + return -EINVAL; + } + + return 0; +} + +static int cs40l50_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(dai->component); + unsigned int asp_rx_wl = params_width(params); + int ret; + + ret = regmap_update_bits(codec->regmap, CS40L50_ASP_DATA_CONTROL5, + CS40L50_ASP_RX_WL_MASK, asp_rx_wl); + if (ret) + return ret; + + codec->daifmt |= (asp_rx_wl << CS40L50_ASP_RX_WIDTH_SHIFT); + + return regmap_update_bits(codec->regmap, CS40L50_ASP_CONTROL2, + CS40L50_ASP_FSYNC_INV_MASK | + CS40L50_ASP_BCLK_INV_MASK | + CS40L50_ASP_FMT_MASK | + CS40L50_ASP_RX_WIDTH_MASK, codec->daifmt); +} + +static const struct snd_soc_dai_ops cs40l50_dai_ops = { + .set_fmt = cs40l50_set_dai_fmt, + .hw_params = cs40l50_hw_params, +}; + +static struct snd_soc_dai_driver cs40l50_dai[] = { + { + .name = "cs40l50-pcm", + .id = 0, + .playback = { + .stream_name = "ASP Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .formats = CS40L50_FORMATS, + }, + .ops = &cs40l50_dai_ops, + }, +}; + +static int cs40l50_codec_probe(struct snd_soc_component *component) +{ + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(component); + + codec->sysclk_rate = CS40L50_PLL_CLK_FRQ_1536000; + + return 0; +} + +static const struct snd_soc_component_driver soc_codec_dev_cs40l50 = { + .probe = cs40l50_codec_probe, + .set_sysclk = cs40l50_component_set_sysclk, + .dapm_widgets = cs40l50_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs40l50_dapm_widgets), + .dapm_routes = cs40l50_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(cs40l50_dapm_routes), +}; + +static int cs40l50_codec_driver_probe(struct platform_device *pdev) +{ + struct cs40l50 *cs40l50 = dev_get_drvdata(pdev->dev.parent); + struct cs40l50_codec *codec; + + codec = devm_kzalloc(&pdev->dev, sizeof(*codec), GFP_KERNEL); + if (!codec) + return -ENOMEM; + + codec->regmap = cs40l50->regmap; + codec->dev = &pdev->dev; + + return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cs40l50, + cs40l50_dai, ARRAY_SIZE(cs40l50_dai)); +} + +static struct platform_driver cs40l50_codec_driver = { + .probe = cs40l50_codec_driver_probe, + .driver = { + .name = "cs40l50-codec", + }, +}; +module_platform_driver(cs40l50_codec_driver); + +MODULE_DESCRIPTION("ASoC CS40L50 driver"); +MODULE_AUTHOR("James Ogletree "); +MODULE_LICENSE("GPL");