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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:43:44 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs Date: Thu, 8 Feb 2024 14:42:44 +0200 Message-Id: <20240208124300.2740313-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add power domain IDs for RZ/G2UL (R9A07G043) SoC. Signed-off-by: Claudiu Beznea --- include/dt-bindings/clock/r9a07g043-cpg.h | 48 +++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h index 77cde8effdc7..eabfeec7ac37 100644 --- a/include/dt-bindings/clock/r9a07g043-cpg.h +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -200,5 +200,53 @@ #define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ #define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ +/* Power domain IDs. */ +#define R9A07G043_PD_ALWAYS_ON 0 +#define R9A07G043_PD_GIC 1 +#define R9A07G043_PD_IA55 2 +#define R9A07G043_PD_MHU 3 +#define R9A07G043_PD_CORESIGHT 4 +#define R9A07G043_PD_SYC 5 +#define R9A07G043_PD_DMAC 6 +#define R9A07G043_PD_GTM0 7 +#define R9A07G043_PD_GTM1 8 +#define R9A07G043_PD_GTM2 9 +#define R9A07G043_PD_MTU 10 +#define R9A07G043_PD_POE3 11 +#define R9A07G043_PD_WDT0 12 +#define R9A07G043_PD_SPI 13 +#define R9A07G043_PD_SDHI0 14 +#define R9A07G043_PD_SDHI1 15 +#define R9A07G043_PD_ISU 16 +#define R9A07G043_PD_CRU 17 +#define R9A07G043_PD_LCDC 18 +#define R9A07G043_PD_SSI0 19 +#define R9A07G043_PD_SSI1 20 +#define R9A07G043_PD_SSI2 21 +#define R9A07G043_PD_SSI3 22 +#define R9A07G043_PD_SRC 23 +#define R9A07G043_PD_USB0 24 +#define R9A07G043_PD_USB1 25 +#define R9A07G043_PD_USB_PHY 26 +#define R9A07G043_PD_ETHER0 27 +#define R9A07G043_PD_ETHER1 28 +#define R9A07G043_PD_I2C0 29 +#define R9A07G043_PD_I2C1 30 +#define R9A07G043_PD_I2C2 31 +#define R9A07G043_PD_I2C3 32 +#define R9A07G043_PD_SCIF0 33 +#define R9A07G043_PD_SCIF1 34 +#define R9A07G043_PD_SCIF2 35 +#define R9A07G043_PD_SCIF3 36 +#define R9A07G043_PD_SCIF4 37 +#define R9A07G043_PD_SCI0 38 +#define R9A07G043_PD_SCI1 39 +#define R9A07G043_PD_IRDA 40 +#define R9A07G043_PD_RSPI0 41 +#define R9A07G043_PD_RSPI1 42 +#define R9A07G043_PD_RSPI2 43 +#define R9A07G043_PD_CANFD 44 +#define R9A07G043_PD_ADC 45 +#define R9A07G043_PD_TSU 46 #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ From patchwork Thu Feb 8 12:42:45 2024 Content-Type: text/plain; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:43:46 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: Add power domain IDs Date: Thu, 8 Feb 2024 14:42:45 +0200 Message-Id: <20240208124300.2740313-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add power domain IDs for RZ/G2L (R9A07G044) SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a07g044-cpg.h | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h index 0bb17ff1a01a..e209f96f92b7 100644 --- a/include/dt-bindings/clock/r9a07g044-cpg.h +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -217,4 +217,62 @@ #define R9A07G044_ADC_ADRST_N 82 #define R9A07G044_TSU_PRESETN 83 +/* Power domain IDs. */ +#define R9A07G044_PD_ALWAYS_ON 0 +#define R9A07G044_PD_GIC 1 +#define R9A07G044_PD_IA55 2 +#define R9A07G044_PD_MHU 3 +#define R9A07G044_PD_CORESIGHT 4 +#define R9A07G044_PD_SYC 5 +#define R9A07G044_PD_DMAC 6 +#define R9A07G044_PD_GTM0 7 +#define R9A07G044_PD_GTM1 8 +#define R9A07G044_PD_GTM2 9 +#define R9A07G044_PD_MTU 10 +#define R9A07G044_PD_POE3 11 +#define R9A07G044_PD_GPT 12 +#define R9A07G044_PD_POEGA 13 +#define R9A07G044_PD_POEGB 14 +#define R9A07G044_PD_POEGC 15 +#define R9A07G044_PD_POEGD 16 +#define R9A07G044_PD_WDT0 17 +#define R9A07G044_PD_WDT1 18 +#define R9A07G044_PD_SPI 19 +#define R9A07G044_PD_SDHI0 20 +#define R9A07G044_PD_SDHI1 21 +#define R9A07G044_PD_3DGE 22 +#define R9A07G044_PD_ISU 23 +#define R9A07G044_PD_VCPL4 24 +#define R9A07G044_PD_CRU 25 +#define R9A07G044_PD_MIPI_DSI 26 +#define R9A07G044_PD_LCDC 27 +#define R9A07G044_PD_SSI0 28 +#define R9A07G044_PD_SSI1 29 +#define R9A07G044_PD_SSI2 30 +#define R9A07G044_PD_SSI3 31 +#define R9A07G044_PD_SRC 32 +#define R9A07G044_PD_USB0 33 +#define R9A07G044_PD_USB1 34 +#define R9A07G044_PD_USB_PHY 35 +#define R9A07G044_PD_ETHER0 36 +#define R9A07G044_PD_ETHER1 37 +#define R9A07G044_PD_I2C0 38 +#define R9A07G044_PD_I2C1 39 +#define R9A07G044_PD_I2C2 40 +#define R9A07G044_PD_I2C3 41 +#define R9A07G044_PD_SCIF0 42 +#define R9A07G044_PD_SCIF1 43 +#define R9A07G044_PD_SCIF2 44 +#define R9A07G044_PD_SCIF3 45 +#define R9A07G044_PD_SCIF4 46 +#define R9A07G044_PD_SCI0 47 +#define R9A07G044_PD_SCI1 48 +#define R9A07G044_PD_IRDA 49 +#define R9A07G044_PD_RSPI0 50 +#define R9A07G044_PD_RSPI1 51 +#define R9A07G044_PD_RSPI2 52 +#define R9A07G044_PD_CANFD 53 +#define R9A07G044_PD_ADC 54 +#define R9A07G044_PD_TSU 55 + #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ From patchwork Thu Feb 8 12:42:46 2024 Content-Type: text/plain; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:43:49 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 03/17] dt-bindings: clock: r9a07g054-cpg: Add power domain IDs Date: Thu, 8 Feb 2024 14:42:46 +0200 Message-Id: <20240208124300.2740313-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add power domain IDs for RZ/V2L (R9A07G054) SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a07g054-cpg.h | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h index 43f4dbda872c..2c99f89397c4 100644 --- a/include/dt-bindings/clock/r9a07g054-cpg.h +++ b/include/dt-bindings/clock/r9a07g054-cpg.h @@ -226,4 +226,62 @@ #define R9A07G054_TSU_PRESETN 83 #define R9A07G054_STPAI_ARESETN 84 +/* Power domain IDs. */ +#define R9A07G054_PD_ALWAYS_ON 0 +#define R9A07G054_PD_GIC 1 +#define R9A07G054_PD_IA55 2 +#define R9A07G054_PD_MHU 3 +#define R9A07G054_PD_CORESIGHT 4 +#define R9A07G054_PD_SYC 5 +#define R9A07G054_PD_DMAC 6 +#define R9A07G054_PD_GTM0 7 +#define R9A07G054_PD_GTM1 8 +#define R9A07G054_PD_GTM2 9 +#define R9A07G054_PD_MTU 10 +#define R9A07G054_PD_POE3 11 +#define R9A07G054_PD_GPT 12 +#define R9A07G054_PD_POEGA 13 +#define R9A07G054_PD_POEGB 14 +#define R9A07G054_PD_POEGC 15 +#define R9A07G054_PD_POEGD 16 +#define R9A07G054_PD_WDT0 17 +#define R9A07G054_PD_WDT1 18 +#define R9A07G054_PD_SPI 19 +#define R9A07G054_PD_SDHI0 20 +#define R9A07G054_PD_SDHI1 21 +#define R9A07G054_PD_3DGE 22 +#define R9A07G054_PD_ISU 23 +#define R9A07G054_PD_VCPL4 24 +#define R9A07G054_PD_CRU 25 +#define R9A07G054_PD_MIPI_DSI 26 +#define R9A07G054_PD_LCDC 27 +#define R9A07G054_PD_SSI0 28 +#define R9A07G054_PD_SSI1 29 +#define R9A07G054_PD_SSI2 30 +#define R9A07G054_PD_SSI3 31 +#define R9A07G054_PD_SRC 32 +#define R9A07G054_PD_USB0 33 +#define R9A07G054_PD_USB1 34 +#define R9A07G054_PD_USB_PHY 35 +#define R9A07G054_PD_ETHER0 36 +#define R9A07G054_PD_ETHER1 37 +#define R9A07G054_PD_I2C0 38 +#define R9A07G054_PD_I2C1 39 +#define R9A07G054_PD_I2C2 40 +#define R9A07G054_PD_I2C3 41 +#define R9A07G054_PD_SCIF0 42 +#define R9A07G054_PD_SCIF1 43 +#define R9A07G054_PD_SCIF2 44 +#define R9A07G054_PD_SCIF3 45 +#define R9A07G054_PD_SCIF4 46 +#define R9A07G054_PD_SCI0 47 +#define R9A07G054_PD_SCI1 48 +#define R9A07G054_PD_IRDA 49 +#define R9A07G054_PD_RSPI0 50 +#define R9A07G054_PD_RSPI1 51 +#define R9A07G054_PD_RSPI2 52 +#define R9A07G054_PD_CANFD 53 +#define R9A07G054_PD_ADC 54 +#define R9A07G054_PD_TSU 55 + #endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */ From patchwork Thu Feb 8 12:42:47 2024 Content-Type: text/plain; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:43:50 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 04/17] dt-bindings: clock: r9a08g045-cpg: Add power domain IDs Date: Thu, 8 Feb 2024 14:42:47 +0200 Message-Id: <20240208124300.2740313-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add power domain IDs for RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a08g045-cpg.h | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h index 410725b778a8..8281e9caf3a9 100644 --- a/include/dt-bindings/clock/r9a08g045-cpg.h +++ b/include/dt-bindings/clock/r9a08g045-cpg.h @@ -239,4 +239,74 @@ #define R9A08G045_I3C_PRESETN 92 #define R9A08G045_VBAT_BRESETN 93 +/* Power domain IDs. */ +#define R9A08G045_PD_ALWAYS_ON 0 +#define R9A08G045_PD_GIC 1 +#define R9A08G045_PD_IA55 2 +#define R9A08G045_PD_MHU 3 +#define R9A08G045_PD_CORESIGHT 4 +#define R9A08G045_PD_SYC 5 +#define R9A08G045_PD_DMAC 6 +#define R9A08G045_PD_GTM0 7 +#define R9A08G045_PD_GTM1 8 +#define R9A08G045_PD_GTM2 9 +#define R9A08G045_PD_GTM3 10 +#define R9A08G045_PD_GTM4 11 +#define R9A08G045_PD_GTM5 12 +#define R9A08G045_PD_GTM6 13 +#define R9A08G045_PD_GTM7 14 +#define R9A08G045_PD_MTU 15 +#define R9A08G045_PD_POE3 16 +#define R9A08G045_PD_GPT 17 +#define R9A08G045_PD_POEGA 18 +#define R9A08G045_PD_POEGB 19 +#define R9A08G045_PD_POEGC 20 +#define R9A08G045_PD_POEGD 21 +#define R9A08G045_PD_WDT0 22 +#define R9A08G045_PD_XSPI 23 +#define R9A08G045_PD_SDHI0 24 +#define R9A08G045_PD_SDHI1 25 +#define R9A08G045_PD_SDHI2 26 +#define R9A08G045_PD_SSI0 27 +#define R9A08G045_PD_SSI1 28 +#define R9A08G045_PD_SSI2 29 +#define R9A08G045_PD_SSI3 30 +#define R9A08G045_PD_SRC 31 +#define R9A08G045_PD_USB0 32 +#define R9A08G045_PD_USB1 33 +#define R9A08G045_PD_USB_PHY 34 +#define R9A08G045_PD_ETHER0 35 +#define R9A08G045_PD_ETHER1 36 +#define R9A08G045_PD_I2C0 37 +#define R9A08G045_PD_I2C1 38 +#define R9A08G045_PD_I2C2 39 +#define R9A08G045_PD_I2C3 40 +#define R9A08G045_PD_SCIF0 41 +#define R9A08G045_PD_SCIF1 42 +#define R9A08G045_PD_SCIF2 43 +#define R9A08G045_PD_SCIF3 44 +#define R9A08G045_PD_SCIF4 45 +#define R9A08G045_PD_SCIF5 46 +#define R9A08G045_PD_SCI0 47 +#define R9A08G045_PD_SCI1 48 +#define R9A08G045_PD_IRDA 49 +#define R9A08G045_PD_RSPI0 50 +#define R9A08G045_PD_RSPI1 51 +#define R9A08G045_PD_RSPI2 52 +#define R9A08G045_PD_RSPI3 53 +#define R9A08G045_PD_RSPI4 54 +#define R9A08G045_PD_CANFD 55 +#define R9A08G045_PD_ADC 56 +#define R9A08G045_PD_TSU 57 +#define R9A08G045_PD_OCTA 58 +#define R9A08G045_PD_PDM 59 +#define R9A08G045_PD_PCI 60 +#define R9A08G045_PD_SPDIF 61 +#define R9A08G045_PD_I3C 62 +#define R9A08G045_PD_VBAT 63 + +#define R9A08G045_PD_DDR 64 +#define R9A08G045_PD_TZCDDR 65 +#define R9A08G045_PD_OTFDE_DDR 66 + #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */ From patchwork Thu Feb 8 12:42:48 2024 Content-Type: text/plain; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:43:53 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 05/17] dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs Date: Thu, 8 Feb 2024 14:42:48 +0200 Message-Id: <20240208124300.2740313-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add always-on power domain ID for RZ/V2M (R9A09G011) SoC. Signed-off-by: Claudiu Beznea --- include/dt-bindings/clock/r9a09g011-cpg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h index 41dd585d7115..250499faf049 100644 --- a/include/dt-bindings/clock/r9a09g011-cpg.h +++ b/include/dt-bindings/clock/r9a09g011-cpg.h @@ -349,4 +349,7 @@ #define R9A09G011_DDI_RESET 93 #define R9A09G011_DDI_RESETN_APB 94 +/* Power domain IDs. */ +#define R9A09G011_PD_ALWAYS_ON 0 + #endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */ From patchwork Thu Feb 8 12:42:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13549755 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06AF678B6E for ; Thu, 8 Feb 2024 12:43:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707396239; cv=none; b=LjCCdLrHEVqgaF8g+1slugdKSV47mjnmaenpNx+QesXxP+/orOG241GAabAKBfcf862eQhvYjnX+o/YGTtPiaSGRb+t5oAKh9rLdjxhAcxTwzppPuJENXm5v0V2WCPEywCMRJ1Wx3PGMMWzJv47Qr7hP5GqiJR5utRz6q1kR7wk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707396239; c=relaxed/simple; bh=v//21KnnDrpqx39OxUt/lqL3cNOdm1jgjiI36bhErsE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oCMhsEZgxYp3ABMXXvoSShldb1wsO6UvYQfxhw+mV5yOEKzal0TSxHRe+yp/1nMQbeJ4gwm6UCnhoUfz3gJKGOYTm/EDd2QVDZ4xO/oqJXLTG/jnlWpp2+1oV1Mc5gFTg0ahYVX2oLKnTUajVgYr+yQcp39EjOTCT3gl8pG4NVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=Xp8nbnL6; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Xp8nbnL6" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-41008ab427fso16154145e9.0 for ; Thu, 08 Feb 2024 04:43:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1707396236; x=1708001036; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ryh17vkvT9rK0W07k4+YFM6FrPWL3ef1PYzKuNba8sI=; b=Xp8nbnL67o19u+sNe+HrLLxRdoXz6kuwP1cNB20SZueg9926xxqxRmc9vH2SPKcs4c J8u9O0uLlltCgW7saB79WMq2pOBQsv32FQfa4pOqJlLpI3EHej93ot0QKlnuCBt5abCE 2cNV8pyGrxaFzX1LD+UdZOyOBmFnuABFY+zt1sfubowSX0XIQnLX/CtlQ415LdVYDx7h nuOWrrYLptYpYAChgLVNsfryreXxubVQp8m3bc/4KdkukVun4ZYxpo3iqVObR1knLpcm 0R/CpV3VvhKrq+iv89Ou4NW3TcLXPySZnFlhXN6irXlTHdywglSr1VdsOmCRE2Q1G8S6 /+dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707396236; x=1708001036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ryh17vkvT9rK0W07k4+YFM6FrPWL3ef1PYzKuNba8sI=; b=f0ZHb/Np7MPZw0ixD3jZw8YTVt/6ThSIKacrX6RhUq1ij2QCM7Cvrc4U7khmOP7Fqq oVlht7ay+Wrg/cyWrDG2u5XIN9srfs9+JjiHueICxHJrCfhr7Ii0hJzz2tWtyiwRuWab lk8nfFg/EsU57LC4K2r4LUhokfYNT15pQBRnr0dtwRxaExYbKorbv1mh9SbpbrStoPO8 MN/sqvCwgjD1lz2s6d5oUkOWh4Dr25vWKfshZxVoPhvyLXzSJQ83fVj3+OKYhwhMWXii UGDFMXWEdZ0soFhVKwzNa9qObIjRbxG/dNV01uQI+2qQAm8030NgBqOnih/adD7/8S+a O2LA== X-Gm-Message-State: AOJu0YybERpJLFDU9GA4HDSghRWMA+ZceV2GciochA2jHU/SdiLqw5oo fxs5Qcb2InaMByyVGGVa+Ynvn4+o8r9WYNui98rG/73zhhFeGB3tAjs/McqTjXo= X-Google-Smtp-Source: AGHT+IHunpYJbYbBjEl+8Rn5E8DhUzBiGFBc6/YTorX+D5VQ+y5VLngR+jFaUnHhz8Rw+cH4nUY4yA== X-Received: by 2002:a05:600c:548e:b0:40f:ba01:6125 with SMTP id iv14-20020a05600c548e00b0040fba016125mr7327127wmb.32.1707396236421; Thu, 08 Feb 2024 04:43:56 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCVaVxKvgjdrUHMcn+vDtcSzWaDLuDkKGG1MKSWLY3PNZ0O8PwbQ/8uKSqKMrqsQyqbOXAvtKOsO1LiBcuVvKeuoJx/oI6dD0l+RKX2QOWKdpr1o20p4aJVnt9tdtQVLVnhgLycsbb0MxgH8LB4WbTuAL2XDwzB5Zl4Rzg1ujmlof7uMPM4JuCUmoaQjhm1yeySRXnRdu0m7SxyBzq4hhN7AUVPRnkUG9Od2zTGWQWtP3uzmqD4IOp99FGsKRXP2RVqFf/7rsH2xbwC4umSG+DsLKMgAYh1jBS1cVLJ8reXQ95Kt2dZyD+dqaa3OZ2TKL+wd0TaHTvsUF685HHjxJmb1MFPemn1IMMFHQ5SDchoPTqUuEtydBYfK4Bna0OuO43zXHHHDpGgJENqzdos6kbRBndcwPaLKecp8w+qSOlcZeun+FZn5SOSL9hG2I0UghoAdsJjm2wzRQvyBGvK45w/YznQaw0mhfYpvHJHNwf+VoRuJTR0X+SwDStf+YxKzZKBFvcUWqE/eH8EKHSLN8tzSHCXW8KKjCt7vT47cvh0+bQ+Oa4H96qsLHH3XRAJGMOg= Received: from claudiu-X670E-Pro-RS.. ([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:43:56 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 06/17] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> Date: Thu, 8 Feb 2024 14:42:49 +0200 Message-Id: <20240208124300.2740313-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The driver will be modified (in the next commits) to be able to specify individual power domain ID for each IP. Update the documentation to cope with this. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 80a8c7114c31..d7de3ddbc613 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -57,7 +57,7 @@ properties: can be power-managed through Module Standby should refer to the CPG device node in their "power-domains" property, as documented by the generic PM Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. - const: 0 + const: 1 '#reset-cells': description: @@ -84,6 +84,6 @@ examples: clocks = <&extal_clk>; clock-names = "extal"; #clock-cells = <2>; - #power-domain-cells = <0>; + #power-domain-cells = <1>; #reset-cells = <1>; }; From patchwork Thu Feb 8 12:42:50 2024 Content-Type: text/plain; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:43:58 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support Date: Thu, 8 Feb 2024 14:42:50 +0200 Message-Id: <20240208124300.2740313-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra power when clocks are disabled by activating module standby. This is done through MSTOP-specific registers that are part of CPG. Each individual module has one or more bits associated with one MSTOP register (see table "Registers for Module Standby Mode" from HW manuals). Hardware manual associates modules' clocks with one or more MSTOP bits. There are 3 mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals): case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X}) case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X}) case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y}) Case 3 has been currently identified on RZ/V2L for the VCPL4 module. To cover all three cases, the individual platform drivers will provide to clock driver MSTOP register offset and associated bits in this register as a bitmask and the clock driver will apply this bitmask to proper MSTOP register. Apart from MSTOP support, RZ/G3S can save more power by powering down the individual IPs (after MSTOP has been set) if proper bits in CPG_PWRDN_IP{1,2} registers are set. The MSTOP and IP power down support were implemented through power domains. Platform-specific clock drivers will register an array of type struct rzg2l_cpg_pm_domain_init_data, which will be used to instantiate properly the power domains. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 227 ++++++++++++++++++++++++++++++-- drivers/clk/renesas/rzg2l-cpg.h | 68 ++++++++++ 2 files changed, 281 insertions(+), 14 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3d2daa4ba2a4..3a7168c314c2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -139,7 +139,6 @@ struct rzg2l_pll5_mux_dsi_div_param { * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @info: Pointer to platform data - * @genpd: PM domain * @mux_dsi_div_params: pll5 mux and dsi div parameters */ struct rzg2l_cpg_priv { @@ -156,8 +155,6 @@ struct rzg2l_cpg_priv { const struct rzg2l_cpg_info *info; - struct generic_pm_domain genpd; - struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; }; @@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv, return true; } +/** + * struct rzg2l_cpg_pm_domain - RZ/G2L PM domains data structure + * @domains: generic PM domains + * @onecell_data: cell data + */ +struct rzg2l_cpg_pm_domain { + struct generic_pm_domain **domains; + struct genpd_onecell_data onecell_data; +}; + +/** + * struct rzg2l_cpg_pd - RZ/G2L power domain data structure + * @priv: pointer to CPG private data structure + * @genpd: generic PM domain + * @conf: CPG PM domain configuration info + * @id: RZ/G2L power domain ID + */ +struct rzg2l_cpg_pd { + struct rzg2l_cpg_priv *priv; + struct generic_pm_domain genpd; + struct rzg2l_cpg_pm_domain_conf conf; + u16 id; +}; + static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev) { - struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd); + struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd); + struct rzg2l_cpg_priv *priv = pd->priv; struct device_node *np = dev->of_node; struct of_phandle_args clkspec; bool once = true; @@ -1617,31 +1639,208 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device } static void rzg2l_cpg_genpd_remove(void *data) +{ + struct genpd_onecell_data *celldata = data; + + for (unsigned int i = 0; i < celldata->num_domains; i++) + pm_genpd_remove(celldata->domains[i]); +} + +static void rzg2l_cpg_genpd_remove_simple(void *data) { pm_genpd_remove(data); } +static int rzg2l_cpg_power_on(struct generic_pm_domain *domain) +{ + struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd); + struct rzg2l_cpg_priv *priv = pd->priv; + u32 off, mask; + + /* Set PWRDN. */ + if (pd->conf.pwrdn) { + off = PWRDN_OFF(pd->conf.pwrdn); + mask = PWRDN_MASK(pd->conf.pwrdn) << 16; + writel(mask, priv->base + off); + } + + /* Set MSTOP. */ + if (pd->conf.mstop) { + off = MSTOP_OFF(pd->conf.mstop); + mask = MSTOP_MASK(pd->conf.mstop) << 16; + writel(mask, priv->base + off); + } + + return 0; +} + +static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) +{ + struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd); + struct rzg2l_cpg_priv *priv = pd->priv; + u32 off, mask; + + /* Set MSTOP. */ + if (pd->conf.mstop) { + off = MSTOP_OFF(pd->conf.mstop); + mask = MSTOP_MASK(pd->conf.mstop); + writel(mask | (mask << 16), priv->base + off); + } + + /* Set PWRDN. */ + if (pd->conf.pwrdn) { + off = PWRDN_OFF(pd->conf.pwrdn); + mask = PWRDN_MASK(pd->conf.pwrdn); + writel(mask | (mask << 16), priv->base + off); + } + + return 0; +} + +static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) +{ + struct dev_power_governor *governor; + + pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; + pd->genpd.attach_dev = rzg2l_cpg_attach_dev; + pd->genpd.detach_dev = rzg2l_cpg_detach_dev; + if (always_on) { + pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON; + governor = &pm_domain_always_on_gov; + } else { + pd->genpd.power_on = rzg2l_cpg_power_on; + pd->genpd.power_off = rzg2l_cpg_power_off; + governor = &simple_qos_governor; + } + + return pm_genpd_init(&pd->genpd, governor, false); +} + static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) { struct device *dev = priv->dev; struct device_node *np = dev->of_node; - struct generic_pm_domain *genpd = &priv->genpd; + struct rzg2l_cpg_pd *pd; int ret; - genpd->name = np->name; - genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | - GENPD_FLAG_ACTIVE_WAKEUP; - genpd->attach_dev = rzg2l_cpg_attach_dev; - genpd->detach_dev = rzg2l_cpg_detach_dev; - ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false); + pd = devm_kzalloc(priv->dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return -ENOMEM; + + pd->genpd.name = np->name; + pd->priv = priv; + ret = rzg2l_cpg_pd_setup(pd, true); if (ret) return ret; - ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd); + ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd); if (ret) return ret; - return of_genpd_add_provider_simple(np, genpd); + return of_genpd_add_provider_simple(np, &pd->genpd); +} + +static struct generic_pm_domain * +rzg2l_cpg_pm_domain_xlate(struct of_phandle_args *spec, void *data) +{ + struct generic_pm_domain *domain = ERR_PTR(-ENOENT); + struct genpd_onecell_data *genpd = data; + + if (spec->args_count != 1) + return ERR_PTR(-EINVAL); + + for (unsigned int i = 0; i < genpd->num_domains; i++) { + struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd, + genpd); + + if (pd->id == spec->args[0]) { + domain = &pd->genpd; + break; + } + } + + return domain; +} + +static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) +{ + const struct rzg2l_cpg_info *info = priv->info; + struct device *dev = priv->dev; + struct device_node *np = dev->of_node; + struct rzg2l_cpg_pm_domain *domains; + struct generic_pm_domain *parent; + u32 ncells; + int ret; + + ret = of_property_read_u32(np, "#power-domain-cells", &ncells); + if (ret) + return ret; + + /* For backward compatibility. */ + if (!ncells) + return rzg2l_cpg_add_clk_domain(priv); + + domains = devm_kzalloc(priv->dev, sizeof(*domains), GFP_KERNEL); + if (!domains) + return -ENOMEM; + + domains->domains = devm_kcalloc(priv->dev, info->num_pm_domains, + sizeof(struct generic_pm_domain *), GFP_KERNEL); + if (!domains->domains) + return -ENOMEM; + + domains->onecell_data.domains = domains->domains; + domains->onecell_data.num_domains = info->num_pm_domains; + domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate; + + ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data); + if (ret) + return ret; + + for (unsigned int i = 0; i < info->num_pm_domains; i++) { + bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON); + struct rzg2l_cpg_pd *pd; + + pd = devm_kzalloc(priv->dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return -ENOMEM; + + pd->genpd.name = info->pm_domains[i].name; + pd->conf = info->pm_domains[i].conf; + pd->id = info->pm_domains[i].id; + pd->priv = priv; + + ret = rzg2l_cpg_pd_setup(pd, always_on); + if (ret) + return ret; + + if (always_on) { + ret = rzg2l_cpg_power_on(&pd->genpd); + if (ret) + return ret; + } + + domains->domains[i] = &pd->genpd; + /* Parent should be on the very first entry of info->pm_domains[]. */ + if (info->pm_domains[i].flags & RZG2L_PD_F_PARENT) { + parent = &pd->genpd; + continue; + } + + ret = pm_genpd_add_subdomain(parent, &pd->genpd); + if (ret) + return ret; + } + + ret = of_genpd_add_provider_onecell(np, &domains->onecell_data); + if (ret) + return ret; + + /* Prepare for power down the BUSes in power down mode. */ + if (info->pm_domain_pwrdn_mstop) + writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP); + + return 0; } static int __init rzg2l_cpg_probe(struct platform_device *pdev) @@ -1697,7 +1896,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) if (error) return error; - error = rzg2l_cpg_add_clk_domain(priv); + error = rzg2l_cpg_add_pm_domains(priv); if (error) return error; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 6e38c8fc888c..00d12b04ba2f 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -27,6 +27,16 @@ #define CPG_PL6_ETH_SSEL (0x418) #define CPG_PL5_SDIV (0x420) #define CPG_RST_MON (0x680) +#define CPG_ACPU_MSTOP (0xB60) +#define CPG_MCPU2_MSTOP (0xB68) +#define CPG_PERI_COM_MSTOP (0xB6C) +#define CPG_PERI_CPU_MSTOP (0xB70) +#define CPG_PERI_DDR_MSTOP (0xB74) +#define CPG_REG1_MSTOP (0xB80) +#define CPG_TZCDDR_MSTOP (0xB84) +#define CPG_PWRDN_IP1 (0xBB0) +#define CPG_PWRDN_IP2 (0xBB4) +#define CPG_PWRDN_MSTOP (0xBC0) #define CPG_OTHERFUNC1_REG (0xBE8) #define CPG_SIPLL5_STBY_RESETB BIT(0) @@ -70,6 +80,8 @@ #define EXTAL_FREQ_IN_MEGA_HZ (24) +#define CPG_PWRDN_MSTOP_ENABLE (BIT(16) | BIT(0)) + /** * Definitions of CPG Core Clocks * @@ -234,6 +246,54 @@ struct rzg2l_reset { #define DEF_RST(_id, _off, _bit) \ DEF_RST_MON(_id, _off, _bit, -1) +/** + * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure + * @mstop: MSTOP configuration (MSB = register offset, LSB = bitmask) + * @pwrdn: PWRDN configuration (MSB = register offset, LSB = register bit) + */ +struct rzg2l_cpg_pm_domain_conf { + u32 mstop; + u32 pwrdn; +}; + +/** + * struct rzg2l_cpg_pm_domain_init_data - PM domain init data + * @name: PM domain name + * @conf: PM domain configuration + * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*) + * @id: PM domain ID (similar to the ones defined in + * include/dt-bindings/clock/-cpg.h) + */ +struct rzg2l_cpg_pm_domain_init_data { + const char * const name; + struct rzg2l_cpg_pm_domain_conf conf; + u32 flags; + u16 id; +}; + +#define DEF_PD(_name, _id, _mstop_conf, _pwrdn_conf, _flags) \ + { \ + .name = (_name), \ + .id = (_id), \ + .conf = { \ + .mstop = (_mstop_conf), \ + .pwrdn = (_pwrdn_conf), \ + }, \ + .flags = (_flags), \ + } + +#define MSTOP(name, bitmask) ((CPG_##name##_MSTOP) << 16 | (bitmask)) +#define MSTOP_OFF(conf) ((conf) >> 16) +#define MSTOP_MASK(conf) ((conf) & GENMASK(15, 0)) + +#define PWRDN(name, bit) ((CPG_PWRDN_##name) << 16 | BIT(bit)) +#define PWRDN_OFF(conf) ((conf) >> 16) +#define PWRDN_MASK(conf) ((conf) & GENMASK(15, 0)) + +/* Power domain flags. */ +#define RZG2L_PD_F_PARENT BIT(0) +#define RZG2L_PD_F_ALWAYS_ON BIT(1) + /** * struct rzg2l_cpg_info - SoC-specific CPG Description * @@ -252,6 +312,9 @@ struct rzg2l_reset { * @crit_mod_clks: Array with Module Clock IDs of critical clocks that * should not be disabled without a knowledgeable driver * @num_crit_mod_clks: Number of entries in crit_mod_clks[] + * @pm_domains: PM domains init data array + * @num_pm_domains: Number of PM domains + * @pm_domain_pwrdn_mstop: Specifies if PWRDN MSTOP is supported * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers */ struct rzg2l_cpg_info { @@ -278,6 +341,11 @@ struct rzg2l_cpg_info { const unsigned int *crit_mod_clks; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:00 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 08/17] clk: renesas: r9a07g043: Add initial support for power domains Date: Thu, 8 Feb 2024 14:42:51 +0200 Message-Id: <20240208124300.2740313-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Instantiate always-on power domain for R9A07G043 SoC. At the moment, all the IPs are part of this domain. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index acfb06cad441..3a7fddd1fa61 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -358,6 +358,11 @@ static const unsigned int r9a07g043_no_pm_mod_clks[] = { }; #endif +static const struct rzg2l_cpg_pm_domain_init_data r9a07g043_pm_domains[] = { + DEF_PD("always-on", R9A07G043_PD_ALWAYS_ON, 0, 0, + RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON), +}; + const struct rzg2l_cpg_info r9a07g043_cpg_info = { /* Core Clocks */ .core_clks = r9a07g043_core_clks, @@ -392,5 +397,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ #endif + /* Power domains. */ + .pm_domains = r9a07g043_pm_domains, + .num_pm_domains = ARRAY_SIZE(r9a07g043_pm_domains), + .has_clk_mon_regs = true, }; From patchwork Thu Feb 8 12:42:52 2024 Content-Type: text/plain; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:03 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 09/17] clk: renesas: r9a07g044: Add initial support for power domains Date: Thu, 8 Feb 2024 14:42:52 +0200 Message-Id: <20240208124300.2740313-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Instantiate always-on power domain for R9A07G044 SoC. At the moment, all the IPs are part of this domain. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 1047278c9079..3755e506fc65 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -443,6 +443,11 @@ static const unsigned int r9a07g044_no_pm_mod_clks[] = { MOD_CLK_BASE + R9A07G044_CRU_VCLK, }; +static const struct rzg2l_cpg_pm_domain_init_data r9a07g044_pm_domains[] = { + DEF_PD("always-on", R9A07G044_PD_ALWAYS_ON, 0, 0, + RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON), +}; + #ifdef CONFIG_CLK_R9A07G044 const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Core Clocks */ @@ -468,6 +473,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { .resets = r9a07g044_resets, .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ + /* PM domains */ + .pm_domains = r9a07g044_pm_domains, + .num_pm_domains = ARRAY_SIZE(r9a07g044_pm_domains), + .has_clk_mon_regs = true, }; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:05 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 10/17] clk: renesas: r9a08g045: Add support for power domains Date: Thu, 8 Feb 2024 14:42:53 +0200 Message-Id: <20240208124300.2740313-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Instantiate power domains for the currently enabled IPs of R9A08G045 SoC. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index c3e6da2de197..b06d8e93707f 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -240,6 +240,28 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_DMAC_ACLK, }; +static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { + DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, 0, 0, + RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON), + DEF_PD("gic", R9A08G045_PD_GIC, MSTOP(ACPU, BIT(3)), PWRDN(IP1, 2), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("ia55", R9A08G045_PD_IA55, MSTOP(PERI_CPU, BIT(13)), PWRDN(IP1, 3), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("dmac", R9A08G045_PD_DMAC, MSTOP(REG1, GENMASK(3, 0)), 0, + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("ddr", R9A08G045_PD_DDR, MSTOP(PERI_DDR, BIT(1)), PWRDN(IP2, 0), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("tzcddr", R9A08G045_PD_TZCDDR, MSTOP(TZCDDR, GENMASK(2, 0)), + PWRDN(IP2, 1), RZG2L_PD_F_ALWAYS_ON), + DEF_PD("otfde_ddr", R9A08G045_PD_OTFDE_DDR, 0, PWRDN(IP2, 2), RZG2L_PD_F_ALWAYS_ON), + DEF_PD("sdhi0", R9A08G045_PD_SDHI0, MSTOP(PERI_COM, BIT(0)), PWRDN(IP1, 13), 0), + DEF_PD("sdhi1", R9A08G045_PD_SDHI1, MSTOP(PERI_COM, BIT(1)), PWRDN(IP1, 14), 0), + DEF_PD("sdhi2", R9A08G045_PD_SDHI2, MSTOP(PERI_COM, BIT(11)), PWRDN(IP1, 15), 0), + DEF_PD("eth0", R9A08G045_PD_ETHER0, MSTOP(PERI_COM, BIT(2)), PWRDN(IP1, 11), 0), + DEF_PD("eth1", R9A08G045_PD_ETHER1, MSTOP(PERI_COM, BIT(3)), PWRDN(IP1, 12), 0), + DEF_PD("scif0", R9A08G045_PD_SCIF0, MSTOP(MCPU2, BIT(1)), 0, 0), +}; + const struct rzg2l_cpg_info r9a08g045_cpg_info = { /* Core Clocks */ .core_clks = r9a08g045_core_clks, @@ -260,5 +282,10 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = { .resets = r9a08g045_resets, .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ + /* Power domains */ + .pm_domains = r9a08g045_pm_domains, + .num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains), + .pm_domain_pwrdn_mstop = true, + .has_clk_mon_regs = true, }; From patchwork Thu Feb 8 12:42:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13549760 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AEFC7C095 for ; Thu, 8 Feb 2024 12:44:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:06 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 11/17] clk: renesas: r9a09g011: Add initial support for power domains Date: Thu, 8 Feb 2024 14:42:54 +0200 Message-Id: <20240208124300.2740313-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Instantiate always-on power domain for R9A09G011 SoC. At the moment, all the IPs are part of this domain. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a09g011-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index dda9f29dff33..9d090075f3be 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -245,6 +245,11 @@ static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A09G011_URT_PCLK, }; +static const struct rzg2l_cpg_pm_domain_init_data r9a09g011_pm_domains[] = { + DEF_PD("always-on", R9A09G011_PD_ALWAYS_ON, 0, 0, + RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON), +}; + const struct rzg2l_cpg_info r9a09g011_cpg_info = { /* Core Clocks */ .core_clks = r9a09g011_core_clks, @@ -265,5 +270,9 @@ const struct rzg2l_cpg_info r9a09g011_cpg_info = { .resets = r9a09g011_resets, .num_resets = ARRAY_SIZE(r9a09g011_resets), + /* PM domains */ + .pm_domains = r9a09g011_pm_domains, + .num_pm_domains = ARRAY_SIZE(r9a09g011_pm_domains), + .has_clk_mon_regs = false, }; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:09 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 12/17] arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs with proper flags Date: Thu, 8 Feb 2024 14:42:55 +0200 Message-Id: <20240208124300.2740313-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Ethernet IRQ GPIOs are marked as gpio-hog. Thus, these GPIOs are requested at probe w/o considering if there are other peripherals that needs them. The Ethernet IRQ GPIOs are shared w/ SDHI2. Selection b/w Ethernet and SDHI2 is done through a hardware switch. To avoid scenarios where one wants to boot with SDHI2 support and some SDHI pins are not propertly configured because of gpio-hog guard Ethernet IRQ GPIO with proper build flag. Fixes: 932ff0c802c6 ("arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 2b7fa5817d58..acac4666ae59 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -193,12 +193,14 @@ &sdhi2 { #endif &pinctrl { +#if SW_CONFIG3 == SW_ON eth0-phy-irq-hog { gpio-hog; gpios = ; input; line-name = "eth0-phy-irq"; }; +#endif eth0_pins: eth0 { txc { @@ -234,12 +236,14 @@ mux { }; }; +#if SW_CONFIG3 == SW_ON eth1-phy-irq-hog { gpio-hog; gpios = ; input; line-name = "eth1-phy-irq"; }; +#endif eth1_pins: eth1 { txc { From patchwork Thu Feb 8 12:42:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13549762 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DDF67D3FD for ; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:12 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 13/17] arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1> Date: Thu, 8 Feb 2024 14:42:56 +0200 Message-Id: <20240208124300.2740313-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Update CPG #power-domain-cells = <1> and move all the IPs to be part of the always on power domain as the driver has been modified to support multiple power domains. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 84 ++++++++++----------- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 6 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 3 files changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 8721f4c9fa0f..3e12f9dd3c6a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -138,7 +138,7 @@ mtu3: timer@10001200 { "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8"; clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>; #pwm-cells = <2>; status = "disabled"; @@ -159,7 +159,7 @@ ssi0: ssi@10049c00 { resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; dmas = <&dmac 0x2655>, <&dmac 0x2656>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -179,7 +179,7 @@ ssi1: ssi@1004a000 { resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; dmas = <&dmac 0x2659>, <&dmac 0x265a>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -198,7 +198,7 @@ ssi2: ssi@1004a400 { resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; dmas = <&dmac 0x265f>; dma-names = "rt"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -218,7 +218,7 @@ ssi3: ssi@1004a800 { resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; dmas = <&dmac 0x2661>, <&dmac 0x2662>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -234,7 +234,7 @@ spi0: spi@1004ac00 { resets = <&cpg R9A07G043_RSPI0_RST>; dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -252,7 +252,7 @@ spi1: spi@1004b000 { resets = <&cpg R9A07G043_RSPI1_RST>; dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -270,7 +270,7 @@ spi2: spi@1004b400 { resets = <&cpg R9A07G043_RSPI2_RST>; dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -291,7 +291,7 @@ scif0: serial@1004b800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; @@ -310,7 +310,7 @@ scif1: serial@1004bc00 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; status = "disabled"; }; @@ -329,7 +329,7 @@ scif2: serial@1004c000 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; status = "disabled"; }; @@ -348,7 +348,7 @@ scif3: serial@1004c400 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; status = "disabled"; }; @@ -367,7 +367,7 @@ scif4: serial@1004c800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; status = "disabled"; }; @@ -382,7 +382,7 @@ sci0: serial@1004d000 { interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_SCI0_RST>; status = "disabled"; }; @@ -397,7 +397,7 @@ sci1: serial@1004d400 { interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_SCI1_RST>; status = "disabled"; }; @@ -425,7 +425,7 @@ canfd: can@10050000 { resets = <&cpg R9A07G043_CANFD_RSTP_N>, <&cpg R9A07G043_CANFD_RSTC_N>; reset-names = "rstp_n", "rstc_n"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; channel0 { @@ -454,7 +454,7 @@ i2c0: i2c@10058000 { clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G043_I2C0_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -476,7 +476,7 @@ i2c1: i2c@10058400 { clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G043_I2C1_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -498,7 +498,7 @@ i2c2: i2c@10058800 { clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G043_I2C2_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -520,7 +520,7 @@ i2c3: i2c@10058c00 { clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G043_I2C3_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -534,7 +534,7 @@ adc: adc@10059000 { resets = <&cpg R9A07G043_ADC_PRESETN>, <&cpg R9A07G043_ADC_ADRST_N>; reset-names = "presetn", "adrst-n"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; #address-cells = <1>; @@ -554,7 +554,7 @@ tsu: thermal@10059400 { reg = <0 0x10059400 0 0x400>; clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; resets = <&cpg R9A07G043_TSU_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #thermal-sensor-cells = <1>; }; @@ -568,7 +568,7 @@ sbc: spi@10060000 { clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, <&cpg CPG_MOD R9A07G043_SPI_CLK>; resets = <&cpg R9A07G043_SPI_RST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -581,7 +581,7 @@ cpg: clock-controller@11010000 { clock-names = "extal"; #clock-cells = <2>; #reset-cells = <1>; - #power-domain-cells = <0>; + #power-domain-cells = <1>; }; sysc: system-controller@11020000 { @@ -599,7 +599,7 @@ pinctrl: pinctrl@11030000 { #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_GPIO_RSTN>, <&cpg R9A07G043_GPIO_PORT_RESETN>, <&cpg R9A07G043_GPIO_SPARE_RESETN>; @@ -635,7 +635,7 @@ dmac: dma-controller@11820000 { clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; clock-names = "main", "register"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; resets = <&cpg R9A07G043_DMAC_ARESETN>, <&cpg R9A07G043_DMAC_RST_ASYNC>; reset-names = "arst", "rst_async"; @@ -655,7 +655,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G043_SDHI0_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -671,7 +671,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G043_SDHI1_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -689,7 +689,7 @@ eth0: ethernet@11c20000 { <&cpg CPG_CORE R9A07G043_CLK_HP>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A07G043_ETH0_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -709,7 +709,7 @@ eth1: ethernet@11c30000 { <&cpg CPG_CORE R9A07G043_CLK_HP>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A07G043_ETH1_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -721,7 +721,7 @@ phyrst: usbphy-ctrl@11c40000 { reg = <0 0x11c40000 0 0x10000>; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; resets = <&cpg R9A07G043_USB_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; #reset-cells = <1>; status = "disabled"; }; @@ -736,7 +736,7 @@ ohci0: usb@11c50000 { <&cpg R9A07G043_USB_U2H0_HRESETN>; phys = <&usb2_phy0 1>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -750,7 +750,7 @@ ohci1: usb@11c70000 { <&cpg R9A07G043_USB_U2H1_HRESETN>; phys = <&usb2_phy1 1>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -765,7 +765,7 @@ ehci0: usb@11c50100 { phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -780,7 +780,7 @@ ehci1: usb@11c70100 { phys = <&usb2_phy1 2>; phy-names = "usb"; companion = <&ohci1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -793,7 +793,7 @@ usb2_phy0: usb-phy@11c50200 { <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>; #phy-cells = <1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -806,7 +806,7 @@ usb2_phy1: usb-phy@11c70200 { <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>; #phy-cells = <1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -825,7 +825,7 @@ hsusb: usb@11c60000 { renesas,buswait = <7>; phys = <&usb2_phy0 3>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -840,7 +840,7 @@ wdt0: watchdog@12800800 { ; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A07G043_WDT0_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -851,7 +851,7 @@ ostm0: timer@12801000 { interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; resets = <&cpg R9A07G043_OSTM0_PRESETZ>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -862,7 +862,7 @@ ostm1: timer@12801400 { interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; resets = <&cpg R9A07G043_OSTM1_PRESETZ>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; @@ -873,7 +873,7 @@ ostm2: timer@12801800 { interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; resets = <&cpg R9A07G043_OSTM2_PRESETZ>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 01d08ebb4a78..1ac71b9cbbb6 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -75,7 +75,7 @@ cru: video@10830000 { resets = <&cpg R9A07G043_CRU_PRESETN>, <&cpg R9A07G043_CRU_ARESETN>; reset-names = "presetn", "aresetn"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; ports { @@ -106,7 +106,7 @@ csi2: csi2@10830400 { resets = <&cpg R9A07G043_CRU_PRESETN>, <&cpg R9A07G043_CRU_CMN_RSTB>; reset-names = "presetn", "cmn-rstb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G043_PD_ALWAYS_ON>; status = "disabled"; ports { @@ -194,7 +194,7 @@ irqc: interrupt-controller@110a0000 { clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, <&cpg CPG_MOD R9A07G043_IA55_PCLK>; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:14 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 14/17] arm64: dts: renesas: r9a07g044: Update #power-domain-cells = <1> Date: Thu, 8 Feb 2024 14:42:57 +0200 Message-Id: <20240208124300.2740313-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Update CPG #power-domain-cells = <1> and move all the IPs to be part of the always on power domain as the driver has been modified to support multiple power domains. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 100 ++++++++++----------- 1 file changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 66f68fc2b241..c6aa62351b89 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -238,7 +238,7 @@ mtu3: timer@10001200 { "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8"; clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; #pwm-cells = <2>; status = "disabled"; @@ -259,7 +259,7 @@ ssi0: ssi@10049c00 { resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; dmas = <&dmac 0x2655>, <&dmac 0x2656>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -279,7 +279,7 @@ ssi1: ssi@1004a000 { resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; dmas = <&dmac 0x2659>, <&dmac 0x265a>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -298,7 +298,7 @@ ssi2: ssi@1004a400 { resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; dmas = <&dmac 0x265f>; dma-names = "rt"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -318,7 +318,7 @@ ssi3: ssi@1004a800 { resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; dmas = <&dmac 0x2661>, <&dmac 0x2662>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -334,7 +334,7 @@ spi0: spi@1004ac00 { resets = <&cpg R9A07G044_RSPI0_RST>; dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -352,7 +352,7 @@ spi1: spi@1004b000 { resets = <&cpg R9A07G044_RSPI1_RST>; dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -370,7 +370,7 @@ spi2: spi@1004b400 { resets = <&cpg R9A07G044_RSPI2_RST>; dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -390,7 +390,7 @@ scif0: serial@1004b800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; @@ -408,7 +408,7 @@ scif1: serial@1004bc00 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; status = "disabled"; }; @@ -426,7 +426,7 @@ scif2: serial@1004c000 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; status = "disabled"; }; @@ -444,7 +444,7 @@ scif3: serial@1004c400 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; status = "disabled"; }; @@ -462,7 +462,7 @@ scif4: serial@1004c800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; status = "disabled"; }; @@ -477,7 +477,7 @@ sci0: serial@1004d000 { interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_SCI0_RST>; status = "disabled"; }; @@ -492,7 +492,7 @@ sci1: serial@1004d400 { interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_SCI1_RST>; status = "disabled"; }; @@ -520,7 +520,7 @@ canfd: can@10050000 { resets = <&cpg R9A07G044_CANFD_RSTP_N>, <&cpg R9A07G044_CANFD_RSTC_N>; reset-names = "rstp_n", "rstc_n"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; channel0 { @@ -549,7 +549,7 @@ i2c0: i2c@10058000 { clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G044_I2C0_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -571,7 +571,7 @@ i2c1: i2c@10058400 { clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G044_I2C1_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -593,7 +593,7 @@ i2c2: i2c@10058800 { clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G044_I2C2_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -615,7 +615,7 @@ i2c3: i2c@10058c00 { clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G044_I2C3_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -629,7 +629,7 @@ adc: adc@10059000 { resets = <&cpg R9A07G044_ADC_PRESETN>, <&cpg R9A07G044_ADC_ADRST_N>; reset-names = "presetn", "adrst-n"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; #address-cells = <1>; @@ -667,7 +667,7 @@ tsu: thermal@10059400 { reg = <0 0x10059400 0 0x400>; clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; resets = <&cpg R9A07G044_TSU_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #thermal-sensor-cells = <1>; }; @@ -682,7 +682,7 @@ sbc: spi@10060000 { clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, <&cpg CPG_MOD R9A07G044_SPI_CLK>; resets = <&cpg R9A07G044_SPI_RST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -702,7 +702,7 @@ cru: video@10830000 { resets = <&cpg R9A07G044_CRU_PRESETN>, <&cpg R9A07G044_CRU_ARESETN>; reset-names = "presetn", "aresetn"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; ports { @@ -743,7 +743,7 @@ csi2: csi2@10830400 { resets = <&cpg R9A07G044_CRU_PRESETN>, <&cpg R9A07G044_CRU_CMN_RSTB>; reset-names = "presetn", "cmn-rstb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; ports { @@ -791,7 +791,7 @@ dsi: dsi@10850000 { <&cpg R9A07G044_MIPI_DSI_ARESET_N>, <&cpg R9A07G044_MIPI_DSI_PRESET_N>; reset-names = "rst", "arst", "prst"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -803,7 +803,7 @@ vspd: vsp@10870000 { <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; clock-names = "aclk", "pclk", "vclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_LCDC_RESET_N>; renesas,fcp = <&fcpvd>; }; @@ -816,7 +816,7 @@ fcpvd: fcp@10880000 { <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; clock-names = "aclk", "pclk", "vclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_LCDC_RESET_N>; }; @@ -827,7 +827,7 @@ cpg: clock-controller@11010000 { clock-names = "extal"; #clock-cells = <2>; #reset-cells = <1>; - #power-domain-cells = <0>; + #power-domain-cells = <1>; }; sysc: system-controller@11020000 { @@ -852,7 +852,7 @@ pinctrl: pinctrl@11030000 { interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; @@ -909,7 +909,7 @@ irqc: interrupt-controller@110a0000 { clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, <&cpg CPG_MOD R9A07G044_IA55_PCLK>; clock-names = "clk", "pclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_IA55_RESETN>; }; @@ -943,7 +943,7 @@ dmac: dma-controller@11820000 { clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; clock-names = "main", "register"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_DMAC_ARESETN>, <&cpg R9A07G044_DMAC_RST_ASYNC>; reset-names = "arst", "rst_async"; @@ -964,7 +964,7 @@ gpu: gpu@11840000 { <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; clock-names = "gpu", "bus", "bus_ace"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; resets = <&cpg R9A07G044_GPU_RESETN>, <&cpg R9A07G044_GPU_AXI_RESETN>, <&cpg R9A07G044_GPU_ACE_RESETN>; @@ -994,7 +994,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI0_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1010,7 +1010,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G044_SDHI1_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1028,7 +1028,7 @@ eth0: ethernet@11c20000 { <&cpg CPG_CORE R9A07G044_CLK_HP>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A07G044_ETH0_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1048,7 +1048,7 @@ eth1: ethernet@11c30000 { <&cpg CPG_CORE R9A07G044_CLK_HP>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A07G044_ETH1_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1060,7 +1060,7 @@ phyrst: usbphy-ctrl@11c40000 { reg = <0 0x11c40000 0 0x10000>; clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; resets = <&cpg R9A07G044_USB_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; #reset-cells = <1>; status = "disabled"; }; @@ -1075,7 +1075,7 @@ ohci0: usb@11c50000 { <&cpg R9A07G044_USB_U2H0_HRESETN>; phys = <&usb2_phy0 1>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1089,7 +1089,7 @@ ohci1: usb@11c70000 { <&cpg R9A07G044_USB_U2H1_HRESETN>; phys = <&usb2_phy1 1>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1104,7 +1104,7 @@ ehci0: usb@11c50100 { phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1119,7 +1119,7 @@ ehci1: usb@11c70100 { phys = <&usb2_phy1 2>; phy-names = "usb"; companion = <&ohci1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1132,7 +1132,7 @@ usb2_phy0: usb-phy@11c50200 { <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; resets = <&phyrst 0>; #phy-cells = <1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1145,7 +1145,7 @@ usb2_phy1: usb-phy@11c70200 { <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; resets = <&phyrst 1>; #phy-cells = <1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1164,7 +1164,7 @@ hsusb: usb@11c60000 { renesas,buswait = <7>; phys = <&usb2_phy0 3>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1179,7 +1179,7 @@ wdt0: watchdog@12800800 { ; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A07G044_WDT0_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1194,7 +1194,7 @@ wdt1: watchdog@12800c00 { ; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A07G044_WDT1_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1205,7 +1205,7 @@ ostm0: timer@12801000 { interrupts = ; clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; resets = <&cpg R9A07G044_OSTM0_PRESETZ>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1216,7 +1216,7 @@ ostm1: timer@12801400 { interrupts = ; clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; resets = <&cpg R9A07G044_OSTM1_PRESETZ>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G044_PD_ALWAYS_ON>; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:16 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 15/17] arm64: dts: renesas: r9a07g054: Update #power-domain-cells = <1> Date: Thu, 8 Feb 2024 14:42:58 +0200 Message-Id: <20240208124300.2740313-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Update CPG #power-domain-cells = <1> and move all the IPs to be part of the always on power domain as the driver has been modified to support multiple power domains. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 100 ++++++++++----------- 1 file changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 1f1d481dc783..15fc6e6f79ce 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -238,7 +238,7 @@ mtu3: timer@10001200 { "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8"; clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>; #pwm-cells = <2>; status = "disabled"; @@ -259,7 +259,7 @@ ssi0: ssi@10049c00 { resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; dmas = <&dmac 0x2655>, <&dmac 0x2656>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -279,7 +279,7 @@ ssi1: ssi@1004a000 { resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; dmas = <&dmac 0x2659>, <&dmac 0x265a>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -298,7 +298,7 @@ ssi2: ssi@1004a400 { resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; dmas = <&dmac 0x265f>; dma-names = "rt"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -318,7 +318,7 @@ ssi3: ssi@1004a800 { resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; dmas = <&dmac 0x2661>, <&dmac 0x2662>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -334,7 +334,7 @@ spi0: spi@1004ac00 { resets = <&cpg R9A07G054_RSPI0_RST>; dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -352,7 +352,7 @@ spi1: spi@1004b000 { resets = <&cpg R9A07G054_RSPI1_RST>; dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -370,7 +370,7 @@ spi2: spi@1004b400 { resets = <&cpg R9A07G054_RSPI2_RST>; dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; dma-names = "tx", "rx"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -391,7 +391,7 @@ scif0: serial@1004b800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; @@ -410,7 +410,7 @@ scif1: serial@1004bc00 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>; status = "disabled"; }; @@ -429,7 +429,7 @@ scif2: serial@1004c000 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>; status = "disabled"; }; @@ -448,7 +448,7 @@ scif3: serial@1004c400 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>; status = "disabled"; }; @@ -467,7 +467,7 @@ scif4: serial@1004c800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>; status = "disabled"; }; @@ -482,7 +482,7 @@ sci0: serial@1004d000 { interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_SCI0_RST>; status = "disabled"; }; @@ -497,7 +497,7 @@ sci1: serial@1004d400 { interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_SCI1_RST>; status = "disabled"; }; @@ -525,7 +525,7 @@ canfd: can@10050000 { resets = <&cpg R9A07G054_CANFD_RSTP_N>, <&cpg R9A07G054_CANFD_RSTC_N>; reset-names = "rstp_n", "rstc_n"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; channel0 { @@ -554,7 +554,7 @@ i2c0: i2c@10058000 { clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G054_I2C0_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -576,7 +576,7 @@ i2c1: i2c@10058400 { clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G054_I2C1_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -598,7 +598,7 @@ i2c2: i2c@10058800 { clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G054_I2C2_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -620,7 +620,7 @@ i2c3: i2c@10058c00 { clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G054_I2C3_MRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -634,7 +634,7 @@ adc: adc@10059000 { resets = <&cpg R9A07G054_ADC_PRESETN>, <&cpg R9A07G054_ADC_ADRST_N>; reset-names = "presetn", "adrst-n"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; #address-cells = <1>; @@ -672,7 +672,7 @@ tsu: thermal@10059400 { reg = <0 0x10059400 0 0x400>; clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; resets = <&cpg R9A07G054_TSU_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #thermal-sensor-cells = <1>; }; @@ -687,7 +687,7 @@ sbc: spi@10060000 { clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, <&cpg CPG_MOD R9A07G054_SPI_CLK>; resets = <&cpg R9A07G054_SPI_RST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -707,7 +707,7 @@ cru: video@10830000 { resets = <&cpg R9A07G054_CRU_PRESETN>, <&cpg R9A07G054_CRU_ARESETN>; reset-names = "presetn", "aresetn"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; ports { @@ -748,7 +748,7 @@ csi2: csi2@10830400 { resets = <&cpg R9A07G054_CRU_PRESETN>, <&cpg R9A07G054_CRU_CMN_RSTB>; reset-names = "presetn", "cmn-rstb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; ports { @@ -796,7 +796,7 @@ dsi: dsi@10850000 { <&cpg R9A07G054_MIPI_DSI_ARESET_N>, <&cpg R9A07G054_MIPI_DSI_PRESET_N>; reset-names = "rst", "arst", "prst"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -809,7 +809,7 @@ vspd: vsp@10870000 { <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; clock-names = "aclk", "pclk", "vclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_LCDC_RESET_N>; renesas,fcp = <&fcpvd>; }; @@ -822,7 +822,7 @@ fcpvd: fcp@10880000 { <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; clock-names = "aclk", "pclk", "vclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_LCDC_RESET_N>; }; @@ -833,7 +833,7 @@ cpg: clock-controller@11010000 { clock-names = "extal"; #clock-cells = <2>; #reset-cells = <1>; - #power-domain-cells = <0>; + #power-domain-cells = <1>; }; sysc: system-controller@11020000 { @@ -859,7 +859,7 @@ pinctrl: pinctrl@11030000 { interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_GPIO_RSTN>, <&cpg R9A07G054_GPIO_PORT_RESETN>, <&cpg R9A07G054_GPIO_SPARE_RESETN>; @@ -916,7 +916,7 @@ irqc: interrupt-controller@110a0000 { clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>, <&cpg CPG_MOD R9A07G054_IA55_PCLK>; clock-names = "clk", "pclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_IA55_RESETN>; }; @@ -950,7 +950,7 @@ dmac: dma-controller@11820000 { clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; clock-names = "main", "register"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_DMAC_ARESETN>, <&cpg R9A07G054_DMAC_RST_ASYNC>; reset-names = "arst", "rst_async"; @@ -971,7 +971,7 @@ gpu: gpu@11840000 { <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; clock-names = "gpu", "bus", "bus_ace"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; resets = <&cpg R9A07G054_GPU_RESETN>, <&cpg R9A07G054_GPU_AXI_RESETN>, <&cpg R9A07G054_GPU_ACE_RESETN>; @@ -1001,7 +1001,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G054_SDHI0_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1017,7 +1017,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A07G054_SDHI1_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1035,7 +1035,7 @@ eth0: ethernet@11c20000 { <&cpg CPG_CORE R9A07G054_CLK_HP>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A07G054_ETH0_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1055,7 +1055,7 @@ eth1: ethernet@11c30000 { <&cpg CPG_CORE R9A07G054_CLK_HP>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A07G054_ETH1_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1067,7 +1067,7 @@ phyrst: usbphy-ctrl@11c40000 { reg = <0 0x11c40000 0 0x10000>; clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; resets = <&cpg R9A07G054_USB_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; #reset-cells = <1>; status = "disabled"; }; @@ -1082,7 +1082,7 @@ ohci0: usb@11c50000 { <&cpg R9A07G054_USB_U2H0_HRESETN>; phys = <&usb2_phy0 1>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1096,7 +1096,7 @@ ohci1: usb@11c70000 { <&cpg R9A07G054_USB_U2H1_HRESETN>; phys = <&usb2_phy1 1>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1111,7 +1111,7 @@ ehci0: usb@11c50100 { phys = <&usb2_phy0 2>; phy-names = "usb"; companion = <&ohci0>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1126,7 +1126,7 @@ ehci1: usb@11c70100 { phys = <&usb2_phy1 2>; phy-names = "usb"; companion = <&ohci1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1139,7 +1139,7 @@ usb2_phy0: usb-phy@11c50200 { <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; resets = <&phyrst 0>; #phy-cells = <1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1152,7 +1152,7 @@ usb2_phy1: usb-phy@11c70200 { <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; resets = <&phyrst 1>; #phy-cells = <1>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1171,7 +1171,7 @@ hsusb: usb@11c60000 { renesas,buswait = <7>; phys = <&usb2_phy0 3>; phy-names = "usb"; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1186,7 +1186,7 @@ wdt0: watchdog@12800800 { ; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A07G054_WDT0_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1201,7 +1201,7 @@ wdt1: watchdog@12800c00 { ; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A07G054_WDT1_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1212,7 +1212,7 @@ ostm0: timer@12801000 { interrupts = ; clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; resets = <&cpg R9A07G054_OSTM0_PRESETZ>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1223,7 +1223,7 @@ ostm1: timer@12801400 { interrupts = ; clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; resets = <&cpg R9A07G054_OSTM1_PRESETZ>; - power-domains = <&cpg>; + power-domains = <&cpg R9A07G054_PD_ALWAYS_ON>; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:19 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 16/17] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1> Date: Thu, 8 Feb 2024 14:42:59 +0200 Message-Id: <20240208124300.2740313-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Update CPG #power-domain-cells = <1> and move all the IPs to be part of the IP specific power domain as the driver has been modified to support multiple power domains. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index dfee878c0f49..11be621aaa82 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -62,7 +62,7 @@ scif0: serial@1004b800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SCIF0>; resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; @@ -74,7 +74,7 @@ cpg: clock-controller@11010000 { clock-names = "extal"; #clock-cells = <2>; #reset-cells = <1>; - #power-domain-cells = <0>; + #power-domain-cells = <1>; }; sysc: system-controller@11020000 { @@ -99,7 +99,7 @@ pinctrl: pinctrl@11030000 { interrupt-parent = <&irqc>; gpio-ranges = <&pinctrl 0 0 152>; clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>; resets = <&cpg R9A08G045_GPIO_RSTN>, <&cpg R9A08G045_GPIO_PORT_RESETN>, <&cpg R9A08G045_GPIO_SPARE_RESETN>; @@ -168,7 +168,7 @@ irqc: interrupt-controller@11050000 { clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, <&cpg CPG_MOD R9A08G045_IA55_PCLK>; clock-names = "clk", "pclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>; resets = <&cpg R9A08G045_IA55_RESETN>; }; @@ -183,7 +183,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI0_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI0>; status = "disabled"; }; @@ -198,7 +198,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI1_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI1>; status = "disabled"; }; @@ -213,7 +213,7 @@ sdhi2: mmc@11c20000 { <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI2_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI2>; status = "disabled"; }; @@ -230,7 +230,7 @@ eth0: ethernet@11c30000 { <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A08G045_ETH0_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ETHER0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -249,7 +249,7 @@ eth1: ethernet@11c40000 { <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A08G045_ETH1_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ETHER1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -275,7 +275,7 @@ wdt0: watchdog@12800800 { ; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A08G045_WDT0_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_WDT0>; status = "disabled"; }; }; From patchwork Thu Feb 8 12:43:00 2024 Content-Type: text/plain; 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([82.78.167.45]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0041047382b76sm790244wmq.37.2024.02.08.04.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 04:44:20 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 17/17] arm64: dts: renesas: r9a09g011: Update #power-domain-cells = <1> Date: Thu, 8 Feb 2024 14:43:00 +0200 Message-Id: <20240208124300.2740313-18-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Update CPG #power-domain-cells = <1> and move all the IPs to be part of the always on power domain as the driver has been modified to support multiple power domains. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 28 +++++++++++----------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 50ed66d42a24..74af0f730b89 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -81,7 +81,7 @@ sdhi0: mmc@85000000 { <&cpg CPG_MOD R9A09G011_SDI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A09G011_SDI0_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; status = "disabled"; }; @@ -97,7 +97,7 @@ sdhi1: mmc@85010000 { <&cpg CPG_MOD R9A09G011_SDI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A09G011_SDI1_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; status = "disabled"; }; @@ -113,7 +113,7 @@ emmc: mmc@85020000 { <&cpg CPG_MOD R9A09G011_EMM_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A09G011_EMM_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; status = "disabled"; }; @@ -129,7 +129,7 @@ usb3drd: usb3drd@85070400 { <&cpg CPG_MOD R9A09G011_USB_PCLK>; clock-names = "axi", "reg"; resets = <&cpg R9A09G011_USB_DRD_RESET>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; ranges; #address-cells = <2>; #size-cells = <2>; @@ -144,7 +144,7 @@ usb3host: usb@85060000 { <&cpg CPG_MOD R9A09G011_USB_PCLK>; clock-names = "axi", "reg"; resets = <&cpg R9A09G011_USB_ARESETN_H>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; status = "disabled"; }; @@ -157,7 +157,7 @@ usb3peri: usb3peri@85070000 { <&cpg CPG_MOD R9A09G011_USB_PCLK>; clock-names = "axi", "reg"; resets = <&cpg R9A09G011_USB_ARESETN_P>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; status = "disabled"; }; }; @@ -207,7 +207,7 @@ avb: ethernet@a3300000 { <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; clock-names = "axi", "chi", "gptp"; resets = <&cpg R9A09G011_ETH0_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -220,7 +220,7 @@ cpg: clock-controller@a3500000 { clock-names = "extal"; #clock-cells = <2>; #reset-cells = <1>; - #power-domain-cells = <0>; + #power-domain-cells = <1>; }; pwc: pwc@a3700000 { @@ -244,7 +244,7 @@ csi0: spi@a4020000 { <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>; clock-names = "csiclk", "pclk"; resets = <&cpg R9A09G011_CSI_GPG_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -258,7 +258,7 @@ csi4: spi@a4020200 { <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>; clock-names = "csiclk", "pclk"; resets = <&cpg R9A09G011_CSI_GPH_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -274,7 +274,7 @@ i2c0: i2c@a4030000 { interrupt-names = "tia", "tis"; clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>; resets = <&cpg R9A09G011_IIC_GPA_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; status = "disabled"; }; @@ -288,7 +288,7 @@ i2c2: i2c@a4030100 { interrupt-names = "tia", "tis"; clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>; resets = <&cpg R9A09G011_IIC_GPB_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; status = "disabled"; }; @@ -311,7 +311,7 @@ wdt0: watchdog@a4050000 { clock-names = "pclk", "oscclk"; interrupts = ; resets = <&cpg R9A09G011_WDT0_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; status = "disabled"; }; @@ -361,7 +361,7 @@ pinctrl: pinctrl@b6250000 { , ; clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>; - power-domains = <&cpg>; + power-domains = <&cpg R9A09G011_PD_ALWAYS_ON>; resets = <&cpg R9A09G011_PFC_PRESETN>; }; };