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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id vk9-20020a170907cbc900b00a36c499c935sm450575ejc.43.2024.02.08.22.41.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 22:41:26 -0800 (PST) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Daniel Henrique Barboza , Andrew Jones Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , Weiwei Li , Liu Zhiwei Subject: [RFC PATCH v2 1/4] RISC-V: Add support for Ssdtso Date: Fri, 9 Feb 2024 07:41:14 +0100 Message-ID: <20240209064117.2746701-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209064117.2746701-1-christoph.muellner@vrull.eu> References: <20240209064117.2746701-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Ssdtso extension introduces a DTSO field to the {m,s,h}envcfg register to enable TSO at run-time. Building on top of Ztso support, this patch treats Ssdtso just like Ztso (always execute in TSO mode), which should be fine from a correctness perspective. Similar like Ztso, this is expected to have little overhead on host machines that operate in TSO mode (e.g. x86). However, executing the TSO fences on guests without TSO, will have a negative performance impact, regardless if TSO is enabled in the guest or not (e.g. running a RV guest with Ssdtso and disabled DTSO bit on an aarch64 host). Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 8 ++++++-- target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 14 +++++++++++--- target/riscv/translate.c | 2 +- 5 files changed, 22 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b679ecd8c7..ee90c09600 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -174,6 +174,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(ssdtso, PRIV_VERSION_1_12_0, ext_ssdtso), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -950,9 +951,11 @@ static void riscv_cpu_reset_hold(Object *obj) env->two_stage_lookup = false; env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); + (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0) | + (cpu->cfg.ext_ztso && cpu->cfg.ext_ssdtso ? MENVCFG_DTSO : 0); env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); + (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0) | + (cpu->cfg.ext_ztso && cpu->cfg.ext_ssdtso ? HENVCFG_DTSO : 0); /* Initialized default priorities of local interrupts. */ for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { @@ -1460,6 +1463,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false), MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), + MULTI_EXT_CFG_BOOL("ssdtso", ext_ssdtso, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fc2068ee4d..e11191977d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -744,6 +744,7 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_DTSO BIT(8) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -757,11 +758,13 @@ typedef enum RISCVException { #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE +#define SENVCFG_DTSO MENVCFG_DTSO #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_DTSO MENVCFG_DTSO #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index afba8ed0b2..606ae5a120 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -73,6 +73,7 @@ struct RISCVCPUConfig { bool ext_zihpm; bool ext_ztso; bool ext_smstateen; + bool ext_ssdtso; bool ext_sstc; bool ext_svadu; bool ext_svinval; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4e8ac13b9..c06b674994 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2058,7 +2058,9 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); - uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; + uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | + MENVCFG_CBZE | + (cfg->ext_ssdtso && !cfg->ext_ztso ? MENVCFG_DTSO : 0); if (riscv_cpu_mxl(env) == MXL_RV64) { mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | @@ -2108,7 +2110,10 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno, static RISCVException write_senvcfg(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; + const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); + uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | + SENVCFG_CBZE | + (cfg->ext_ssdtso && !cfg->ext_ztso ? SENVCFG_DTSO : 0); RISCVException ret; ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); @@ -2143,7 +2148,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, static RISCVException write_henvcfg(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); + uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | + HENVCFG_CBZE | + (cfg->ext_ssdtso && !cfg->ext_ztso ? HENVCFG_DTSO : 0); RISCVException ret; ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ea5d52b2ef..f0d4db0b64 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1198,7 +1198,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); - ctx->ztso = cpu->cfg.ext_ztso; + ctx->ztso = cpu->cfg.ext_ztso || cpu->cfg.ext_ssdtso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false; From patchwork Fri Feb 9 06:41:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 13550903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03AC5C4828F for ; Fri, 9 Feb 2024 06:42:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rYKZy-0005x1-8Z; Fri, 09 Feb 2024 01:41:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rYKZn-0005kn-Gn for qemu-devel@nongnu.org; Fri, 09 Feb 2024 01:41:32 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rYKZl-0002OE-HY for qemu-devel@nongnu.org; Fri, 09 Feb 2024 01:41:31 -0500 Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-558f523c072so918301a12.2 for ; Thu, 08 Feb 2024 22:41:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1707460888; x=1708065688; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EUtumchVWAjnFsnLqrfLNxKYwp3IzTxvepBmSvQHMis=; b=USnNRk/B5IDja+g17J+m/dD/Xk7l7RxMTxxANfYgv69tquNdeLLa1tSesk3dRJkD3A KbY5BeaRYI+wXV9haQVmNI4bqhwOJ75jztvdvQnDBv7Q91DWigz+NugdGMzkgSvTws6p TlVjmw1CgQVizz+EPPRKci4hwjbvkiQJFtH4BhIOPTZ35kDHuZKc23UCCNI2sn3680It PaBkLF3tYq66LtwQsjIL8QHejva6H74NCYtbX9bV6LAjhWPE1cFSp4gneZiA7KQUfv7A Oi2zgKUWH9axdyMi7QY3+Dijla2ItL4Ctm0prtovtG4ZDc2F/uFQzohWrIBVuvLkWyoS IQMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707460888; x=1708065688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EUtumchVWAjnFsnLqrfLNxKYwp3IzTxvepBmSvQHMis=; b=nHwBjo2rpaVcK62/ay4OnuFTzBHp3I0nI9vgtByY+Rj45fW3mABLvpmJwoIrUuNBzk FpzglVeqcYPT5cf/1nDGuuLcAblBrBWefazHPSj4sprerdUf1dgq1hWEBF1l+XFnpTt2 e+h18imT5HcEPbAXf01yc8n6r1BnSP/H97T8s2EdsSvgzhMFbWi7RAtT4j0vF6x6fs75 t8/yDw5k93kt5CTFMaiz+R9m7ubNN7VSUBoGOZyHLsS0mQkF6ojJfFSyJSXjkepkzc+w 9/uAdJ5FPz5OVtq052GLLXFtnXz0nuPtmnf3/uC0K7CcsHeJAqcH7X4jsy9BDzzSS6jy EuEA== X-Gm-Message-State: AOJu0YyKthsEuRYfN7wIkrpo2JVbuo9Jy32hcM+WS3cnMiZGV9onElCa DrHuQdI38RjsyeXkQx4aPitQjgXdGbu+cYFq4cleJEFK80NoHbzIQN8zXlRfVSk= X-Google-Smtp-Source: AGHT+IGsK3WqE/n5HdtWollG/0f1PKEWUQcdsSUUHRmuIs1eIfzrw80IAhDLp9C+l4mUaBLJRqeiSQ== X-Received: by 2002:a17:906:b2c9:b0:a37:76df:be40 with SMTP id cf9-20020a170906b2c900b00a3776dfbe40mr469668ejb.36.1707460887941; Thu, 08 Feb 2024 22:41:27 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWmMnpgfP7SL9AMOeYk/4RPOp12RZO/c3RGu+ogxsjxT/R3WKCdoR2U6r0eKrwFHykbSSVctB0wHpjiQsbytjigZrYZ3ifQwbGm/9K6bl33U8UTUSM/lKaoLPbJVCNPmBnQrqHCpDpPBwkPM7LR0e6Xa593sWHnoscIDAc1MlEU82JfzACVm9SPJ+s6ISMCyjSuIa3kQ/Rb7Oo7UyudanXpaXYWhjh6gmKzVrHW6yyzMljVtHc6C/a8LdrHQ5aa3WK0dNF8/FMUB6B1AJruAFcJWUvC1SUSyCy2WblzBKoQF1Af5Vi0RJYFD+/ttLFdfGzjQfQMjmjQc7HZ5JIsHJxRn1pZQDHqNZrujw== Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id vk9-20020a170907cbc900b00a36c499c935sm450575ejc.43.2024.02.08.22.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 22:41:27 -0800 (PST) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Daniel Henrique Barboza , Andrew Jones Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , Laurent Vivier Subject: [RFC PATCH v2 2/4] linux-user/riscv: Add Ssdtso extension to hwprobe Date: Fri, 9 Feb 2024 07:41:15 +0100 Message-ID: <20240209064117.2746701-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209064117.2746701-1-christoph.muellner@vrull.eu> References: <20240209064117.2746701-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch exposes Ssdtso via hwprobe in QEMU's user space emulator. Signed-off-by: Christoph Müllner --- linux-user/syscall.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 24fa11d946..bf0d66b8a8 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8829,6 +8829,7 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count) #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) +#define RISCV_HWPROBE_EXT_SSDTSO (1ULL << 36) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) @@ -8947,6 +8948,8 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env, RISCV_HWPROBE_EXT_ZACAS : 0; value |= cfg->ext_zicond ? RISCV_HWPROBE_EXT_ZICOND : 0; + value |= cfg->ext_ssdtso ? + RISCV_HWPROBE_EXT_SSDTSO : 0; __put_user(value, &pair->value); break; case RISCV_HWPROBE_KEY_CPUPERF_0: From patchwork Fri Feb 9 06:41:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 13550905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BA4AC4829D for ; Fri, 9 Feb 2024 06:42:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rYKZs-0005tp-K0; Fri, 09 Feb 2024 01:41:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rYKZo-0005mq-PA for qemu-devel@nongnu.org; Fri, 09 Feb 2024 01:41:34 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rYKZm-0002Oc-Nf for qemu-devel@nongnu.org; Fri, 09 Feb 2024 01:41:32 -0500 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a3916c1f9b0so73545566b.1 for ; Thu, 08 Feb 2024 22:41:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1707460889; x=1708065689; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ytTPrgvmcSAVYKXxwo9D3fPgoAujr29L9BQ2PXjBjJU=; b=GUwlIrfMJLi+m0QhrP+rDM9csRnx8WhKzdvziezTCKCl4/Hyzfg0oJHXxvsLPa6UkC vw+2g7YcD9C9XE2W5RliUMejAb5qA4cabirr2q1i87/P9t0VCiFdo2YMcWHUGpBe4/oD 4WbQFiUKMqjI6Urq6VaTBQ/mn7QXz178lismOKkYi9l8/1c51AHOdzC5z16sW+VR1eF+ gbxMtxadjIGI5BI1Kt03UFRQKJbNcN6cDeCNyeJ3vQ0aKSfW9Iatyp97h5N/PBR8DIM0 r3A7Ie+83zib4EhQk0CwDkxyVEOrm0n5HIr0u15Cmr64mJ9rw4EvffXAe5+wCTwfM3+1 MKMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707460889; x=1708065689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ytTPrgvmcSAVYKXxwo9D3fPgoAujr29L9BQ2PXjBjJU=; b=bvdAQ96STLoZ6JYCyW3n34KQFX1I8vORF0FASpqM4uBRyIQeEeZaF6+zWbDqsZoScD wtjQtxJv1iWBygACXf9FYuv+ZehLujxR3EMwOhXyTDJpWCGlNFISDTI+8fq/D1vG7gm8 J2LtrW0OG2p2etvTGyVSQLI/WAqnwb+M2bCBMSK4OgRSyPM5xf15AYucrnScJG8ZCaOc iRkIMfsBUhvtM3dkk4LWodY6qSIOVrC3PbAi5JT8Rrl7Cu2FvFEBI3fTg/enuODpVpBU i/r00c3GBI2g7ibpREr76R7z8yl5Hl23lJZcEl1oybc98NSdWsv2X+YFmAhVT+hermNg dAWg== X-Gm-Message-State: AOJu0Yzj295KE9T4WOjccZcG6k3GiyxAmWtmSLOm18QY8hb3RkLup0ec 3ZYL6aMlFp62A74Y7B3knPmuOjJg5sHJhEExJKXm+/U9n5NMrncdiCOKK3HOMIM= X-Google-Smtp-Source: AGHT+IFVg4lO8zkHhRZCGeDc2MDr2YQcPD8It/U0CsIDnPbxPJxfIBzw6pOBCu/rKHCc+ukuID9cwQ== X-Received: by 2002:a17:906:3b5a:b0:a3b:721a:9162 with SMTP id h26-20020a1709063b5a00b00a3b721a9162mr409548ejf.66.1707460889359; Thu, 08 Feb 2024 22:41:29 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWR+BGDglxI4JrKwy7PM9PtB7wk/zlH9clO2KU+SaMEc5HYGP6818LRYYzni3w9RdJNoXM91X8rVEr5nFYgjOIIoZB0f99OlA4LQ3LGVCpO6eqW7bv9lj+ElVSDNGrEE1uJcq9QvOJhO2C43pMYwn7oP3VU/SCF0Gs45ZvTINicfDhEItIi1K6p7xy0HLGlWL/JsInD6RN5f17TlbR2Oom/RpL1VjEQRnwWD1gr5KxC14yPlp+TYobLea7Lz4QsCNP2Alo0GyMQgr6g8qhycZvbs7o4AxOUBVem2ahTmphQf7Y6VI/0kK4lIo/2R2ytHRhv3iz9bpVHsWxJLi2CoA8jgZxakVm4JK1KHg== Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id vk9-20020a170907cbc900b00a36c499c935sm450575ejc.43.2024.02.08.22.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 22:41:28 -0800 (PST) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Daniel Henrique Barboza , Andrew Jones Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , Laurent Vivier Subject: [RFC PATCH v2 3/4] linux-user/prctl: Add dynamic memory consistency model prctl API Date: Fri, 9 Feb 2024 07:41:16 +0100 Message-ID: <20240209064117.2746701-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209064117.2746701-1-christoph.muellner@vrull.eu> References: <20240209064117.2746701-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch implements the prctl calls to set and get the current memory consistency model. This patch does not implement any real functionality but just defines the relevant hooks, where target code take over. Signed-off-by: Christoph Müllner --- linux-user/syscall.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index bf0d66b8a8..cf0845a074 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6309,6 +6309,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) # define PR_SME_VL_LEN_MASK 0xffff # define PR_SME_VL_INHERIT (1 << 17) #endif +#ifndef PR_SET_MEMORY_CONSISTENCY_MODEL +# define PR_SET_MEMORY_CONSISTENCY_MODEL 71 +# define PR_GET_MEMORY_CONSISTENCY_MODEL 72 +# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO 1 +# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO 2 +#endif #include "target_prctl.h" @@ -6355,6 +6361,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_sme_set_vl #define do_prctl_sme_set_vl do_prctl_inval1 #endif +#ifndef do_prctl_set_memory_consistency_model +#define do_prctl_set_memory_consistency_model do_prctl_inval1 +#endif +#ifndef do_prctl_get_memory_consistency_model +#define do_prctl_get_memory_consistency_model do_prctl_inval0 +#endif static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6481,6 +6493,11 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, /* Disable to prevent the target disabling stuff we need. */ return -TARGET_EINVAL; + case PR_SET_MEMORY_CONSISTENCY_MODEL: + return do_prctl_set_memory_consistency_model(env, arg2); + case PR_GET_MEMORY_CONSISTENCY_MODEL: + return do_prctl_get_memory_consistency_model(env); + default: qemu_log_mask(LOG_UNIMP, "Unsupported prctl: " TARGET_ABI_FMT_ld "\n", option); From patchwork Fri Feb 9 06:41:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 13550902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 222B6C48297 for ; Fri, 9 Feb 2024 06:42:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rYKa0-0005yf-6w; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id vk9-20020a170907cbc900b00a36c499c935sm450575ejc.43.2024.02.08.22.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 22:41:30 -0800 (PST) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Daniel Henrique Barboza , Andrew Jones Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , Laurent Vivier , Weiwei Li , Liu Zhiwei Subject: [RFC PATCH v2 4/4] linux-user/riscv: Implement dynamic memory consistency model support Date: Fri, 9 Feb 2024 07:41:17 +0100 Message-ID: <20240209064117.2746701-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240209064117.2746701-1-christoph.muellner@vrull.eu> References: <20240209064117.2746701-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch implements the dynamic memory consistency model prctl calls for RISC-V. The implementation introduces a single boolean variable to keep the DTSO state. Signed-off-by: Christoph Müllner --- linux-user/riscv/target_prctl.h | 76 ++++++++++++++++++++++++++++++++- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 1 + 3 files changed, 81 insertions(+), 1 deletion(-) diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prctl.h index eb53b31ad5..e54321d872 100644 --- a/linux-user/riscv/target_prctl.h +++ b/linux-user/riscv/target_prctl.h @@ -1 +1,75 @@ -/* No special prctl support required. */ +/* + * RISC-V specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef RISCV_TARGET_PRCTL_H +#define RISCV_TARGET_PRCTL_H + +static inline void riscv_dtso_set_enable(CPURISCVState *env, bool enable) +{ + env->dtso_ena = enable; +} + +static inline bool riscv_dtso_is_enabled(CPURISCVState *env) +{ + return env->dtso_ena; +} + +static abi_long do_prctl_set_memory_consistency_model(CPUArchState *cpu_env, + abi_long arg2) +{ + RISCVCPU *cpu = env_archcpu(cpu_env); + bool dtso_ena_old = riscv_dtso_is_enabled(cpu_env); + bool dtso_ena_new; + bool has_dtso = cpu->cfg.ext_ssdtso; + + switch (arg2) { + case PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO: + dtso_ena_new = false; + break; + case PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO: + dtso_ena_new = true; + break; + default: + return -TARGET_EINVAL; + } + + /* No change requested. */ + if (dtso_ena_old == dtso_ena_new) + return 0; + + /* Enabling TSO only works if DTSO is available. */ + if (dtso_ena_new && !has_dtso) + return -TARGET_EINVAL; + + /* Switchin TSO->WMO is not allowed. */ + if (!dtso_ena_new) + return -TARGET_EINVAL; + + riscv_dtso_set_enable(cpu_env, dtso_ena_new); + + /* + * No need to reschedule other threads, because the emulation + * of DTSO is fine (from a memory model view) if they are out + * of sync until they will eventually reschedule. + */ + + return 0; +} + +#define do_prctl_set_memory_consistency_model \ + do_prctl_set_memory_consistency_model + +static abi_long do_prctl_get_memory_consistency_model(CPUArchState *cpu_env) +{ + if (riscv_dtso_is_enabled(cpu_env)) + return PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO; + + return PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO; +} + +#define do_prctl_get_memory_consistency_model \ + do_prctl_get_memory_consistency_model + +#endif /* RISCV_TARGET_PRCTL_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ee90c09600..2e2aac73dc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -922,6 +922,11 @@ static void riscv_cpu_reset_hold(Object *obj) if (mcc->parent_phases.hold) { mcc->parent_phases.hold(obj); } +#ifdef CONFIG_USER_ONLY + /* Default is true if Ztso is enabled, false otherwise. */ + env->dtso_ena = cpu->cfg.ext_ztso; +#endif + #ifndef CONFIG_USER_ONLY env->misa_mxl = mcc->misa_mxl_max; env->priv = PRV_M; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f52dce78ba..69420b2ae3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -200,6 +200,7 @@ struct CPUArchState { #ifdef CONFIG_USER_ONLY uint32_t elf_flags; + bool dtso_ena; /* Dynamic TSO enable */ #endif #ifndef CONFIG_USER_ONLY