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Tue, 13 Feb 2024 02:22:27 -0600 From: Luc Michel To: , CC: Luc Michel , Eric Auger , "Peter Maydell" , Francisco Iglesias Subject: [PATCH v2] hw/arm/smmuv3: add support for stage 1 access fault Date: Tue, 13 Feb 2024 09:22:11 +0100 Message-ID: <20240213082211.3330400-1-luc.michel@amd.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A345:EE_|DS0PR12MB8443:EE_ X-MS-Office365-Filtering-Correlation-Id: 94ccec07-03dc-4b7d-b46f-08dc2c6ceadd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QQO3NoxLHZ2D2NuKYd1vasIMCCEgfroN7Gmv41RsQJCL1zuJYVufJ9SljRiVqon+PAxX0XIzOK4qc63ORgdxF5DvoWOA7GRW/koGHU9ikzq8uEBNkQNne3Gdc27nmjp7whRjB7zmWeIeXYrg94DyCKgHi70JHUtER/1muLDHycpMC7K9+khb4bU4yW5Tct24JyoeaktXRxOzRT5Z5DKLZCiL8gM50RYquvFMyDl0IfCnAnFK87g0O5DEqxyp0J+QXPzc8FjIfbFJXWRCa7sp4tZ+5j5QS6AQyd5PT5pDb73ybUPyGa59Kv3904pDoe8tfa8yB4Ka6EfKzNITFLEQcLK3ioC05DVlnoanVKzKiB2W6k4KTsMKDccNwQ+/Mlsjsbg6RWwAZyYaB+bZhekSS2fSg0C8OdIy9kxqtUdCVD/ZlYk5TmxoyPdE3XCs523tNFP/bYoNsK0BxYKeLAglnMoqKhows9kJVpOpd8wDHzBI9Qdkhd/ZtA6jna/imzwRxQHsTe1s9Fcd+hvAmPJxK3WkD3hj/U0zqDt3lwu8pfKoLoLm6UeIIXf8vLK84ttsTPFk8/4cS8PyFmYf2payoeOq2rY9qUd5kAZ5hXJN3fk= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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envelope-from=Luc.Michel@amd.com; helo=NAM12-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.774, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org An access fault is raised when the Access Flag is not set in the looked-up PTE and the AFFD field is not set in the corresponding context descriptor. This was already implemented for stage 2. Implement it for stage 1 as well. Signed-off-by: Luc Michel Reviewed-by: Mostafa Saleh Tested-by: Mostafa Saleh Reviewed-by: Eric Auger --- v2: drop erroneous submodule modification --- hw/arm/smmuv3-internal.h | 1 + include/hw/arm/smmu-common.h | 1 + hw/arm/smmu-common.c | 10 ++++++++++ hw/arm/smmuv3.c | 1 + 4 files changed, 13 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index e987bc4686b..e4dd11e1e62 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -622,10 +622,11 @@ static inline int pa_range(STE *ste) #define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6) #define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2) #define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1) #define CD_ENDI(x) extract32((x)->word[0], 15, 1) #define CD_IPS(x) extract32((x)->word[1], 0 , 3) +#define CD_AFFD(x) extract32((x)->word[1], 3 , 1) #define CD_TBI(x) extract32((x)->word[1], 6 , 2) #define CD_HD(x) extract32((x)->word[1], 10 , 1) #define CD_HA(x) extract32((x)->word[1], 11 , 1) #define CD_S(x) extract32((x)->word[1], 12, 1) #define CD_R(x) extract32((x)->word[1], 13, 1) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index fd8d772da11..5ec2e6c1a43 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -90,10 +90,11 @@ typedef struct SMMUTransCfg { /* Shared fields between stage-1 and stage-2. */ int stage; /* translation stage */ bool disabled; /* smmu is disabled */ bool bypassed; /* translation is bypassed */ bool aborted; /* translation is aborted */ + bool affd; /* AF fault disable */ uint32_t iotlb_hits; /* counts IOTLB hits */ uint32_t iotlb_misses; /* counts IOTLB misses*/ /* Used by stage-1 only. */ bool aa64; /* arch64 or aarch32 translation table */ bool record_faults; /* record fault events */ diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 9a8ac45431a..09ff72e55f5 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -362,10 +362,20 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, &block_size); trace_smmu_ptw_block_pte(stage, level, baseaddr, pte_addr, pte, iova, gpa, block_size >> 20); } + + /* + * If AFFD and PTE.AF are 0 => fault. (5.4. Context Descriptor) + * An Access fault takes priority over a Permission fault. + */ + if (!PTE_AF(pte) && !cfg->affd) { + info->type = SMMU_PTW_ERR_ACCESS; + goto error; + } + ap = PTE_AP(pte); if (is_permission_fault(ap, perm)) { info->type = SMMU_PTW_ERR_PERMISSION; goto error; } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 68eeef3e1d4..c416b8c0030 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -682,10 +682,11 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) cfg->oas = oas2bits(CD_IPS(cd)); cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); cfg->tbi = CD_TBI(cd); cfg->asid = CD_ASID(cd); + cfg->affd = CD_AFFD(cd); trace_smmuv3_decode_cd(cfg->oas); /* decode data dependent on TT */ for (i = 0; i <= 1; i++) {