From patchwork Tue Feb 13 14:28:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 13555187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E9D1C48260 for ; Tue, 13 Feb 2024 14:29:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=51qao2Xhqd0CKJt0s0+9dbr+BUH1r4Kg9vt7hqfIT50=; b=oUE58kl4cx8JqHjK04cqR/2b7W eJF6pYy1Nu9fTfW1FwTNpuEV0SKQSGwrEZiZdwp5FsBsQOnCVLDgnqOJ2orA9hlSirdLpLv8sGhPK XvN6KuFt1csOPOXa4CwoV4kh6wZ+ih8cJcOeS2GtAQZsolt5Nkq4ltmZSHtlB+Wsk/odJq/uNHpkj 4A/teO3tAlQ7JQKs2j0n9Xhpz357CvxbGCHK7jAPRBd004KmL5/CdAyr5J1SW+9nSoU9TLac5lATM XaKDeYlIP7Dm6ay0M21JdWNfho/fqYvNDdoLBvMdHXH7o/lQuUyLow2O0ZeNnF3CghSsHXGGfTuRK 4YqyUL5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtn8-00000009W46-0Q6M; Tue, 13 Feb 2024 14:29:46 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtmX-00000009Vuy-0QTj for linux-riscv@bombadil.infradead.org; Tue, 13 Feb 2024 14:29:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:Cc:To:From:Subject: Message-ID:References:Mime-Version:In-Reply-To:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=eGMdDRwTTa13t5SlPIuZSJHa36hYXdnKoaK7iYV4TM8=; b=mlp9aYrhUBqMlF/5BjXBgBUaFS QCh+rur6YnfI0kRy0vQ7Lh2KGj12Yr0AdrZ4jQaXfyz7jcfjK4s//G1i1wpBhsMf4Iw+mJCIxoKEh 3dka0UeMAxRSFX8jUncYxnyka0TwSZj3PWpMDt2MkmQ+QdwdBMuqvewLpdAZ1oSh7+uCrO2pSMlos WG7ln2uxcyKJ/qE1EfIHRGk2jar3REWhpEJKfZfbqy1pGz5X+2uKMPb2hxr1TN0+CWUv4d55sYxr2 KF7oPeu/xz7y+A044Nz7zZA3o5Mqch1TnNJqHS3yVMOva7bv+A+ZHi/tKq2Wek7yWZpPdQWVocmbC He05yttw==; Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtmT-0000000Fm62-3S3z for linux-riscv@lists.infradead.org; Tue, 13 Feb 2024 14:29:07 +0000 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-60753c3fab9so24957717b3.0 for ; Tue, 13 Feb 2024 06:29:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1707834542; x=1708439342; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=eGMdDRwTTa13t5SlPIuZSJHa36hYXdnKoaK7iYV4TM8=; b=MeEuQ57deraAv5+28QawUWBqei9zqWjdoOO1Oxp2UCiR5S6Ndl+f2j4jW1SbvMf9Ry pY6IEeTTsqoiBobd/51ayKiB1jGxJnBBdQCvJOlXJ1j/JsLil9w5WIIewPPfZWtMirtw /m0hMZejSohzp9NhSm6ecOrJM/GsUidDJ6uyYsrFXg75MafV35W0qPemCU/6MaJlh4RV UGslFCIZBjnu0uBDLvnqVOaOKsHaYZgN2ATmvRwv/IxYPyf66saUAoPQzYCVUX2gRTIO +DagDfyrbjB3Grb0v14GMNBXFZ+wojKCJ9THsfbHUaEcC/76R9L0XA1+fo8mdilIvXtC BKEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707834542; x=1708439342; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=eGMdDRwTTa13t5SlPIuZSJHa36hYXdnKoaK7iYV4TM8=; b=qObJLQKlqaQ3O4hFCwMWsOF5/AHcvsNUicmvBAvoBX8nsLMldlQIYC/lQ748Gz4RKc gpJNZTJ4w7eh5we3BgfzgjHVAkAr4hmS77X9TyP/uhP64LsUroXPQoRgNNSW6Vv7TAS+ OCFJRIrrPf6XhjAdk8Ddc/9yi0ECdMhvoAqpnf2uW+oRsD4JiQ7QrenmN4f32rN4kbgK 7mV9uEpvbVnWoSxbHnBOFA7B2IXvzjWpkzKt+6uKDzSl3naV623w8etGWCs0ufp1kcL7 2oQyojQVMclvjYlwbtL96QRFQmoJzvrpwBmlLMRScpu3Ig8HNS+A9/IChskL3/IZqwqx 6H0A== X-Gm-Message-State: AOJu0YyzvnHzc9OAf8bzv2nxIb1NBmDFzKs1SAAQgLKDG+BC/t5EFXXT IRhWFozXi14EUmOm+AjAHSNMlOK6GdQP20mfibEqaJ55O3J4LN9fKpzRMCkUpdeUEmVLPbFlQqP llwG4VywaV/Z0QVIELw== X-Google-Smtp-Source: AGHT+IEjRJkAWZBtGKgOvWcIgZrlfSHYWUmdK6a6QAGG5yPvxwXI45ku3lc1Z4IJzt1ZqVxJm+1omyh4oxPsoQYL X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a81:920c:0:b0:5ff:6ec3:b8da with SMTP id j12-20020a81920c000000b005ff6ec3b8damr564874ywg.1.1707834542765; Tue, 13 Feb 2024 06:29:02 -0800 (PST) Date: Tue, 13 Feb 2024 14:28:56 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213142856.2416073-1-ericchancf@google.com> Subject: [PATCH v3 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_142906_188280_F7659274 X-CRM114-Status: UNSURE ( 8.49 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more consistent with generic instrumentation. Signed-off-by: Eric Chan --- arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..4c49a8ff2c68 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw,iorw) +#define __rmb() RISCV_FENCE(ir,ir) +#define __wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw) From patchwork Tue Feb 13 14:29:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 13555186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FF92C48BC1 for ; Tue, 13 Feb 2024 14:29:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Wfhau4lNy2cAl3EGf77+Hf+ilhxK4tjJQtenUD7aXls=; b=V11wWjYNjvcxYDc/YHmtY7t9nF BbEtMxuw4IYipW1MwK7fI7hogVChWMEZqwkSVbJoUyfwjkMd8GXEYbFlWcMC0r11S7nzvZUCT0fkO xkAOvIALQyH457FLkaRocjbjNu7//vQVEQ69r0ZHoYODM7Ub7W58xed7vnayzGvhsGNx+pj9yc9x+ eaz34OtOMSqIxFZWAIrio3ot5CQlariFYZrW1UUQvXfpV1CWUvZSUOc9zLeZzAX2sbVvcqcy/nU8q d1FAXhtCZsDgtHE3KJOx3njZ8Nag2wms1FbFYeqxnnGsYWUuFTBhsdRy5wHdsXIOnUTfdEbPwkCRZ sseWYcjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtn5-00000009W26-2PEU; Tue, 13 Feb 2024 14:29:43 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtmv-00000009Vwg-2GzB for linux-riscv@bombadil.infradead.org; Tue, 13 Feb 2024 14:29:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:Cc:To:From:Subject: Message-ID:References:Mime-Version:In-Reply-To:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; b=PZevmN0/oVityjvvVfwcVR82A5 M9TLbttUn6JWySCzvELlJj1hfnJ9rItSGpZ6K2G9dCCBeJhSKalWtMCJVgMIF1tQKvf74nzTZPNHi wNpeBqR8pnkudSXWrnj7eB1XMQttbiyhEsU+2ILQYBMZPcM2+2YJq6K8Fc303ApJhIyprycbSOWi7 2jUtXY9PqAyjngrJkF86qUlwf3p8gsMcGaRxZ/fyAptdvHKqulOzl7V4jKcOwzLbREF8tWIyyL+/K 6lvuUWtQGDy2NyND1/zCelJ1fBoN41QN4m9LH3mbl3vn4ZAY4c68qhkLZnApfwM756Scr4ZPVLf/H GRtKZ92Q==; Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtmr-0000000Fm8J-3REV for linux-riscv@lists.infradead.org; Tue, 13 Feb 2024 14:29:32 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-dc6b26783b4so5250259276.0 for ; Tue, 13 Feb 2024 06:29:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1707834565; x=1708439365; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; b=Lb84zdsL5VfDkZ0b7D2ZOzAcQ5oAY9rK2NYK7OUmB4NOUBj0UnOzOscrnzplHm4m1X NKZ9ApBHZorE6EA2Vr+bMXjjK4n5Vz+sQYaBBd4qaIvITtmkdeuBlAPsOtkJhEiUIBkb zCnLn6Auc8Lw7UHROoBnUKYYQI2e2poeBFsWnXy0GZEqJDlSN1KmfOjm33Q9VIXD2QgC sXHhu46I+Tgu3lJKr0lCk28999/hpUaSrNzN9ryb6HEcti3m5wzMHQ3+4X3PUQssZS34 HfsedoCosRhf36WLzrl6t4IxDHvcXwFlRryAq9Bn4hdxGWgLSa4QhTgTuw3xDgb85mRT wrjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707834565; x=1708439365; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; b=qPKLeJfEhUPiihXTf80Gwf3hgK40pwbEBZUTQC/Y1+0wg+xGeWNdLrvB+TdZNroysM n2CXl5LmfP6c+LesuUquNWGkvcfgEOyv9ImbRRJhXtvgFwQej5cfDkw7FaHeR6SPx4Kt uMu9TvJ0nZ4+V97Qi8vXENtEX/+TRFhr4rA+4+B7Yuyp1ijHnvhpwqAtj/WAt2XJDItD V/XgIuZrwr2XOV+DE1H7ZMZHkFr9iJTqLeYDCIMFe3flryXtgvy/qLCkQIuIG88p+de3 L04/8Xpx+crp5kp04R7fVOXpVtmYwP2b4ROMzBz6XR1Ra8czcB+cnIybiIAQiJegUhG6 Hhcw== X-Gm-Message-State: AOJu0YyPqOygYQSXfQZ376plJEFO1wpFs74aPTRFSem9vdGgJDpoUxeh 6RUCJ4+ZFtqV66x/8LimSBQrZPyNVpA/fwLPdSCouLw3VdO+51Qw2YJnGrgD+hc57znJ7yBqmqc URc7xNY9KONuYB32xFA== X-Google-Smtp-Source: AGHT+IEFfDoRwQ206s3vRpeCnYcR/ybaOaF2/O1U/21MDlmy9oENsuSN3eESDaGFpf658j2sMYStzQ152cIojUz6 X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a25:69c4:0:b0:dcc:53c6:1133 with SMTP id e187-20020a2569c4000000b00dcc53c61133mr76167ybc.13.1707834565189; Tue, 13 Feb 2024 06:29:25 -0800 (PST) Date: Tue, 13 Feb 2024 14:29:19 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213142919.2416728-1-ericchancf@google.com> Subject: [PATCH v3 2/4] riscv/barrier: Define RISCV_FULL_BARRIER From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_142929_980250_C854CFD2 X-CRM114-Status: UNSURE ( 8.88 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Introduce RISCV_FULL_BARRIER and use in arch_atomic* function. like RISCV_ACQUIRE_BARRIER and RISCV_RELEASE_BARRIER, the fence instruction can be eliminated When SMP is not enabled. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 16 ++++++++-------- arch/riscv/include/asm/cmpxchg.h | 4 ++-- arch/riscv/include/asm/fence.h | 2 ++ 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index f5dfef6c2153..31e6e2e7cc18 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -207,7 +207,7 @@ static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int " add %[rc], %[p], %[a]\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -228,7 +228,7 @@ static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, " add %[rc], %[p], %[a]\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -248,7 +248,7 @@ static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v) " addi %[rc], %[p], 1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -268,7 +268,7 @@ static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v) " addi %[rc], %[p], -1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -288,7 +288,7 @@ static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -310,7 +310,7 @@ static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v) " addi %[rc], %[p], 1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -331,7 +331,7 @@ static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v) " addi %[rc], %[p], -1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -352,7 +352,7 @@ static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2f4726d3cfcc..a608e4d1a0a4 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -313,7 +313,7 @@ " bne %0, %z3, 1f\n" \ " sc.w.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" ((long)__old), "rJ" (__new) \ @@ -325,7 +325,7 @@ " bne %0, %z3, 1f\n" \ " sc.d.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" (__old), "rJ" (__new) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 2b443a3a487f..6c26c44dfcd6 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -4,9 +4,11 @@ #ifdef CONFIG_SMP #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" #define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#define RISCV_FULL_BARRIER "\tfence rw, rw\n" #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER +#define RISCV_FULL_BARRIER #endif #endif /* _ASM_RISCV_FENCE_H */ From patchwork Tue Feb 13 14:29:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 13555188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3CFAC48BC1 for ; Tue, 13 Feb 2024 14:29:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=IjYUq5q0JZRV3ErpxGvxOwjUA2Inu6/i3tXvboMtl8w=; b=UUHX9YqpBx2S8ka4c/3FfFloB+ zTwzPhSXeIiVo0ReU8/A4pwZZmJO3+4ywlm19GupiEVFUkV1UE9hba+puud8tpoOhjMJVGsI9PGKE udPkDWJBcVL/FYO7OfgOLqhpDonsA7bDw7VyGYAWXJmZTGBFvtEhEToC2cvVH2O8LZOa0tvvo6Ecl d8CjULWISal7Q3o1HpMe4iVwjq67iwxC4BHQV7NnwU5vbWRAskfWaPxkPZyd0dBR5Xfm1UflWJl4c 2CrukAC3cqPEj4xvDiBbygY33gWw5jTXoA1qMXLKIe7MJUT9IjxL8BLvypYAtWfZ37PenqpEsScSW OuCbfcOQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtnA-00000009W5e-1qMk; Tue, 13 Feb 2024 14:29:48 +0000 Received: from mail-yb1-xb49.google.com ([2607:f8b0:4864:20::b49]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtn3-00000009Vyu-3SHq for linux-riscv@lists.infradead.org; Tue, 13 Feb 2024 14:29:43 +0000 Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-dcc6c9b6014so1675261276.3 for ; Tue, 13 Feb 2024 06:29:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1707834579; x=1708439379; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=bjHBvtVzi/tC9ODHchdE1QaPBdrPAE+kD8d5Z9zVo4E=; b=hqUmLYXJNdUYyrtXvzN7zTUEZd6ZdRV1mrhAbxIRpJbPJpHoalO7VMlMVYXzxhway7 M37ePAir4xEiUPmWBISGK7MrKfh7yEKSm3NPD04S44cCwjAi0cN1wBjyIJ0WxRIBMsiu ia0jpHtbDEUzvXfPIrCCMcFT/7/A5CZw/uX45J7vhE00/HXPFWSKv7PM3ByvwcAL8Ndl pNqgxhvQ2/qEwLD5pLLziIJQTJOKAjOCyxKOdV2vgKpbtCDn/5Nayk0fdmM/WC7H1Afp Yab6kNIkFuE1HtREKpXyHzDztZVh69e9BTkhmSVhdTxQ5WyQKvD8934ZySvJIINq4PKY CnJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707834579; x=1708439379; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=bjHBvtVzi/tC9ODHchdE1QaPBdrPAE+kD8d5Z9zVo4E=; b=gn25/s+hDeFCzG8i0bZyBiDAwRCNj6sBLDZbapVjPKNZs+LqOwqxBFI9W/rYOtfCwT uZBhL6OfBbhnIFFp7eSPHplv/kMirbSsv6MUtFsXXEHN0WZsog36dQPV+tViCmvF1Vcc IeZt+VNHVHsY1IvsRAU8RsEzbvlCSJ9B4wW4r3znNbjBa3OdkHRcJIPocM+HlsETRQU0 b+ALWx1kBfE7g4HNBUhfG09OHukpdstPZuBYtly8/cnNbzEIqm9HLioWKD7BJlFyNh/Y odnCLUcnRib807pgb1XB/jWp4/R7n2SfcyWqKrh8ab4xqAUFgiVXHXm4n/HJ/x8LY/f9 WhiQ== X-Gm-Message-State: AOJu0YyC8+9uBxVIckJ+qkVFDvieQuaaEaXwuJy3iVWx7TtItFE08L+J wOhY80wjVs/qjr6VELyCG/BVprALEigelApL5dBxOpDAV5aQKYAaYWGh4aZqtdCBtwKnOFSKng9 XjA6/K0GIkDO6m1J5gw== X-Google-Smtp-Source: AGHT+IEnRJCLwueO7eGhQ0rGhmrv6mGsg0TspHtOVgdQaw4v/YUHbGoNtQMQmcFS8B1QPArMjVa90Vp9ttsYRXQZ X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1884:b0:dc7:68b5:4f3d with SMTP id cj4-20020a056902188400b00dc768b54f3dmr2393690ybb.11.1707834578969; Tue, 13 Feb 2024 06:29:38 -0800 (PST) Date: Tue, 13 Feb 2024 14:29:33 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213142933.2417154-1-ericchancf@google.com> Subject: [PATCH v3 3/4] riscv/barrier: Consolidate fence definitions From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_062941_974612_8F4E83B9 X-CRM114-Status: GOOD ( 14.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Disparate fence implementations are consolidated into fence.h. And align with the existing form. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 8 ++------ arch/riscv/include/asm/barrier.h | 3 +-- arch/riscv/include/asm/cmpxchg.h | 1 - arch/riscv/include/asm/fence.h | 10 +++++++--- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 5 +++-- arch/riscv/include/asm/mmiowb.h | 2 +- 7 files changed, 18 insertions(+), 19 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 31e6e2e7cc18..1b2ae3259f1d 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -17,13 +17,9 @@ #endif #include -#include -#define __atomic_acquire_fence() \ - __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") - -#define __atomic_release_fence() \ - __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); +#define __atomic_acquire_fence() RISCV_FENCE(r,rw) +#define __atomic_release_fence() RISCV_FENCE(rw,r) static __always_inline int arch_atomic_read(const atomic_t *v) { diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4c49a8ff2c68..4f4743d7440d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -11,13 +11,12 @@ #define _ASM_RISCV_BARRIER_H #ifndef __ASSEMBLY__ +#include #define nop() __asm__ __volatile__ ("nop") #define __nops(n) ".rept " #n "\nnop\n.endr\n" #define nops(n) __asm__ __volatile__ (__nops(n)) -#define RISCV_FENCE(p, s) \ - __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ #define __mb() RISCV_FENCE(iorw,iorw) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index a608e4d1a0a4..2fee65cc8443 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -8,7 +8,6 @@ #include -#include #include #define __xchg_relaxed(ptr, new, size) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 6c26c44dfcd6..ca094d72ec20 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -1,10 +1,14 @@ #ifndef _ASM_RISCV_FENCE_H #define _ASM_RISCV_FENCE_H +#define RISCV_FENCE_ASM(p, s) "\tfence " #p "," #s "\n" +#define RISCV_FENCE(p, s) \ + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) + #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" -#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" -#define RISCV_FULL_BARRIER "\tfence rw, rw\n" +#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r,rw) +#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw,r) +#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw,rw) #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 42497d487a17..afb5ead7552e 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -47,10 +47,10 @@ * sufficient to ensure this works sanely on controllers that support I/O * writes. */ -#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); -#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); -#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); -#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); +#define __io_pbr() RISCV_FENCE(io,i) +#define __io_par(v) RISCV_FENCE(i,ior) +#define __io_pbw() RISCV_FENCE(iow,o) +#define __io_paw() RISCV_FENCE(o,io) /* * Accesses from a single hart to a single I/O address must be ordered. This diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 4c58ee7f95ec..a708968d4a0f 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -12,6 +12,7 @@ #define _ASM_RISCV_MMIO_H #include +#include #include /* Generic IO read/write. These perform native-endian accesses. */ @@ -131,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) -#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) +#define __io_ar(v) RISCV_FENCE(i,ir) +#define __io_bw() RISCV_FENCE(w,o) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h index 0b2333e71fdc..3bcae97d4803 100644 --- a/arch/riscv/include/asm/mmiowb.h +++ b/arch/riscv/include/asm/mmiowb.h @@ -7,7 +7,7 @@ * "o,w" is sufficient to ensure that all writes to the device have completed * before the write to the spinlock is allowed to commit. */ -#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); +#define mmiowb() RISCV_FENCE(o,w) #include #include From patchwork Tue Feb 13 14:31:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 13555189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1150C48260 for ; Tue, 13 Feb 2024 14:31:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=JP2f0zBW9mD1e1ZDtR/zzj/Kyj6uIkJmTqGpcW4Vq9E=; b=uEtEE2jkVlnv7gXHGwX73FACix p5FkVUahzZ7zLiSKbgnMZSuFnENLGhwkKHvGUvyVmLTAKCgHqCqvJqGHiN9s+uB4WhpqjUdcGf6Sm C/FDtNCJXuTHu5+yUzT3w/RGGQcEBaYVsYHaTayu9GvRhxEwKX7DxR6qsl0txOgsGavtft02TjPOS lt+gYcJ8PBnWNOMljE1g1+fUWlY1zjnah1UPk6Vs0+hKjBG4lgjNh4noQUqD9+g5y/DCiH5JnP2EA OsHbqF1egSOXK9Mm5aBoqgFI1kzQumGE0q1IHssjRNCDhXO4+6u2DYCRxCyaxOyij8l4+KzAtdmSe /1gyS3wQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtp2-00000009WlO-0GXz; Tue, 13 Feb 2024 14:31:44 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZtoj-00000009WbE-2CHo for linux-riscv@lists.infradead.org; Tue, 13 Feb 2024 14:31:33 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-dbf618042daso1566808276.0 for ; Tue, 13 Feb 2024 06:31:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1707834671; x=1708439471; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=zzWDY0mBU7/wSOckVTmjGeC7uR6OHBXvGcRFd04Rqsk=; b=TIQ1JGtcH+WgQEv7VAzo2pJXFKcGli7X424SeQsYwSL7ibEz3i2FmbKFAC1cKFkE6s GjANfXnrU3I1IoPTaBMprFvy3N20Q7SiHN48GJlXv6rxmSfgIOUJQTNPVvIJDV/HVwlC Cw+BcmXDlkwNXuO7mD3kajoBV9yPYeQony/P3VvopMq0V3D++d2FNSTIywjHm0rKFTLZ QnjMVQGQc58BXK0MXq5nIIUkopwm7i8hRCXTOnYrKsUgPLyGGqCBG0tjdifLKW0yaSy+ v7BeTT29rEBUjkBNMhKCKaOcRMMMw/BQWfPLYQBKj6b2x/aQbDKoqtQQDcbchn0exnpY 2gtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707834671; x=1708439471; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=zzWDY0mBU7/wSOckVTmjGeC7uR6OHBXvGcRFd04Rqsk=; b=Srqf/M/i1EXV7pKVjqJpgqUBh0OX+4mzexbc1U+RqU8iDSuZ0i0I6j09imZn+kwf5+ PErWVLbeKNmx+Z+8ryDCnpltj4xtrH4lKyRxtai4s4dFEy0PH3fQ9kKYX9z3NRK1fX8x qlrdHy4Uum+Pwjb6j19X/NBWtJ1othn6P0dhTMUJna1gFyOjOY6SCSaQYYYZgJwC84n7 k2oLlTBU2r0ApSwYgLLVBGS7LfiPTQg+uaWPlWBIGo7RDEBz7v8erROHMK9oaAc1KWsV wLFtZ5N+g0j/A3xwntaj83Ht3JGTrHs+enBJewFd1oVu/V0qsfHj+207r4RRmyUmfuMt 3X+Q== X-Gm-Message-State: AOJu0YwrAR8mohaLYy8wrzuJsqB468Z8wu8g9ZLM87UL8xvzFe0P3PLr Hi0nk8i1egx2TYPGXoIkUrEB0G4kvGLmx36ddFf3fbEcGMjknQLRStr0qgZzORH8tySEjwDRat7 mQGWM/XgxZcPtzBGsKQ== X-Google-Smtp-Source: AGHT+IG1EP97jJJl0nKHqVDmwFVseRqKM6YlcjU/nrMn/gsTAqxMXErcgrlGclTN3Km1NnzLTpHhZiOxV5OTsuBX X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1027:b0:dc6:207c:dc93 with SMTP id x7-20020a056902102700b00dc6207cdc93mr345253ybt.2.1707834671075; Tue, 13 Feb 2024 06:31:11 -0800 (PST) Date: Tue, 13 Feb 2024 14:31:05 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213143105.2418044-1-ericchancf@google.com> Subject: [PATCH v3 4/4] riscv/barrier: Resolve checkpath.pl error From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_063125_867820_C3FBBDC9 X-CRM114-Status: GOOD ( 13.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The original form would cause checkpath.pl to issue a error. The error message is as follows: ERROR: space required after that ',' (ctx:VxV) +#define __atomic_acquire_fence() RISCV_FENCE(r,rw) ^ correct the form of RISCV_FENCE and RISCV_FENCE_ASM even if they already exist. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 4 ++-- arch/riscv/include/asm/barrier.h | 18 +++++++++--------- arch/riscv/include/asm/fence.h | 6 +++--- arch/riscv/include/asm/io.h | 8 ++++---- arch/riscv/include/asm/mmio.h | 4 ++-- arch/riscv/include/asm/mmiowb.h | 2 +- 6 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 1b2ae3259f1d..19050d13b6c1 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -18,8 +18,8 @@ #include -#define __atomic_acquire_fence() RISCV_FENCE(r,rw) -#define __atomic_release_fence() RISCV_FENCE(rw,r) +#define __atomic_acquire_fence() RISCV_FENCE(r, rw) +#define __atomic_release_fence() RISCV_FENCE(rw, r) static __always_inline int arch_atomic_read(const atomic_t *v) { diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4f4743d7440d..880b56d8480d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -19,19 +19,19 @@ /* These barriers need to enforce ordering on both devices or memory. */ -#define __mb() RISCV_FENCE(iorw,iorw) -#define __rmb() RISCV_FENCE(ir,ir) -#define __wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw, iorw) +#define __rmb() RISCV_FENCE(ir, ir) +#define __wmb() RISCV_FENCE(ow, ow) /* These barriers do not need to enforce ordering on devices, just memory. */ -#define __smp_mb() RISCV_FENCE(rw,rw) -#define __smp_rmb() RISCV_FENCE(r,r) -#define __smp_wmb() RISCV_FENCE(w,w) +#define __smp_mb() RISCV_FENCE(rw, rw) +#define __smp_rmb() RISCV_FENCE(r, r) +#define __smp_wmb() RISCV_FENCE(w, w) #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(rw,w); \ + RISCV_FENCE(rw, w); \ WRITE_ONCE(*p, v); \ } while (0) @@ -39,7 +39,7 @@ do { \ ({ \ typeof(*p) ___p1 = READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(r,rw); \ + RISCV_FENCE(r, rw); \ ___p1; \ }) @@ -68,7 +68,7 @@ do { \ * instances the scheduler pairs this with an mb(), so nothing is necessary on * the new hart. */ -#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) +#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw) #include diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index ca094d72ec20..5b46f96a3ec8 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -6,9 +6,9 @@ ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) #ifdef CONFIG_SMP -#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r,rw) -#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw,r) -#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw,rw) +#define RISCV_ACQUIRE_BARRIER RISCV_FENCE_ASM(r, rw) +#define RISCV_RELEASE_BARRIER RISCV_FENCE_ASM(rw, r) +#define RISCV_FULL_BARRIER RISCV_FENCE_ASM(rw, rw) #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index afb5ead7552e..1c5c641075d2 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -47,10 +47,10 @@ * sufficient to ensure this works sanely on controllers that support I/O * writes. */ -#define __io_pbr() RISCV_FENCE(io,i) -#define __io_par(v) RISCV_FENCE(i,ior) -#define __io_pbw() RISCV_FENCE(iow,o) -#define __io_paw() RISCV_FENCE(o,io) +#define __io_pbr() RISCV_FENCE(io, i) +#define __io_par(v) RISCV_FENCE(i, ior) +#define __io_pbw() RISCV_FENCE(iow, o) +#define __io_paw() RISCV_FENCE(o, io) /* * Accesses from a single hart to a single I/O address must be ordered. This diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index a708968d4a0f..06cadfd7a237 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -132,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) RISCV_FENCE(i,ir) -#define __io_bw() RISCV_FENCE(w,o) +#define __io_ar(v) RISCV_FENCE(i, ir) +#define __io_bw() RISCV_FENCE(w, o) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h index 3bcae97d4803..52ce4a399d9b 100644 --- a/arch/riscv/include/asm/mmiowb.h +++ b/arch/riscv/include/asm/mmiowb.h @@ -7,7 +7,7 @@ * "o,w" is sufficient to ensure that all writes to the device have completed * before the write to the spinlock is allowed to commit. */ -#define mmiowb() RISCV_FENCE(o,w) +#define mmiowb() RISCV_FENCE(o, w) #include #include