From patchwork Thu Feb 15 09:20:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13557744 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE97717592 for ; Thu, 15 Feb 2024 09:20:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988835; cv=none; b=T6WvwJ3eb0YQRlRJZVqJf1d10t7PFHPHvucH7ej2lWe3ypt+OeUF55YAtYVB6ceUphPkc49+hOFn7FDAv5FM8LDEEfJcK0j92yQ1I7mwHm/pK0dkzG67Ci7xLSNkU4kvH7DviPqPcWfAYy5geQS4NC0wyJMJyxnsyr/AAU+5V24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988835; c=relaxed/simple; bh=QCkz/HAlxsbVXDc+FMCgFBx5P0nVAWSA4UynpoVJyfQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Nlkl8I/eq9lnxzigl4KhLpdxYg6+D2N4pdF4d0nm9kNNS4TxDKteggKH9F5gatntc2X6tfLjgdHRMd7uFJnS5PjkWtZAN1yeQF4ub7JiKQz7oXufAk2eHRRz3HKQPfuGxDQI4lwHNUN9chHus8SAWgYyU9yOcJBWQaaT6WeHOSU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=lGzFFgtZ; arc=none smtp.client-ip=209.85.208.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lGzFFgtZ" Received: by mail-lj1-f177.google.com with SMTP id 38308e7fff4ca-2d0e5212559so7383361fa.0 for ; Thu, 15 Feb 2024 01:20:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707988832; x=1708593632; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/RMgnrHnFvnkqmQ/HYz89uTL6/4/6fzEmMqCiEApO7Y=; b=lGzFFgtZA/fn31PIAbZDA3SW2rGnyHVTqmtZH11z7UEWKpNKHtxwJZx0bH4gVyrsNj 4Y8Gg/5+Obe3v5EkUk++5Rl7CZrnWfAknPPcgdUaXWxGWtPmw0E9RJCYZ68Lt3ngzdxr i75kUXusHP3VAwjIB+dqx2DmQLAqIRXHsFtiMDEFoeqEg7fhsdWLmTDoL8HFp2ZwUtTu TsuizPmVFywGasE4VVu2YLJ8EzR/RtwZx2F0s6qAUfxzTalcp3m+xltMcE4o7aTnN61a jk7124DC5M4i3btsAccIHL/H61KREs8tqW8p14Quyhs6dwSl5YG1fMrbTrDmakOYehbw wRoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707988832; x=1708593632; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/RMgnrHnFvnkqmQ/HYz89uTL6/4/6fzEmMqCiEApO7Y=; b=wEGHpru+J19uEdmw2w2l3M4Yo8bV2LFZqZR/BlO4W7jqC379yoCu4lLC0aMU2QUgfo Y6zRqI9k11teTs3/c5s9YJfxH1O42pgEuil+urQFnbqMZzCalww3p0uVLph2WS4fm+i9 T6RzUnewU9wHOfdNKN2gmOBI8c40/R68EBkRRQenp2FWZNXt9Noro4xObkVQdhvALD2+ 9JjyycaQDsWV2clNKey3YbjmrvSxsIRXzlAqnOHHljeiOqWR2jJ3gtsCAZNySGccbiVj jyhN318qWnFVK5TjDuaXnRGiFymEYwe+Tz4pu4OoKa6EmNauDBWdyturKpx75BPu9uV7 gkNg== X-Gm-Message-State: AOJu0YxH4mTHLwpAjng0P+IJ+IvVg0vuT029CUSPpOOfOdF88dJ3+2Ga ZL47uuZHbE7fVJzYRnI7u+e6ABK+ptuCffACOeLrinWf9/PwWXJKVxLa6JHyZJ4= X-Google-Smtp-Source: AGHT+IHjoLYwjQO2evmWDkGzS21OU9pSICDlRxJhWfQtTk/vibTdzci6Q9CTyCXn5Ys3Glr07s+Xqg== X-Received: by 2002:a2e:a1c9:0:b0:2d0:c308:5f6e with SMTP id c9-20020a2ea1c9000000b002d0c3085f6emr771443ljm.44.1707988831872; Thu, 15 Feb 2024 01:20:31 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l8-20020adfa388000000b0033b66c2d61esm1156435wrb.48.2024.02.15.01.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 01:20:31 -0800 (PST) From: Neil Armstrong Date: Thu, 15 Feb 2024 10:20:23 +0100 Subject: [PATCH v2 1/6] dt-bindings: display/msm/gmu: Document Adreno 750 GMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-topic-sm8650-gpu-v2-1-6be0b4bf2e09@linaro.org> References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> In-Reply-To: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=799; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=QCkz/HAlxsbVXDc+FMCgFBx5P0nVAWSA4UynpoVJyfQ=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlzddasnMca9nUPOla3cwN7PCE0JduOPzXxA2qqUzW e2kOVoeJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc3XWgAKCRB33NvayMhJ0Wj9D/ 0RrWe9Gn5RAb867YZH0V9YAQVDSuc+HT6lV+Agq2y2GLHtzIvXJ4JsruwNsmuq+ZqPe2MkIMFnx+/X MjUYuej5kzmpVhL6yKUf8hm1MGWPg603I+yQpGGDbRtv/LMwkXU/25tTDKJVWNA51megauxy0xhMcE iyNW00psGC5hAqM8sz7hoIfgxkH3en1jUV1FRO/SqwecGflASYiAu3ipm966nrm0+slYNljFvYHhfs KsfSSCFLpDtSF32DZxeBvCEXlqWpZ0iatAC16NfWMcxvwnVDRC5Uvg8zZ2cjXR4HJCH9UG4xUI5MjZ 5R57NvkOFIENTbZlLisDk+KCJrKjwxia2SYeIXvSAt8tXtRC0ptAu8nAjQlukMpigIoz3qwnDduS0x Xc7RSPzhVpLd7nayvRfGvqKGJrpoyQYQXCK/WKvln+fVnOJjKCkxJW0OSBSIIXl7s4CUpLU8PNhRiA 0VGRhC7l6fpzGNMKk3ROgQ7IEQIJpqr/Sk0HtuobQh+a8hid4CV0EDYZylLf7neHtwD2dIK6N8WML6 tTK8CC0A0vJYJOUlYuSfXlQU0F59EBeq8S+5xUI+nLMsVPaOr74uQjXV+uXpQdemascqVz3dWudKwF MJat0Wecksh1yK/yjz0ofkVSRa5Bdv/rpEx2JhojBfqBnGuGL5yEJp2AMPQw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the Adreno 750 GMU found on the SM8650 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 4e1c25b42908..b3837368a260 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -224,6 +224,7 @@ allOf: enum: - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 + - qcom,adreno-gmu-750.1 then: properties: reg: From patchwork Thu Feb 15 09:20:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13557745 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1915316415 for ; Thu, 15 Feb 2024 09:20:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988836; cv=none; b=hYxJcAQUubM9SZhvEbueLipKBdWe3v2hACRBkJqipD6T7gdqmohhMD1/Gx0u8+MQLxg9T+SuwO9tjTvCo6cUDvMHifupmic2t8B1yrVdSV6wF4iYTj2bp0Qw1xJfDMYEKcXo5bC5lVzBsE88hdqIlKWh6kzD6rw/h2toTE5Xrhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988836; c=relaxed/simple; bh=yo2bcPgq0Ry4Dz1DgWE+noJk1QUbw0wPoiksjLdYOBo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z9AFKPoa+/3b6fzmOfLyPhmsrMLpdi50NY12DRChdVTrWNRshMIqy8Lat4o8FghJRSBWtdGjNli93fo/ytWDgzOHSRvhBXCQmWazGXo/yFLL0jOvJQ5RNo0ZwkYLcn6rBFibMl337GGu/NQoaDtiPrNLHgRtL6a5KHetn4PtBmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=sZJBTARU; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sZJBTARU" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-33ce2121d5dso243755f8f.3 for ; Thu, 15 Feb 2024 01:20:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707988833; x=1708593633; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rJagULZ78/2FNiklIv2V0yaJYekfWzVBl7+5o+wg9ug=; b=sZJBTARU6ztM5Gke4bQOBPOZX51bxcb0HypOqODWdtsEoB2afwQTciB6umGFyghL7j BDppjI2/4vBdUwwY/FyWnDNkbCMkB7ySg7kvP3N482pE62m7Ygo6sop3+c1y2Dc1FitX kRlsUNkghcKUgpY9tnyfyyCqrMlnX35SHNVfaD3ooV9dzAhiGVfHiPVh+gCixxK4lmu9 XrLqTknn6u6/eFwaYtqCiQ7guWIVaY3PSLSMUVfedyprTqQD8T3qOUjoHiUfiTzS2v8h gNMz3MBtXBAG9YX0UF957pI2SVXSBaqTHVjHTzxhCt9okKrxXKjHL84uyyW9OBjx8mZw sUjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707988833; x=1708593633; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rJagULZ78/2FNiklIv2V0yaJYekfWzVBl7+5o+wg9ug=; b=vGEBwOpRDVRQwAqlPETojuesKERPL91cAfiYbzA4YfXXeqP5YBN4KAL2sdAnzKJDpO uLoVkjtsLO03INUbuIqjoCW4Dno5CqhApWKwkhVO2b2rad15CrePwQteSsIRbpz1oYvA gJLiXwJJ04P4oQzKCe6i9FiKbHZn7l11U6iBn2SfpsYCSGcQh/2XApPFk60jCuOE2FuK Zp2zwCEUhITGBF5fBGGkZ1TWR0KvgrClZ6Hl6VOjqy4sI4ZIdkhkADoWt6MmyeMInMEL auNRJoVMsMxi9swYOAeA7IKqekktvgiIsl0wfQGICeIumUlZEo6RDc7nUDcvvW4dMyvJ 3LdQ== X-Gm-Message-State: AOJu0YwNNlsyLq6kVvkbpyq9eSNnnO8A8zBN3IBEVdfjgQVFeRUfm9A/ gHZZL2O1fQSUZJ5WVUanoJXHhq3cZM9Ao7yP/UMbYzqNOIjzwyPZ0jBREVZV2mM= X-Google-Smtp-Source: AGHT+IGp8PMtl4/BQOIm+djYPcum7f8RPFzzwdqiXF8XlH48cA5EQ/oqgfoCl+h6vhKoGtgOFNP4gQ== X-Received: by 2002:a5d:6ac5:0:b0:33c:e29b:f5cd with SMTP id u5-20020a5d6ac5000000b0033ce29bf5cdmr1177257wrw.24.1707988833298; Thu, 15 Feb 2024 01:20:33 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l8-20020adfa388000000b0033b66c2d61esm1156435wrb.48.2024.02.15.01.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 01:20:32 -0800 (PST) From: Neil Armstrong Date: Thu, 15 Feb 2024 10:20:24 +0100 Subject: [PATCH v2 2/6] dt-bindings: arm-smmu: Document SM8650 GPU SMMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-topic-sm8650-gpu-v2-2-6be0b4bf2e09@linaro.org> References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> In-Reply-To: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1386; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=yo2bcPgq0Ry4Dz1DgWE+noJk1QUbw0wPoiksjLdYOBo=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlzddbAVFrIBQkQc8wMo3rdp9H43W74Ogf7rPLLvlB Pp2ObIuJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc3XWwAKCRB33NvayMhJ0XWFD/ 90BnRPN6dApDP/mf/zTfMk+WPjxCgiRKD9B5wOVXHmserUOVv4XQjNbeSnmKiPHIrlA2diwPMLUQW5 gldygkZKP/cKbNfC7aXmrDV3kzll9YnfrIfR8V9Ofd24GFWdevVhfZK95UCROl0ETK5LsWizLKAcPt 1ASrOZziaNSQOIH7ROV8AszH8knJdYLs8AzIzc+bpGYwJ2hHwI9rAcksVDZJY1qgHvR4mO0Y3ygS9t kErNXLjvPAtlytDCjUh9GFFft6IZoF3Tq50VcYk8e73pOYDH15ke9huAPevApViaQZfhMgMNlEvS1g HKpxQ7NSWSK3Ht39GwzxDw7JBh7U5pmU8f+0DJq+QS2V+Cjjns3L73O0u+hujvD1lmE+23PmuEse9y IHUTUqD0w4Uy+WGigKDnMcj7sbh/a4Ij3QUnDU/U8PO4Dav9d//50iKe7xlYIkbSmqJ19MSq2Z2R4j ifQRWVp61pZGXzF2w/ET1xRrK45+YUffB2vkPO2USc20WFM505lX4gOP9yLOkirH/6T0u6Ew9nZOTv prdfEyL6z6l9L4UDPtA4AqdpbfmIUJrzpHfkKoHkjhzKgJmYwQ8dpfbz0zJvH7Aos2R1MItpDpqvUY 7+ez6OVQ9TzbkKl9IESBxQACvj+aXm16MisovuPwclaI6Ip0zlL9qsMBs31Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the GPU SMMU found on the SM8650 platform. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a4042ae24770..3ad5c850f3bf 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -93,6 +93,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -508,7 +509,10 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + contains: + enum: + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 then: properties: clock-names: @@ -544,7 +548,6 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 then: properties: From patchwork Thu Feb 15 09:20:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13557746 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41D1217581 for ; Thu, 15 Feb 2024 09:20:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988838; cv=none; b=T+qvWXM9BUbSwd3C0USXoN4do1ijeJwYlnQJCa4GWmGCIyYtrHQTx6BM9rsFLXxq4W5cYiDRcoVMBG5XYPztn0rvu6E9fuGoQEEleUd1vV4dOYTiyioxJ3jyWPnUVR7zb6BDxPb0AuUlDu9dOIlI5XaA77SVacinVS9PDWC0VXk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988838; c=relaxed/simple; bh=B2VkxjrRCyr4kbi/Ih6iBNEXikEKFqg0faRJON0SE+g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VbXvXkxDpRTPntgqaAbpXjwrZHcIxA7IgRGGJhLvKzZ77lSl7nW1Pdq7D7k4fldtq5z3zLsOf3XOycAUa2PfZcr5yJ4r8wIKJ3k5ijbEFaFG5t3QYkh0GXzt2EW/wxfYQhawEPF8mzP7fCkD0fOyChT/OCbqeKdUjyEbJziDDto= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=uT5LL9Zd; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="uT5LL9Zd" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-411f17700ffso5432015e9.0 for ; Thu, 15 Feb 2024 01:20:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707988834; x=1708593634; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5ygFt5WEvBpqUpx/ZfEWpp/27W6mJ4fXmmus9YC0aao=; b=uT5LL9ZdVrzsCndwmJUyxxkOZre1UwZJZsxEWvwPVjoDKsjTQ5HerQ6P5JYTQhVL4d eDo8m/HLFHKYFMO/+94Rh5xWcj9jjaLQba+Nf6a+oHu6wXS/FsYs+5GiWBs32Xps+ne9 pCsJIZIREeEkqF6nIktbI6jynFDh9L8h4CyUOwj7sWB1fKNW1x4NqShx4DOiB9kLAuLh MnazYASm2vhxTJa1/fxKBDmF654Rvqp0KiNVhuPZSHQwC/+rbiOgStXOccnz/u8iahvz Jb77u59lzO+97HfPNVFvgRxepZH74QOQwiEx7vcIDGrIvfs/ahBagr54smf70HPHvTaW Z5Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707988834; x=1708593634; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5ygFt5WEvBpqUpx/ZfEWpp/27W6mJ4fXmmus9YC0aao=; b=haU1TKWOKtd1UI7/IQlHEWNwVBj71qteAjjI/OEavT+itumQIpkXY1SuOw66ZnXr5M s4fyO7GJe6TmqqCWrmxfwcLbsZb7r8IXiXKBfONskjJsbYIfcHYkH88G9GEKa1IawWmQ qfS652J+c39iVVrHv/6Fhu+cANBboPNUJ6UxGAtDEwPLAg1YLgIaM37zYP5elSpIgKWH QiBzZx6LH2bWWnK9TLQkSYmIMwORoAUBXH1SYdqibfbI9zX+CQDTvz9Xq8j0gCor8jcV nNfnV5cssAqX1+ZV0cr8W+ROZps4bUxGDNcjRoBZBDbqf0RnKpewDXtlynEj617xpahZ IyVA== X-Gm-Message-State: AOJu0YyJd+5iUV0Xyg4lO3WikvKTebISZLRK+/2BLksxVyhTecET6jHB rK4813A4uGmE7x5/n/aYZXueHcfDPEK6Wb8pU6QRNao2LAxC3YR5Xvb6/+BUQSE= X-Google-Smtp-Source: AGHT+IHr6EIY5IaqJsX6nTJIJL95gxp6F5b/cqLuuSuiPNhGAbkKg8Oqmhr9/MhVWmYu+JmkeXZw2A== X-Received: by 2002:a5d:6205:0:b0:33b:131b:d8c1 with SMTP id y5-20020a5d6205000000b0033b131bd8c1mr830193wru.66.1707988834512; Thu, 15 Feb 2024 01:20:34 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l8-20020adfa388000000b0033b66c2d61esm1156435wrb.48.2024.02.15.01.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 01:20:34 -0800 (PST) From: Neil Armstrong Date: Thu, 15 Feb 2024 10:20:25 +0100 Subject: [PATCH v2 3/6] drm/msm/a6xx: Add missing regs for A750 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-topic-sm8650-gpu-v2-3-6be0b4bf2e09@linaro.org> References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> In-Reply-To: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1661; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=B2VkxjrRCyr4kbi/Ih6iBNEXikEKFqg0faRJON0SE+g=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlzddb1o2L2JxYU4dBpeU0HKoP1vroEL7LdMCezqtZ gfjwvXCJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc3XWwAKCRB33NvayMhJ0YUkD/ 9qLaDOjrM6piXhQRYK/i3fQkR18QxDH9oUXsgK71P1WL7T/sD8NNMAoo703snTLkzqTlmnf4CXu1qd 7lC7wxhiKxpQXO3B5GdZ/RKiesscwFJn44lVY1ybLECyxTldEu7k4RpkeZ+tslnzVw/D990cKWHViI 2QbZ1/KogldxveyiRY8iPVTjJI/YB/JiKrDJlIKE9dKcwpurOIt9ezL05fCs4lejcvcKcgOup46guY wfSsjHyFzWkeiBAtuk0XPAuo3gGFrXIvWobHrEhfvArLoPVihzapOipOwP4LI5HMONmcQKIlyoWfFT OqOmbrHNHR9Zt7pUS589p/9EZIIARfbX7pXxHkd85yDxt05Xx2CBdAeN+R5ntmxOjthtvpyPpivqfV SRp8exyNiJo5PskG49xEhVPNK0lCuLMie/tA3EGzz65+7mHUDG4mHDUS1iFwIvi+ueq0k+gLOWj1pD NkmRfvclMXK7tW/tEEsdiRq9J0V7ff07QWwOo6Aht6u8nXT4PTl4QLU4HUL5l74RB37Y8u/VCe/xWc leZE6NwHMngwOo4np7EQUu2AeCyKefiFsCErQEs4CPecO2H6rRhfoZkBvc3g6hauQ45kln3lEoggnr 6eog8DskhoUC+fXUOhab9hmCAba/BIQdkfLJuDMcrgJ5/2Mygit3ECp9JPiA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Sync missing regs for A750 clock gating control related registers from Mesa a6xx.xml.h generated file. Those registers were added in the !27576 merge request [1]. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27576 Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..58877464692a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1725,6 +1725,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 +#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad + #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 @@ -1939,12 +1941,19 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d +#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e + +#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f + #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 +#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff From patchwork Thu Feb 15 09:20:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13557747 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B099C1798E for ; Thu, 15 Feb 2024 09:20:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988839; cv=none; b=MC1v7OqBiucTlCw+at6yz+OYrblCbshJCNzvw0T8vvm3UkEYJR2GRvMsAor20kS5jU+24XPcojZsUTod71nXXhNUANZKY0SglJpesb19byTjGxiSxQ79iRswETGmdsX6ycJUqF37PlbAtoRcGmFz2+GQF4caVYEPXme+Jb16xgA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988839; c=relaxed/simple; bh=ixdWRZ9//fnKbR3faHjO8JwXZWGtnv2p+6cX0KLfh90=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tGN8xICyDIWTEho8ORjzZOtSFU9R1nd+WzfGgerMCswNuOINE/rE/xfjglsctU6vgtBLvv2XkcE4qKezDvJKTzpYrw5dg3+/UecUu1UgFXv70yT65HVTXdOhWWml21bCrWXIzODI9BkVoHRdVjgfA1YDNJ66xCPX3AOmaMYe6kU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WSq2SiQQ; arc=none smtp.client-ip=209.85.167.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WSq2SiQQ" Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-5116b540163so1027596e87.1 for ; Thu, 15 Feb 2024 01:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707988836; x=1708593636; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Wz/R+OttvCXysokn6zYBH1UjPAsuemNSOQvMKQiaZxo=; b=WSq2SiQQDfJ0iZO2MyTBrMGvh6AkDXX7wNWpWWlLWAfk+y0LY3ion6yjyP6lAqD2+b 6MR+P1sjH38P4k7/Ncqh37vmh61HPFRUAj5Nqx3VqRqNC3apRza+xG+eGk4Kzks3nypW bFVp74H79eQvlaBQAAdm9VYtKQMulMUQSiBCa1/oGVz0MxlzhVCiJVN2jmx8V9BSqNC7 UekydgkOgfQeE+qCD6eO2qV/4+Vv8IWVSFxgXH/EjAMlqgK26qeZLB9z0436ZcYj8fMy S6ghR6KQBL3Wc5MqTOp9KzgtvIBI06pedol6yoswcE77dmY7Kh02My09vP6FKZuaUT7o lJCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707988836; x=1708593636; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wz/R+OttvCXysokn6zYBH1UjPAsuemNSOQvMKQiaZxo=; b=CrcZ+bJh8BiEn/wUrYyktjLLlEZOzYM99CQvb30eHLqDY0DrM0aRaimIqWUUkmXnW7 47Lwm9p3snwbT3VIavOVrlQMZQ6eHwFv704OTenIDcFi3CoFraWgfU0FSZYFGsoLsq/N ZZ9yF3JIhHKtOmR3TkFye9+4r2OHFJ3NZcMHsWYdyLmyAE9C9FXlxdfzKdXpDGldxKeW OiZbUbySsSX3V+uFpzZNQrxqCLCC+OPlfWyA55qZPIgXUan47BKtd7dFCjEqCNxavN3u 6y0sATRCnai6atZ0pqtaXpU7Uhfw0KS1l5B6FolAChmV2tUg7YYkmccPZ1Bx4f/uGYlN OsTg== X-Gm-Message-State: AOJu0Yz5Jt7lZa0tHMEuMJKJeFXNN+iHhhfCQpeNnKN5FGOj2MdFHRFi VQN+LNGRbkutjzDwGOcHhzhYpiz8MZu+y+R5sUKpEHk7db+vMf77J9jSrmAXad8= X-Google-Smtp-Source: AGHT+IHBmz4GVIy7zAi8s3FiY53U4JGKrIlZnsRERqf4vG0ewFy912D5q7no0BNnnpGjpNZ9tS3lbw== X-Received: by 2002:ac2:4e6b:0:b0:511:4f21:4517 with SMTP id y11-20020ac24e6b000000b005114f214517mr811967lfs.33.1707988835788; Thu, 15 Feb 2024 01:20:35 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l8-20020adfa388000000b0033b66c2d61esm1156435wrb.48.2024.02.15.01.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 01:20:35 -0800 (PST) From: Neil Armstrong Date: Thu, 15 Feb 2024 10:20:26 +0100 Subject: [PATCH v2 4/6] drm/msm: add support for A750 GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-topic-sm8650-gpu-v2-4-6be0b4bf2e09@linaro.org> References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> In-Reply-To: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5285; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=ixdWRZ9//fnKbR3faHjO8JwXZWGtnv2p+6cX0KLfh90=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlzddcnLjmvv0nTN8GFLC9Fke9petDEfzJ7VXUKlfj +3W/SP2JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc3XXAAKCRB33NvayMhJ0RGvD/ 9QocmR+Xa8sAWfqhRHvsj7tM+SuPd43FlQR3B7be5t+4qWg95KJW0oalbulAmlNPrCjMG9Jx+hlg3U YwSh+MQ3mRH+SjE6SqjVnnlO6YxgHgF7X+c2IjebRQX/BIx3W5wgsJanACdEmA8BRhfynOmxLFFVDN 9YvBn2jeyx6Zs8vj69Q72rjFO7eLKvUcOBr9CA06EhV0N5qCYe85rJkzHc86GcjEQB2EULNlv5iOCO ZH0juLzthp5OM9URIHs7jV8aKTnFxQbK7stw9XMnXLFrZANah/SaOECKbFbK+5aHcPpzZiUlVjA5Vq QMMjIw5TvYC2Xas8ZkO4rN04vNCDom3mDETtjcIz5TdZw2aiPqwzd7I3RgpGIFBoNH/68Plmm1oBkG JP+zRjZgES2o8MecLmeLwJBIY+OE5cfmohzi5o9Im9jha0aDVTFOqBn294/X4Sp/XnowpOh5CtjtCP r3isnEgxpAvj8ZUXfVun2YNSnyfCeUla+2RRLRLUB4BvMdAu08JvIqRsrnUtYyP5lcFsLCsJ0IAmdA EI51WCbV0mqxPil1zWVq3VbzewR/QsQLjHwtBTb76Tw0lm7JZbMltmajK9QsbXIi/EKSrfjThqWB/p +yyu5M8x6WVOpzG5KdLu3dDCQoiqW4k6oWZxCrWpVk8hm7RBx9UtYM4vsxMA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++++++-- 4 files changed, 49 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 8c4900444b2c..325881d8ff08 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -842,6 +842,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) */ if (adreno_is_a740(adreno_gpu)) chipid_min = 2; + else if (adreno_is_a750(adreno_gpu)) + chipid_min = 9; else return -EINVAL; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..475b601a48ee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -961,7 +961,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu))) return; if (adreno_is_a630(adreno_gpu)) @@ -982,6 +982,25 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) state ? 0x5555 : 0); } + if (!adreno_gpu->info->hwcg) { + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); + gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); + + if (state) { + gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); + + if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, + val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { + dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); + return; + } + + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); + } + + return; + } + val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); /* Don't re-program the registers if they are already correct */ @@ -1239,7 +1258,9 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) count = ARRAY_SIZE(a660_protect); count_max = 48; BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) { + } else if (adreno_is_a730(adreno_gpu) || + adreno_is_a740(adreno_gpu) || + adreno_is_a750(adreno_gpu)) { regs = a730_protect; count = ARRAY_SIZE(a730_protect); count_max = 48; @@ -2880,7 +2901,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || - config->info->family == ADRENO_7XX_GEN2; + config->info->family == ADRENO_7XX_GEN2 || + config->info->family == ADRENO_7XX_GEN3; a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..e2582c91d7e7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -522,6 +522,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "gen70900_zap.mbn", + .address_space_size = SZ_16G, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..9e9415df2cea 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -48,6 +48,7 @@ enum adreno_family { ADRENO_6XX_GEN4, /* a660 family */ ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ + ADRENO_7XX_GEN3, /* a750 family */ }; #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -423,12 +424,17 @@ static inline int adreno_is_a740(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x43050a01; } -/* Placeholder to make future diffs smaller */ +static inline int adreno_is_a750(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x43051401; +} + static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return gpu->info->family == ADRENO_7XX_GEN2; + return gpu->info->family == ADRENO_7XX_GEN2 || + gpu->info->family == ADRENO_7XX_GEN3; } static inline int adreno_is_a7xx(struct adreno_gpu *gpu) From patchwork Thu Feb 15 09:20:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13557748 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7B0518651 for ; Thu, 15 Feb 2024 09:20:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988841; cv=none; b=mL04hJ+85/IpjRjlQds0A6HugFQVRyRmsUe6/s6QoAiCOD0uJ+97thidAWqRW+82+7sRHwoBevK4ateDX6Hyo1yJrNMi/5KquT0INANheO+qJm3/KEMQtlxaMVr3YtLZt7ijgrF+cMXvEMZdScyKP9uLR3U9kxQfZiOo3TKJueE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988841; c=relaxed/simple; bh=YnfJMxPEw+Crbp0x61Gr7hpcpYLyCY6opDQJsdz5YLA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oySMxEmKvtjbfo+z05DM6eXJ4+h2o5YNVrtCPYRQiFLwqW/xJn7iH4O4IYMjjvZhBkw58Bv05cQ1AxpdVa9dbx/TMGlXtL0/60dQXOJSESJmo6wpuPXyIcI3XNxTrwwgCqEvber4x/DTetlKDuHwVUn90jwfBDpGxdL2myB2mCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=W6h4hsPC; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="W6h4hsPC" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-411f165ef9bso5741555e9.0 for ; Thu, 15 Feb 2024 01:20:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707988837; x=1708593637; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eoTug8oI3rc0EGfqabXi49TIa0elLz1yO0hJ7mVAsJQ=; b=W6h4hsPC+DkUixiozRIH8dQFAJb5uUI9XGrcpsH5V1Hvo4HZoBjDtFdJLGtT+N/1i2 ALm96oM5grXu2jYJvEG9OQ8/QNwTNDbQyQepn2fTp5CEcOxHCzyGVooC6t7cCUQVEmlb I2EB3cd6D1GIdVl29uDDEW8/n2JrcqbgflZsaiQCXr+5J2V6vHnbTa6hwPQb6BpdAu/T yHg3rkVBEIQzvjk/qJWEHWePDpJQyhvxpL9jAxa31mIJV7+whs99oXjZzE9GBvPxiK8P kDY/SF6wZ/jZG67zU3uYo7iP6/Cd1TXVjpDLeNVpacltWidpv+g/KF1i+US8WGbrVG63 xnSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707988837; x=1708593637; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eoTug8oI3rc0EGfqabXi49TIa0elLz1yO0hJ7mVAsJQ=; b=Y4l8tnZBZlvKTpdVMAq5AY6gq0os/AWuSFaokeFVq6ohmgcRRlxYwSwGyJCw8kE/xA F97ctHHje6zTWmCBISYd52K9Ck1WAoImDYS9qJE/khqVn/IdStVXVAwIhQ6rNi9pgYI7 DQIgQhU+k8HE8Xz53rFll76Vq0zeUImtzDupb4SCwuD9u2WCleuavJtUxV3CGdZmXRMs LOyfDzm7mG0rUF9nW61y9Ysq1QFBTBwC16SliJM8Ff9d60bOO84Tnw1jBmvwn7aky9+t 9XMyK5T1byF3hA+0SPtdGdM9ncCLnPK4FbcFCc6EaXLoNXcRtT/3YvAhcsDDUzSoz61n QhKQ== X-Gm-Message-State: AOJu0YyEesYfQ1UB0dkgz0Jw5OYus7wCf+6QKlUIZZVAEqN4cnR0vYgf yzn7i4SpP4ahHvoT8EYZBObtcFZxgd8BM6A3MtAfMpJ9jo4g+CsZdT/t/we37JI= X-Google-Smtp-Source: AGHT+IGrvfbJ1uUDMa21ZnoJEdi5tRVea1OtDbDqHW32HWnjFevw0x1eHUUlkCjL4h415agx3thpXA== X-Received: by 2002:a5d:5751:0:b0:33b:3cb0:3081 with SMTP id q17-20020a5d5751000000b0033b3cb03081mr995363wrw.6.1707988837100; Thu, 15 Feb 2024 01:20:37 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l8-20020adfa388000000b0033b66c2d61esm1156435wrb.48.2024.02.15.01.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 01:20:36 -0800 (PST) From: Neil Armstrong Date: Thu, 15 Feb 2024 10:20:27 +0100 Subject: [PATCH v2 5/6] arm64: dts: qcom: sm8650: add GPU nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-topic-sm8650-gpu-v2-5-6be0b4bf2e09@linaro.org> References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> In-Reply-To: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5727; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=YnfJMxPEw+Crbp0x61Gr7hpcpYLyCY6opDQJsdz5YLA=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlzddcRfimUONnmrWNCX250+syb3LF/WRnexivnTqi rWBuVceJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc3XXAAKCRB33NvayMhJ0Z6nD/ 9fbuMf2jo4kFuN4Na5g4SaGhBo9f5t7RS2YyuolvNgbmiOCWUxBT2WnpRWGLXxfed+y2oP7H4byB0T 9xy7Yb+566tShTaC9KwLQfkZcVS+86cXGQwocurs7RX9mJPuvnp8B6C0kEGcG7WcFC0CzPijpHwzo0 uvosOjOze6t+bxceWJXwCp01m7aZWVdbSVXFORderPanxV8VYSUI3FJByB2Meb5XjvoBJDQM/E43hE ZcQYcCimF1FVVgn0B+/vrQ6QGB6UJ1McO3Gp1UjM0iz+Wd5v1GjIng3k/lmiRVUULg8aMqbhRIGk6L uT6021tW0ixDYZGfOxr4UnoveSCRlTbmVk/sc2vFj1NBJHygWxSX6VggeEoUmIeOge95mwAxd4zzXq 0n9GX+7HArdNA4ud4AtphXsicXhLoGncRtd9hw/47IZmrT54tI0cqycl9KRjGl5SuUMdoNLp4zt10y UAoDcWClAcfzGd0ajfZYXXdIQb3I1wam5Ao5A4YBgQD6WYL4Jvn5TPQ/V3kWp/jvwyRN4gevsstM8v vkKoq3wyVxvmyBXxulhkHS/Os7qd0/6R04JE8Uj8dQb8nA+lC/sIaqLVg1Yn8Y4jCg5i7ay32cDSMA WFhAmjzAuYwbvGXjQEoIILRaZGUC9M7BhCsGo6jCR8m0QCN253r8w8sEjfnw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 62e6ae93a9a8..27dcef27b6ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2589,6 +2589,128 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = ; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = ; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + }; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2602,6 +2724,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; From patchwork Thu Feb 15 09:20:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13557749 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00E0D1B815 for ; Thu, 15 Feb 2024 09:20:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988841; cv=none; b=ZeL+RmLMh+GdBo1sW/PsV8XidatxdfXqnTKNgjh4kLpGEtf1hG68o0gneXKWQ4V7Nm6ZwI2UjQkV/TnM67C7kgfATgijPPIjZD5xAvEFNs+KYC8ma/iG9Mj8W7MQGfIm+lnlkosk3WFHvBXMIzsnfEkUR8oFWq0uPrQDlpmawwQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707988841; c=relaxed/simple; bh=eK619A8Ja/rJOcWssIzBbWM6D0kuHt0880KvRuYuMKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i8PXNP0k442RBx+n7kJPP3boz5VRXSdhEHW323X/wl48fLbc0DR/bnT5zutQoNG7497T0efmsNU8Ll8xE9JxbAD0BcYxxrsnRoLZsLwBFUoi9WKSazdMAy9TMKemXDIZaUTSrJvK23DOze245PVHaBSALYlS6tbfqIY4yi8pgfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=aZUjHMiP; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aZUjHMiP" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-41211acfcfcso3870395e9.1 for ; Thu, 15 Feb 2024 01:20:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707988838; x=1708593638; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=M4VUVivuxhBItwCnLx0xGdHQH3tLZmkPnVy151EVhso=; b=aZUjHMiP++lWCKRStAIBEX/Yog2Uxl9v/fsfVM/oR/Bhidn5hGe/1nfu74cbxc9zZU 5JIuT+KuCF9hHhDYEY5p6fuMUnvwmLN20xHBFO244HCo7gwG6rrmPUY2Y61bX3b55UQ0 pk0445Kcc091Cjme6+GrV11AsYC3IojTi03+CJyngHUCrxDZSvbkzmTXWQ3SJsTFPcaz CPuT5ry6mH3empq/FwrPkBNHYaEkvxASO4I8yYsEZh6L38NoG83DdihTb3P1nH8eV3T3 PjbaXWYTt47YptiiB1pAYF09oxJ81JCxLukluGB3ReumUFCDE7UIX2gNICLRw/804k2+ P45Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707988838; x=1708593638; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M4VUVivuxhBItwCnLx0xGdHQH3tLZmkPnVy151EVhso=; b=drcVUebOEENDNh79rQF+PxgKMZtF3JnnCm11hGO9daF8fYpNsf0NPX3uiFt6X6HFUr j7Wne5oV4rD8bndjJ+HiiZV3WbrjVtxwdNodCG9yq6oBt5348n4hoTOvv0JXboCo51j6 hoq9dtQ51HU9ZFHMrZfaddatRqkyZabmhifD5coOKIqPKbEqsXhIOf2s98zMO4B0dg5y vlRmomuS1qqpaDXuJmbNueDq3MKcc78qH74du8NrBI8X88BMap+Vb/qCXYMBybeGp10h Lhex0YmdaBpX0yLn0qVVgxyeZuXCHTQZ8LgVcgHssgv0DNdrg8Kw5o6FXecSHrg9h2WX 5H2Q== X-Gm-Message-State: AOJu0YxxxUc14mN2uDahUBeWSWuwXioNF4uqGG3bMCCbhepxU2y9ahl7 bHC3RpAoBBps4Tw4NTNpW1EEZN1lCtb6GodvZuqSoTagUXlsczpT26hEXpQUfic= X-Google-Smtp-Source: AGHT+IFXVVQ/uxEk2n2UTx3FliemDL2HGwWD3N47dVkf/bJsy8vsKAGapR4cnCOAJNCWIz4P+M5s3A== X-Received: by 2002:a05:600c:310c:b0:40f:bd81:e738 with SMTP id g12-20020a05600c310c00b0040fbd81e738mr956462wmo.29.1707988838302; Thu, 15 Feb 2024 01:20:38 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l8-20020adfa388000000b0033b66c2d61esm1156435wrb.48.2024.02.15.01.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 01:20:37 -0800 (PST) From: Neil Armstrong Date: Thu, 15 Feb 2024 10:20:28 +0100 Subject: [PATCH v2 6/6] arm64: dts: qcom: sm8650-qrd: enable GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240215-topic-sm8650-gpu-v2-6-6be0b4bf2e09@linaro.org> References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> In-Reply-To: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=771; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=eK619A8Ja/rJOcWssIzBbWM6D0kuHt0880KvRuYuMKM=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlzddcVOTYaWXhqXz7CR0Hulwvc1BGcUEkmWvV2LSR NKZ9k7WJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc3XXAAKCRB33NvayMhJ0eCAD/ sGA6LkVKECsn38P5DH+wqPkMbxKjQP2fox10vCL1kOfmXAKY/TaOdQkclGH3g5hLpEOBA6CGarOlrU 2kLTIui0bQVTUNKVtHdGewsVaGpZN5nCMv4Wdkg49nAZcS24QNPFFOf+L1AJtcLGM/F9lCH/J+89qv NgItVT649rOPF27s7wX1fSsFPZINwwsNY67B1I2bxKAEJC4I/nkTUPYnfwHlE0cGXTnlmPRJ+pVDhQ LHR0O0YnsS3Le9JGqEPyXxgjuil1IgUbKHiIa1/1uebw+aeeovJWnvsnFlMFhLltxJN8rTRFsa0Ht5 vrqvc6TRjKwunCDjeQXaNsI4s9UQUA1bH1rQW7S9uji5sNURGP8FBNaYvbaLOmWkZLaJIFeXxNdjlt MvQ+TLWxwVU0/rsUG7j0qWlaN+i5zCEL+LVpY/Ewy/ENXU24l2iJYdNqRcvwg8WU1m7ryjIzBLPt7O +j1wfBYW/j+LCzrMonIWxtC+EOZW075OCV8Tdn90s97iADzC1nPKs4R4igTsm5H9/c20PVBejk3lep tjFjyda0GmKOGOYLxHSriW32Jacwk8nqT7Rd31uwmS+91HwYTCdiCzgxC/kYx+qUvHnIznYLeq0r9f Kv1VFYO/ReEoD5Dx+S0CnoWDPQO4CpB6v5J2zsqYVi+s2F/zjKwonhjw+XEA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add path of the GPU firmware for the SM8650-QRD board Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..dc91f0bf4b8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -766,6 +766,14 @@ &ipa { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21";