From patchwork Thu Feb 15 17:56:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 204E6C4829E for ; Thu, 15 Feb 2024 17:58:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rafzr-0001CJ-NN; Thu, 15 Feb 2024 12:58:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rafzq-0001AJ-J4 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 12:58:06 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rafzo-0001Pq-Sw for qemu-devel@nongnu.org; Thu, 15 Feb 2024 12:58:06 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-41223e0777dso5675385e9.2 for ; Thu, 15 Feb 2024 09:58:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708019882; x=1708624682; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H+IRUZ5jWxcqPuMBnPz4ZPr8dlbjAv9aNyQYimjXdkc=; b=WUxqx0ZFvEEJ3erOLv7hFlEQMe6iGuRr1JjHhULd1hD64AyCifWg5fC8uvFO8er7b9 oHza77w0dL92X57JPMALYVhIpBHSzQ/4CmCNQqahEemaJKhhKxuM+6HN8TqFn2sMmglh MKUfPrGq+nIx1koUY3Cdq2cnWDRd/lJ1r7N9z0BB58RM/dZOf1WBs4oMOsF7iBf6ZWX7 OluZb6ucg+hnZX6/tMEOiEDbr14fW3L+hM7QCACmghjlPH6sCOwGg5NuHNyOe5GemdjO CrfvNZzegHwETp27HIXefOWYuuOpRZO22lPjo3+rqo/C0CMkJm8e8ENBIi4FHfdE1gFf d44A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708019882; x=1708624682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H+IRUZ5jWxcqPuMBnPz4ZPr8dlbjAv9aNyQYimjXdkc=; b=R4WeXUeWpNjzlvuFtxKuflcE7d/T4//WHgScLkxpEcLfIbz4Ad5LwJVTuUqY4+kJ1Q EMnlKXJki3zykIFV1jtyw1R0Jd+AAONEFXovBdkR+pc6hLY+YKKHbNqXR0sObdX7liUV sNz4/Oq0s1JS7bqRCPdixtgL50A6e/p5Cz8tAaKwAe63FhdggU46qZ3h9GkAws1okTOw CIZzTSfbOLQUkJJT1cOIjxHol2IrRrnks7KdAZlYXCzUzwmFni4lWeb1M3ar7GCStzAy uZcbO2+UW4mvBkf/mvLJ2D4dQ2H0kfJWbgsVG/bLUKNjHqDKxUU0rzBIJ5e+q5Eob6gC oNgQ== X-Gm-Message-State: AOJu0YxqApgfqANE3paCgY+X+F1dGAuhXGJMmw4GjbhtX9QBNKYcc1ch xWLCScTNL+VtrgYKTuhsAxjg3we7NMsv94g6zy2UYTmp/gucrW5CLtEB2gNJPAgFCMlpsd0m8Pw TZRc= X-Google-Smtp-Source: AGHT+IEo/r7nzbH8BmIlhi5mTe+NeSsVhJI7MNENkuol/wgiPkkgeQ1r1Wc4mvp14QTgpAze7VRk8A== X-Received: by 2002:a05:600c:45c8:b0:412:2b7a:67fa with SMTP id s8-20020a05600c45c800b004122b7a67famr968825wmo.0.1708019882504; Thu, 15 Feb 2024 09:58:02 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id z11-20020a1c4c0b000000b0040d5ae2906esm5644695wmf.30.2024.02.15.09.58.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Yoshinori Sato , Magnus Damm , Kevin Wolf , Hanna Reitz Subject: [PULL 01/56] hw/block/tc58128: Don't emit deprecation warning under qtest Date: Thu, 15 Feb 2024 18:56:55 +0100 Message-ID: <20240215175752.82828-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Peter Maydell Suppress the deprecation warning when we're running under qtest, to avoid "make check" including warning messages in its output. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240206154151.155620-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/tc58128.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c index 6944cf58fa..0984e37417 100644 --- a/hw/block/tc58128.c +++ b/hw/block/tc58128.c @@ -202,7 +202,9 @@ static sh7750_io_device tc58128 = { int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2) { - warn_report_once("The TC58128 flash device is deprecated"); + if (!qtest_enabled()) { + warn_report_once("The TC58128 flash device is deprecated"); + } init_dev(&tc58128_devs[0], zone1); init_dev(&tc58128_devs[1], zone2); return sh7750_register_io_device(s, &tc58128); From patchwork Thu Feb 15 17:56:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C282C48BC4 for ; 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Thu, 15 Feb 2024 09:58:08 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id ba3-20020a0560001c0300b0033b406bc689sm2495039wrb.75.2024.02.15.09.58.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PULL 02/56] hw/mips: remove unnecessary "select PTIMER" Date: Thu, 15 Feb 2024 18:56:56 +0100 Message-ID: <20240215175752.82828-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philmd@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Paolo Bonzini There is no use of ptimer functions in mips_cps.c or any other related code. Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240129115811.1039965-1-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 505381a0bb..ab61af209a 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -50,7 +50,6 @@ config LOONGSON3V config MIPS_CPS bool - select PTIMER select MIPS_ITU config MIPS_BOSTON From patchwork Thu Feb 15 17:56:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6686C48BC4 for ; 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Thu, 15 Feb 2024 09:58:15 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id ci3-20020a5d5d83000000b0033d10bd6612sm1315244wrb.81.2024.02.15.09.58.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Alex?= =?utf-8?q?_Benn=C3=A9e?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 03/56] target/mips: Use qemu_irq typedef for CPUMIPSState::irq member Date: Thu, 15 Feb 2024 18:56:57 +0100 Message-ID: <20240215175752.82828-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Missed during commit d537cf6c86 ("Unify IRQ handling") when qemu_irq typedef was introduced for IRQState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-Id: <20240130111111.6372-1-philmd@linaro.org> --- target/mips/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index ef26fe03c7..b4788e1af2 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1183,7 +1183,7 @@ typedef struct CPUArchState { CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; - void *irq[8]; + qemu_irq irq[8]; struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ From patchwork Thu Feb 15 17:56:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 381C3C4829E for ; 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Thu, 15 Feb 2024 09:58:21 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id k2-20020adff282000000b0033b8808355fsm2424533wro.28.2024.02.15.09.58.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 04/56] target/mips: Remove helpers accessing SAAR registers Date: Thu, 15 Feb 2024 18:56:58 +0100 Message-ID: <20240215175752.82828-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org DisasContext::saar boolean is never set, so this code is not reachable. Remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-2-philmd@linaro.org> --- target/mips/tcg/sysemu_helper.h.inc | 5 --- target/mips/tcg/sysemu/cp0_helper.c | 55 ----------------------------- target/mips/tcg/translate.c | 42 ---------------------- 3 files changed, 102 deletions(-) diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc index f163af1eac..78f7272208 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -31,8 +31,6 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) DEF_HELPER_1(mfc0_tcschefback, tl, env) DEF_HELPER_1(mftc0_tcschefback, tl, env) DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) DEF_HELPER_1(mftc0_entryhi, tl, env) DEF_HELPER_1(mftc0_status, tl, env) DEF_HELPER_1(mftc0_cause, tl, env) @@ -57,7 +55,6 @@ DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ DEF_HELPER_2(mtc0_index, void, env, tl) @@ -104,8 +101,6 @@ DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index 62f6fb4bf6..f8883a3515 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -371,22 +371,6 @@ target_ulong helper_mfc0_count(CPUMIPSState *env) return (int32_t)cpu_mips_get_count(env); } -target_ulong helper_mfc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; - } - return 0; -} - -target_ulong helper_mfhc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; - } - return 0; -} - target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); @@ -514,13 +498,6 @@ target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) return env->CP0_WatchHi[sel]; } -target_ulong helper_dmfc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; - } - return 0; -} #endif /* TARGET_MIPS64 */ void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1108,38 +1085,6 @@ void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) } } -void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target = env->CP0_SAARI & 0x3f; - if (target < 2) { - env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL; - switch (target) { - case 0: - if (env->itu) { - itc_reconfigure(env->itu); - } - break; - } - } -} - -void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target = env->CP0_SAARI & 0x3f; - if (target < 2) { - env->CP0_SAAR[target] = - (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | - (env->CP0_SAAR[target] & 0x00000000ffffffffULL); - switch (target) { - case 0: - if (env->itu) { - itc_reconfigure(env->itu); - } - break; - } - } -} - void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 12094cc1e7..173b19a090 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -5151,17 +5151,6 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CP0_REGISTER_09: - switch (sel) { - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mfhc0_saar(arg, tcg_env); - register_name = "SAAR"; - break; - default: - goto cp0_unimplemented; - } - break; case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: @@ -5252,17 +5241,6 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; - case CP0_REGISTER_09: - switch (sel) { - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mthc0_saar(tcg_env, arg); - register_name = "SAAR"; - break; - default: - goto cp0_unimplemented; - } - break; case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: @@ -5680,11 +5658,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); register_name = "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mfc0_saar(arg, tcg_env); - register_name = "SAAR"; - break; default: goto cp0_unimplemented; } @@ -6406,11 +6379,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_saari(tcg_env, arg); register_name = "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saar(tcg_env, arg); - register_name = "SAAR"; - break; default: goto cp0_unimplemented; } @@ -7180,11 +7148,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); register_name = "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_dmfc0_saar(arg, tcg_env); - register_name = "SAAR"; - break; default: goto cp0_unimplemented; } @@ -7892,11 +7855,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_saari(tcg_env, arg); register_name = "SAARI"; break; - case CP0_REG09__SAAR: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saar(tcg_env, arg); - register_name = "SAAR"; - break; default: goto cp0_unimplemented; } From patchwork Thu Feb 15 17:56:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36C9DC48BC4 for ; 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Thu, 15 Feb 2024 09:58:27 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id y5-20020a7bcd85000000b00410ab50f70fsm5602288wmj.15.2024.02.15.09.58.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang Subject: [PULL 05/56] hw/misc/mips: Reduce itc_reconfigure() scope Date: Thu, 15 Feb 2024 18:56:59 +0100 Message-ID: <20240215175752.82828-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Previous commit removed the MT*C0(SAAR) helpers which were the only calls to itc_reconfigure() out of hw/, we can reduce its scope and declare it statically. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-3-philmd@linaro.org> --- include/hw/misc/mips_itu.h | 2 -- hw/misc/mips_itu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 5caed6cc36..3a7330ac07 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -79,6 +79,4 @@ struct MIPSITUState { /* Get ITC Configuration Tag memory region. */ MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu); -void itc_reconfigure(struct MIPSITUState *tag); - #endif /* MIPS_ITU_H */ diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 37aea0e737..db1220f8e0 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -86,7 +86,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size) return tag->ITCAddressMap[index]; } -void itc_reconfigure(MIPSITUState *tag) +static void itc_reconfigure(MIPSITUState *tag) { uint64_t *am = &tag->ITCAddressMap[0]; MemoryRegion *mr = &tag->storage_io; From patchwork Thu Feb 15 17:57:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14695C4829E for ; Thu, 15 Feb 2024 17:59:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag0U-0002Jm-WA; Thu, 15 Feb 2024 12:58:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag0R-0002Dc-JT for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 09:58:34 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id a1-20020a05600c224100b00412260889d9sm1614375wmm.1.2024.02.15.09.58.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 06/56] target/mips: Remove MIPSITUState::itu field Date: Thu, 15 Feb 2024 18:57:00 +0100 Message-ID: <20240215175752.82828-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Previous commits removed the MT*C0(SAAR) helpers which were using CPUMIPSState::itu, we can now remove it too. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-4-philmd@linaro.org> --- target/mips/cpu.h | 1 - hw/mips/cps.c | 1 - 2 files changed, 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index b4788e1af2..d54e9a4a1c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1184,7 +1184,6 @@ typedef struct CPUArchState { #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; qemu_irq irq[8]; - struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ /* Loongson IOCSR memory */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4f12e23ab5..988ceaa0b9 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -96,7 +96,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) itu_present = true; /* Attach ITC Tag to the VP */ env->itc_tag = mips_itu_get_tag_region(&s->itu); - env->itu = &s->itu; } qemu_register_reset(main_cpu_reset, cpu); } From patchwork Thu Feb 15 17:57:01 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 09:58:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 07/56] target/mips: Remove CPUMIPSState::saarp field Date: Thu, 15 Feb 2024 18:57:01 +0100 Message-ID: <20240215175752.82828-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=philmd@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This field is never set, so remove the unreachable code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-5-philmd@linaro.org> --- target/mips/cpu.h | 1 - hw/misc/mips_itu.c | 6 ------ 2 files changed, 7 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d54e9a4a1c..ef1d9f279c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1174,7 +1174,6 @@ typedef struct CPUArchState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ - int saarp; /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index db1220f8e0..d259a88d22 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -516,7 +516,6 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s = MIPS_ITU(dev); - CPUMIPSState *env; if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -533,11 +532,6 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) return; } - env = &MIPS_CPU(s->cpu0)->env; - if (env->saarp) { - s->saar = env->CP0_SAAR; - } - s->cell = g_new(ITCStorageCell, get_num_cells(s)); } From patchwork Thu Feb 15 17:57:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CDCDC48BF0 for ; Thu, 15 Feb 2024 17:59:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag0d-0002la-Dl; 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Thu, 15 Feb 2024 09:58:47 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id bh8-20020a05600005c800b0033b888a0a63sm2640261wrb.0.2024.02.15.09.58.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang Subject: [PULL 08/56] hw/misc/mips_itu: Remove MIPSITUState::cpu0 field Date: Thu, 15 Feb 2024 18:57:02 +0100 Message-ID: <20240215175752.82828-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since previous commit the MIPSITUState::cpu0 field is not used anymore. Remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-6-philmd@linaro.org> --- include/hw/misc/mips_itu.h | 1 - hw/mips/cps.c | 2 -- hw/misc/mips_itu.c | 5 ----- 3 files changed, 8 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 3a7330ac07..de7400c1fe 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -73,7 +73,6 @@ struct MIPSITUState { /* SAAR */ uint64_t *saar; - ArchCPU *cpu0; }; /* Get ITC Configuration Tag memory region. */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 988ceaa0b9..07b73b0a1f 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -103,8 +103,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); - object_property_set_link(OBJECT(&s->itu), "cpu[0]", - OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); 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Thu, 15 Feb 2024 09:58:53 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id by7-20020a056000098700b0033b684d6d5csm2601836wrb.20.2024.02.15.09.58.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang Subject: [PULL 09/56] hw/misc/mips_itu: Remove MIPSITUState::saar field Date: Thu, 15 Feb 2024 18:57:03 +0100 Message-ID: <20240215175752.82828-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This field is not set. Remove it along with the dead code it was guarding. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-7-philmd@linaro.org> --- include/hw/misc/mips_itu.h | 3 --- hw/misc/mips_itu.c | 22 +++------------------- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index de7400c1fe..27c9a1090d 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -70,9 +70,6 @@ struct MIPSITUState { /* ITU Control Register */ uint64_t icr0; - - /* SAAR */ - uint64_t *saar; }; /* Get ITC Configuration Tag memory region. */ diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 9705efeafe..f8acfb3ee2 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -94,12 +94,6 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; - if (tag->saar) { - address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; - size = 1ULL << ((tag->saar[0] >> 1) & 0x1f); - is_enabled = tag->saar[0] & 1; - } - memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); @@ -158,12 +152,7 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain = 0) is 128 B */ - if (s->saar) { - return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & - ITC_ICR0_BLK_GRAIN_MASK); - } else { - return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); - } + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); } static inline ITCStorageCell *get_cell(MIPSITUState *s, @@ -535,15 +524,10 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s = MIPS_ITU(dev); - if (s->saar) { - s->saar[0] = 0x11 << 1; - s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM; - } else { - s->ITCAddressMap[0] = 0; - s->ITCAddressMap[1] = + s->ITCAddressMap[0] = 0; + s->ITCAddressMap[1] = ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); - } itc_reconfigure(s); itc_reset_cells(s); From patchwork Thu Feb 15 17:57:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E483C48BC4 for ; Thu, 15 Feb 2024 17:59:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag0o-0003PZ-0H; Thu, 15 Feb 2024 12:59:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag0m-0003Ec-5j for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 09:58:59 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id fl16-20020a05600c0b9000b0040fd3121c4asm2801783wmb.46.2024.02.15.09.58.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:58:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 10/56] target/mips: Remove unused mips_def_t::SAARP field Date: Thu, 15 Feb 2024 18:57:04 +0100 Message-ID: <20240215175752.82828-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The SAARP field added in commit 5fb2dcd179 ("target/mips: Provide R/W access to SAARI and SAAR CP0 registers") has never been used, remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240215080629.51190-1-philmd@linaro.org> --- target/mips/internal.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 1d0c026c7d..a9a22ea00e 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -83,7 +83,6 @@ struct mips_def_t { uint32_t lcsr_cpucfg2; uint64_t insn_flags; enum mips_mmu_types mmu_type; - int32_t SAARP; }; extern const char regnames[32][3]; From patchwork Thu Feb 15 17:57:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39F0FC4829E for ; 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Thu, 15 Feb 2024 09:59:06 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id m22-20020a7bcb96000000b0040fafd84095sm5636762wmi.41.2024.02.15.09.59.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:59:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PULL 11/56] target/mips: Remove CPUMIPSState::CP0_SAAR[2] field Date: Thu, 15 Feb 2024 18:57:05 +0100 Message-ID: <20240215175752.82828-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=philmd@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Remove the unused CP0_SAAR[2] registers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-8-philmd@linaro.org> --- target/mips/cpu.h | 1 - target/mips/sysemu/machine.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index ef1d9f279c..5e97b5b422 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -749,7 +749,6 @@ typedef struct CPUArchState { int32_t CP0_Count; uint32_t CP0_SAARI; #define CP0SAARI_TARGET 0 /* 5..0 */ - uint64_t CP0_SAAR[2]; #define CP0SAAR_BASE 12 /* 43..12 */ #define CP0SAAR_SIZE 1 /* 5..1 */ #define CP0SAAR_EN 0 diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c index 218f4c3a67..6d1299a89e 100644 --- a/target/mips/sysemu/machine.c +++ b/target/mips/sysemu/machine.c @@ -282,7 +282,7 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), - VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), + VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */ VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Status, MIPSCPU), From patchwork Thu Feb 15 17:57:06 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 09:59:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 12/56] target/mips: Remove helpers accessing SAARI register Date: Thu, 15 Feb 2024 18:57:06 +0100 Message-ID: <20240215175752.82828-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org DisasContext::saar boolean is never set, so this code is not reachable. Remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-9-philmd@linaro.org> --- target/mips/tcg/sysemu_helper.h.inc | 1 - target/mips/tcg/sysemu/cp0_helper.c | 8 -------- target/mips/tcg/translate.c | 20 -------------------- 3 files changed, 29 deletions(-) diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc index 78f7272208..1861d538de 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -100,7 +100,6 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index f8883a3515..ded6c78e9a 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -1077,14 +1077,6 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) cpu_mips_store_count(env, arg1); } -void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target = arg1 & 0x3f; - if (target <= 1) { - env->CP0_SAARI = target; - } -} - void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 173b19a090..3ba2101647 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -5653,11 +5653,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) ctx->base.is_jmp = DISAS_EXIT; register_name = "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); - register_name = "SAARI"; - break; default: goto cp0_unimplemented; } @@ -6374,11 +6369,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_count(tcg_env, arg); register_name = "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saari(tcg_env, arg); - register_name = "SAARI"; - break; default: goto cp0_unimplemented; } @@ -7143,11 +7133,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) ctx->base.is_jmp = DISAS_EXIT; register_name = "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); - register_name = "SAARI"; - break; default: goto cp0_unimplemented; } @@ -7850,11 +7835,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_helper_mtc0_count(tcg_env, arg); register_name = "Count"; break; - case CP0_REG09__SAARI: - CP0_CHECK(ctx->saar); - gen_helper_mtc0_saari(tcg_env, arg); - register_name = "SAARI"; - break; default: goto cp0_unimplemented; } From patchwork Thu Feb 15 17:57:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA94DC4829E for ; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-10-philmd@linaro.org> --- target/mips/cpu.h | 1 - target/mips/sysemu/machine.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5e97b5b422..7329226d39 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -747,7 +747,6 @@ typedef struct CPUArchState { * CP0 Register 9 */ int32_t CP0_Count; - uint32_t CP0_SAARI; #define CP0SAARI_TARGET 0 /* 5..0 */ #define CP0SAAR_BASE 12 /* 43..12 */ #define CP0SAAR_SIZE 1 /* 5..1 */ diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c index 6d1299a89e..213fd637fc 100644 --- a/target/mips/sysemu/machine.c +++ b/target/mips/sysemu/machine.c @@ -281,7 +281,7 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU), - VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), + VMSTATE_UNUSED(sizeof(uint32_t)), /* was CP0_SAARI */ VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */ VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU), From patchwork Thu Feb 15 17:57:08 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 09:59:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 14/56] target/mips: Remove the unused DisasContext::saar field Date: Thu, 15 Feb 2024 18:57:08 +0100 Message-ID: <20240215175752.82828-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org DisasContext::saar is not used, remove it. Reported-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-11-philmd@linaro.org> --- target/mips/tcg/translate.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 93a78b8121..2b6646b339 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -49,7 +49,6 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; - bool saar; bool mi; int gi; } DisasContext; From patchwork Thu Feb 15 17:57:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 505A3C4829E for ; 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Thu, 15 Feb 2024 09:59:32 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id o1-20020a5d4081000000b0033b6e26f0f9sm2427415wrp.42.2024.02.15.09.59.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:59:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 15/56] hw/isa: clean up Kconfig selections for ISA_SUPERIO Date: Thu, 15 Feb 2024 18:57:09 +0100 Message-ID: <20240215175752.82828-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Paolo Bonzini All users of ISA_SUPERIO include a floppy disk controller, serial port and parallel port via the automatic creation mechanism of isa-superio.c. Select the symbol and remove it from the dependents. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini Message-ID: <20240213155005.109954-3-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/Kconfig | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 040a18c070..7884179d08 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -17,7 +17,11 @@ config ISA_SUPERIO bool select ISA_BUS select PCKBD + select PARALLEL + select SERIAL_ISA select FDC_ISA + # Some users of ISA_SUPERIO do not use it + #select IDE_ISA config PC87312 bool @@ -26,9 +30,6 @@ config PC87312 select I8254 select I8257 select MC146818RTC - select SERIAL_ISA - select PARALLEL - select FDC_ISA select IDE_ISA config PIIX @@ -49,8 +50,6 @@ config VT82C686 select ISA_SUPERIO select ACPI select ACPI_SMBUS - select SERIAL_ISA - select FDC_ISA select USB_UHCI select APM select I8254 @@ -58,14 +57,10 @@ config VT82C686 select I8259 select IDE_VIA select MC146818RTC - select PARALLEL config SMC37C669 bool select ISA_SUPERIO - select SERIAL_ISA - select PARALLEL - select FDC_ISA config LPC_ICH9 bool From patchwork Thu Feb 15 17:57:10 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 09:59:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Bernhard Beschow , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Jiaxun Yang Subject: [PULL 16/56] hw/mips/Kconfig: Remove ISA dependencies from MIPSsim board Date: Thu, 15 Feb 2024 18:57:10 +0100 Message-ID: <20240215175752.82828-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=philmd@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bernhard Beschow The board doesn't have a working ISA bus, only some I/O space. Selecting ISA_BUS and including hw/isa/isa.h is not necessary. Signed-off-by: Bernhard Beschow Message-ID: <20230109204124.102592-3-shentey@gmail.com> Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240213155005.109954-4-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/mipssim.c | 7 +++++-- hw/mips/Kconfig | 3 +-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index 16af31648e..a12427b6c8 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -31,7 +31,6 @@ #include "hw/clock.h" #include "hw/mips/mips.h" #include "hw/char/serial.h" -#include "hw/isa/isa.h" #include "net/net.h" #include "sysemu/sysemu.h" #include "hw/boards.h" @@ -206,7 +205,11 @@ mips_mipssim_init(MachineState *machine) cpu_mips_irq_init_cpu(cpu); cpu_mips_clock_init(cpu); - /* Register 64 KB of ISA IO space at 0x1fd00000. */ + /* + * Register 64 KB of ISA IO space at 0x1fd00000. But without interrupts + * (except for the hardcoded serial port interrupt) -device cannot work, + * so do not expose the ISA bus to the user. + */ memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(), 0, 0x00010000); memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa); diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index ab61af209a..afcfb2b8ec 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -6,8 +6,7 @@ config MALTA config MIPSSIM bool - select ISA_BUS - select SERIAL_ISA + select SERIAL select MIPSNET config JAZZ From patchwork Thu Feb 15 17:57:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A9CAC48BC4 for ; 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Thu, 15 Feb 2024 09:59:46 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id fa25-20020a05600c519900b0041228b2e179sm1436839wmb.39.2024.02.15.09.59.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:59:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Paolo Bonzini , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PULL 17/56] hw/isa: fix ISA_SUPERIO dependencies Date: Thu, 15 Feb 2024 18:57:11 +0100 Message-ID: <20240215175752.82828-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Paolo Bonzini ISA_SUPERIO does not provide an ISA bus, so it should not select the symbol: instead it requires one. Among its users, VT82C686 is the only one that is a PCI-ISA bridge and does not already select ISA_BUS. Reviewed-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bernhard Beschow Signed-off-by: Paolo Bonzini Message-ID: <20240213155005.109954-5-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 7884179d08..5df3c09cd5 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -15,7 +15,7 @@ config I82378 config ISA_SUPERIO bool - select ISA_BUS + depends on ISA_BUS select PCKBD select PARALLEL select SERIAL_ISA @@ -47,6 +47,7 @@ config PIIX config VT82C686 bool + select ISA_BUS select ISA_SUPERIO select ACPI select ACPI_SMBUS From patchwork Thu Feb 15 17:57:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68306C4829E for ; Thu, 15 Feb 2024 18:08:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag1m-00079Y-9U; Thu, 15 Feb 2024 13:00:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag1i-0006pZ-Cx for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:00:02 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rag1e-0001tC-Gm for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:00:01 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-412345cca4eso1641045e9.2 for ; Thu, 15 Feb 2024 09:59:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708019992; x=1708624792; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KrDWAyGRgS7V1HXGadIwipz2b43fHU+C3C1ocsMbGSU=; b=eSLdhUi4QXO3Q4APHbiB67wLcgis0wcTKvILLJ6Aw1XL43jad83bipoBhnWZaakNxK InhpHO0sXjpyZIAMIPcNbX3dQxzitCiveCWYq/96L1aHH3N/rwkUbvwEavL13a8P+Y5q bxBDw4Tvw05plZ0t+vfnPbx7lm1XfWS+qFxYBLy4ARdO1Q8yRLtE3ZaVJwTSX8156sk9 AHXJjXWkashzsb5nsjSVvCqdxjsqA0ePxiD5hXORPJZjGoDoMlT2G371BoRzI3jbAbaX GpkPeNRvAM5LGvIC9x+FPCbskY+pxFmuzEwHzkt4rZiiyGK411jXS5lmei5Bp4tal3Hp +RDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708019992; x=1708624792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KrDWAyGRgS7V1HXGadIwipz2b43fHU+C3C1ocsMbGSU=; b=r6M+HJSUDcKxlvpAreGwXyssoEvhsMAqlpJLAS5H5pcFMYAPc1CczkP585ddc6gWdV sR0l0p2DpnQjTbn0QvVvJKq51kOec3VWUQ6lUHKif2CRP4NKJ7ytW3a/nbrWElsYEI5M ZT0BaZ8vVaf+gt6eJ7r/LzPm0/+i8UUBL09EJZzW4M3FUqxiH02V5q9RoBFINix7Trf5 YGZAQuGvC3McFDF97kDjh5B5rGzp+5vUeQmKnpGAn3DANtTatfWFYvZPOxc2UjfIObm7 4u9NNNMppLd5jubVlXtn7IzlhYUgDJQNT+fnsIWBROvj7j7ceSSliod0NJhx7yRHYD6Y NqYw== X-Gm-Message-State: AOJu0Yw0RMAU2cFx3eLEu/PFY1L8vS+2eNu5vI4iyzwex2LZ7wSz/uQG KgU3tQR+fGh+WuSqTib9BD9HGL8uet5Vz8Rw5X0rJ+Yso5A2QPCZ+Pf20zC7BG2G5/i6Cs3yLCn B3BA= X-Google-Smtp-Source: AGHT+IEge+7N7R5Dv+aWhleCePe/xXWie3Ax8OjFhYHUQVNaLC46zf2vna8295JbBHhsrvOyp0WM+A== X-Received: by 2002:a05:600c:91a:b0:40e:f46d:ad35 with SMTP id m26-20020a05600c091a00b0040ef46dad35mr2161791wmp.36.1708019992628; Thu, 15 Feb 2024 09:59:52 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id z11-20020a7bc7cb000000b00411b7c91470sm5630301wmk.12.2024.02.15.09.59.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:59:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Bernhard Beschow , "Michael S. Tsirkin" , Richard Henderson Subject: [PULL 18/56] hw/isa: specify instance_size in isa_superio_type_info Date: Thu, 15 Feb 2024 18:57:12 +0100 Message-ID: <20240215175752.82828-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Paolo Bonzini Right now all subclasses of TYPE_ISA_SUPERIO have to specify an instance_size, because the ISASuperIODevice struct adds fields to ISADevice but the type does not include the increased instance size. Failure to do so results in an access past the bounds of struct ISADevice as soon as isa_superio_realize is called. Fix this by specifying the instance_size already in the superclass. Fixes: 4c3119a6e3 ("hw/isa/superio: Factor out the parallel code from pc87312.c") Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bernhard Beschow Signed-off-by: Paolo Bonzini Message-ID: <20240213155005.109954-6-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/isa-superio.c | 2 +- hw/isa/smc37c669-superio.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c index 7dbfc374da..d85f22db1a 100644 --- a/hw/isa/isa-superio.c +++ b/hw/isa/isa-superio.c @@ -185,6 +185,7 @@ static const TypeInfo isa_superio_type_info = { .abstract = true, .class_size = sizeof(ISASuperIOClass), .class_init = isa_superio_class_init, + .instance_size = sizeof(ISASuperIODevice), }; /* SMS FDC37M817 Super I/O */ @@ -201,7 +202,6 @@ static void fdc37m81x_class_init(ObjectClass *klass, void *data) static const TypeInfo fdc37m81x_type_info = { .name = TYPE_FDC37M81X_SUPERIO, .parent = TYPE_ISA_SUPERIO, - .instance_size = sizeof(ISASuperIODevice), .class_init = fdc37m81x_class_init, }; diff --git a/hw/isa/smc37c669-superio.c b/hw/isa/smc37c669-superio.c index 18287741cb..9e59dc1603 100644 --- a/hw/isa/smc37c669-superio.c +++ b/hw/isa/smc37c669-superio.c @@ -103,7 +103,6 @@ static void smc37c669_class_init(ObjectClass *klass, void *data) static const TypeInfo smc37c669_type_info = { .name = TYPE_SMC37C669_SUPERIO, .parent = TYPE_ISA_SUPERIO, - .instance_size = sizeof(ISASuperIODevice), .class_size = sizeof(ISASuperIOClass), .class_init = smc37c669_class_init, }; From patchwork Thu Feb 15 17:57:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED243C48BC4 for ; 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Thu, 15 Feb 2024 09:59:59 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id k2-20020adff282000000b0033b8808355fsm2427810wro.28.2024.02.15.09.59.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 09:59:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Paolo Bonzini , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , "Michael S. Tsirkin" Subject: [PULL 19/56] hw/isa: extract FDC37M81X to a separate file Date: Thu, 15 Feb 2024 18:57:13 +0100 Message-ID: <20240215175752.82828-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Paolo Bonzini isa-superio.c currently defines a SuperIO chip that is not used by any other user of the file. Extract the chip to a separate file. Reviewed-by: Bernhard Beschow Signed-off-by: Paolo Bonzini Message-ID: <20240213155005.109954-7-pbonzini@redhat.com> [PMD: Update MAINTAINERS] Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + hw/isa/fdc37m81x-superio.c | 32 ++++++++++++++++++++++++++++++++ hw/isa/isa-superio.c | 18 ------------------ hw/isa/Kconfig | 4 ++++ hw/isa/meson.build | 1 + hw/mips/Kconfig | 2 +- 6 files changed, 39 insertions(+), 19 deletions(-) create mode 100644 hw/isa/fdc37m81x-superio.c diff --git a/MAINTAINERS b/MAINTAINERS index a24c2b51b6..8920ba403d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1357,6 +1357,7 @@ M: Philippe Mathieu-Daudé R: Aurelien Jarno S: Odd Fixes F: hw/isa/piix.c +F: hw/isa/fdc37m81x-superio.c F: hw/acpi/piix4.c F: hw/mips/malta.c F: hw/pci-host/gt64120.c diff --git a/hw/isa/fdc37m81x-superio.c b/hw/isa/fdc37m81x-superio.c new file mode 100644 index 0000000000..55e91fbca1 --- /dev/null +++ b/hw/isa/fdc37m81x-superio.c @@ -0,0 +1,32 @@ +/* + * SMS FDC37M817 Super I/O + * + * Copyright (c) 2018 Philippe Mathieu-Daudé + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/isa/superio.h" + +static void fdc37m81x_class_init(ObjectClass *klass, void *data) +{ + ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); + + sc->serial.count = 2; /* NS16C550A */ + sc->parallel.count = 1; + sc->floppy.count = 1; /* SMSC 82077AA Compatible */ + sc->ide.count = 0; +} + +static const TypeInfo types[] = { + { + .name = TYPE_FDC37M81X_SUPERIO, + .parent = TYPE_ISA_SUPERIO, + .class_init = fdc37m81x_class_init, + }, +}; + +DEFINE_TYPES(types) diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c index d85f22db1a..ad9cd129af 100644 --- a/hw/isa/isa-superio.c +++ b/hw/isa/isa-superio.c @@ -188,27 +188,9 @@ static const TypeInfo isa_superio_type_info = { .instance_size = sizeof(ISASuperIODevice), }; -/* SMS FDC37M817 Super I/O */ -static void fdc37m81x_class_init(ObjectClass *klass, void *data) -{ - ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); - - sc->serial.count = 2; /* NS16C550A */ - sc->parallel.count = 1; - sc->floppy.count = 1; /* SMSC 82077AA Compatible */ - sc->ide.count = 0; -} - -static const TypeInfo fdc37m81x_type_info = { - .name = TYPE_FDC37M81X_SUPERIO, - .parent = TYPE_ISA_SUPERIO, - .class_init = fdc37m81x_class_init, -}; - static void isa_superio_register_types(void) { type_register_static(&isa_superio_type_info); - type_register_static(&fdc37m81x_type_info); } type_init(isa_superio_register_types) diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 5df3c09cd5..73c6470805 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -23,6 +23,10 @@ config ISA_SUPERIO # Some users of ISA_SUPERIO do not use it #select IDE_ISA +config FDC37M81X + bool + select ISA_SUPERIO + config PC87312 bool select ISA_SUPERIO diff --git a/hw/isa/meson.build b/hw/isa/meson.build index 2ab99ce0c6..f650b39507 100644 --- a/hw/isa/meson.build +++ b/hw/isa/meson.build @@ -4,6 +4,7 @@ system_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c')) system_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c')) system_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c')) system_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c')) +system_ss.add(when: 'CONFIG_FDC37M81X', if_true: files('fdc37m81x-superio.c')) system_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c')) system_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c')) diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index afcfb2b8ec..e57db4f641 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,7 +1,7 @@ config MALTA bool + select FDC37M81X select GT64120 - select ISA_SUPERIO select PIIX config MIPSSIM From patchwork Thu Feb 15 17:57:14 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 10:00:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Yoshinori Sato , Richard Henderson Subject: [PULL 20/56] hw/rx/rx62n: Reduce inclusion of 'qemu/units.h' Date: Thu, 15 Feb 2024 18:57:14 +0100 Message-ID: <20240215175752.82828-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org "qemu/units.h" is not used in the "hw/rx/rx62n.h" header, include it in the source where it is. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-3-philmd@linaro.org> --- include/hw/rx/rx62n.h | 1 - hw/rx/rx-gdbsim.c | 1 + hw/rx/rx62n.c | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index 73ceeb58e5..bcda583ab3 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -29,7 +29,6 @@ #include "hw/timer/renesas_tmr.h" #include "hw/timer/renesas_cmt.h" #include "hw/char/renesas_sci.h" -#include "qemu/units.h" #include "qom/object.h" #define TYPE_RX62N_MCU "rx62n-mcu" diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 47c17026c7..bb4746c556 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -20,6 +20,7 @@ #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" +#include "qemu/units.h" #include "qapi/error.h" #include "hw/loader.h" #include "hw/rx/rx62n.h" diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 4dc44afd9d..d3f61a6837 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -23,6 +23,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/error-report.h" +#include "qemu/units.h" #include "hw/rx/rx62n.h" #include "hw/loader.h" #include "hw/sysbus.h" From patchwork Thu Feb 15 17:57:15 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 10:00:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Yoshinori Sato , Richard Henderson Subject: [PULL 21/56] hw/rx/rx62n: Only call qdev_get_gpio_in() when necessary Date: Thu, 15 Feb 2024 18:57:15 +0100 Message-ID: <20240215175752.82828-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of filling an array of all the possible IRQs, only call qdev_get_gpio_in() when an IRQ is used. Remove the array from RX62NState. Doing so we avoid calling qdev_get_gpio_in() on an unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-4-philmd@linaro.org> --- include/hw/rx/rx62n.h | 1 - hw/rx/rx62n.c | 16 ++++++++-------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h index bcda583ab3..766fe0e435 100644 --- a/include/hw/rx/rx62n.h +++ b/include/hw/rx/rx62n.h @@ -67,7 +67,6 @@ struct RX62NState { MemoryRegion iomem2; MemoryRegion iomem3; MemoryRegion c_flash; - qemu_irq irq[NR_IRQS]; /* Input Clock (XTAL) frequency */ uint32_t xtal_freq_hz; diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index d3f61a6837..560f53a58a 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -148,14 +148,11 @@ static void register_icu(RX62NState *s) qlist_append_int(trigger_level, levelirq[i]); } qdev_prop_set_array(DEVICE(icu), "trigger-level", trigger_level); - - for (i = 0; i < NR_IRQS; i++) { - s->irq[i] = qdev_get_gpio_in(DEVICE(icu), i); - } sysbus_realize(icu, &error_abort); + sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IRQ)); sysbus_connect_irq(icu, 1, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_FIR)); - sysbus_connect_irq(icu, 2, s->irq[SWI]); + sysbus_connect_irq(icu, 2, qdev_get_gpio_in(DEVICE(&s->icu), SWI)); sysbus_mmio_map(icu, 0, RX62N_ICU_BASE); } @@ -172,7 +169,8 @@ static void register_tmr(RX62NState *s, int unit) irqbase = RX62N_TMR_IRQ + TMR_NR_IRQ * unit; for (i = 0; i < TMR_NR_IRQ; i++) { - sysbus_connect_irq(tmr, i, s->irq[irqbase + i]); + sysbus_connect_irq(tmr, i, + qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i)); } sysbus_mmio_map(tmr, 0, RX62N_TMR_BASE + unit * 0x10); } @@ -190,7 +188,8 @@ static void register_cmt(RX62NState *s, int unit) irqbase = RX62N_CMT_IRQ + CMT_NR_IRQ * unit; for (i = 0; i < CMT_NR_IRQ; i++) { - sysbus_connect_irq(cmt, i, s->irq[irqbase + i]); + sysbus_connect_irq(cmt, i, + qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i)); } sysbus_mmio_map(cmt, 0, RX62N_CMT_BASE + unit * 0x10); } @@ -209,7 +208,8 @@ static void register_sci(RX62NState *s, int unit) irqbase = RX62N_SCI_IRQ + SCI_NR_IRQ * unit; for (i = 0; i < SCI_NR_IRQ; i++) { - sysbus_connect_irq(sci, i, s->irq[irqbase + i]); + sysbus_connect_irq(sci, i, + qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i)); } sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08); } From patchwork Thu Feb 15 17:57:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EAB4AC48BC4 for ; Thu, 15 Feb 2024 18:05:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag2O-0000Wp-Cj; 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Thu, 15 Feb 2024 10:00:18 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id pj7-20020a170906d78700b00a3d1b41bb48sm787064ejb.130.2024.02.15.10.00.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:00:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Damien Hedde , BALATON Zoltan , Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Subject: [PULL 22/56] hw/i386/q35: Realize LPC PCI function before accessing it Date: Thu, 15 Feb 2024 18:57:16 +0100 Message-ID: <20240215175752.82828-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should not wire IRQs on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Damien Hedde Reviewed-by: BALATON Zoltan Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-5-philmd@linaro.org> --- hw/i386/pc_q35.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 7ca3f465e0..b7c69d55d6 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -248,13 +248,13 @@ static void pc_q35_init(MachineState *machine) /* create ISA bus */ lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), TYPE_ICH9_LPC_DEVICE); - qdev_prop_set_bit(DEVICE(lpc), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); lpc_dev = DEVICE(lpc); + qdev_prop_set_bit(lpc_dev, "smm-enabled", + x86_machine_is_smm_enabled(x86ms)); + pci_realize_and_unref(lpc, host_bus, &error_fatal); for (i = 0; i < IOAPIC_NUM_PINS; i++) { qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); } - pci_realize_and_unref(lpc, host_bus, &error_fatal); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 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Thu, 15 Feb 2024 10:00:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Mark Cave-Ayland , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= Subject: [PULL 23/56] hw/ppc/prep: Realize ISA bridge before accessing it Date: Thu, 15 Feb 2024 18:57:17 +0100 Message-ID: <20240215175752.82828-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=philmd@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should not wire IRQs on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-6-philmd@linaro.org> --- hw/ppc/prep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 1a6cd05c61..4eb5477069 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -278,9 +278,9 @@ static void ibm_40p_init(MachineState *machine) /* PCI -> ISA bridge */ i82378_dev = DEVICE(pci_new(PCI_DEVFN(11, 0), "i82378")); + qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal); qdev_connect_gpio_out(i82378_dev, 0, qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); - qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal); sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); From patchwork Thu Feb 15 17:57:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2165C48BC4 for ; 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Thu, 15 Feb 2024 10:00:33 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id a7-20020a170906670700b00a3d2d81daafsm791088ejp.172.2024.02.15.10.00.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:00:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , BALATON Zoltan , Richard Henderson Subject: [PULL 24/56] hw/misc/macio: Realize IDE controller before accessing it Date: Thu, 15 Feb 2024 18:57:18 +0100 Message-ID: <20240215175752.82828-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should not wire IRQs on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Reviewed-by: BALATON Zoltan Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-7-philmd@linaro.org> --- hw/misc/macio/macio.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index c9f22f8515..3f449f91c0 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -123,14 +123,17 @@ static bool macio_realize_ide(MacIOState *s, MACIOIDEState *ide, { SysBusDevice *sbd = SYS_BUS_DEVICE(ide); - sysbus_connect_irq(sbd, 0, irq0); - sysbus_connect_irq(sbd, 1, irq1); qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma), &error_abort); macio_ide_register_dma(ide); + if (!qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp)) { + return false; + } + sysbus_connect_irq(sbd, 0, irq0); + sysbus_connect_irq(sbd, 1, irq1); - return qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp); + return true; } static void macio_oldworld_realize(PCIDevice *d, Error **errp) From patchwork Thu Feb 15 17:57:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72514C4829E for ; Thu, 15 Feb 2024 18:06:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag2U-0001Ed-Fb; Thu, 15 Feb 2024 13:00:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag2P-0000hA-8k for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 10:00:41 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id fj5-20020a1709069c8500b00a3d310a2684sm783255ejc.158.2024.02.15.10.00.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:00:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Yoshinori Sato , Richard Henderson , Magnus Damm Subject: [PULL 25/56] hw/sh4/r2d: Realize IDE controller before accessing it Date: Thu, 15 Feb 2024 18:57:19 +0100 Message-ID: <20240215175752.82828-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should not wire IRQs on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-8-philmd@linaro.org> --- hw/sh4/r2d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index e9f316a6ce..c73e8f49b8 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -285,9 +285,9 @@ static void r2d_init(MachineState *machine) dinfo = drive_get(IF_IDE, 0, 0); dev = qdev_new("mmio-ide"); busdev = SYS_BUS_DEVICE(dev); - sysbus_connect_irq(busdev, 0, irq[CF_IDE]); qdev_prop_set_uint32(dev, "shift", 1); sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_connect_irq(busdev, 0, irq[CF_IDE]); sysbus_mmio_map(busdev, 0, 0x14001000); sysbus_mmio_map(busdev, 1, 0x1400080c); mmio_ide_init_drives(dev, dinfo, NULL); From patchwork Thu Feb 15 17:57:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BE35C48BEF for ; Thu, 15 Feb 2024 18:05:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag2s-0002A6-60; Thu, 15 Feb 2024 13:01:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag2b-0001nM-Ha for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:00:59 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rag2U-0002MH-K5 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:00:57 -0500 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-55a5e7fa471so1614582a12.1 for ; Thu, 15 Feb 2024 10:00:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708020048; x=1708624848; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+ubSQX0s8XFIX39hOsqAJ21CHgufQEziwezWtT3SVxQ=; b=NdyP/VV2u7egJYv8FmmbmbmB/X2HN2b4XDxhpCaag+Ng0hsxouIBLxagswdFXToxou 8lkDyt0/VDgzfC2EaUSj0pflzkirbaBG+9HHiP5gtyPvZMdZtuLA62TvR0HidW0/o1CT gEbL7IggrmXab2/mEN7sj6QEx/D8sHOcmRNwnq6SzfxGLOOL9BtTQJdZt5V9PNpD+VCA OkmrgyDqjtFwKiUgjHeuvnyuvy99wfl+JWA2UJ3negeU6PywE8pxlJDZUMPisVDs8klI +3PcH9PrHJNluQgUeJ31IuJgWAJJ/kOauU1m+WRvSpRZPbTOmtqVvIdOkULTwRYz3AeK 3ppQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708020048; x=1708624848; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+ubSQX0s8XFIX39hOsqAJ21CHgufQEziwezWtT3SVxQ=; b=jGmr4hDf8BYgAVUeXgrGNVY6KUsyaRJ2908Lv86dt96vxlpNRk5GTAgjLGfpPn7GpD OqHXgKd3negThsf+3FaKiiNRbc4QBomSj469NeiSSZ1DbuWXDo4TPSOpthUIDRxwFs2i DXHRFiQdUQ5vFjGw2O9eFMYAZPhamDstcPUE97n5lauxuIYaC3YYVhqvEk3V20Ce7RBy Wo8s1OqHObQs7ONhTq4On7rfkmMFtOfgZlzuHDjgjb6Ox5UDvRQQi8WdAawltzeFjZ7Y wEJ5Q6tpp0U+q1TTurtna/E1hJicU+Z7yUO4eHyk/ZFaxLVfQrbBAwwCE/CuKEXieZQl MD6w== X-Gm-Message-State: AOJu0YweE+IPV6UlwQl6SCQjPer/0GE9q4Z0JpzrzB/Ns180xc2sci83 kSg0Vt3W7Ak9Qc8uSM3a7atg5vY7RUPfSOKRNfxjCc8c4WzU8LzJQfhMJCYIyGrvFsiHevBwsfN G2aU= X-Google-Smtp-Source: AGHT+IGJbaHQZ1eeAOaIiG/S1WoGru5XoFqTkRGsl13ISfMES8bQ2V27fYMKtcfrPg6Pt1oI6wpyiQ== X-Received: by 2002:aa7:d38e:0:b0:562:f25:b125 with SMTP id x14-20020aa7d38e000000b005620f25b125mr1825343edq.36.1708020048674; Thu, 15 Feb 2024 10:00:48 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id fg8-20020a056402548800b00562ee409ea0sm740914edb.62.2024.02.15.10.00.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:00:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , "Michael S. Tsirkin" , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , BALATON Zoltan , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 26/56] hw/dma: Pass parent object to i8257_dma_init() Date: Thu, 15 Feb 2024 18:57:20 +0100 Message-ID: <20240215175752.82828-27-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set I8257 instances parent (migration isn't affected). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240213114426.87836-1-philmd@linaro.org> --- include/hw/dma/i8257.h | 2 +- hw/dma/i82374.c | 2 +- hw/dma/i8257.c | 4 +++- hw/i386/pc_piix.c | 2 +- hw/isa/lpc_ich9.c | 2 +- hw/isa/piix.c | 2 +- hw/isa/vt82c686.c | 2 +- hw/mips/jazz.c | 2 +- 8 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/hw/dma/i8257.h b/include/hw/dma/i8257.h index f652345d65..4342e4a91e 100644 --- a/include/hw/dma/i8257.h +++ b/include/hw/dma/i8257.h @@ -45,6 +45,6 @@ struct I8257State { PortioList portio_pageh; }; -void i8257_dma_init(ISABus *bus, bool high_page_enable); +void i8257_dma_init(Object *parent, ISABus *bus, bool high_page_enable); #endif diff --git a/hw/dma/i82374.c b/hw/dma/i82374.c index f6ddfc51c5..e72aa2e1ce 100644 --- a/hw/dma/i82374.c +++ b/hw/dma/i82374.c @@ -129,7 +129,7 @@ static void i82374_realize(DeviceState *dev, Error **errp) error_setg(errp, "DMA already initialized on ISA bus"); return; } - i8257_dma_init(isa_bus, true); + i8257_dma_init(OBJECT(dev), isa_bus, true); portio_list_init(&s->port_list, OBJECT(s), i82374_portio_list, s, "i82374"); diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index de1d5b110c..24a54ca272 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -632,12 +632,13 @@ static void i8257_register_types(void) type_init(i8257_register_types) -void i8257_dma_init(ISABus *bus, bool high_page_enable) +void i8257_dma_init(Object *parent, ISABus *bus, bool high_page_enable) { ISADevice *isa1, *isa2; DeviceState *d; isa1 = isa_new(TYPE_I8257); + object_property_add_child(parent, "dma[*]", OBJECT(isa1)); d = DEVICE(isa1); qdev_prop_set_int32(d, "base", 0x00); qdev_prop_set_int32(d, "page-base", 0x80); @@ -646,6 +647,7 @@ void i8257_dma_init(ISABus *bus, bool high_page_enable) isa_realize_and_unref(isa1, bus, &error_fatal); isa2 = isa_new(TYPE_I8257); + object_property_add_child(parent, "dma[*]", OBJECT(isa2)); d = DEVICE(isa2); qdev_prop_set_int32(d, "base", 0xc0); qdev_prop_set_int32(d, "page-base", 0x88); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 70d12bb1b5..999b7b806c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -310,7 +310,7 @@ static void pc_init1(MachineState *machine, qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); isa_realize_and_unref(rtc_state, isa_bus, &error_fatal); - i8257_dma_init(isa_bus, 0); + i8257_dma_init(OBJECT(machine), isa_bus, 0); pcms->hpet_enabled = false; idebus[0] = NULL; idebus[1] = NULL; diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 3924eec483..70c6e8a093 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -739,7 +739,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) isa_bus_register_input_irqs(isa_bus, lpc->gsi); - i8257_dma_init(isa_bus, 0); + i8257_dma_init(OBJECT(d), isa_bus, 0); /* RTC */ qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 344bf32e54..2d30711b17 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -336,7 +336,7 @@ static void pci_piix_realize(PCIDevice *dev, const char *uhci_type, i8254_pit_init(isa_bus, 0x40, 0, NULL); } - i8257_dma_init(isa_bus, 0); + i8257_dma_init(OBJECT(dev), isa_bus, 0); /* RTC */ qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000); diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 0c504de36e..aa91942745 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -731,7 +731,7 @@ static void via_isa_realize(PCIDevice *d, Error **errp) s->isa_irqs_in = i8259_init(isa_bus, *isa_irq); isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in); i8254_pit_init(isa_bus, 0x40, 0, NULL); - i8257_dma_init(isa_bus, 0); + i8257_dma_init(OBJECT(d), isa_bus, 0); /* RTC */ qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 5bf3e328db..1bc17e69d3 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -289,7 +289,7 @@ static void mips_jazz_init(MachineState *machine, /* ISA devices */ i8259 = i8259_init(isa_bus, env->irq[4]); isa_bus_register_input_irqs(isa_bus, i8259); - i8257_dma_init(isa_bus, 0); + i8257_dma_init(OBJECT(rc4030), isa_bus, 0); pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); pcspk = isa_new(TYPE_PC_SPEAKER); object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal); From patchwork Thu Feb 15 17:57:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0239BC48BEF for ; Thu, 15 Feb 2024 18:05:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag2q-000292-Tq; Thu, 15 Feb 2024 13:01:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag2d-0001qa-Ic for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 10:00:55 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id g6-20020aa7c586000000b005619eea3d52sm754712edq.8.2024.02.15.10.00.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:00:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Mark Cave-Ayland , Richard Henderson , Artyom Tarasenko Subject: [PULL 27/56] hw/sparc/sun4m: Realize DMA controller before accessing it Date: Thu, 15 Feb 2024 18:57:21 +0100 Message-ID: <20240215175752.82828-28-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should not wire IRQs on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-9-philmd@linaro.org> --- hw/sparc/sun4m.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index e782c8ec7a..d52e6a7213 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -312,13 +312,11 @@ static void *sparc32_dma_init(hwaddr dma_base, dma = qdev_new(TYPE_SPARC32_DMA); espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( OBJECT(dma), "espdma")); - sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( OBJECT(dma), "ledma")); - sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); lance = SYSBUS_PCNET(object_resolve_path_component( OBJECT(ledma), "lance")); @@ -332,6 +330,11 @@ static void *sparc32_dma_init(hwaddr dma_base, } sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); + + sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); + + sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); + sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); From patchwork Thu Feb 15 17:57:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65B4AC48BC4 for ; Thu, 15 Feb 2024 18:02:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag2v-0002MF-Ts; Thu, 15 Feb 2024 13:01:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag2n-00022O-Ny for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 10:01:02 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id s12-20020a17090699cc00b00a3d943558b8sm744210ejn.134.2024.02.15.10.01.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:01:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Mark Cave-Ayland , Damien Hedde , Richard Henderson , Artyom Tarasenko Subject: [PULL 28/56] hw/sparc64/cpu: Initialize GPIO before realizing CPU devices Date: Thu, 15 Feb 2024 18:57:22 +0100 Message-ID: <20240215175752.82828-29-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Inline cpu_create() in order to call qdev_init_gpio_in_named_with_opaque() before the CPU is realized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Mark Cave-Ayland Reviewed-by: Damien Hedde Reviewed-by: Richard Henderson Message-Id: <20240213130341.1793-13-philmd@linaro.org> --- hw/sparc64/sparc64.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index 72f0849f50..3091cde586 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" +#include "qapi/error.h" #include "cpu.h" #include "hw/boards.h" #include "hw/sparc/sparc64.h" @@ -271,9 +272,10 @@ SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr) uint32_t stick_frequency = 100 * 1000000; uint32_t hstick_frequency = 100 * 1000000; - cpu = SPARC_CPU(cpu_create(cpu_type)); + cpu = SPARC_CPU(object_new(cpu_type)); qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq, "ivec-irq", IVEC_MAX); + qdev_realize(DEVICE(cpu), NULL, &error_fatal); env = &cpu->env; env->tick = cpu_timer_create("tick", cpu, tick_irq, From patchwork Thu Feb 15 17:57:23 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 10:01:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Cl?= =?utf-8?q?=C3=A9ment_Chigot?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 29/56] target/sparc: Provide hint about CPUSPARCState::irq_manager member Date: Thu, 15 Feb 2024 18:57:23 +0100 Message-ID: <20240215175752.82828-30-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org CPUSPARCState::irq_manager holds a pointer to a QDev, so declare it as DeviceState instead of void. Move the comment about Leon3 fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Clément Chigot Message-Id: <20240130113102.6732-3-philmd@linaro.org> --- target/sparc/cpu.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index edf46b387e..f3cdd17c62 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -545,10 +545,9 @@ struct CPUArchState { #endif sparc_def_t def; - void *irq_manager; + /* Leon3 */ + DeviceState *irq_manager; void (*qemu_irq_ack)(CPUSPARCState *env, int intno); - - /* Leon3 cache control */ uint32_t cache_control; }; From patchwork Thu Feb 15 17:57:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BECC3C4829E for ; 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Thu, 15 Feb 2024 10:01:15 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id et5-20020a056402378500b00563c63e0a13sm400264edb.49.2024.02.15.10.01.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:01:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Cl?= =?utf-8?q?=C3=A9ment_Chigot?= , Frederic Konrad , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 30/56] hw/sparc/leon3: Remove duplicate code Date: Thu, 15 Feb 2024 18:57:24 +0100 Message-ID: <20240215175752.82828-31-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=philmd@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since commit b04d989054 ("SPARC: Emulation of Leon3") the main_cpu_reset() handler sets both pc/npc when the CPU is reset, after the machine is realized. It is pointless to set it in leon3_generic_hw_init(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Clément Chigot Message-Id: <20240130113102.6732-3-philmd@linaro.org> --- hw/sparc/leon3.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 2dfb742566..1ae9a37583 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -343,8 +343,6 @@ static void leon3_generic_hw_init(MachineState *machine) bootloader_entry = memory_region_get_ram_ptr(prom); write_bootloader(env, bootloader_entry, entry); - env->pc = LEON3_PROM_OFFSET; - env->npc = LEON3_PROM_OFFSET + 4; reset_info->entry = LEON3_PROM_OFFSET; } } From patchwork Thu Feb 15 17:57:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D86A1C4829E for ; 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Thu, 15 Feb 2024 10:01:21 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id wb4-20020a170907d50400b00a3cf4e8fdf5sm788702ejc.150.2024.02.15.10.01.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:01:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 31/56] hw/sparc/leon3: Remove unused 'env' argument of write_bootloader() Date: Thu, 15 Feb 2024 18:57:25 +0100 Message-ID: <20240215175752.82828-32-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 'CPUSPARCState *env' argument is unused, remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-Id: <20240215132824.67363-2-philmd@linaro.org> --- hw/sparc/leon3.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 1ae9a37583..5c670b92db 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -94,8 +94,7 @@ static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) * state (eg: initialized by the bootloader). This little code reproduces * this behavior. */ -static void write_bootloader(CPUSPARCState *env, uint8_t *base, - hwaddr kernel_addr) +static void write_bootloader(uint8_t *base, hwaddr kernel_addr) { uint32_t *p = (uint32_t *) base; @@ -342,7 +341,7 @@ static void leon3_generic_hw_init(MachineState *machine) uint8_t *bootloader_entry; bootloader_entry = memory_region_get_ram_ptr(prom); - write_bootloader(env, bootloader_entry, entry); + write_bootloader(bootloader_entry, entry); reset_info->entry = LEON3_PROM_OFFSET; } } From patchwork Thu Feb 15 17:57:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C91BC4829E for ; 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Thu, 15 Feb 2024 10:01:28 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id kt22-20020a170906aad600b00a3d07f3ac61sm789679ejb.101.2024.02.15.10.01.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:01:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 32/56] hw/sparc/leon3: Have write_bootloader() take a void pointer argument Date: Thu, 15 Feb 2024 18:57:26 +0100 Message-ID: <20240215175752.82828-33-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Directly use the void pointer argument returned by memory_region_get_ram_ptr(). Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240215132824.67363-3-philmd@linaro.org> --- hw/sparc/leon3.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 5c670b92db..fa4fbe4b30 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -94,9 +94,9 @@ static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) * state (eg: initialized by the bootloader). This little code reproduces * this behavior. */ -static void write_bootloader(uint8_t *base, hwaddr kernel_addr) +static void write_bootloader(void *ptr, hwaddr kernel_addr) { - uint32_t *p = (uint32_t *) base; + uint32_t *p = ptr; /* Initialize the UARTs */ /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */ @@ -338,10 +338,7 @@ static void leon3_generic_hw_init(MachineState *machine) * the machine in an initialized state through a little * bootloader. */ - uint8_t *bootloader_entry; - - bootloader_entry = memory_region_get_ram_ptr(prom); - write_bootloader(bootloader_entry, entry); + write_bootloader(memory_region_get_ram_ptr(prom), entry); reset_info->entry = LEON3_PROM_OFFSET; } } From patchwork Thu Feb 15 17:57:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD80DC4829E for ; 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Thu, 15 Feb 2024 10:01:35 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id b11-20020a05600003cb00b0033d07edbaa6sm2087249wrg.110.2024.02.15.10.01.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:01:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 33/56] hw/sparc/grlib: split out the headers for each peripherals Date: Thu, 15 Feb 2024 18:57:27 +0100 Message-ID: <20240215175752.82828-34-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot Split out the headers for each peripherals and move them in their right hardware directory. Update Copyright and add SPDX-License-Identifier at the same time. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240131085047.18458-2-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/char/grlib_uart.h | 32 +++++++++++++++++++ .../hw/{sparc/grlib.h => intc/grlib_irqmp.h} | 16 ++++------ include/hw/timer/grlib_gptimer.h | 32 +++++++++++++++++++ hw/char/grlib_apbuart.c | 6 ++-- hw/intc/grlib_irqmp.c | 6 ++-- hw/sparc/leon3.c | 8 +++-- hw/timer/grlib_gptimer.c | 6 ++-- 7 files changed, 88 insertions(+), 18 deletions(-) create mode 100644 include/hw/char/grlib_uart.h rename include/hw/{sparc/grlib.h => intc/grlib_irqmp.h} (86%) create mode 100644 include/hw/timer/grlib_gptimer.h diff --git a/include/hw/char/grlib_uart.h b/include/hw/char/grlib_uart.h new file mode 100644 index 0000000000..7496f8fd5e --- /dev/null +++ b/include/hw/char/grlib_uart.h @@ -0,0 +1,32 @@ +/* + * QEMU GRLIB UART + * + * SPDX-License-Identifier: MIT + * + * Copyright (c) 2024 AdaCore + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef GRLIB_UART_H +#define GRLIB_UART_H + +#define TYPE_GRLIB_APB_UART "grlib-apbuart" + +#endif diff --git a/include/hw/sparc/grlib.h b/include/hw/intc/grlib_irqmp.h similarity index 86% rename from include/hw/sparc/grlib.h rename to include/hw/intc/grlib_irqmp.h index ef1946c7f8..c5a90cbb3e 100644 --- a/include/hw/sparc/grlib.h +++ b/include/hw/intc/grlib_irqmp.h @@ -1,7 +1,9 @@ /* * QEMU GRLIB Components * - * Copyright (c) 2010-2019 AdaCore + * SPDX-License-Identifier: MIT + * + * Copyright (c) 2010-2024 AdaCore * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -22,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef GRLIB_H -#define GRLIB_H +#ifndef GRLIB_IRQMP_H +#define GRLIB_IRQMP_H #include "hw/sysbus.h" @@ -36,10 +38,4 @@ void grlib_irqmp_ack(DeviceState *dev, int intno); -/* GPTimer */ -#define TYPE_GRLIB_GPTIMER "grlib-gptimer" - -/* APB UART */ -#define TYPE_GRLIB_APB_UART "grlib-apbuart" - -#endif /* GRLIB_H */ +#endif /* GRLIB_IRQMP_H */ diff --git a/include/hw/timer/grlib_gptimer.h b/include/hw/timer/grlib_gptimer.h new file mode 100644 index 0000000000..e56f1b8bf3 --- /dev/null +++ b/include/hw/timer/grlib_gptimer.h @@ -0,0 +1,32 @@ +/* + * QEMU GRLIB GPTimer + * + * SPDX-License-Identifier: MIT + * + * Copyright (c) 2024 AdaCore + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef GRLIB_GPTIMER_H +#define GRLIB_GPTIMER_H + +#define TYPE_GRLIB_GPTIMER "grlib-gptimer" + +#endif diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c index 82ff40a530..515b65bc07 100644 --- a/hw/char/grlib_apbuart.c +++ b/hw/char/grlib_apbuart.c @@ -1,7 +1,9 @@ /* * QEMU GRLIB APB UART Emulator * - * Copyright (c) 2010-2019 AdaCore + * SPDX-License-Identifier: MIT + * + * Copyright (c) 2010-2024 AdaCore * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,7 +28,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" -#include "hw/sparc/grlib.h" +#include "hw/char/grlib_uart.h" #include "hw/sysbus.h" #include "qemu/module.h" #include "chardev/char-fe.h" diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 3bfe2544b7..11eef62457 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -3,7 +3,9 @@ * * (Multiprocessor and extended interrupt not supported) * - * Copyright (c) 2010-2019 AdaCore + * SPDX-License-Identifier: MIT + * + * Copyright (c) 2010-2024 AdaCore * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,7 +31,7 @@ #include "hw/sysbus.h" #include "hw/qdev-properties.h" -#include "hw/sparc/grlib.h" +#include "hw/intc/grlib_irqmp.h" #include "trace.h" #include "qapi/error.h" diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index fa4fbe4b30..e80b9410d4 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -1,7 +1,9 @@ /* * QEMU Leon3 System Emulator * - * Copyright (c) 2010-2019 AdaCore + * SPDX-License-Identifier: MIT + * + * Copyright (c) 2010-2024 AdaCore * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -40,7 +42,9 @@ #include "elf.h" #include "trace.h" -#include "hw/sparc/grlib.h" +#include "hw/timer/grlib_gptimer.h" +#include "hw/char/grlib_uart.h" +#include "hw/intc/grlib_irqmp.h" #include "hw/misc/grlib_ahb_apb_pnp.h" /* Default system clock. */ diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index 5c4923c1e0..4990885451 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -1,7 +1,9 @@ /* * QEMU GRLIB GPTimer Emulator * - * Copyright (c) 2010-2019 AdaCore + * SPDX-License-Identifier: MIT + * + * Copyright (c) 2010-2024 AdaCore * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,7 +25,7 @@ */ #include "qemu/osdep.h" -#include "hw/sparc/grlib.h" +#include "hw/timer/grlib_gptimer.h" #include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/irq.h" From patchwork Thu Feb 15 17:57:28 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 10:01:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 34/56] hw/intc/grlib_irqmp: add ncpus property Date: Thu, 15 Feb 2024 18:57:28 +0100 Message-ID: <20240215175752.82828-35-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=philmd@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot This adds a "ncpus" property to the "grlib-irqmp" device to be used later, this required a little refactoring of how we initialize the device (ie: use realize instead of init). Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240131085047.18458-3-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/grlib_irqmp.c | 30 +++++++++++++++++++++--------- hw/sparc/leon3.c | 2 +- 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 11eef62457..744cd64c58 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -1,7 +1,7 @@ /* * QEMU GRLIB IRQMP Emulator * - * (Multiprocessor and extended interrupt not supported) + * (Extended interrupt not supported) * * SPDX-License-Identifier: MIT * @@ -63,6 +63,7 @@ struct IRQMP { MemoryRegion iomem; + unsigned int ncpus; IRQMPState *state; qemu_irq irq; }; @@ -326,33 +327,44 @@ static void grlib_irqmp_reset(DeviceState *d) irqmp->state->parent = irqmp; } -static void grlib_irqmp_init(Object *obj) +static void grlib_irqmp_realize(DeviceState *dev, Error **errp) { - IRQMP *irqmp = GRLIB_IRQMP(obj); - SysBusDevice *dev = SYS_BUS_DEVICE(obj); + IRQMP *irqmp = GRLIB_IRQMP(dev); - qdev_init_gpio_in(DEVICE(obj), grlib_irqmp_set_irq, MAX_PILS); - qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1); - memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp, + if ((!irqmp->ncpus) || (irqmp->ncpus > IRQMP_MAX_CPU)) { + error_setg(errp, "Invalid ncpus properties: " + "%u, must be 0 < ncpus =< %u.", irqmp->ncpus, + IRQMP_MAX_CPU); + } + + qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS); + qdev_init_gpio_out_named(dev, &irqmp->irq, "grlib-irq", 1); + memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp, "irqmp", IRQMP_REG_SIZE); irqmp->state = g_malloc0(sizeof *irqmp->state); - sysbus_init_mmio(dev, &irqmp->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &irqmp->iomem); } +static Property grlib_irqmp_properties[] = { + DEFINE_PROP_UINT32("ncpus", IRQMP, ncpus, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void grlib_irqmp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = grlib_irqmp_realize; dc->reset = grlib_irqmp_reset; + device_class_set_props(dc, grlib_irqmp_properties); } static const TypeInfo grlib_irqmp_info = { .name = TYPE_GRLIB_IRQMP, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(IRQMP), - .instance_init = grlib_irqmp_init, .class_init = grlib_irqmp_class_init, }; diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index e80b9410d4..bc6a85be9c 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -264,11 +264,11 @@ static void leon3_generic_hw_init(MachineState *machine) /* Allocate IRQ manager */ irqmpdev = qdev_new(TYPE_GRLIB_IRQMP); + sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal); qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in, env, "pil", 1); qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0, qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0)); - sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET); env->irq_manager = irqmpdev; env->qemu_irq_ack = leon3_irq_manager; From patchwork Thu Feb 15 17:57:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F9ABC4829E for ; Thu, 15 Feb 2024 18:04:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag41-0004Z6-2Z; Thu, 15 Feb 2024 13:02:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag3Y-0003JH-Uj for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 10:01:48 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id bu23-20020a056000079700b0033cdf4bea19sm2621169wrb.9.2024.02.15.10.01.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:01:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 35/56] hw/intc/grlib_irqmp: implements the multiprocessor status register Date: Thu, 15 Feb 2024 18:57:29 +0100 Message-ID: <20240215175752.82828-36-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot This implements the multiprocessor status register in grlib-irqmp and bind it to a start signal, which will be later wired in leon3-generic to start a cpu. The EIRQ and BA bits are not implemented. Based on https://gaisler.com/doc/gr712rc-usermanual.pdf, §8.3.5. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240131085047.18458-4-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/grlib_irqmp.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 744cd64c58..1e073bd232 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -52,6 +52,10 @@ #define FORCE_OFFSET 0x80 #define EXTENDED_OFFSET 0xC0 +/* Multiprocessor Status Register */ +#define MP_STATUS_CPU_STATUS_MASK ((1 << IRQMP_MAX_CPU)-2) +#define MP_STATUS_NCPU_SHIFT 28 + #define MAX_PILS 16 OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP) @@ -65,6 +69,7 @@ struct IRQMP { unsigned int ncpus; IRQMPState *state; + qemu_irq start_signal[IRQMP_MAX_CPU]; qemu_irq irq; }; @@ -72,6 +77,7 @@ struct IRQMPState { uint32_t level; uint32_t pending; uint32_t clear; + uint32_t mpstatus; uint32_t broadcast; uint32_t mask[IRQMP_MAX_CPU]; @@ -182,10 +188,12 @@ static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr, return state->force[0]; case CLEAR_OFFSET: - case MP_STATUS_OFFSET: /* Always read as 0 */ return 0; + case MP_STATUS_OFFSET: + return state->mpstatus; + case BROADCAST_OFFSET: return state->broadcast; @@ -224,8 +232,9 @@ static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr, static void grlib_irqmp_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - IRQMP *irqmp = opaque; + IRQMP *irqmp = opaque; IRQMPState *state; + int i; assert(irqmp != NULL); state = irqmp->state; @@ -258,7 +267,18 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr, return; case MP_STATUS_OFFSET: - /* Read Only (no SMP support) */ + /* + * Writing and reading operations are reversed for the CPU status. + * Writing "1" will start the CPU, but reading "1" means that the CPU + * is power-down. + */ + value &= MP_STATUS_CPU_STATUS_MASK; + for (i = 0; i < irqmp->ncpus; i++) { + if ((value >> i) & 1) { + qemu_set_irq(irqmp->start_signal[i], 1); + state->mpstatus &= ~(1 << i); + } + } return; case BROADCAST_OFFSET: @@ -325,6 +345,8 @@ static void grlib_irqmp_reset(DeviceState *d) memset(irqmp->state, 0, sizeof *irqmp->state); irqmp->state->parent = irqmp; + irqmp->state->mpstatus = ((irqmp->ncpus - 1) << MP_STATUS_NCPU_SHIFT) | + ((1 << irqmp->ncpus) - 2); } static void grlib_irqmp_realize(DeviceState *dev, Error **errp) @@ -338,6 +360,13 @@ static void grlib_irqmp_realize(DeviceState *dev, Error **errp) } qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS); + + /* + * Transitionning from 0 to 1 starts the CPUs. The opposite can't + * happen. + */ + qdev_init_gpio_out_named(dev, irqmp->start_signal, "grlib-start-cpu", + IRQMP_MAX_CPU); qdev_init_gpio_out_named(dev, &irqmp->irq, "grlib-irq", 1); memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp, "irqmp", IRQMP_REG_SIZE); From patchwork Thu Feb 15 17:57:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A21DC48BC4 for ; Thu, 15 Feb 2024 18:08:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag47-0005BD-Kr; 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Thu, 15 Feb 2024 10:01:56 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id n9-20020a05600c294900b00410cc2f5550sm5662269wmd.19.2024.02.15.10.01.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:01:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 36/56] hw/intc/grlib_irqmp: implements multicore irq Date: Thu, 15 Feb 2024 18:57:30 +0100 Message-ID: <20240215175752.82828-37-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot Now there is an ncpus property, use it in order to deliver the IRQ to multiple CPU. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240131085047.18458-5-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/grlib_irqmp.h | 2 +- hw/intc/grlib_irqmp.c | 41 +++++++++++++++++------------------ hw/sparc/leon3.c | 3 ++- 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/hw/intc/grlib_irqmp.h b/include/hw/intc/grlib_irqmp.h index c5a90cbb3e..a76acbf940 100644 --- a/include/hw/intc/grlib_irqmp.h +++ b/include/hw/intc/grlib_irqmp.h @@ -36,6 +36,6 @@ /* IRQMP */ #define TYPE_GRLIB_IRQMP "grlib-irqmp" -void grlib_irqmp_ack(DeviceState *dev, int intno); +void grlib_irqmp_ack(DeviceState *dev, unsigned int cpu, int intno); #endif /* GRLIB_IRQMP_H */ diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 1e073bd232..144b121d48 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -70,7 +70,7 @@ struct IRQMP { unsigned int ncpus; IRQMPState *state; qemu_irq start_signal[IRQMP_MAX_CPU]; - qemu_irq irq; + qemu_irq irq[IRQMP_MAX_CPU]; }; struct IRQMPState { @@ -89,37 +89,35 @@ struct IRQMPState { static void grlib_irqmp_check_irqs(IRQMPState *state) { - uint32_t pend = 0; - uint32_t level0 = 0; - uint32_t level1 = 0; + int i; assert(state != NULL); assert(state->parent != NULL); - /* IRQ for CPU 0 (no SMP support) */ - pend = (state->pending | state->force[0]) - & state->mask[0]; + for (i = 0; i < state->parent->ncpus; i++) { + uint32_t pend = (state->pending | state->force[i]) & state->mask[i]; + uint32_t level0 = pend & ~state->level; + uint32_t level1 = pend & state->level; - level0 = pend & ~state->level; - level1 = pend & state->level; + trace_grlib_irqmp_check_irqs(state->pending, state->force[i], + state->mask[i], level1, level0); - trace_grlib_irqmp_check_irqs(state->pending, state->force[0], - state->mask[0], level1, level0); - - /* Trigger level1 interrupt first and level0 if there is no level1 */ - qemu_set_irq(state->parent->irq, level1 ?: level0); + /* Trigger level1 interrupt first and level0 if there is no level1 */ + qemu_set_irq(state->parent->irq[i], level1 ?: level0); + } } -static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask) +static void grlib_irqmp_ack_mask(IRQMPState *state, unsigned int cpu, + uint32_t mask) { /* Clear registers */ state->pending &= ~mask; - state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */ + state->force[cpu] &= ~mask; grlib_irqmp_check_irqs(state); } -void grlib_irqmp_ack(DeviceState *dev, int intno) +void grlib_irqmp_ack(DeviceState *dev, unsigned int cpu, int intno) { IRQMP *irqmp = GRLIB_IRQMP(dev); IRQMPState *state; @@ -133,7 +131,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno) trace_grlib_irqmp_ack(intno); - grlib_irqmp_ack_mask(state, mask); + grlib_irqmp_ack_mask(state, cpu, mask); } static void grlib_irqmp_set_irq(void *opaque, int irq, int level) @@ -159,7 +157,6 @@ static void grlib_irqmp_set_irq(void *opaque, int irq, int level) s->pending |= 1 << irq; } grlib_irqmp_check_irqs(s); - } } @@ -263,7 +260,9 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr, case CLEAR_OFFSET: value &= ~1; /* clean up the value */ - grlib_irqmp_ack_mask(state, value); + for (i = 0; i < irqmp->ncpus; i++) { + grlib_irqmp_ack_mask(state, i, value); + } return; case MP_STATUS_OFFSET: @@ -367,7 +366,7 @@ static void grlib_irqmp_realize(DeviceState *dev, Error **errp) */ qdev_init_gpio_out_named(dev, irqmp->start_signal, "grlib-start-cpu", IRQMP_MAX_CPU); - qdev_init_gpio_out_named(dev, &irqmp->irq, "grlib-irq", 1); + qdev_init_gpio_out_named(dev, irqmp->irq, "grlib-irq", irqmp->ncpus); memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp, "irqmp", IRQMP_REG_SIZE); diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index bc6a85be9c..3f86b74ba4 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -169,7 +169,8 @@ static void leon3_cache_control_int(CPUSPARCState *env) static void leon3_irq_ack(CPUSPARCState *env, int intno) { - grlib_irqmp_ack(env->irq_manager, intno); + /* No SMP support yet, only CPU #0 available so far. */ + grlib_irqmp_ack(env->irq_manager, 0, intno); } /* From patchwork Thu Feb 15 17:57:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 503C7C4829E for ; Thu, 15 Feb 2024 18:03:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag41-0004aC-8P; Thu, 15 Feb 2024 13:02:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag3q-0003le-00 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:02:15 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rag3j-0002h2-JK for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 10:02:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 37/56] target/sparc: implement asr17 feature for smp Date: Thu, 15 Feb 2024 18:57:31 +0100 Message-ID: <20240215175752.82828-38-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot This allows the guest program to know its cpu id. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240131085047.18458-6-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/helper.h | 1 + target/sparc/helper.c | 16 ++++++++++++++++ target/sparc/translate.c | 13 +++---------- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 6a42ba4e9e..e55fad5b8c 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -2,6 +2,7 @@ DEF_HELPER_1(rett, void, env) DEF_HELPER_2(wrpsr, void, env, tl) DEF_HELPER_1(rdpsr, tl, env) +DEF_HELPER_1(rdasr17, tl, env) DEF_HELPER_1(power_down, void, env) #else DEF_HELPER_FLAGS_2(wrpil, TCG_CALL_NO_RWG, void, env, tl) diff --git a/target/sparc/helper.c b/target/sparc/helper.c index bd10b60e4b..2247e243b5 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -212,4 +212,20 @@ void helper_power_down(CPUSPARCState *env) env->npc = env->pc + 4; cpu_loop_exit(cs); } + +target_ulong helper_rdasr17(CPUSPARCState *env) +{ + CPUState *cs = env_cpu(env); + target_ulong val; + + /* + * TODO: There are many more fields to be filled, + * some of which are writable. + */ + val = env->def.nwindows - 1; /* [4:0] NWIN */ + val |= 1 << 8; /* [8] V8 */ + val |= (cs->cpu_index) << 28; /* [31:28] INDEX */ + + return val; +} #endif diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d9304a5bc4..692ce0b010 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -37,6 +37,7 @@ #ifdef TARGET_SPARC64 # define gen_helper_rdpsr(D, E) qemu_build_not_reached() +# define gen_helper_rdasr17(D, E) qemu_build_not_reached() # define gen_helper_rett(E) qemu_build_not_reached() # define gen_helper_power_down(E) qemu_build_not_reached() # define gen_helper_wrpsr(E, S) qemu_build_not_reached() @@ -2382,16 +2383,8 @@ static bool trans_RDY(DisasContext *dc, arg_RDY *a) static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst) { - uint32_t val; - - /* - * TODO: There are many more fields to be filled, - * some of which are writable. - */ - val = dc->def->nwindows - 1; /* [4:0] NWIN */ - val |= 1 << 8; /* [8] V8 */ - - return tcg_constant_tl(val); + gen_helper_rdasr17(dst, tcg_env); + return dst; } TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config) From patchwork Thu Feb 15 17:57:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B564C4829E for ; Thu, 15 Feb 2024 18:08:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag47-0005Bz-Pm; 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Thu, 15 Feb 2024 10:02:09 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id o4-20020a05600c4fc400b00411d0b58056sm2900310wmq.5.2024.02.15.10.02.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:02:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Cl=C3=A9ment_Chigot?= , =?utf-8?q?Philippe_Ma?= =?utf-8?q?thieu-Daud=C3=A9?= , Frederic Konrad , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 38/56] hw/sparc/leon3: remove SP initialization Date: Thu, 15 Feb 2024 18:57:32 +0100 Message-ID: <20240215175752.82828-39-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot According to the doc (see §4.2.15 in [1]), the reset operation should not impact %SP. [1] https://gaisler.com/doc/gr712rc-usermanual.pdf Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240131085047.18458-7-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/sparc/leon3.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 3f86b74ba4..46fc1e783a 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -69,7 +69,6 @@ typedef struct ResetData { SPARCCPU *cpu; uint32_t entry; /* save kernel entry in case of reset */ - target_ulong sp; /* initial stack pointer */ } ResetData; static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) @@ -135,7 +134,6 @@ static void main_cpu_reset(void *opaque) cpu->halted = 0; env->pc = s->entry; env->npc = s->entry + 4; - env->regbase[6] = s->sp; } static void leon3_cache_control_int(CPUSPARCState *env) @@ -246,7 +244,6 @@ static void leon3_generic_hw_init(MachineState *machine) /* Reset data */ reset_info = g_new0(ResetData, 1); reset_info->cpu = cpu; - reset_info->sp = LEON3_RAM_OFFSET + ram_size; qemu_register_reset(main_cpu_reset, reset_info); ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP)); From patchwork Thu Feb 15 17:57:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17257C48BC4 for ; Thu, 15 Feb 2024 18:04:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag4E-00064k-J3; Thu, 15 Feb 2024 13:02:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag45-0004wi-SX for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 10:02:16 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id bt13-20020a056000080d00b0033d1739aedbsm18872wrb.95.2024.02.15.10.02.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:02:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 39/56] hw/sparc/leon3: implement multiprocessor Date: Thu, 15 Feb 2024 18:57:33 +0100 Message-ID: <20240215175752.82828-40-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot This allows to register more than one CPU on the leon3_generic machine. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Message-ID: <20240131085047.18458-8-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/sparc/leon3.c | 93 +++++++++++++++++++++++++++++++++++------------- 1 file changed, 68 insertions(+), 25 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 46fc1e783a..1637900162 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -54,6 +54,8 @@ #define LEON3_PROM_OFFSET (0x00000000) #define LEON3_RAM_OFFSET (0x40000000) +#define MAX_CPUS 4 + #define LEON3_UART_OFFSET (0x80000100) #define LEON3_UART_IRQ (3) @@ -67,8 +69,11 @@ #define LEON3_AHB_PNP_OFFSET (0xFFFFF000) typedef struct ResetData { - SPARCCPU *cpu; - uint32_t entry; /* save kernel entry in case of reset */ + struct CPUResetData { + int id; + SPARCCPU *cpu; + } info[MAX_CPUS]; + uint32_t entry; /* save kernel entry in case of reset */ } ResetData; static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) @@ -123,17 +128,19 @@ static void write_bootloader(void *ptr, hwaddr kernel_addr) stl_p(p++, 0x01000000); /* nop */ } -static void main_cpu_reset(void *opaque) +static void leon3_cpu_reset(void *opaque) { - ResetData *s = (ResetData *)opaque; - CPUState *cpu = CPU(s->cpu); - CPUSPARCState *env = &s->cpu->env; + struct CPUResetData *info = (struct CPUResetData *) opaque; + int id = info->id; + ResetData *s = (ResetData *)DO_UPCAST(ResetData, info[id], info); + CPUState *cpu = CPU(s->info[id].cpu); + CPUSPARCState *env = cpu_env(cpu); cpu_reset(cpu); - cpu->halted = 0; - env->pc = s->entry; - env->npc = s->entry + 4; + cpu->halted = cpu->cpu_index != 0; + env->pc = s->entry; + env->npc = s->entry + 4; } static void leon3_cache_control_int(CPUSPARCState *env) @@ -167,8 +174,8 @@ static void leon3_cache_control_int(CPUSPARCState *env) static void leon3_irq_ack(CPUSPARCState *env, int intno) { - /* No SMP support yet, only CPU #0 available so far. */ - grlib_irqmp_ack(env->irq_manager, 0, intno); + CPUState *cpu = CPU(env_cpu(env)); + grlib_irqmp_ack(env->irq_manager, cpu->cpu_index, intno); } /* @@ -210,6 +217,19 @@ static void leon3_set_pil_in(void *opaque, int n, int level) } } +static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data) +{ + cpu->halted = 0; +} + +static void leon3_start_cpu(void *opaque, int n, int level) +{ + CPUState *cs = CPU(opaque); + + assert(level == 1); + async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL); +} + static void leon3_irq_manager(CPUSPARCState *env, int intno) { leon3_irq_ack(env, intno); @@ -235,16 +255,20 @@ static void leon3_generic_hw_init(MachineState *machine) AHBPnp *ahb_pnp; APBPnp *apb_pnp; - /* Init CPU */ - cpu = SPARC_CPU(cpu_create(machine->cpu_type)); - env = &cpu->env; + reset_info = g_malloc0(sizeof(ResetData)); - cpu_sparc_set_id(env, 0); + for (i = 0; i < machine->smp.cpus; i++) { + /* Init CPU */ + cpu = SPARC_CPU(cpu_create(machine->cpu_type)); + env = &cpu->env; - /* Reset data */ - reset_info = g_new0(ResetData, 1); - reset_info->cpu = cpu; - qemu_register_reset(main_cpu_reset, reset_info); + cpu_sparc_set_id(env, i); + + /* Reset data */ + reset_info->info[i].id = i; + reset_info->info[i].cpu = cpu; + qemu_register_reset(leon3_cpu_reset, &reset_info->info[i]); + } ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP)); sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal); @@ -262,14 +286,28 @@ static void leon3_generic_hw_init(MachineState *machine) /* Allocate IRQ manager */ irqmpdev = qdev_new(TYPE_GRLIB_IRQMP); + object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus, + &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal); - qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in, - env, "pil", 1); - qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0, - qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0)); + + for (i = 0; i < machine->smp.cpus; i++) { + cpu = reset_info->info[i].cpu; + env = &cpu->env; + qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_start_cpu, + cpu, "start_cpu", 1); + qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i, + qdev_get_gpio_in_named(DEVICE(cpu), + "start_cpu", 0)); + qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in, + env, "pil", 1); + qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i, + qdev_get_gpio_in_named(DEVICE(cpu), + "pil", 0)); + env->irq_manager = irqmpdev; + env->qemu_irq_ack = leon3_irq_manager; + } + sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET); - env->irq_manager = irqmpdev; - env->qemu_irq_ack = leon3_irq_manager; grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF, GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV, 2, 0, GRLIB_APBIO_AREA); @@ -342,6 +380,10 @@ static void leon3_generic_hw_init(MachineState *machine) */ write_bootloader(memory_region_get_ram_ptr(prom), entry); reset_info->entry = LEON3_PROM_OFFSET; + for (i = 0; i < machine->smp.cpus; i++) { + reset_info->info[i].cpu->env.pc = LEON3_PROM_OFFSET; + reset_info->info[i].cpu->env.npc = LEON3_PROM_OFFSET + 4; + } } } @@ -380,6 +422,7 @@ static void leon3_generic_machine_init(MachineClass *mc) mc->init = leon3_generic_hw_init; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3"); mc->default_ram_id = "leon3.ram"; + mc->max_cpus = MAX_CPUS; } DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init) From patchwork Thu Feb 15 17:57:34 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 10:02:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Cl=C3=A9ment_Chigot?= , Frederic Konrad , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PULL 40/56] hw/sparc/leon3: check cpu_id in the tiny bootloader Date: Thu, 15 Feb 2024 18:57:34 +0100 Message-ID: <20240215175752.82828-41-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot Now that SMP is possible, the asr17 must be checked in the little boot code or the secondary CPU will reinitialize the Timer and the Uart. Co-developed-by: Frederic Konrad Signed-off-by: Clément Chigot Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240131085047.18458-9-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/sparc/leon3.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 1637900162..bea84f3ad6 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -99,12 +99,26 @@ static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) /* * When loading a kernel in RAM the machine is expected to be in a different - * state (eg: initialized by the bootloader). This little code reproduces - * this behavior. + * state (eg: initialized by the bootloader). This little code reproduces + * this behavior. Also this code can be executed by the secondary cpus as + * well since it looks at the %asr17 register before doing any + * initialization, it allows to use the same reset address for all the + * cpus. */ static void write_bootloader(void *ptr, hwaddr kernel_addr) { uint32_t *p = ptr; + uint32_t *sec_cpu_branch_p = NULL; + + /* If we are running on a secondary CPU, jump directly to the kernel. */ + + stl_p(p++, 0x85444000); /* rd %asr17, %g2 */ + stl_p(p++, 0x8530a01c); /* srl %g2, 0x1c, %g2 */ + stl_p(p++, 0x80908000); /* tst %g2 */ + /* Filled below. */ + sec_cpu_branch_p = p; + stl_p(p++, 0x0BADC0DE); /* bne xxx */ + stl_p(p++, 0x01000000); /* nop */ /* Initialize the UARTs */ /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */ @@ -118,6 +132,10 @@ static void write_bootloader(void *ptr, hwaddr kernel_addr) /* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART; */ p = gen_store_u32(p, 0x80000318, 3); + /* Now, the relative branch above can be computed. */ + stl_p(sec_cpu_branch_p, 0x12800000 + + (p - sec_cpu_branch_p)); + /* JUMP to the entry point */ stl_p(p++, 0x82100000); /* mov %g0, %g1 */ stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22)); From patchwork Thu Feb 15 17:57:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20DD1C4829E for ; Thu, 15 Feb 2024 18:06:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag4G-0006OL-U3; Thu, 15 Feb 2024 13:02:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag4E-00064L-Bv for qemu-devel@nongnu.org; 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Thu, 15 Feb 2024 10:02:31 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id n5-20020adffe05000000b0033b47ee01f1sm2432289wrr.49.2024.02.15.10.02.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:02:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , =?utf-8?q?Cl=C3=A9ment_Ch?= =?utf-8?q?igot?= , Frederic Konrad , Artyom Tarasenko Subject: [PULL 41/56] hw/sparc/leon3: Pass DeviceState opaque argument to leon3_set_pil_in() Date: Thu, 15 Feb 2024 18:57:35 +0100 Message-ID: <20240215175752.82828-42-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org By passing a DeviceState context to a QDev IRQ handler, we can simplify and use qdev_init_gpio_in_named() instead of qdev_init_gpio_in_named_with_opaque(). Suggested-by: Mark Cave-Ayland Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20240215144623.76233-2-philmd@linaro.org> --- hw/sparc/leon3.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index bea84f3ad6..a15f90e142 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -202,9 +202,10 @@ static void leon3_irq_ack(CPUSPARCState *env, int intno) */ static void leon3_set_pil_in(void *opaque, int n, int level) { - CPUSPARCState *env = opaque; + DeviceState *cpu = opaque; + CPUState *cs = CPU(cpu); + CPUSPARCState *env = cpu_env(cs); uint32_t pil_in = level; - CPUState *cs; assert(env != NULL); @@ -220,7 +221,6 @@ static void leon3_set_pil_in(void *opaque, int n, int level) env->interrupt_index = TT_EXTINT | i; if (old_interrupt != env->interrupt_index) { - cs = env_cpu(env); trace_leon3_set_irq(i); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -228,7 +228,6 @@ static void leon3_set_pil_in(void *opaque, int n, int level) } } } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { - cs = env_cpu(env); trace_leon3_reset_irq(env->interrupt_index & 15); env->interrupt_index = 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -316,8 +315,7 @@ static void leon3_generic_hw_init(MachineState *machine) qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i, qdev_get_gpio_in_named(DEVICE(cpu), "start_cpu", 0)); - qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in, - env, "pil", 1); + qdev_init_gpio_in_named(DEVICE(cpu), leon3_set_pil_in, "pil", 1); qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i, qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0)); From patchwork Thu Feb 15 17:57:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CEB4C48BC4 for ; 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Thu, 15 Feb 2024 10:02:39 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id bi20-20020a05600c3d9400b004103e15441dsm2693413wmb.6.2024.02.15.10.02.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:02:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , =?utf-8?q?Cl=C3=A9ment_Ch?= =?utf-8?q?igot?= , Frederic Konrad , Artyom Tarasenko Subject: [PULL 42/56] hw/sparc/leon3: Pass DeviceState opaque argument to leon3_start_cpu() Date: Thu, 15 Feb 2024 18:57:36 +0100 Message-ID: <20240215175752.82828-43-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philmd@linaro.org; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org By passing a DeviceState context to a QDev IRQ handler, we can simplify and use qdev_init_gpio_in_named() instead of qdev_init_gpio_in_named_with_opaque(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-Id: <20240215144623.76233-3-philmd@linaro.org> --- hw/sparc/leon3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index a15f90e142..44fca1487d 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -241,7 +241,8 @@ static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data) static void leon3_start_cpu(void *opaque, int n, int level) { - CPUState *cs = CPU(opaque); + DeviceState *cpu = opaque; + CPUState *cs = CPU(cpu); assert(level == 1); async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL); @@ -310,8 +311,7 @@ static void leon3_generic_hw_init(MachineState *machine) for (i = 0; i < machine->smp.cpus; i++) { cpu = reset_info->info[i].cpu; env = &cpu->env; - qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_start_cpu, - cpu, "start_cpu", 1); + qdev_init_gpio_in_named(DEVICE(cpu), leon3_start_cpu, "start_cpu", 1); qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i, qdev_get_gpio_in_named(DEVICE(cpu), "start_cpu", 0)); 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Thu, 15 Feb 2024 10:02:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Mark Cave-Ayland , =?utf-8?q?Cl=C3=A9ment_Ch?= =?utf-8?q?igot?= , Frederic Konrad , Artyom Tarasenko Subject: [PULL 43/56] hw/sparc/leon3: Initialize GPIO before realizing CPU devices Date: Thu, 15 Feb 2024 18:57:37 +0100 Message-ID: <20240215175752.82828-44-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Inline cpu_create() in order to call qdev_init_gpio_in_named() before the CPU is realized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Mark Cave-Ayland Message-Id: <20240215144623.76233-4-philmd@linaro.org> --- hw/sparc/leon3.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 44fca1487d..4873b59b6c 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -277,7 +277,10 @@ static void leon3_generic_hw_init(MachineState *machine) for (i = 0; i < machine->smp.cpus; i++) { /* Init CPU */ - cpu = SPARC_CPU(cpu_create(machine->cpu_type)); + cpu = SPARC_CPU(object_new(machine->cpu_type)); + qdev_init_gpio_in_named(DEVICE(cpu), leon3_start_cpu, "start_cpu", 1); + qdev_init_gpio_in_named(DEVICE(cpu), leon3_set_pil_in, "pil", 1); + qdev_realize(DEVICE(cpu), NULL, &error_fatal); env = &cpu->env; cpu_sparc_set_id(env, i); @@ -311,11 +314,9 @@ static void leon3_generic_hw_init(MachineState *machine) for (i = 0; i < machine->smp.cpus; i++) { cpu = reset_info->info[i].cpu; env = &cpu->env; - qdev_init_gpio_in_named(DEVICE(cpu), leon3_start_cpu, "start_cpu", 1); qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i, qdev_get_gpio_in_named(DEVICE(cpu), "start_cpu", 0)); - qdev_init_gpio_in_named(DEVICE(cpu), leon3_set_pil_in, "pil", 1); qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i, qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0)); From patchwork Thu Feb 15 17:57:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D911C48BC4 for ; Thu, 15 Feb 2024 18:05:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag5S-0002Bb-8Q; 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Thu, 15 Feb 2024 10:02:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PULL 45/56] MAINTAINERS: Add myself as reviewer for TCG Plugins Date: Thu, 15 Feb 2024 18:57:39 +0100 Message-ID: <20240215175752.82828-46-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Pierrick Bouvier Message-ID: <20240118032400.3762658-14-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0ab73b265a..6c19ea41d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3706,6 +3706,7 @@ TCG Plugins M: Alex Bennée R: Alexandre Iooss R: Mahmoud Mandour +R: Pierrick Bouvier S: Maintained F: docs/devel/tcg-plugins.rst F: plugins/ From patchwork Thu Feb 15 17:57:40 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 10:03:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PULL 46/56] hw/i386/q35: Simplify pc_q35_init() since PCI is always enabled Date: Thu, 15 Feb 2024 18:57:40 +0100 Message-ID: <20240215175752.82828-47-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We can not create the Q35 machine without PCI, so simplify pc_q35_init() removing pointless checks. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240213041952.58840-1-philmd@linaro.org> --- hw/i386/pc_q35.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index b7c69d55d6..a785bf7366 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -130,8 +130,7 @@ static void pc_q35_init(MachineState *machine) ISADevice *rtc_state; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *system_io = get_system_io(); - MemoryRegion *pci_memory; - MemoryRegion *rom_memory; + MemoryRegion *pci_memory = g_new(MemoryRegion, 1); GSIState *gsi_state; ISABus *isa_bus; int i; @@ -143,6 +142,8 @@ static void pc_q35_init(MachineState *machine) bool keep_pci_slot_hpc; uint64_t pci_hole64_size = 0; + assert(pcmc->pci_enabled); + /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping * also known as MMCFG). @@ -189,16 +190,6 @@ static void pc_q35_init(MachineState *machine) kvmclock_create(pcmc->kvmclock_create_always); } - /* pci enabled */ - if (pcmc->pci_enabled) { - pci_memory = g_new(MemoryRegion, 1); - memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); - rom_memory = pci_memory; - } else { - pci_memory = NULL; - rom_memory = system_memory; - } - pc_guest_info_init(pcms); if (pcmc->smbios_defaults) { @@ -212,14 +203,13 @@ static void pc_q35_init(MachineState *machine) /* create pci host bus */ phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); - if (pcmc->pci_enabled) { - pci_hole64_size = object_property_get_uint(phb, - PCI_HOST_PROP_PCI_HOLE64_SIZE, - &error_abort); - } + pci_hole64_size = object_property_get_uint(phb, + PCI_HOST_PROP_PCI_HOLE64_SIZE, + &error_abort); /* allocate ram and load rom/bios */ - pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); + memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); + pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); object_property_add_child(OBJECT(machine), "q35", phb); object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, @@ -243,7 +233,7 @@ static void pc_q35_init(MachineState *machine) pcms->bus = host_bus; /* irq lines */ - gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); + gsi_state = pc_gsi_create(&x86ms->gsi, true); /* create ISA bus */ lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), @@ -286,9 +276,7 @@ static void pc_q35_init(MachineState *machine) pc_i8259_create(isa_bus, gsi_state->i8259_irq); } - if (pcmc->pci_enabled) { - ioapic_init_gsi(gsi_state, "q35"); - } + ioapic_init_gsi(gsi_state, "q35"); if (tcg_enabled()) { x86_register_ferr_irq(x86ms->gsi[13]); From patchwork Thu Feb 15 17:57:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00478C48BC4 for ; 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Tsirkin" , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL 47/56] hw/i386/q35: Use DEVICE() cast macro with PCIDevice object Date: Thu, 15 Feb 2024 18:57:41 +0100 Message-ID: <20240215175752.82828-48-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org QDev API provides the DEVICE() macro to access the 'qdev' parent field of the PCIDevice structure. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-2-philmd@linaro.org> --- hw/i386/pc_q35.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a785bf7366..a81c86b255 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -297,8 +297,8 @@ static void pc_q35_init(MachineState *machine) PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); - idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); - idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); + idebus[0] = qdev_get_child_bus(DEVICE(ahci), "ide.0"); + idebus[1] = qdev_get_child_bus(DEVICE(ahci), "ide.1"); g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); ide_drive_get(hd, ahci_get_num_ports(ahci)); ahci_ide_create_devs(ahci, hd); From patchwork Thu Feb 15 17:57:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B69CC48BC4 for ; Thu, 15 Feb 2024 18:08:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag5m-0003Zn-Mo; Thu, 15 Feb 2024 13:04:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag50-0000bY-19 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:03:26 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rag4v-00036Y-GI for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:03:24 -0500 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-a34c5ca2537so143203766b.0 for ; Thu, 15 Feb 2024 10:03:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708020198; x=1708624998; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zv0rwoijSdDo8xIDgkkDnlRfaEZ/bLwEpbnDkMeyuSU=; b=w5pvYt96CON05tBbhV+mBu1jCQVTvHsuLrNahQcc3PFchz+4XMbAnjFBnJby2xJj/I pcM6/99+Gpdtshho/EjJcHNnREIVh3Oc2cRpDUOXTXILOPZfblCSyaY1Y9RABXX6LbKL sepO7B1F38mAtCRl44qCo3uM3b/1i/OCjl33AnELcC0K3GQdV+fcskez90JjLNiWL3mB cfw6TexiP6kjCezpms0umHVv9s0nPN+zH9B2flxbA5gYXDkDtoVYezWLCFq/2QvS2Can 7sTcfA3HEe9+e8XuAQfWwR9jyo5C1aFi9qJfTHvUmd2aNbytwobGXKzyoNSm4OioNYKr 3uCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708020198; x=1708624998; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zv0rwoijSdDo8xIDgkkDnlRfaEZ/bLwEpbnDkMeyuSU=; b=lP7FAB8T0EX+BiKc7ARdti3MQL84KvdrqXsuA0RDzxpB8zO5zVaBme4A1dHrb//Dqg LMV8TsZnpaGGarh9CkwGmxB5qmAtZxXM1b8jyHpa+J1OKOG0kCxHBDM/TBDx+CjY/M5U 3/SlGMJ/r2IMpZyp+jxB/zuVd2DALe1ydXVaEgLTLm/4g2/AUpysFreDS92BcP8lqGsm QE/F/zz1upPrY7iYo6KEQ5lDR0w6xAAdxDGNOuXikgLp7eFhPrickATu5y8MuXXL63Vi 7A2anOoYult4B/xmGBTwTRtnkAjkUqt3nYBVu0Ojb0HIukF5+q1IE/p2qUmog0aES0Pf a/tg== X-Gm-Message-State: AOJu0YxNLv8VNnyv/VZFFXfu5gjskQhQ3r5EENFyvAs8ZiFe0doXpo2F ZdMoYhs0pNfTuhyhuhFXjiI5ptBHMnDwgTRB2PI7BFI8DAQ/KrLbVSYnYUgt4pOWya9fESNpQrQ F+WI= X-Google-Smtp-Source: AGHT+IEiI7lxr4JeVw2hsBMeVDu8TkR+CvLr/LWJj+beQC1JsUhXkkvmeHjcuqP7bK/nljgHOsdgPA== X-Received: by 2002:a17:906:ad5:b0:a3d:b3a7:b8ce with SMTP id z21-20020a1709060ad500b00a3db3a7b8cemr991576ejf.0.1708020198368; Thu, 15 Feb 2024 10:03:18 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id j7-20020a170906278700b00a3d76518122sm783781ejc.9.2024.02.15.10.03.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:03:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S . Tsirkin" , Richard Henderson , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , John Snow , Paul Burton , Aleksandar Rikalo Subject: [PULL 48/56] hw/ide/ahci: Expose AHCIPCIState structure Date: Thu, 15 Feb 2024 18:57:42 +0100 Message-ID: <20240215175752.82828-49-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In order to be able to QOM-embed a structure, we need its full definition. Move it from "ahci_internal.h" to the new "hw/ide/ahci-pci.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-3-philmd@linaro.org> --- hw/ide/ahci_internal.h | 8 -------- include/hw/ide/ahci-pci.h | 22 ++++++++++++++++++++++ include/hw/ide/ahci.h | 3 --- hw/i386/pc_q35.c | 2 +- hw/ide/ahci.c | 1 + hw/ide/ich.c | 1 + hw/mips/boston.c | 2 +- 7 files changed, 26 insertions(+), 13 deletions(-) create mode 100644 include/hw/ide/ahci-pci.h diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index c244bbd8be..4dc2805d21 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -324,14 +324,6 @@ struct AHCIDevice { MemReentrancyGuard mem_reentrancy_guard; }; -struct AHCIPCIState { - /*< private >*/ - PCIDevice parent_obj; - /*< public >*/ - - AHCIState ahci; -}; - extern const VMStateDescription vmstate_ahci; #define VMSTATE_AHCI(_field, _state) { \ diff --git a/include/hw/ide/ahci-pci.h b/include/hw/ide/ahci-pci.h new file mode 100644 index 0000000000..c2ee616962 --- /dev/null +++ b/include/hw/ide/ahci-pci.h @@ -0,0 +1,22 @@ +/* + * QEMU AHCI Emulation (PCI devices) + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_IDE_AHCI_PCI_H +#define HW_IDE_AHCI_PCI_H + +#include "qom/object.h" +#include "hw/ide/ahci.h" +#include "hw/pci/pci_device.h" + +#define TYPE_ICH9_AHCI "ich9-ahci" +OBJECT_DECLARE_SIMPLE_TYPE(AHCIPCIState, ICH9_AHCI) + +struct AHCIPCIState { + PCIDevice parent_obj; + + AHCIState ahci; +}; + +#endif diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index 210e5e734c..6818d02063 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -52,9 +52,6 @@ typedef struct AHCIState { } AHCIState; -#define TYPE_ICH9_AHCI "ich9-ahci" -OBJECT_DECLARE_SIMPLE_TYPE(AHCIPCIState, ICH9_AHCI) - int32_t ahci_get_num_ports(PCIDevice *dev); void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a81c86b255..76b3b6032b 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -47,7 +47,7 @@ #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" #include "hw/ide/pci.h" -#include "hw/ide/ahci.h" +#include "hw/ide/ahci-pci.h" #include "hw/intc/ioapic.h" #include "hw/southbridge/ich9.h" #include "hw/usb.h" diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 0eb83a6d46..aa9381a7b2 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -36,6 +36,7 @@ #include "sysemu/dma.h" #include "hw/ide/internal.h" #include "hw/ide/pci.h" +#include "hw/ide/ahci-pci.h" #include "ahci_internal.h" #include "trace.h" diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 49f8eb8a7d..d190012a95 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -69,6 +69,7 @@ #include "hw/isa/isa.h" #include "sysemu/dma.h" #include "hw/ide/pci.h" +#include "hw/ide/ahci-pci.h" #include "ahci_internal.h" #define ICH9_MSI_CAP_OFFSET 0x80 diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 4e11ff6cd6..cbcefdd693 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -24,7 +24,7 @@ #include "hw/boards.h" #include "hw/char/serial.h" #include "hw/ide/pci.h" -#include "hw/ide/ahci.h" +#include "hw/ide/ahci-pci.h" #include "hw/loader.h" #include "hw/loader-fit.h" #include "hw/mips/bootloader.h" From patchwork Thu Feb 15 17:57:43 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 10:03:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Paul Burton , Aleksandar Rikalo Subject: [PULL 49/56] hw/ide/ahci: Rename AHCI PCI function as 'pdev' Date: Thu, 15 Feb 2024 18:57:43 +0100 Message-ID: <20240215175752.82828-50-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We want to access AHCIPCIState::ahci field. In order to keep the code simple (avoiding &ahci->ahci), rename the current 'ahci' variable as 'pdev' Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-4-philmd@linaro.org> --- hw/i386/pc_q35.c | 15 ++++++++------- hw/mips/boston.c | 10 +++++----- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 76b3b6032b..a89f900c4c 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -134,7 +134,6 @@ static void pc_q35_init(MachineState *machine) GSIState *gsi_state; ISABus *isa_bus; int i; - PCIDevice *ahci; ram_addr_t lowmem; DriveInfo *hd[MAX_SATA_PORTS]; MachineClass *mc = MACHINE_GET_CLASS(machine); @@ -292,16 +291,18 @@ static void pc_q35_init(MachineState *machine) 0xff0104); if (pcms->sata_enabled) { + PCIDevice *pdev; + /* ahci and SATA device, for q35 1 ahci controller is built-in */ - ahci = pci_create_simple_multifunction(host_bus, + pdev = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); - idebus[0] = qdev_get_child_bus(DEVICE(ahci), "ide.0"); - idebus[1] = qdev_get_child_bus(DEVICE(ahci), "ide.1"); - g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); - ide_drive_get(hd, ahci_get_num_ports(ahci)); - ahci_ide_create_devs(ahci, hd); + idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); + idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); + g_assert(MAX_SATA_PORTS == ahci_get_num_ports(pdev)); + ide_drive_get(hd, ahci_get_num_ports(pdev)); + ahci_ide_create_devs(pdev, hd); } else { idebus[0] = idebus[1] = NULL; } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index cbcefdd693..0ec0b98066 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -677,7 +677,7 @@ static void boston_mach_init(MachineState *machine) MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; MemoryRegion *sys_mem = get_system_memory(); XilinxPCIEHost *pcie2; - PCIDevice *ahci; + PCIDevice *pdev; DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; @@ -769,11 +769,11 @@ static void boston_mach_init(MachineState *machine) qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, boston_lcd_event, NULL, s, NULL, true); - ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, + pdev = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, PCI_DEVFN(0, 0), TYPE_ICH9_AHCI); - g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci)); - ide_drive_get(hd, ahci_get_num_ports(ahci)); - ahci_ide_create_devs(ahci, hd); + g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(pdev)); + ide_drive_get(hd, ahci_get_num_ports(pdev)); + ahci_ide_create_devs(pdev, hd); if (machine->firmware) { fw_size = load_image_targphys(machine->firmware, From patchwork Thu Feb 15 17:57:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99559C48BC4 for ; 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Tsirkin" , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , John Snow , Paul Burton , Aleksandar Rikalo Subject: [PULL 50/56] hw/ide/ahci: Inline ahci_get_num_ports() Date: Thu, 15 Feb 2024 18:57:44 +0100 Message-ID: <20240215175752.82828-51-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=philmd@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce the 'ich9' variable and inline ahci_get_num_ports(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-5-philmd@linaro.org> --- include/hw/ide/ahci.h | 1 - hw/i386/pc_q35.c | 6 ++++-- hw/ide/ahci.c | 8 -------- hw/mips/boston.c | 6 ++++-- 4 files changed, 8 insertions(+), 13 deletions(-) diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index 6818d02063..dbef377f3d 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -52,7 +52,6 @@ typedef struct AHCIState { } AHCIState; -int32_t ahci_get_num_ports(PCIDevice *dev); void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd); #define TYPE_SYSBUS_AHCI "sysbus-ahci" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a89f900c4c..09e12418f9 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -292,16 +292,18 @@ static void pc_q35_init(MachineState *machine) if (pcms->sata_enabled) { PCIDevice *pdev; + AHCIPCIState *ich9; /* ahci and SATA device, for q35 1 ahci controller is built-in */ pdev = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), "ich9-ahci"); + ich9 = ICH9_AHCI(pdev); idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); - g_assert(MAX_SATA_PORTS == ahci_get_num_ports(pdev)); - ide_drive_get(hd, ahci_get_num_ports(pdev)); + g_assert(MAX_SATA_PORTS == ich9->ahci.ports); + ide_drive_get(hd, ich9->ahci.ports); ahci_ide_create_devs(pdev, hd); } else { idebus[0] = idebus[1] = NULL; diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index aa9381a7b2..8b97c6b0e7 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1896,14 +1896,6 @@ static void sysbus_ahci_register_types(void) type_init(sysbus_ahci_register_types) -int32_t ahci_get_num_ports(PCIDevice *dev) -{ - AHCIPCIState *d = ICH9_AHCI(dev); - AHCIState *ahci = &d->ahci; - - return ahci->ports; -} - void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) { AHCIPCIState *d = ICH9_AHCI(dev); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 0ec0b98066..a6c7bc18ff 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -678,6 +678,7 @@ static void boston_mach_init(MachineState *machine) MemoryRegion *sys_mem = get_system_memory(); XilinxPCIEHost *pcie2; PCIDevice *pdev; + AHCIPCIState *ich9; DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; @@ -771,8 +772,9 @@ static void boston_mach_init(MachineState *machine) pdev = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, PCI_DEVFN(0, 0), TYPE_ICH9_AHCI); - g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(pdev)); - ide_drive_get(hd, ahci_get_num_ports(pdev)); + ich9 = ICH9_AHCI(pdev); + g_assert(ARRAY_SIZE(hd) == ich9->ahci.ports); + ide_drive_get(hd, ich9->ahci.ports); ahci_ide_create_devs(pdev, hd); if (machine->firmware) { From patchwork Thu Feb 15 17:57:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD3A4C4829E for ; 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Thu, 15 Feb 2024 10:03:37 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id t22-20020a1709063e5600b00a3c091ead20sm784624eji.222.2024.02.15.10.03.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:03:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S . Tsirkin" , Richard Henderson , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , John Snow , Paul Burton , Aleksandar Rikalo Subject: [PULL 51/56] hw/ide/ahci: Pass AHCI context to ahci_ide_create_devs() Date: Thu, 15 Feb 2024 18:57:45 +0100 Message-ID: <20240215175752.82828-52-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since ahci_ide_create_devs() is not PCI specific, pass it an AHCIState argument instead of PCIDevice. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-6-philmd@linaro.org> --- include/hw/ide/ahci.h | 2 +- hw/i386/pc_q35.c | 2 +- hw/ide/ahci.c | 5 +---- hw/mips/boston.c | 2 +- 4 files changed, 4 insertions(+), 7 deletions(-) diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index dbef377f3d..8cd55b1333 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -52,7 +52,7 @@ typedef struct AHCIState { } AHCIState; -void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd); +void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd); #define TYPE_SYSBUS_AHCI "sysbus-ahci" OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 09e12418f9..d346fa3b1d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -304,7 +304,7 @@ static void pc_q35_init(MachineState *machine) idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); g_assert(MAX_SATA_PORTS == ich9->ahci.ports); ide_drive_get(hd, ich9->ahci.ports); - ahci_ide_create_devs(pdev, hd); + ahci_ide_create_devs(&ich9->ahci, hd); } else { idebus[0] = idebus[1] = NULL; } diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 8b97c6b0e7..bac1871a31 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1896,10 +1896,8 @@ static void sysbus_ahci_register_types(void) type_init(sysbus_ahci_register_types) -void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) +void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd) { - AHCIPCIState *d = ICH9_AHCI(dev); - AHCIState *ahci = &d->ahci; int i; for (i = 0; i < ahci->ports; i++) { @@ -1908,5 +1906,4 @@ void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) } ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); } - } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index a6c7bc18ff..1b44fb354c 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -775,7 +775,7 @@ static void boston_mach_init(MachineState *machine) ich9 = ICH9_AHCI(pdev); g_assert(ARRAY_SIZE(hd) == ich9->ahci.ports); ide_drive_get(hd, ich9->ahci.ports); - ahci_ide_create_devs(pdev, hd); + ahci_ide_create_devs(&ich9->ahci, hd); if (machine->firmware) { fw_size = load_image_targphys(machine->firmware, From patchwork Thu Feb 15 17:57:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69168C4829E for ; Thu, 15 Feb 2024 18:05:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag5U-0002O7-TA; Thu, 15 Feb 2024 13:03:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag5L-0001wn-Ho for qemu-devel@nongnu.org; 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Tsirkin" , Richard Henderson , John Snow Subject: [PULL 52/56] hw/ide/ahci: Convert AHCIState::ports to unsigned Date: Thu, 15 Feb 2024 18:57:46 +0100 Message-ID: <20240215175752.82828-53-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org AHCIState::ports should be unsigned. Besides, we never check it for negative value. It is unlikely it was ever used with more than INT32_MAX ports, so it is safe to convert it to unsigned. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-7-philmd@linaro.org> --- include/hw/ide/ahci.h | 2 +- hw/ide/ahci.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index 8cd55b1333..604d3a0994 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -46,7 +46,7 @@ typedef struct AHCIState { MemoryRegion idp; /* Index-Data Pair I/O port space */ unsigned idp_offset; /* Offset of index in I/O port space */ uint32_t idp_index; /* Current IDP index */ - int32_t ports; + uint32_t ports; qemu_irq irq; AddressSpace *as; } AHCIState; diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index bac1871a31..2c3306dae4 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1819,7 +1819,7 @@ const VMStateDescription vmstate_ahci = { .version_id = 1, .post_load = ahci_state_post_load, .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(dev, AHCIState, ports, vmstate_ahci_device, AHCIDevice), VMSTATE_UINT32(control_regs.cap, AHCIState), VMSTATE_UINT32(control_regs.ghc, AHCIState), @@ -1827,7 +1827,7 @@ const VMStateDescription vmstate_ahci = { VMSTATE_UINT32(control_regs.impl, AHCIState), VMSTATE_UINT32(control_regs.version, AHCIState), VMSTATE_UINT32(idp_index, AHCIState), - VMSTATE_INT32_EQUAL(ports, AHCIState, NULL), + VMSTATE_UINT32_EQUAL(ports, AHCIState, NULL), VMSTATE_END_OF_LIST() }, }; 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Thu, 15 Feb 2024 10:03:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S . Tsirkin" , Richard Henderson , John Snow Subject: [PULL 53/56] hw/ide/ahci: Do not pass 'ports' argument to ahci_realize() Date: Thu, 15 Feb 2024 18:57:47 +0100 Message-ID: <20240215175752.82828-54-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Explicitly set AHCIState::ports before calling ahci_realize(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-8-philmd@linaro.org> --- hw/ide/ahci_internal.h | 2 +- hw/ide/ahci.c | 9 +++++---- hw/ide/ich.c | 3 ++- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index 4dc2805d21..4e13329bb2 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -377,7 +377,7 @@ typedef struct SDBFIS { uint32_t payload; } QEMU_PACKED SDBFIS; -void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports); +void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as); void ahci_init(AHCIState *s, DeviceState *qdev); void ahci_uninit(AHCIState *s); diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 2c3306dae4..33f7e83687 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1614,14 +1614,14 @@ void ahci_init(AHCIState *s, DeviceState *qdev) "ahci-idp", 32); } -void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) +void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as) { qemu_irq *irqs; int i; s->as = as; - s->ports = ports; - s->dev = g_new0(AHCIDevice, ports); + assert(s->ports > 0); + s->dev = g_new0(AHCIDevice, s->ports); ahci_reg_init(s); irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); for (i = 0; i < s->ports; i++) { @@ -1862,7 +1862,8 @@ static void sysbus_ahci_realize(DeviceState *dev, Error **errp) { SysbusAHCIState *s = SYSBUS_AHCI(dev); - ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports); + s->ahci.ports = s->num_ports; + ahci_realize(&s->ahci, dev, &address_space_memory); } static Property sysbus_ahci_properties[] = { diff --git a/hw/ide/ich.c b/hw/ide/ich.c index d190012a95..122fc7e0ab 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -113,7 +113,8 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) d = ICH9_AHCI(dev); int ret; - ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6); + d->ahci.ports = 6; + ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev)); pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1); 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Thu, 15 Feb 2024 10:03:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S . Tsirkin" , Richard Henderson , John Snow Subject: [PULL 54/56] hw/ide/ahci: Remove SysbusAHCIState::num_ports field Date: Thu, 15 Feb 2024 18:57:48 +0100 Message-ID: <20240215175752.82828-55-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org No need to duplicate AHCIState::ports, directly access it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Message-Id: <20240213081201.78951-9-philmd@linaro.org> --- include/hw/ide/ahci.h | 1 - hw/ide/ahci.c | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index 604d3a0994..c0b10c2bb4 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -63,7 +63,6 @@ struct SysbusAHCIState { /*< public >*/ AHCIState ahci; - uint32_t num_ports; }; #define TYPE_ALLWINNER_AHCI "allwinner-ahci" diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 33f7e83687..041cc87c11 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1862,12 +1862,11 @@ static void sysbus_ahci_realize(DeviceState *dev, Error **errp) { SysbusAHCIState *s = SYSBUS_AHCI(dev); - s->ahci.ports = s->num_ports; ahci_realize(&s->ahci, dev, &address_space_memory); } static Property sysbus_ahci_properties[] = { - DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), + DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, ahci.ports, 1), DEFINE_PROP_END_OF_LIST(), }; From patchwork Thu Feb 15 17:57:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13558987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D8CFC4829E for ; Thu, 15 Feb 2024 18:07:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rag6D-0004pL-OT; Thu, 15 Feb 2024 13:04:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rag5s-0003k5-Sk for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:04:21 -0500 Received: from mail-lf1-x132.google.com ([2a00:1450:4864:20::132]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rag5c-0003Gj-75 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 13:04:20 -0500 Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-511898b6c9eso1445331e87.3 for ; Thu, 15 Feb 2024 10:04:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708020242; x=1708625042; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pbWJfttw2i/6nkY9oTBvXTNqjF14WXnlPS1ndEBwSeA=; b=EO4AJs4JF5F4yqS/JhrgfEDmec71NJscSPIKghS9QnP6mQVHM8WtCHr47JqhexT7Kg 88qs9tBwmC3B7KijzRmhVct4LlCm3HmqZ9H/05QXM2QEC1x5CHCcVJw1zfMG4NKPo6Q6 7XmWLleScphA5EHN81ctwB6TXAsAS0XqJvAYnuREyC7ypPNiPzjMhErGzSu9mogarwxi qPB1kkE++MyAyTYx+H69FIy7T9VuYfdGK3aNA1cGoPtbhsi6pzrR82k5nXiOyp3YGXWb CmRN+a8LFrxBVL4+ITf5Gbsec+2dXyAIHQreEzDMMk8lJvQzVMJ+6U1XdhDxs1OgpAUA wivQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708020242; x=1708625042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pbWJfttw2i/6nkY9oTBvXTNqjF14WXnlPS1ndEBwSeA=; b=JL8WofBkTIDsStWWfCkaVchDZqMXivHUfxe2Oz84u6KgHBk4z1PMMHFdLfNNrCAs2A G/1VKSinZ7DmxSAM896AVS1o7qbL3pk1fkqiexmzKCizUo+4nrVhCTFvJesDtbtAvacs N4k+RRZ8udpj/hHyWnuaTZVcjgLQDJHCxoDbSMdtq+eF2r62L2gTLE4VSK/W5aqzEHf9 oE4yLgn9I1FjWk8qX2TKiH+kRkHmrvmG3AmdhSlEB76eb6qI93tLWeSGJLT1BAIsZ8VJ nFcbOSgyQbzqM2+YqOKRMvKKawBqx3RMTniP3bsKbWDkY6QdPZMBxkEArPImHjZHgCPa Pwcg== X-Gm-Message-State: AOJu0Ywxp0UKtB7+PQKnXRiP/KYsLrmg6lvKCZ2HdCgXVqUZpR8xAaZf 0V+NV7IloIYRW4AgZJCn1wMe+1lQh32b3hsblLAXOIkyIPLoLDuSdtbyRyJzvu9ODJ4ZcU3BHci Dv1Y= X-Google-Smtp-Source: AGHT+IFP/WpfmQBEAHodl2/Mt7aZKbTQSePuDkjkTMlGUROPE0ikmToK+R1Q3lZRs/SqE73LaDRkWg== X-Received: by 2002:a19:3849:0:b0:511:7a31:d66d with SMTP id d9-20020a193849000000b005117a31d66dmr1604680lfj.57.1708020242033; Thu, 15 Feb 2024 10:04:02 -0800 (PST) Received: from m1x-phil.lan ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id s15-20020a17090699cf00b00a3bd8a34b1bsm793336ejn.164.2024.02.15.10.03.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 15 Feb 2024 10:04:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Leif Lindholm , "Michael S . Tsirkin" , Rob Herring , Peter Maydell , Radoslaw Biernacki , Marcin Juszkiewicz , John Snow , Beniamino Galvani , Strahinja Jankovic , Alistair Francis , "Edgar E. Iglesias" Subject: [PULL 55/56] hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h' Date: Thu, 15 Feb 2024 18:57:49 +0100 Message-ID: <20240215175752.82828-56-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philmd@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Keep "hw/ide/ahci.h" AHCI-generic. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Leif Lindholm Reviewed-by: Michael S. Tsirkin Message-Id: <20240213081201.78951-10-philmd@linaro.org> --- include/hw/arm/allwinner-a10.h | 2 +- include/hw/arm/allwinner-r40.h | 2 +- include/hw/arm/xlnx-zynqmp.h | 2 +- include/hw/ide/ahci-sysbus.h | 35 ++++++++++++++++++++++++++++++++++ include/hw/ide/ahci.h | 29 +--------------------------- hw/arm/highbank.c | 2 +- hw/arm/sbsa-ref.c | 1 + hw/ide/ahci-allwinner.c | 3 +-- hw/ide/ahci.c | 1 + 9 files changed, 43 insertions(+), 34 deletions(-) create mode 100644 include/hw/ide/ahci-sysbus.h diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 2eb83a17ea..67a9a17b86 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -5,7 +5,7 @@ #include "hw/intc/allwinner-a10-pic.h" #include "hw/net/allwinner_emac.h" #include "hw/sd/allwinner-sdhost.h" -#include "hw/ide/ahci.h" +#include "hw/ide/ahci-sysbus.h" #include "hw/usb/hcd-ohci.h" #include "hw/usb/hcd-ehci.h" #include "hw/rtc/allwinner-rtc.h" diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index 66c38e7d90..614e74b7ed 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -22,7 +22,7 @@ #include "qom/object.h" #include "hw/timer/allwinner-a10-pit.h" -#include "hw/ide/ahci.h" +#include "hw/ide/ahci-sysbus.h" #include "hw/intc/arm_gic.h" #include "hw/sd/allwinner-sdhost.h" #include "hw/misc/allwinner-r40-ccu.h" diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 96358d51eb..48f7948092 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -22,7 +22,7 @@ #include "hw/net/cadence_gem.h" #include "hw/char/cadence_uart.h" #include "hw/net/xlnx-zynqmp-can.h" -#include "hw/ide/ahci.h" +#include "hw/ide/ahci-sysbus.h" #include "hw/sd/sdhci.h" #include "hw/ssi/xilinx_spips.h" #include "hw/dma/xlnx_dpdma.h" diff --git a/include/hw/ide/ahci-sysbus.h b/include/hw/ide/ahci-sysbus.h new file mode 100644 index 0000000000..06eaac8cb6 --- /dev/null +++ b/include/hw/ide/ahci-sysbus.h @@ -0,0 +1,35 @@ +/* + * QEMU AHCI Emulation (MMIO-mapped devices) + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_IDE_AHCI_SYSBUS_H +#define HW_IDE_AHCI_SYSBUS_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/ide/ahci.h" + +#define TYPE_SYSBUS_AHCI "sysbus-ahci" +OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI) + +struct SysbusAHCIState { + SysBusDevice parent_obj; + + AHCIState ahci; +}; + +#define TYPE_ALLWINNER_AHCI "allwinner-ahci" +OBJECT_DECLARE_SIMPLE_TYPE(AllwinnerAHCIState, ALLWINNER_AHCI) + +#define ALLWINNER_AHCI_MMIO_OFF 0x80 +#define ALLWINNER_AHCI_MMIO_SIZE 0x80 + +struct AllwinnerAHCIState { + SysbusAHCIState parent_obj; + + MemoryRegion mmio; + uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE / 4]; +}; + +#endif diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index c0b10c2bb4..ba31e75ff9 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -24,8 +24,7 @@ #ifndef HW_IDE_AHCI_H #define HW_IDE_AHCI_H -#include "hw/sysbus.h" -#include "qom/object.h" +#include "exec/memory.h" typedef struct AHCIDevice AHCIDevice; @@ -54,30 +53,4 @@ typedef struct AHCIState { void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd); -#define TYPE_SYSBUS_AHCI "sysbus-ahci" -OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI) - -struct SysbusAHCIState { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - AHCIState ahci; -}; - -#define TYPE_ALLWINNER_AHCI "allwinner-ahci" -OBJECT_DECLARE_SIMPLE_TYPE(AllwinnerAHCIState, ALLWINNER_AHCI) - -#define ALLWINNER_AHCI_MMIO_OFF 0x80 -#define ALLWINNER_AHCI_MMIO_SIZE 0x80 - -struct AllwinnerAHCIState { - /*< private >*/ - SysbusAHCIState parent_obj; - /*< public >*/ - - MemoryRegion mmio; - uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4]; -}; - #endif /* HW_IDE_AHCI_H */ diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 9fdac1cc81..c71b1a8db3 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -30,7 +30,7 @@ #include "hw/boards.h" #include "qemu/error-report.h" #include "hw/char/pl011.h" -#include "hw/ide/ahci.h" +#include "hw/ide/ahci-sysbus.h" #include "hw/cpu/a9mpcore.h" #include "hw/cpu/a15mpcore.h" #include "qemu/log.h" diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index f2adf30337..5d3a574664 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -38,6 +38,7 @@ #include "hw/boards.h" #include "hw/ide/internal.h" #include "hw/ide/ahci_internal.h" +#include "hw/ide/ahci-sysbus.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" #include "hw/loader.h" diff --git a/hw/ide/ahci-allwinner.c b/hw/ide/ahci-allwinner.c index b173121006..9620de8ce8 100644 --- a/hw/ide/ahci-allwinner.c +++ b/hw/ide/ahci-allwinner.c @@ -19,9 +19,8 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "sysemu/dma.h" -#include "hw/ide/internal.h" #include "migration/vmstate.h" -#include "ahci_internal.h" +#include "hw/ide/ahci-sysbus.h" #include "trace.h" diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 041cc87c11..54c9685495 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -37,6 +37,7 @@ #include "hw/ide/internal.h" #include "hw/ide/pci.h" #include "hw/ide/ahci-pci.h" +#include "hw/ide/ahci-sysbus.h" #include "ahci_internal.h" #include "trace.h" From patchwork Thu Feb 15 17:57:50 2024 Content-Type: text/plain; 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Thu, 15 Feb 2024 10:04:07 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Richard Henderson , John Snow Subject: [PULL 56/56] hw/ide/ich9: Use AHCIPCIState typedef Date: Thu, 15 Feb 2024 18:57:50 +0100 Message-ID: <20240215175752.82828-57-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240215175752.82828-1-philmd@linaro.org> References: <20240215175752.82828-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=philmd@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org QEMU coding style recommend using structure typedefs: https://www.qemu.org/docs/master/devel/style.html#typedefs Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20240208181245.96617-2-philmd@linaro.org> --- hw/ide/ich.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 122fc7e0ab..3ea793d790 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -100,14 +100,14 @@ static void pci_ich9_reset(DeviceState *dev) static void pci_ich9_ahci_init(Object *obj) { - struct AHCIPCIState *d = ICH9_AHCI(obj); + AHCIPCIState *d = ICH9_AHCI(obj); ahci_init(&d->ahci, DEVICE(obj)); } static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) { - struct AHCIPCIState *d; + AHCIPCIState *d; int sata_cap_offset; uint8_t *sata_cap; d = ICH9_AHCI(dev); @@ -156,7 +156,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) static void pci_ich9_uninit(PCIDevice *dev) { - struct AHCIPCIState *d; + AHCIPCIState *d; d = ICH9_AHCI(dev); msi_uninit(dev);