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Signed-off-by: Ben Cheatham --- drivers/cxl/core/regs.c | 7 +++++++ drivers/cxl/cxl.h | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 372786f80955..fe0c19826a6a 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -92,6 +92,12 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, length = CXL_RAS_CAPABILITY_LENGTH; rmap = &map->ras; break; + case CXL_CM_CAP_CAP_ID_TIMEOUT: + dev_dbg(dev, "found Isolation & Timeout capability (0x%x)\n", + offset); + length = CXL_TIMEOUT_CAPABILITY_LENGTH; + rmap = &map->timeout; + break; default: dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id, offset); @@ -211,6 +217,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map, } mapinfo[] = { { &map->component_map.hdm_decoder, ®s->hdm_decoder }, { &map->component_map.ras, ®s->ras }, + { &map->component_map.timeout, ®s->timeout }, }; int i; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index b6017c0c57b4..87f3178d6642 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -36,6 +36,7 @@ #define CXL_CM_CAP_CAP_ID_RAS 0x2 #define CXL_CM_CAP_CAP_ID_HDM 0x5 +#define CXL_CM_CAP_CAP_ID_TIMEOUT 0x9 #define CXL_CM_CAP_CAP_HDM_VERSION 1 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ @@ -126,6 +127,9 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) return 0; } +/* CXL 3.0 8.2.4.23 CXL Timeout and Isolation Capability Structure */ +#define CXL_TIMEOUT_CAPABILITY_OFFSET 0x0 +#define CXL_TIMEOUT_CAPABILITY_LENGTH 0x10 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) @@ -208,6 +212,7 @@ struct cxl_regs { struct_group_tagged(cxl_component_regs, component, void __iomem *hdm_decoder; void __iomem *ras; + void __iomem *timeout; ); /* * Common set of CXL Device register block base pointers @@ -242,6 +247,7 @@ struct cxl_reg_map { struct cxl_component_reg_map { struct cxl_reg_map hdm_decoder; struct cxl_reg_map ras; + struct cxl_reg_map timeout; }; struct cxl_device_reg_map { From patchwork Thu Feb 15 19:40:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 13559104 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2064.outbound.protection.outlook.com [40.107.223.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDB504369A; 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Thu, 15 Feb 2024 13:41:24 -0600 From: Ben Cheatham To: , CC: , , , , , , , , Subject: [RFC PATCH 2/6] pcie/cxl_timeout: Add CXL Timeout & Isolation service driver Date: Thu, 15 Feb 2024 13:40:44 -0600 Message-ID: <20240215194048.141411-3-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> References: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004688:EE_|DS0PR12MB8199:EE_ X-MS-Office365-Filtering-Correlation-Id: a4a82a52-2887-4f6d-5244-08dc2e5e1983 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +7GNBHDyS+fjXqOEXeuUQuB5GcQXQlm5HLc58WaIAfwF/G1PILOHUNlI7TJxgF4qp0RHlDf3PAaTrGUnBFkEQyH6mxCRnpiotowx1J8h//ldrGsFWAy9hPNnW0NJHrCtgnWxc9UUbFTA6JkkcRveYk+LaG84RS7rP4mIGO6fIQMAmdXMTKAZ4qNVY5g0TP57Z3+AfyQcmhwL/3+8nKEMSC/EaR+VudMOoOjTqIJhthoiUuDMRaxwFrV+qDUzqXTVMEjJdong37J/ToL3qXJXeLHON0nQfnJtcRl5VD1oCipz87qtEtvALsVLXPT7kgdkh3Bqef/WHQWz7kmUvfFUYiyHifuE27uu2luhAd/2+O5BZ/f0GGnTCkuuoqjp5wX9v2NIx/NeawT7gSyMic2t/L+iZtwyr+2m+5/WFpRQcKLuCWbnFspPI40+Au3P3aV/A3t6tPRSNRUd1ljtjXye+B3cFMRE8GV2XxLVgq5hwhRyPpulUKUu1IUUrACECdt/3Q/ECErEkqmSbsW8Pg72ejLKNpu3CtXPTKOryDIKPW4DzOF65pEd1qRa9BwHzfiKwtL/wjHpxMaluFDvK65++sgKTMW0yLb2rtoZ3p6SD63xk/PB8xRRDMhBC4gjZnOvmpA+DwsziGGHQFxLo15o9KZrKHcruSnDQpiO0CoHl5U= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(136003)(346002)(376002)(230922051799003)(64100799003)(451199024)(36860700004)(1800799012)(82310400011)(186009)(46966006)(40470700004)(7416002)(8676002)(70586007)(8936002)(70206006)(5660300002)(4326008)(2906002)(82740400003)(110136005)(36756003)(16526019)(356005)(81166007)(83380400001)(86362001)(478600001)(54906003)(316002)(7696005)(6666004)(426003)(2616005)(1076003)(26005)(41300700001)(336012);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2024 19:41:26.9139 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4a82a52-2887-4f6d-5244-08dc2e5e1983 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004688.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8199 Add a CXL Timeout & Isolation (CXL 3.0 12.3) service driver to the PCIe port bus driver for CXL root ports. The service will support enabling/programming CXL.mem transaction timeout, error isolation, and interrupt handling. Add code to find and map CXL Timeout & Isolation capability register (CXL 3.0 8.2.4.23.1) from service driver. Then use capability register mapping to enable CXL.mem transaction timeout with the default value. Signed-off-by: Ben Cheatham --- drivers/cxl/cxl.h | 4 + drivers/pci/pcie/Kconfig | 10 ++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/cxl_timeout.c | 197 +++++++++++++++++++++++++++++++++ drivers/pci/pcie/portdrv.c | 1 + drivers/pci/pcie/portdrv.h | 10 +- 6 files changed, 222 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/pcie/cxl_timeout.c diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 87f3178d6642..0c65f4ec7aae 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -129,7 +129,11 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) /* CXL 3.0 8.2.4.23 CXL Timeout and Isolation Capability Structure */ #define CXL_TIMEOUT_CAPABILITY_OFFSET 0x0 +#define CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP BIT(4) +#define CXL_TIMEOUT_CONTROL_OFFSET 0x8 +#define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE BIT(4) #define CXL_TIMEOUT_CAPABILITY_LENGTH 0x10 + /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 8999fcebde6a..27820af4502e 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -58,6 +58,16 @@ config PCIEAER_CXL If unsure, say Y. +config PCIE_CXL_TIMEOUT + bool "PCI Express CXL.mem Timeout & Isolation Interrupt support" + depends on PCIEPORTBUS + depends on CXL_BUS=PCIEPORTBUS && CXL_PORT + help + Enables the CXL.mem Timeout & Isolation PCIE port service driver. This + driver, in combination with the CXL driver core, is responsible for + handling CXL capable PCIE root ports that undergo CXL.mem error isolation + due to either a CXL.mem transaction timeout or uncorrectable device error. + # # PCI Express ECRC # diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 8de4ed5f98f1..433ef08efc6f 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_PCIE_PME) += pme.o obj-$(CONFIG_PCIE_DPC) += dpc.o obj-$(CONFIG_PCIE_PTM) += ptm.o obj-$(CONFIG_PCIE_EDR) += edr.o +obj-$(CONFIG_PCIE_CXL_TIMEOUT) += cxl_timeout.o diff --git a/drivers/pci/pcie/cxl_timeout.c b/drivers/pci/pcie/cxl_timeout.c new file mode 100644 index 000000000000..84f2df0e0397 --- /dev/null +++ b/drivers/pci/pcie/cxl_timeout.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Implements CXL Timeout & Isolation (CXL 3.0 12.3.2) interrupt support as a + * PCIE port service driver. The driver is set up such that near all of the + * work for setting up and handling interrupts are in this file, while the + * CXL core enables the interrupts during port enumeration. + * + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Author: Ben Cheatham + */ + +#define pr_fmt(fmt) "cxl_timeout: " fmt +#define dev_fmt pr_fmt + +#include +#include + +#include "../../cxl/cxlpci.h" +#include "portdrv.h" + +struct cxl_timeout { + struct pcie_device *dev; + void __iomem *regs; + u32 cap; +}; + +struct pcie_cxlt_data { + struct cxl_timeout *cxlt; + struct cxl_dport *dport; +}; + +static int cxl_map_timeout_regs(struct pci_dev *port, + struct cxl_register_map *map, + struct cxl_component_regs *regs) +{ + int rc = 0; + + rc = cxl_find_regblock(port, CXL_REGLOC_RBI_COMPONENT, map); + if (rc) + return rc; + + rc = cxl_setup_regs(map); + if (rc) + return rc; + + rc = cxl_map_component_regs(map, regs, + BIT(CXL_CM_CAP_CAP_ID_TIMEOUT)); + return rc; +} + +static void cxl_unmap_timeout_regs(struct pci_dev *port, + struct cxl_register_map *map, + struct cxl_component_regs *regs) +{ + struct cxl_reg_map *timeout_map = &map->component_map.timeout; + + devm_iounmap(map->host, regs->timeout); + devm_release_mem_region(map->host, map->resource + timeout_map->offset, + timeout_map->size); +} + +static struct cxl_timeout *cxl_create_cxlt(struct pcie_device *dev) +{ + struct cxl_component_regs *regs; + struct cxl_register_map *map; + struct cxl_timeout *cxlt; + int rc; + + regs = devm_kmalloc(&dev->device, sizeof(*regs), GFP_KERNEL); + if (!regs) + return ERR_PTR(-ENOMEM); + + map = devm_kmalloc(&dev->device, sizeof(*map), GFP_KERNEL); + if (!map) { + devm_kfree(&dev->device, regs); + return ERR_PTR(-ENOMEM); + } + + rc = cxl_map_timeout_regs(dev->port, map, regs); + if (rc) + goto err; + + cxlt = devm_kmalloc(&dev->device, sizeof(*cxlt), GFP_KERNEL); + if (!cxlt) + goto err; + + cxlt->regs = regs->timeout; + cxlt->dev = dev; + cxlt->cap = readl(cxlt->regs + CXL_TIMEOUT_CAPABILITY_OFFSET); + + return cxlt; + +err: + cxl_unmap_timeout_regs(dev->port, map, regs); + return ERR_PTR(rc); +} + +int cxl_find_timeout_cap(struct pci_dev *dev, u32 *cap) +{ + struct cxl_component_regs regs; + struct cxl_register_map map; + int rc = 0; + + rc = cxl_map_timeout_regs(dev, &map, ®s); + if (rc) + return rc; + + *cap = readl(regs.timeout + CXL_TIMEOUT_CAPABILITY_OFFSET); + cxl_unmap_timeout_regs(dev, &map, ®s); + + return rc; +} + +static struct pcie_cxlt_data *cxlt_create_pdata(struct pcie_device *dev) +{ + struct pcie_cxlt_data *data; + + data = devm_kzalloc(&dev->device, sizeof(*data), GFP_KERNEL); + if (IS_ERR_OR_NULL(data)) + return ERR_PTR(-ENOMEM); + + data->cxlt = cxl_create_cxlt(dev); + if (IS_ERR_OR_NULL(data->cxlt)) + return ERR_PTR(PTR_ERR(data->cxlt)); + + data->dport = NULL; + + return data; +} + +static void cxl_disable_timeout(void *data) +{ + struct cxl_timeout *cxlt = data; + u32 cntrl = readl(cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + + cntrl &= ~CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE; + writel(cntrl, cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); +} + +static int cxl_enable_timeout(struct pcie_device *dev, struct cxl_timeout *cxlt) +{ + u32 cntrl; + + if (!cxlt || !FIELD_GET(CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP, cxlt->cap)) + return -ENXIO; + + cntrl = readl(cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + cntrl |= CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE; + writel(cntrl, cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + + return devm_add_action_or_reset(&dev->device, cxl_disable_timeout, + cxlt); +} + +static int cxl_timeout_probe(struct pcie_device *dev) +{ + struct pci_dev *port = dev->port; + struct pcie_cxlt_data *pdata; + struct cxl_timeout *cxlt; + int rc = 0; + + /* Limit to CXL root ports */ + if (!pci_find_dvsec_capability(port, PCI_DVSEC_VENDOR_ID_CXL, + CXL_DVSEC_PORT_EXTENSIONS)) + return -ENODEV; + + pdata = cxlt_create_pdata(dev); + if (IS_ERR_OR_NULL(pdata)) + return PTR_ERR(pdata); + + set_service_data(dev, pdata); + cxlt = pdata->cxlt; + + rc = cxl_enable_timeout(dev, cxlt); + if (rc) + pci_dbg(dev->port, "Failed to enable CXL.mem timeout: %d\n", + rc); + + return rc; +} + +static struct pcie_port_service_driver cxltdriver = { + .name = "cxl_timeout", + .port_type = PCI_EXP_TYPE_ROOT_PORT, + .service = PCIE_PORT_SERVICE_CXLT, + + .probe = cxl_timeout_probe, +}; + +int __init pcie_cxlt_init(void) +{ + return pcie_port_service_register(&cxltdriver); +} + +MODULE_IMPORT_NS(CXL); diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 14a4b89a3b83..7aa0a6f2da4e 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -829,6 +829,7 @@ static void __init pcie_init_services(void) pcie_pme_init(); pcie_dpc_init(); pcie_hp_init(); + pcie_cxlt_init(); } static int __init pcie_portdrv_init(void) diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 1f3803bde7ee..5395a0e36956 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -22,8 +22,10 @@ #define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT) #define PCIE_PORT_SERVICE_BWNOTIF_SHIFT 4 /* Bandwidth notification */ #define PCIE_PORT_SERVICE_BWNOTIF (1 << PCIE_PORT_SERVICE_BWNOTIF_SHIFT) +#define PCIE_PORT_SERVICE_CXLT_SHIFT 5 /* CXL Timeout & Isolation */ +#define PCIE_PORT_SERVICE_CXLT (1 << PCIE_PORT_SERVICE_CXLT_SHIFT) -#define PCIE_PORT_DEVICE_MAXSERVICES 5 +#define PCIE_PORT_DEVICE_MAXSERVICES 6 extern bool pcie_ports_dpc_native; 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Thu, 15 Feb 2024 19:41:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF00004689.mail.protection.outlook.com (10.167.243.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7292.25 via Frontend Transport; Thu, 15 Feb 2024 19:41:46 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 15 Feb 2024 13:41:42 -0600 From: Ben Cheatham To: , CC: , , , , , , , , Subject: [RFC PATCH 3/6] pcie/cxl_timeout: Add CXL.mem timeout range programming Date: Thu, 15 Feb 2024 13:40:45 -0600 Message-ID: <20240215194048.141411-4-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> References: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004689:EE_|MN2PR12MB4565:EE_ X-MS-Office365-Filtering-Correlation-Id: e15fccc8-062f-480f-3955-08dc2e5e252e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2024 19:41:46.5045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e15fccc8-062f-480f-3955-08dc2e5e252e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004689.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4565 Add programming of CXL.mem transaction timeout range (CXL 3.0 8.2.4.23.1 bits 4 & 11:8) through sysfs. To program the device, read the ranges supported from "available_timeout_ranges" in the PCIe service device directory, then write the desired value to "timeout_range". The current value can be found by reading from "timeout_range". Example for CXL-enabled PCIe port 0000:0c:00.0, with CXL timeout service as 020: # cd /sys/bus/pci_express/devices/0000:0c:00.0:pcie020 # cat available_timeout_ranges 0x0 Default range (50us-10ms) 0x1 Range A (50us-100us) 0x2 Range A (1ms-10ms) # cat timeout_range 0 # echo 0x2 > timeout_range # cat timeout_range 2 Signed-off-by: Ben Cheatham --- drivers/cxl/cxl.h | 13 +++ drivers/pci/pcie/cxl_timeout.c | 185 +++++++++++++++++++++++++++++++++ 2 files changed, 198 insertions(+) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 0c65f4ec7aae..4aa5fecc43bd 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -129,11 +129,24 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) /* CXL 3.0 8.2.4.23 CXL Timeout and Isolation Capability Structure */ #define CXL_TIMEOUT_CAPABILITY_OFFSET 0x0 +#define CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP BIT(4) #define CXL_TIMEOUT_CONTROL_OFFSET 0x8 +#define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE BIT(4) #define CXL_TIMEOUT_CAPABILITY_LENGTH 0x10 +/* CXL 3.0 8.2.4.23.2 CXL Timeout and Isolation Control Register, bits 3:0 */ +#define CXL_TIMEOUT_TIMEOUT_RANGE_DEFAULT 0x0 +#define CXL_TIMEOUT_TIMEOUT_RANGE_A1 0x1 +#define CXL_TIMEOUT_TIMEOUT_RANGE_A2 0x2 +#define CXL_TIMEOUT_TIMEOUT_RANGE_B1 0x5 +#define CXL_TIMEOUT_TIMEOUT_RANGE_B2 0x6 +#define CXL_TIMEOUT_TIMEOUT_RANGE_C1 0x9 +#define CXL_TIMEOUT_TIMEOUT_RANGE_C2 0xA +#define CXL_TIMEOUT_TIMEOUT_RANGE_D1 0xD +#define CXL_TIMEOUT_TIMEOUT_RANGE_D2 0xE + /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) diff --git a/drivers/pci/pcie/cxl_timeout.c b/drivers/pci/pcie/cxl_timeout.c index 84f2df0e0397..916dbaf2bb58 100644 --- a/drivers/pci/pcie/cxl_timeout.c +++ b/drivers/pci/pcie/cxl_timeout.c @@ -20,6 +20,8 @@ #include "../../cxl/cxlpci.h" #include "portdrv.h" +#define NUM_CXL_TIMEOUT_RANGES 9 + struct cxl_timeout { struct pcie_device *dev; void __iomem *regs; @@ -130,6 +132,57 @@ static struct pcie_cxlt_data *cxlt_create_pdata(struct pcie_device *dev) return data; } +static bool cxl_validate_timeout_range(struct cxl_timeout *cxlt, u8 range) +{ + u8 timeout_ranges = FIELD_GET(CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK, + cxlt->cap); + + if (!timeout_ranges) + return false; + + switch (range) { + case CXL_TIMEOUT_TIMEOUT_RANGE_DEFAULT: + return true; + case CXL_TIMEOUT_TIMEOUT_RANGE_A1: + case CXL_TIMEOUT_TIMEOUT_RANGE_A2: + return timeout_ranges & BIT(0); + case CXL_TIMEOUT_TIMEOUT_RANGE_B1: + case CXL_TIMEOUT_TIMEOUT_RANGE_B2: + return timeout_ranges & BIT(1); + case CXL_TIMEOUT_TIMEOUT_RANGE_C1: + case CXL_TIMEOUT_TIMEOUT_RANGE_C2: + return timeout_ranges & BIT(2); + case CXL_TIMEOUT_TIMEOUT_RANGE_D1: + case CXL_TIMEOUT_TIMEOUT_RANGE_D2: + return timeout_ranges & BIT(3); + default: + pci_info(cxlt->dev->port, "Invalid timeout range: %d\n", + range); + return false; + } +} + +static int cxl_set_mem_timeout_range(struct cxl_timeout *cxlt, u8 range) +{ + u32 cntrl; + + if (!cxlt) + return -ENXIO; + + if (!FIELD_GET(CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK, cxlt->cap) + || !cxl_validate_timeout_range(cxlt, range)) + return -ENXIO; + + cntrl = readl(cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + cntrl &= ~CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK; + cntrl |= CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK & range; + writel(cntrl, cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + + pci_dbg(cxlt->dev->port, + "Timeout & isolation timeout set to range 0x%x\n", range); + return 0; +} + static void cxl_disable_timeout(void *data) { struct cxl_timeout *cxlt = data; @@ -154,6 +207,135 @@ static int cxl_enable_timeout(struct pcie_device *dev, struct cxl_timeout *cxlt) cxlt); } +static ssize_t timeout_range_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pcie_device *pdev = to_pcie_device(dev); + struct pcie_cxlt_data *pdata = get_service_data(pdev); + u32 cntrl, range; + + if (!pdata || !pdata->cxlt) + return -ENXIO; + + cntrl = readl(pdata->cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + + range = FIELD_GET(CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK, cntrl); + return sysfs_emit(buf, "%u\n", range); +} + +static ssize_t timeout_range_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pcie_device *pdev = to_pcie_device(dev); + struct pcie_cxlt_data *pdata = get_service_data(pdev); + u8 range; + int rc; + + if (kstrtou8(buf, 16, &range) < 0) + return -EINVAL; + + if (!pdata || !pdata->cxlt) + return -ENXIO; + + rc = cxl_set_mem_timeout_range(pdata->cxlt, range); + if (rc) + return rc; + + return count; +} +static DEVICE_ATTR_RW(timeout_range); + +const struct cxl_timeout_range { + const char *str; + u8 range_val; +} cxl_timeout_ranges[NUM_CXL_TIMEOUT_RANGES] = { + { "Default range (50us-10ms)", + CXL_TIMEOUT_TIMEOUT_RANGE_DEFAULT }, + { "Range A (50us-100us)", + CXL_TIMEOUT_TIMEOUT_RANGE_A1 }, + { "Range A (1ms-10ms)", + CXL_TIMEOUT_TIMEOUT_RANGE_A2 }, + { "Range B (16ms-55ms)", + CXL_TIMEOUT_TIMEOUT_RANGE_B1 }, + { "Range B (65ms-210ms)", + CXL_TIMEOUT_TIMEOUT_RANGE_B2 }, + { "Range C (260ms-900ms)", + CXL_TIMEOUT_TIMEOUT_RANGE_C1 }, + { "Range C (1s-3.5s)", + CXL_TIMEOUT_TIMEOUT_RANGE_C2 }, + { "Range D (4s-13s)", + CXL_TIMEOUT_TIMEOUT_RANGE_D1 }, + { "Range D (17s-64s)", + CXL_TIMEOUT_TIMEOUT_RANGE_D2 }, +}; + +static ssize_t available_timeout_ranges_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pcie_device *pdev = to_pcie_device(dev); + struct pcie_cxlt_data *pdata = get_service_data(pdev); + ssize_t count = 0; + u8 range; + + if (!pdata || !pdata->cxlt) + return -ENXIO; + + for (int i = 0; i < ARRAY_SIZE(cxl_timeout_ranges); i++) { + range = cxl_timeout_ranges[i].range_val; + + if (cxl_validate_timeout_range(pdata->cxlt, range)) { + count += sysfs_emit_at(buf, count, "0x%x\t%s\n", + cxl_timeout_ranges[i].range_val, + cxl_timeout_ranges[i].str); + } + } + + return count; +} +static DEVICE_ATTR_RO(available_timeout_ranges); + +static umode_t cxl_timeout_is_visible(struct kobject *kobj, + struct attribute *attr, int val) +{ + struct device *dev = kobj_to_dev(kobj); + struct pcie_device *pdev = to_pcie_device(dev); + struct pcie_cxlt_data *pdata = get_service_data(pdev); + u32 cap; + + if (!pdata || !pdata->cxlt) + return 0; + + cap = pdata->cxlt->cap; + + if ((attr == &dev_attr_timeout_range.attr) && + cap & CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP) + return attr->mode; + + if ((attr == &dev_attr_available_timeout_ranges.attr) && + (FIELD_GET(CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK, cap))) + return attr->mode; + + return 0; +} +static struct attribute *cxl_timeout_timeout_attributes[] = { + &dev_attr_timeout_range.attr, + &dev_attr_available_timeout_ranges.attr, + NULL, +}; + +static struct attribute_group cxl_timeout_timeout_group = { + .attrs = cxl_timeout_timeout_attributes, + .is_visible = cxl_timeout_is_visible, +}; + +static const struct attribute_group *cxl_timeout_attribute_groups[] = { + &cxl_timeout_timeout_group, + NULL, +}; + static int cxl_timeout_probe(struct pcie_device *dev) { struct pci_dev *port = dev->port; @@ -187,6 +369,9 @@ static struct pcie_port_service_driver cxltdriver = { .service = PCIE_PORT_SERVICE_CXLT, .probe = cxl_timeout_probe, + .driver = { + .dev_groups = cxl_timeout_attribute_groups, + }, }; int __init pcie_cxlt_init(void) From patchwork Thu Feb 15 19:40:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 13559106 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2068.outbound.protection.outlook.com [40.107.237.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 050CB13A247; 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Thu, 15 Feb 2024 13:41:55 -0600 From: Ben Cheatham To: , CC: , , , , , , , , Subject: [RFC PATCH 4/6] pcie/cxl_timeout: Add CXL.mem error isolation support Date: Thu, 15 Feb 2024 13:40:46 -0600 Message-ID: <20240215194048.141411-5-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> References: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468A:EE_|LV8PR12MB9207:EE_ X-MS-Office365-Filtering-Correlation-Id: c6779b49-ccdb-415f-ddf7-08dc2e5e2beb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 57mr0ieBlEGSMGCHlkHx+3KbZDPgL/n22d4Mi3CyMRC57eduP3INvL0b2MprTCI33Kg2b3vMiGXpXUB/K8X9JTyaFkvO300h5HRnwlPqhqGwVltjqWRy0wSMv4cTlj0/g6ln6MbWZM2gMzsmparBSDaD8SsE1BEttypLjI6lLZOU6srukiVXkA+SMbKidMxcPTGGZXmG0TMZKQZQ8MQb8dKpwDYWRJxT7a8G2zPr0W4cyLU/kdMi073Fpay7rcFpybDQhmqAR+B2YHmFFjXyuJIe2nqtjlJHwh2h+envpWoPRnjIlEy/wkeDrvOs80cNb3rGCprOyj+34WQQ+dtV8lARvsWU0tDLMJnob/wzNOlLRRTLEd73s1/IyOJTWl0H4vMrOx6bQuKipo9pgeWTppsZMeyC1mNHohtnJSv2MGIdsUnVMNrM2pGr30aWfxiELvaq2rK0xoOk9shPnwb6vIsXj5ymNyBv+qUMdX570jxolNqEpmkw851zcq7ImVTyvvX9FizbYkShxRe5UVdvqZ3a51wX0etAvsoqmbBmzdJ5PKaSO7FAi8/78Xlr/Nz6uB4vh9IB8IpK0EfHFzzR2w3qzsxCPB/cmKbB+OLZxfBqQu0ZiMY/t7ZXjrXfds/LqeYrtIL1UHSkvXAhYYTwy2hE9ZeabTvK1w/kihq8vZs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(376002)(136003)(346002)(396003)(230922051799003)(82310400011)(451199024)(36860700004)(64100799003)(186009)(1800799012)(40470700004)(46966006)(2616005)(7696005)(478600001)(110136005)(5660300002)(7416002)(8676002)(8936002)(2906002)(4326008)(70206006)(41300700001)(70586007)(316002)(26005)(86362001)(83380400001)(426003)(16526019)(54906003)(1076003)(36756003)(336012)(356005)(82740400003)(6666004)(81166007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2024 19:41:57.7980 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6779b49-ccdb-415f-ddf7-08dc2e5e2beb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9207 Add and enable CXL.mem error isolation support (CXL 3.0 12.3.2) to the CXL Timeout & Isolation service driver. Signed-off-by: Ben Cheatham --- drivers/cxl/cxl.h | 2 ++ drivers/pci/pcie/cxl_timeout.c | 40 +++++++++++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4aa5fecc43bd..b1d5232a0127 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -131,9 +131,11 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) #define CXL_TIMEOUT_CAPABILITY_OFFSET 0x0 #define CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP BIT(4) +#define CXL_TIMEOUT_CAP_MEM_ISO_SUPP BIT(16) #define CXL_TIMEOUT_CONTROL_OFFSET 0x8 #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE BIT(4) +#define CXL_TIMEOUT_CONTROL_MEM_ISO_ENABLE BIT(16) #define CXL_TIMEOUT_CAPABILITY_LENGTH 0x10 /* CXL 3.0 8.2.4.23.2 CXL Timeout and Isolation Control Register, bits 3:0 */ diff --git a/drivers/pci/pcie/cxl_timeout.c b/drivers/pci/pcie/cxl_timeout.c index 916dbaf2bb58..5900239e5bbf 100644 --- a/drivers/pci/pcie/cxl_timeout.c +++ b/drivers/pci/pcie/cxl_timeout.c @@ -207,6 +207,31 @@ static int cxl_enable_timeout(struct pcie_device *dev, struct cxl_timeout *cxlt) cxlt); } +static void cxl_disable_isolation(void *data) +{ + struct cxl_timeout *cxlt = data; + u32 cntrl = readl(cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + + cntrl &= ~CXL_TIMEOUT_CONTROL_MEM_ISO_ENABLE; + writel(cntrl, cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); +} + +static int cxl_enable_isolation(struct pcie_device *dev, + struct cxl_timeout *cxlt) +{ + u32 cntrl; + + if (!cxlt || !FIELD_GET(CXL_TIMEOUT_CAP_MEM_ISO_SUPP, cxlt->cap)) + return -ENXIO; + + cntrl = readl(cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + cntrl |= CXL_TIMEOUT_CONTROL_MEM_ISO_ENABLE; + writel(cntrl, cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + + return devm_add_action_or_reset(&dev->device, cxl_disable_isolation, + cxlt); +} + static ssize_t timeout_range_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -341,7 +366,8 @@ static int cxl_timeout_probe(struct pcie_device *dev) struct pci_dev *port = dev->port; struct pcie_cxlt_data *pdata; struct cxl_timeout *cxlt; - int rc = 0; + bool timeout_enabled; + int rc; /* Limit to CXL root ports */ if (!pci_find_dvsec_capability(port, PCI_DVSEC_VENDOR_ID_CXL, @@ -360,6 +386,18 @@ static int cxl_timeout_probe(struct pcie_device *dev) pci_dbg(dev->port, "Failed to enable CXL.mem timeout: %d\n", rc); + timeout_enabled = !rc; + + rc = cxl_enable_isolation(dev, cxlt); + if (rc) + pci_dbg(dev->port, "Failed to enable CXL.mem isolation: %d\n", + rc); + + if (rc && !timeout_enabled) { + pci_info(dev->port, + "Failed to enable CXL.mem timeout and isolation.\n"); + } + return rc; } From patchwork Thu Feb 15 19:40:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 13559107 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2047.outbound.protection.outlook.com [40.107.92.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2D2C13A254; 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Thu, 15 Feb 2024 13:42:15 -0600 From: Ben Cheatham To: , CC: , , , , , , , , Subject: [RFC PATCH 5/6] pcie/portdrv: Add CXL MSI/-X allocation Date: Thu, 15 Feb 2024 13:40:47 -0600 Message-ID: <20240215194048.141411-6-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> References: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468E:EE_|CY8PR12MB7657:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f627258-3b14-4f1e-aea0-08dc2e5e37ec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zb1SOSZ3FvtVFCZlJLolcD0odlF82SvDVBhCmChckUD0dbT/zjCuTs/gKqUMZsd2AcsSekBIqg70BPyWbyYSCQWTq7uBh6VlVnG+zMWd2aiRdEEjBtbDcNQ9L6uN1PNPW3oN2HpiqXR6bj3QCoin9w+5mOj5CDlqkxJtZ1QpMwZGeK8gvxqsL0vS+E0GghdjdZlxHjwLNDIXO7nspq1GmU1ppjvQPFfpe8MFAG4KBxyCfNGp8OzSKic3F6wyktjFxOWb1ZyzQKT9qlEfcFxLilrlWre3OqkuzaqUwcqvo438mY+5z9b2x1b0hNdF/1pEAh5zAXrQISGAjWnxNuycs5272y6BHfrqfdk8Ibu7ZYDRdW+AYzV7CbDMj1phOck9KGtSCD1uGwLYL/lRfNtZsGvwRtwrOAflCsH399X+I/rq3YodUMCwzxAaHf22JpXhZX4bZj2bH4PXttH33OwtI9Jwz0PnM4ACVzsPl0jimjBXn4kf2SGpw3DvkooX7w7QqPfK4KYDS9MoQAeVY0L7uSesMRcauEzcPLjHR2j0KgSO0+xhX66iQlnPuXKS3op0kJ/u+nQPQ4doMuwfUf2bK4xg2JFvKFaUu9WMqtV9GEdMFxRFTNB9ZwEk1USYh+xNOsFgmIlz1++9qrvyruty6gSxBX+Novzm/KZPJfhwASI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(136003)(39860400002)(346002)(230922051799003)(451199024)(36860700004)(1800799012)(64100799003)(82310400011)(186009)(40470700004)(46966006)(478600001)(41300700001)(6666004)(7416002)(2906002)(8676002)(8936002)(4326008)(7696005)(316002)(5660300002)(110136005)(70586007)(54906003)(70206006)(83380400001)(86362001)(336012)(426003)(81166007)(2616005)(26005)(356005)(16526019)(1076003)(82740400003)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2024 19:42:17.9360 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f627258-3b14-4f1e-aea0-08dc2e5e37ec X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7657 Allocate an MSI/-X for CXL-enabled PCIe root ports that support timeout & isolation interrupts. This vector will be used by the CXL timeout & isolation service driver to disable the root port in the CXL port hierarchy and any associated memory if the port enters isolation. Signed-off-by: Ben Cheatham --- drivers/cxl/cxl.h | 2 ++ drivers/pci/pcie/cxl_timeout.c | 11 ++++++++++- drivers/pci/pcie/portdrv.c | 35 +++++++++++++++++++++++++++++++--- drivers/pci/pcie/portdrv.h | 6 ++++++ 4 files changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index b1d5232a0127..3b5645ec95b9 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -132,6 +132,8 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) #define CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP BIT(4) #define CXL_TIMEOUT_CAP_MEM_ISO_SUPP BIT(16) +#define CXL_TIMEOUT_CAP_INTR_SUPP BIT(26) +#define CXL_TIMEOUT_CAP_INTR_MASK GENMASK(31, 27) #define CXL_TIMEOUT_CONTROL_OFFSET 0x8 #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE BIT(4) diff --git a/drivers/pci/pcie/cxl_timeout.c b/drivers/pci/pcie/cxl_timeout.c index 5900239e5bbf..352d9370a999 100644 --- a/drivers/pci/pcie/cxl_timeout.c +++ b/drivers/pci/pcie/cxl_timeout.c @@ -99,7 +99,7 @@ static struct cxl_timeout *cxl_create_cxlt(struct pcie_device *dev) return ERR_PTR(rc); } -int cxl_find_timeout_cap(struct pci_dev *dev, u32 *cap) +int pcie_cxl_find_timeout_cap(struct pci_dev *dev, u32 *cap) { struct cxl_component_regs regs; struct cxl_register_map map; @@ -115,6 +115,15 @@ int cxl_find_timeout_cap(struct pci_dev *dev, u32 *cap) return rc; } +bool pcie_supports_cxl_timeout_interrupts(u32 cap) +{ + if (!(cap & CXL_TIMEOUT_CAP_INTR_SUPP)) + return false; + + return (cap & CXL_TIMEOUT_CAP_MEM_ISO_SUPP) || + (cap & CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP); +} + static struct pcie_cxlt_data *cxlt_create_pdata(struct pcie_device *dev) { struct pcie_cxlt_data *data; diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 7aa0a6f2da4e..c36fe6ccfeae 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -21,6 +21,7 @@ #include "../pci.h" #include "portdrv.h" +#include "../../cxl/cxlpci.h" /* * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must @@ -55,7 +56,7 @@ static void release_pcie_device(struct device *dev) * required to accommodate the largest Message Number. */ static int pcie_message_numbers(struct pci_dev *dev, int mask, - u32 *pme, u32 *aer, u32 *dpc) + u32 *pme, u32 *aer, u32 *dpc, u32 *cxl) { u32 nvec = 0, pos; u16 reg16; @@ -98,6 +99,19 @@ static int pcie_message_numbers(struct pci_dev *dev, int mask, } } +#ifdef CONFIG_PCIE_CXL_TIMEOUT + if (mask & PCIE_PORT_SERVICE_CXLT) { + u32 cap; + + if (!pcie_cxl_find_timeout_cap(dev, &cap) && + pcie_supports_cxl_timeout_interrupts(cap)) { + *cxl = FIELD_GET(CXL_TIMEOUT_CAP_INTR_MASK, + pos); + nvec = max(nvec, *cxl + 1); + } + } +#endif + return nvec; } @@ -113,7 +127,7 @@ static int pcie_message_numbers(struct pci_dev *dev, int mask, static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) { int nr_entries, nvec, pcie_irq; - u32 pme = 0, aer = 0, dpc = 0; + u32 pme = 0, aer = 0, dpc = 0, cxlt = 0; /* Allocate the maximum possible number of MSI/MSI-X vectors */ nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSI_ENTRIES, @@ -122,7 +136,7 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) return nr_entries; /* See how many and which Interrupt Message Numbers we actually use */ - nvec = pcie_message_numbers(dev, mask, &pme, &aer, &dpc); + nvec = pcie_message_numbers(dev, mask, &pme, &aer, &dpc, &cxlt); if (nvec > nr_entries) { pci_free_irq_vectors(dev); return -EIO; @@ -163,6 +177,9 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) if (mask & PCIE_PORT_SERVICE_DPC) irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, dpc); + if (mask & PCIE_PORT_SERVICE_CXLT) + irqs[PCIE_PORT_SERVICE_CXLT_SHIFT] = pci_irq_vector(dev, cxlt); + return 0; } @@ -274,6 +291,18 @@ static int get_port_device_capability(struct pci_dev *dev) services |= PCIE_PORT_SERVICE_BWNOTIF; } +#ifdef CONFIG_PCIE_CXL_TIMEOUT + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && + pci_find_dvsec_capability(dev, PCI_DVSEC_VENDOR_ID_CXL, + CXL_DVSEC_PORT_EXTENSIONS)) { + u32 cap; + + if (!pcie_cxl_find_timeout_cap(dev, &cap) && + pcie_supports_cxl_timeout_interrupts(cap)) + services |= PCIE_PORT_SERVICE_CXLT; + } +#endif + return services; } diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 5395a0e36956..f89e7366e986 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -129,4 +129,10 @@ static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {} #endif /* !CONFIG_PCIE_PME */ struct device *pcie_port_find_device(struct pci_dev *dev, u32 service); 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Thu, 15 Feb 2024 19:42:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF0000468E.mail.protection.outlook.com (10.167.243.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7292.25 via Frontend Transport; Thu, 15 Feb 2024 19:42:30 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 15 Feb 2024 13:42:28 -0600 From: Ben Cheatham To: , CC: , , , , , , , , Subject: [RFC PATCH 6/6] pcie/cxl_timeout: Add CXL.mem Timeout & Isolation interrupt support Date: Thu, 15 Feb 2024 13:40:48 -0600 Message-ID: <20240215194048.141411-7-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> References: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468E:EE_|CY8PR12MB8339:EE_ X-MS-Office365-Filtering-Correlation-Id: c32f69c3-2ab5-4cd0-0a76-08dc2e5e3f60 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2024 19:42:30.4361 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c32f69c3-2ab5-4cd0-0a76-08dc2e5e3f60 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8339 Add support for CXL.mem Timeout & Isolation interrupts. A CXL root port under isolation will not complete writes and will return an exception response (i.e. poison) on reads (CXL 3.0 12.3.2). Therefore, when a CXL-enabled PCIe root port enters isolation, we assume that the memory under the port is unreachable and will need to be unmapped. When an isolation interrupt occurs, the CXL Timeout & Isolation service driver will mark the port (cxl_dport) as isolated, destroy any CXL memory regions under the *bridge* (cxl_port), and attempt to unmap the memory backing the CXL region(s). If the memory was already in use, the mapping is not guaranteed to succeed. Signed-off-by: Ben Cheatham --- drivers/cxl/core/pci.c | 5 + drivers/cxl/core/port.c | 80 ++++++++++++++++ drivers/cxl/core/region.c | 9 ++ drivers/cxl/cxl.h | 10 ++ drivers/cxl/cxlpci.h | 9 ++ drivers/pci/pcie/cxl_timeout.c | 165 ++++++++++++++++++++++++++++++++- drivers/pci/pcie/portdrv.h | 1 + 7 files changed, 278 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 6c9c8d92f8f7..95b6a5f0d0cc 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -64,6 +64,11 @@ static int match_add_dports(struct pci_dev *pdev, void *data) } ctx->count++; + if (type == PCI_EXP_TYPE_ROOT_PORT && !pcie_cxlt_register_dport(dport)) + return devm_add_action_or_reset(dport->dport_dev, + pcie_cxlt_unregister_dport, + dport); + return 0; } diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index e59d9d37aa65..88d114c67596 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2000,6 +2000,86 @@ int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld) } EXPORT_SYMBOL_NS_GPL(cxl_decoder_autoremove, CXL); +/* Checks to see if a dport is above an endpoint */ +static bool cxl_dport_is_parent(struct cxl_dport *parent, struct cxl_ep *ep) +{ + struct cxl_dport *ep_dport = ep->dport; + struct cxl_port *ep_port = ep_dport->port; + + while (!is_cxl_root(ep_port)) { + if (ep_dport == parent) + return true; + + ep_dport = ep_port->parent_dport; + ep_port = ep_dport->port; + } + + return false; +} + +bool cxl_dport_is_in_region(struct cxl_dport *dport, + struct cxl_region_ref *rr) +{ + struct cxl_region_params *p = &rr->region->params; + struct cxl_ep *ep; + int i; + + for (i = 0; i < p->nr_targets; i++) { + if (!p->targets[i]) + continue; + + ep = cxl_ep_load(dport->port, cxled_to_memdev(p->targets[i])); + + if (ep && cxl_dport_is_parent(dport, ep)) + return true; + } + + return false; +} +EXPORT_SYMBOL_NS_GPL(cxl_dport_is_in_region, CXL); + +void cxl_port_kill_regions(struct cxl_port *port) +{ + struct cxl_endpoint_decoder *ep_decoder; + struct cxl_region_params *p; + struct cxl_region_ref *ref; + unsigned long index; + struct cxl_ep *ep; + int i; + + xa_for_each(&port->regions, index, ref) { + p = &ref->region->params; + + for (i = 0; i < p->nr_targets; i++) { + ep_decoder = p->targets[i]; + if (!ep_decoder) + continue; + + ep = cxl_ep_load(port, cxled_to_memdev(ep_decoder)); + if (ep) + cxl_decoder_kill_region(ep_decoder); + } + } +} +EXPORT_SYMBOL_NS_GPL(cxl_port_kill_regions, CXL); + +bool cxl_port_is_isolated(struct cxl_port *port) +{ + struct cxl_dport *dport = port->parent_dport; + + while (!is_cxl_root(port) && dport) { + if (dport->isolated || !dport->port) + return true; + + dport = dport->port->parent_dport; + port = dport->port; + } + + + return false; +} +EXPORT_SYMBOL_NS_GPL(cxl_port_is_isolated, CXL); + /** * __cxl_driver_register - register a driver for the cxl bus * @cxl_drv: cxl driver structure to attach diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 0f05692bfec3..f9aef17db26c 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1699,6 +1699,12 @@ static int cxl_region_attach(struct cxl_region *cxlr, return -ENXIO; } + if (cxl_port_is_isolated(ep_port)) { + dev_err(&cxlr->dev, "%s:%s endpoint is under a dport in error isolation\n", + dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev)); + return -EBUSY; + } + if (cxled->cxld.target_type != cxlr->type) { dev_dbg(&cxlr->dev, "%s:%s type mismatch: %d vs %d\n", dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), @@ -2782,6 +2788,9 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, struct resource *res; int rc; + if (cxl_port_is_isolated(cxlmd->endpoint)) + return ERR_PTR(-EBUSY); + do { cxlr = __create_region(cxlrd, cxled->mode, atomic_read(&cxlrd->region_id)); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 3b5645ec95b9..1bee2560446a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -138,6 +138,10 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE BIT(4) #define CXL_TIMEOUT_CONTROL_MEM_ISO_ENABLE BIT(16) +#define CXL_TIMEOUT_CONTROL_MEM_INTR_ENABLE BIT(26) +#define CXL_TIMEOUT_STATUS_OFFSET 0xC +#define CXL_TIMEOUT_STATUS_MEM_TIMEOUT BIT(0) +#define CXL_TIMEOUT_STATUS_MEM_ISO BIT(8) #define CXL_TIMEOUT_CAPABILITY_LENGTH 0x10 /* CXL 3.0 8.2.4.23.2 CXL Timeout and Isolation Control Register, bits 3:0 */ @@ -700,8 +704,11 @@ struct cxl_dport { struct access_coordinate sw_coord; struct access_coordinate hb_coord; long link_latency; + bool isolated; }; +bool cxl_port_is_isolated(struct cxl_port *port); + /** * struct cxl_ep - track an endpoint's interest in a port * @ep: device that hosts a generic CXL endpoint (expander or accelerator) @@ -735,6 +742,9 @@ struct cxl_region_ref { int nr_targets; }; +bool cxl_dport_is_in_region(struct cxl_dport *dport, struct cxl_region_ref *ref); +void cxl_port_kill_regions(struct cxl_port *port); + /* * The platform firmware device hosting the root is also the top of the * CXL port topology. All other CXL ports have another CXL port as their diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 711b05d9a370..7100e23a1819 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -106,4 +106,13 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); + +#ifdef CONFIG_PCIE_CXL_TIMEOUT +int pcie_cxlt_register_dport(struct cxl_dport *dport); +void pcie_cxlt_unregister_dport(struct cxl_dport *dport); +#else +int pcie_cxlt_register_dport(void *dport) { return -ENXIO; } +void pcie_cxlt_unregister_dport(void *dport) {} +#endif + #endif /* __CXL_PCI_H__ */ diff --git a/drivers/pci/pcie/cxl_timeout.c b/drivers/pci/pcie/cxl_timeout.c index 352d9370a999..2193e872b4b7 100644 --- a/drivers/pci/pcie/cxl_timeout.c +++ b/drivers/pci/pcie/cxl_timeout.c @@ -22,6 +22,8 @@ #define NUM_CXL_TIMEOUT_RANGES 9 +static u32 num_cxlt_devs; + struct cxl_timeout { struct pcie_device *dev; void __iomem *regs; @@ -141,6 +143,141 @@ static struct pcie_cxlt_data *cxlt_create_pdata(struct pcie_device *dev) return data; } +int pcie_cxlt_register_dport(struct cxl_dport *dport) +{ + struct device *dev = dport->dport_dev; + struct pcie_device *pcie_dev; + struct pcie_cxlt_data *pdata; + struct pci_dev *pdev; + + if (!dev_is_pci(dev)) + return -ENXIO; + + pdev = to_pci_dev(dev); + + dev = pcie_port_find_device(pdev, PCIE_PORT_SERVICE_CXLT); + if (!dev) { + dev_warn(dev, + "Device is not registered with cxl_timeout driver.\n"); + return -ENODEV; + } + + pcie_dev = to_pcie_device(dev); + + pdata = get_service_data(pcie_dev); + pdata->dport = dport; + + return 0; +} +EXPORT_SYMBOL_GPL(pcie_cxlt_register_dport); + +void pcie_cxlt_unregister_dport(struct cxl_dport *dport) +{ + struct device *dev = dport->dport_dev; + struct pcie_device *pcie_dev; + struct pcie_cxlt_data *pdata; + struct pci_dev *pdev; + + if (!dev_is_pci(dev)) + return; + + pdev = to_pci_dev(dev); + + dev = pcie_port_find_device(pdev, PCIE_PORT_SERVICE_CXLT); + if (!dev) { + dev_dbg(dev, + "Device was not registered with cxl_timeout driver.\n"); + return; + } + + pcie_dev = to_pcie_device(dev); + pdata = get_service_data(pcie_dev); + pdata->dport = NULL; +} +EXPORT_SYMBOL_GPL(pcie_cxlt_unregister_dport); + +struct cxl_timeout_wq_data { + struct work_struct w; + struct cxl_dport *dport; +}; + +static struct workqueue_struct *cxl_timeout_wq; + +static void cxl_timeout_handler(struct work_struct *w) +{ + struct cxl_timeout_wq_data *data = + container_of(w, struct cxl_timeout_wq_data, w); + struct cxl_dport *dport = data->dport; + struct cxl_port *port; + struct cxl_region_ref *ref; + unsigned long index; + bool kill_regions; + + if (!dport || !dport->port) + return; + + port = dport->port; + + xa_for_each(&port->regions, index, ref) + if (cxl_dport_is_in_region(dport, ref)) + kill_regions = true; + + if (kill_regions) + cxl_port_kill_regions(port); + + kfree(data); +} + +irqreturn_t cxl_timeout_thread(int irq, void *data) +{ + struct cxl_timeout_wq_data *wq_data; + struct cxl_timeout *cxlt = data; + struct pcie_device *pcie_dev = cxlt->dev; + struct pcie_cxlt_data *pdata; + struct cxl_dport *dport; + u32 status; + + /* + * If the CXL core didn't register a cxl_dport with this PCIe device, + * then dport enumeration failed and there's nothing to do CXL-wise. + */ + pdata = get_service_data(pcie_dev); + if (!pdata || !pdata->dport) + return IRQ_HANDLED; + + dport = pdata->dport; + + status = readl(cxlt->regs + CXL_TIMEOUT_STATUS_OFFSET); + if (!(status & CXL_TIMEOUT_STATUS_MEM_ISO + || status & CXL_TIMEOUT_STATUS_MEM_TIMEOUT)) + return IRQ_HANDLED; + + dport->isolated = true; + + wq_data = kzalloc(sizeof(struct cxl_timeout_wq_data), GFP_NOWAIT); + if (!wq_data) + return IRQ_NONE; + + wq_data->dport = dport; + + INIT_WORK(&wq_data->w, cxl_timeout_handler); + queue_work(cxl_timeout_wq, &wq_data->w); + + return IRQ_HANDLED; +} + +static int cxl_enable_interrupts(struct pcie_device *dev, + struct cxl_timeout *cxlt) +{ + if (!cxlt || !FIELD_GET(CXL_TIMEOUT_CAP_INTR_SUPP, cxlt->cap)) + return -ENXIO; + + return devm_request_threaded_irq(&dev->device, dev->irq, NULL, + cxl_timeout_thread, + IRQF_SHARED | IRQF_ONESHOT, "cxltdrv", + cxlt); +} + static bool cxl_validate_timeout_range(struct cxl_timeout *cxlt, u8 range) { u8 timeout_ranges = FIELD_GET(CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK, @@ -405,9 +542,28 @@ static int cxl_timeout_probe(struct pcie_device *dev) if (rc && !timeout_enabled) { pci_info(dev->port, "Failed to enable CXL.mem timeout and isolation.\n"); + return rc; } - return rc; + rc = cxl_enable_interrupts(dev, cxlt); + if (rc) { + pci_info(dev->port, + "Failed to enable CXL.mem timeout & isolation interrupts: %d\n", + rc); + } else { + pci_info(port, "enabled with IRQ %d\n", dev->irq); + } + + num_cxlt_devs++; + return 0; +} + +static void cxl_timeout_remove(struct pcie_device *dev) +{ + num_cxlt_devs--; + + if (!num_cxlt_devs) + destroy_workqueue(cxl_timeout_wq); } static struct pcie_port_service_driver cxltdriver = { @@ -416,6 +572,7 @@ static struct pcie_port_service_driver cxltdriver = { .service = PCIE_PORT_SERVICE_CXLT, .probe = cxl_timeout_probe, + .remove = cxl_timeout_remove, .driver = { .dev_groups = cxl_timeout_attribute_groups, }, @@ -423,6 +580,12 @@ static struct pcie_port_service_driver cxltdriver = { int __init pcie_cxlt_init(void) { + cxl_timeout_wq = alloc_ordered_workqueue("cxl_timeout", 0); + if (!cxl_timeout_wq) + return -ENOMEM; + + num_cxlt_devs = 0; + return pcie_port_service_register(&cxltdriver); } diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index f89e7366e986..c56c629cf563 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -10,6 +10,7 @@ #define _PORTDRV_H_ #include +#include /* Service Type */ #define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */