From patchwork Fri Feb 16 08:58:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 13559706 Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB6571B95D; Fri, 16 Feb 2024 08:58:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.28.160.31 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708073917; cv=none; b=QjcESJ9GvFtq9h1QwuyCODzJz1MyLKUO26X4twDixOTbZwJPdv8fkT4qDRgyWFPB0S0vdrcyeaMPY5SoDLPBi1LlU1AKDDZbp9zr4rXlPFu9z7lc4xvxsUvUUjRu3308rHESriz1Kn0+XhcDBOWiUUssPpzeNfMFR+QbzpdkzrE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708073917; c=relaxed/simple; bh=NcJCcfqi8ekicRsCx7lcKlZxsG+ADiWoan5/EkMI1NU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SXhUAfPp98vVdw/1QA/6CmOJe/PuJs6mtx40CnqDJ+oM3JUCQmKE996vcuKKJUhOf1ciZZwIKpIOtN9OLpMQJzAYAj22mt5FZZjI5QA8+Vq4uPCI4t+X2+SUNR2jMPBXejf93ZPja+Gv389hajSIWUjubncDmVBUc9A7fm5CYUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name; spf=pass smtp.mailfrom=xen0n.name; dkim=pass (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b=mO76rEvU; arc=none smtp.client-ip=115.28.160.31 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=xen0n.name Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="mO76rEvU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1708073910; bh=NcJCcfqi8ekicRsCx7lcKlZxsG+ADiWoan5/EkMI1NU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mO76rEvUz/01p234o2SAAs2to05wG3+DNg3sb00mT0knnk5q422OQL/bhqv+NbnSe I5Kd9N/o4VZ4UPQQ6BlhBp+z9TWsXqViVMaQxsB7VxmdZBpH04C5P9qfhtiHmz3rjk vBcMsrblEov56rBFalDCYfWXXLysYyfeeUvL7QvI= Received: from ld50.lan (unknown [IPv6:240e:388:8d00:6500:cda4:aa27:b0f6:1748]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 21BF760187; Fri, 16 Feb 2024 16:58:30 +0800 (CST) From: WANG Xuerui To: Paolo Bonzini , Huacai Chen Cc: Tianrui Zhao , Bibo Mao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, WANG Xuerui Subject: [PATCH for-6.8 v3 1/3] LoongArch: KVM: Fix input validation of _kvm_get_cpucfg and kvm_check_cpucfg Date: Fri, 16 Feb 2024 16:58:20 +0800 Message-ID: <20240216085822.3032984-2-kernel@xen0n.name> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216085822.3032984-1-kernel@xen0n.name> References: <20240216085822.3032984-1-kernel@xen0n.name> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: WANG Xuerui The range check for the CPUCFG ID is wrong (should have been a || instead of &&); it is conceptually simpler to just express the check as another case of the switch statement on the ID. As it turns out to be the case, the userland (currently only the QEMU/KVM target code) expects to set CPUCFG IDs 0 to 20 inclusive, but only CPUCFG2 values are being validated. Furthermore, the juggling of the temp return value is unnecessary, because it is semantically equivalent and more readable to just return at every switch case's end. This is done too to avoid potential bugs in the future related to the unwanted complexity. Also, the return value of _kvm_get_cpucfg is meant to be checked, but this was not done, so bad CPUCFG IDs wrongly fall back to the default case and 0 is incorrectly returned; check the return value to fix the UAPI behavior. While at it, also remove the redundant range check in kvm_check_cpucfg, because out-of-range CPUCFG IDs are already rejected by the -EINVAL as returned by _kvm_get_cpucfg. Fixes: db1ecca22edf ("LoongArch: KVM: Add LSX (128bit SIMD) support") Signed-off-by: WANG Xuerui --- arch/loongarch/kvm/vcpu.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index 27701991886d..56da0881fc94 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -300,11 +300,6 @@ static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val) static int _kvm_get_cpucfg(int id, u64 *v) { - int ret = 0; - - if (id < 0 && id >= KVM_MAX_CPUCFG_REGS) - return -EINVAL; - switch (id) { case 2: /* Return CPUCFG2 features which have been supported by KVM */ @@ -324,31 +319,33 @@ static int _kvm_get_cpucfg(int id, u64 *v) if (cpu_has_lasx) *v |= CPUCFG2_LASX; - break; + return 0; + case 0 ... 1: + case 3 ... KVM_MAX_CPUCFG_REGS - 1: + /* no restrictions on other CPUCFG IDs' values */ + *v = U64_MAX; + return 0; default: - ret = -EINVAL; - break; + return -EINVAL; } - return ret; } static int kvm_check_cpucfg(int id, u64 val) { - u64 mask; - int ret = 0; - - if (id < 0 && id >= KVM_MAX_CPUCFG_REGS) - return -EINVAL; + u64 mask = 0; + int ret; - if (_kvm_get_cpucfg(id, &mask)) + ret = _kvm_get_cpucfg(id, &mask); + if (ret) return ret; + if (val & ~mask) + /* Unsupported features should not be set */ + return -EINVAL; + switch (id) { case 2: /* CPUCFG2 features checking */ - if (val & ~mask) - /* The unsupported features should not be set */ - ret = -EINVAL; else if (!(val & CPUCFG2_LLFTP)) /* The LLFTP must be set, as guest must has a constant timer */ ret = -EINVAL; From patchwork Fri Feb 16 08:58:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 13559705 Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E9FD1B95A; Fri, 16 Feb 2024 08:58:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.28.160.31 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708073916; cv=none; b=oMgQsztKDh3pWAWo6IDH4sA+jMyE/pJ3uJYNE3cOCGTQHmbbs5ngYZz+BpL5V9AWLY3P/BAKOmt2FWMyZJ2VJKrRwtI9Em2LqdztiIMvKTsQ57XXG0gSvuzDLlCSOO8+/W5H9jt9EvgZ1+JB4t/xO1rj3MLaywEJ7qJ2677X+3Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708073916; c=relaxed/simple; bh=WzF4cixCPUKQp/NgbAjzvNdu2i9KtmYFWq3pDpAX4VY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Cbb4S3nfeRtD0kTYpsz6or5vK3OMZNpn3tF9VmBQnCpssXwNfJi+2dFRmWYztwKjaFwYq7gKbEpkwEot7yX237v8mzGlVLlP/uQN5kNFB0gWjobSnNwwYpZidtXm9J+4QZ63vzAbTlWIfXWnC1IS1bdbMsPIb4WxFFotBF3K/Ss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name; spf=pass smtp.mailfrom=xen0n.name; dkim=pass (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b=F9bXnQpg; arc=none smtp.client-ip=115.28.160.31 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=xen0n.name Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="F9bXnQpg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1708073911; bh=WzF4cixCPUKQp/NgbAjzvNdu2i9KtmYFWq3pDpAX4VY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F9bXnQpgwb2FtaeGfQJodNaSJrq9YUMnHgqBlv1a4o/9oaEQ+z9VH0GKcx9O2cwsK EBzBff4UhzVOI9FHYClUt+t7QFrJVSIxCwOLyQqcqfSlm9p06pl3ry2g05V49biFwg 1vVq1ctq3TmPlJBElaHaf8nu5dRM10xhtdyE3tKI= Received: from ld50.lan (unknown [IPv6:240e:388:8d00:6500:cda4:aa27:b0f6:1748]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 43BF8601C2; Fri, 16 Feb 2024 16:58:31 +0800 (CST) From: WANG Xuerui To: Paolo Bonzini , Huacai Chen Cc: Tianrui Zhao , Bibo Mao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, WANG Xuerui Subject: [PATCH for-6.8 v3 2/3] LoongArch: KVM: Rename _kvm_get_cpucfg to _kvm_get_cpucfg_mask Date: Fri, 16 Feb 2024 16:58:21 +0800 Message-ID: <20240216085822.3032984-3-kernel@xen0n.name> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216085822.3032984-1-kernel@xen0n.name> References: <20240216085822.3032984-1-kernel@xen0n.name> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: WANG Xuerui The function is not actually a getter of guest CPUCFG, but rather validation of the input CPUCFG ID plus information about the supported bit flags of that CPUCFG leaf. So rename it to avoid confusion. Signed-off-by: WANG Xuerui --- arch/loongarch/kvm/vcpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index 56da0881fc94..d86da3811bea 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -298,7 +298,7 @@ static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val) return ret; } -static int _kvm_get_cpucfg(int id, u64 *v) +static int _kvm_get_cpucfg_mask(int id, u64 *v) { switch (id) { case 2: @@ -335,7 +335,7 @@ static int kvm_check_cpucfg(int id, u64 val) u64 mask = 0; int ret; - ret = _kvm_get_cpucfg(id, &mask); + ret = _kvm_get_cpucfg_mask(id, &mask); if (ret) return ret; @@ -563,7 +563,7 @@ static int kvm_loongarch_get_cpucfg_attr(struct kvm_vcpu *vcpu, uint64_t val; uint64_t __user *uaddr = (uint64_t __user *)attr->addr; - ret = _kvm_get_cpucfg(attr->attr, &val); + ret = _kvm_get_cpucfg_mask(attr->attr, &val); if (ret) return ret; From patchwork Fri Feb 16 08:58:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 13559707 Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E9F81B953; Fri, 16 Feb 2024 08:58:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.28.160.31 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708073918; cv=none; b=ZX35v7tIBmobjVExTeOD2r/kOLpQYJlntLqEB4EDLD/WAEyDm258uzCz4UQGjU3SDdMpfQHrBVvyttu9ENLCr3dI89wsITqCcT1CgY/lTAk7oKQZw2+/BxsdWciUPlS96EjHDBEciCFh3xtS0VOcAv7NnZa9haY6xDa92wGUAQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708073918; c=relaxed/simple; bh=DtEFhAQEuWhcL2m4hc/lngoLoAxoNkQBWWwvuXD4w1w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bhO6LEFQ+GPRzTTXuKvaD36daOeo8pJHKkQ55AyagO7fuqo3tgADefSeOKEIEuAHim2ivfhA3PUg0lDiDcMM8Lit/9uNXlRKvx7waAKHbpRINOtk7ofUL7AwZccjLExevy4w0v6omPdWoyoe/uIIssBzmAFSyTKKAw3m/fn3QyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name; spf=pass smtp.mailfrom=xen0n.name; dkim=pass (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b=PUip6ZK8; arc=none smtp.client-ip=115.28.160.31 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=xen0n.name Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="PUip6ZK8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1708073912; bh=DtEFhAQEuWhcL2m4hc/lngoLoAxoNkQBWWwvuXD4w1w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PUip6ZK8USok+nSkBCfF6TN6ppP63mPKCpNJ/IxLhek+TKsh91DmC5X7OcsUq7EC8 JbuIfcen2SFLgSRZmMmrjkj9sdPUJdvHE337ASlx88hHjt5+v1e/vfQEYmx0XKLuWr JlDawwSjaaOOu7jwhyvAFKYSInK99C28SQNol3Do= Received: from ld50.lan (unknown [IPv6:240e:388:8d00:6500:cda4:aa27:b0f6:1748]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 6FCF0601C6; Fri, 16 Feb 2024 16:58:32 +0800 (CST) From: WANG Xuerui To: Paolo Bonzini , Huacai Chen Cc: Tianrui Zhao , Bibo Mao , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, WANG Xuerui Subject: [PATCH for-6.8 v3 3/3] LoongArch: KVM: Streamline kvm_check_cpucfg and improve comments Date: Fri, 16 Feb 2024 16:58:22 +0800 Message-ID: <20240216085822.3032984-4-kernel@xen0n.name> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216085822.3032984-1-kernel@xen0n.name> References: <20240216085822.3032984-1-kernel@xen0n.name> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: WANG Xuerui All the checks currently done in kvm_check_cpucfg can be realized with early returns, so just do that to avoid extra cognitive burden related to the return value handling. While at it, clean up comments of _kvm_get_cpucfg_mask and kvm_check_cpucfg, by removing comments that are merely restatement of the code nearby, and paraphrasing the rest so they read more natural for English speakers (that likely are not familiar with the actual Chinese-influenced grammar). No functional changes intended. Signed-off-by: WANG Xuerui --- arch/loongarch/kvm/vcpu.c | 44 +++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index d86da3811bea..a241db6d77a6 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -302,20 +302,16 @@ static int _kvm_get_cpucfg_mask(int id, u64 *v) { switch (id) { case 2: - /* Return CPUCFG2 features which have been supported by KVM */ + /* CPUCFG2 features unconditionally supported by KVM */ *v = CPUCFG2_FP | CPUCFG2_FPSP | CPUCFG2_FPDP | CPUCFG2_FPVERS | CPUCFG2_LLFTP | CPUCFG2_LLFTPREV | CPUCFG2_LAM; /* - * If LSX is supported by CPU, it is also supported by KVM, - * as we implement it. + * For the ISA extensions listed below, if one is supported + * by the host, then it is also supported by KVM. */ if (cpu_has_lsx) *v |= CPUCFG2_LSX; - /* - * if LASX is supported by CPU, it is also supported by KVM, - * as we implement it. - */ if (cpu_has_lasx) *v |= CPUCFG2_LASX; @@ -345,24 +341,26 @@ static int kvm_check_cpucfg(int id, u64 val) switch (id) { case 2: - /* CPUCFG2 features checking */ - else if (!(val & CPUCFG2_LLFTP)) - /* The LLFTP must be set, as guest must has a constant timer */ - ret = -EINVAL; - else if ((val & CPUCFG2_FP) && (!(val & CPUCFG2_FPSP) || !(val & CPUCFG2_FPDP))) - /* Single and double float point must both be set when enable FP */ - ret = -EINVAL; - else if ((val & CPUCFG2_LSX) && !(val & CPUCFG2_FP)) - /* FP should be set when enable LSX */ - ret = -EINVAL; - else if ((val & CPUCFG2_LASX) && !(val & CPUCFG2_LSX)) - /* LSX, FP should be set when enable LASX, and FP has been checked before. */ - ret = -EINVAL; - break; + if (!(val & CPUCFG2_LLFTP)) + /* Guests must have a constant timer */ + return -EINVAL; + if ((val & CPUCFG2_FP) && (!(val & CPUCFG2_FPSP) || !(val & CPUCFG2_FPDP))) + /* Single and double float point must both be set when FP is enabled */ + return -EINVAL; + if ((val & CPUCFG2_LSX) && !(val & CPUCFG2_FP)) + /* LSX architecturally implies FP but val does not satisfy that */ + return -EINVAL; + if ((val & CPUCFG2_LASX) && !(val & CPUCFG2_LSX)) + /* LASX architecturally implies LSX and FP but val does not satisfy that */ + return -EINVAL; + return 0; default: - break; + /* + * Values for the other CPUCFG IDs are not being further validated + * besides the mask check above. + */ + return 0; } - return ret; } static int kvm_get_one_reg(struct kvm_vcpu *vcpu,