From patchwork Fri Feb 16 11:03:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13559865 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E1058105 for ; Fri, 16 Feb 2024 11:03:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081438; cv=none; b=HQzr/rpudJitPlhjCopv2V5RnJXbKl+s8Kafs4WTOsum8+Nzb8fa6xJy8+OGVvYrsRPou7ZlEzvvmwLiB/3yQv/J4UKSwIQS7QCA6NrNCS+QPdGGwz4bs2dB3xTZ6u0F5+YQLbpQOfTI4q8Ww4TQU75rR6tY/+nWHd0HkquAUM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081438; c=relaxed/simple; bh=7rJgqOrASH1+9XrvkT4uAGIQBP7+drYr4P1tenEnLrU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EkG4I7GdY9HHas/e/N7LSwl/Sy+qehidqUKbBmyiAhdef88ruC0LElrsjBspmOQpp3m/slhwESaskWZJXX8F+5jStIKAJz59Ne/i1QNWTifNPiwCbsh4UqXRWNHgVazIG9yV6MvMmMLIcJwgFsRBIzQBjOFs17z+f0hYY8oGZ9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=vHbYtuH9; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vHbYtuH9" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-41241f64c6bso3883295e9.0 for ; Fri, 16 Feb 2024 03:03:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708081434; x=1708686234; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=M3p79qEtfp2ZjIJ+XTjXE+1hnr3OUwv786b7yeYiOaw=; b=vHbYtuH9FeDfiEFVS+hHfrp3/Mw1yXUwy33R1nb441voux464wagNysJABoEZS77bg kEBkzIGjGg41AV1OfnRVwAiaoRpOBn/uYUQR6+kVX2Si1CArrldRTEKVqpItaoMJPqjt uLsMfFbxe4TXnRxINcHX6UgOewWYzS+XNzLab1Jih53y9Z048mHHIZYD7tHow6cdQDLC QLKkydlBsTMJe2Z8FAzJthp3J3ZLh5f5qMP1PK0LmOmFRrztaVOJkBS9CCG7f0sF7Ods YQYnzIeWFUFM/p/C0bq646KtQw/u4j2In7BOTRBBn61V5VWzXqLjybjYPMRLVDsqT+4z G6eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708081434; x=1708686234; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M3p79qEtfp2ZjIJ+XTjXE+1hnr3OUwv786b7yeYiOaw=; b=ISaROKq2T7544aVjzu1S3CgCccD+1XZ5doPNvvTtwPN50l30OfzqH5A5Kdqg/4o9Bz tkhfFtQ2k+WwT+4uQzHax4rlziKgEnnvHt34ImhR19nKN7/ko5JC2PAjOWQZHEoR0UGb ERhja85lB42OqaO0W3XIRFT2a53MgDBFTOu81TOsfsNpTonvsv65OEdku+QU9feTVR27 smWEb7RKVnb9Svt8H3/Ej389EUNxjD+RBiPVnnomK5PS9AXO77E/GumfCbdzJAoK9xx2 sAX+gnTuCvsZsa/bjuR9cTEJ1wP2LMzHDdaF/PShaKX7UuwDmZVjznwzAzFYwARuPFCk pyXA== X-Gm-Message-State: AOJu0YypoSCFJP+hznucSfhdznHwTlOuJSQ+pFaLz+Uzqxc+jyYRRpbt 6v5YHfuXqLbFpom0V7U1/PAnjBCvx/lSyPG0qgPU2QA+IgcAwr3kg/zlZVColNA= X-Google-Smtp-Source: AGHT+IGBdNL8KeMG/RG+D3xrVj+pgMbj754F04oy4yi1RpZ6V0RRLQa/LsZkNh4S2dCingJr9VMEQQ== X-Received: by 2002:a05:600c:198f:b0:40f:ddc8:f804 with SMTP id t15-20020a05600c198f00b0040fddc8f804mr3001191wmq.17.1708081434548; Fri, 16 Feb 2024 03:03:54 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r2-20020a05600c35c200b004123b049f86sm1993174wmq.37.2024.02.16.03.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:03:54 -0800 (PST) From: Neil Armstrong Date: Fri, 16 Feb 2024 12:03:48 +0100 Subject: [PATCH v3 1/7] dt-bindings: display/msm/gmu: Document Adreno 750 GMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-topic-sm8650-gpu-v3-1-eb1f4b86d8d3@linaro.org> References: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> In-Reply-To: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Krzysztof Kozlowski , Neil Armstrong , Conor Dooley X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=852; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=7rJgqOrASH1+9XrvkT4uAGIQBP7+drYr4P1tenEnLrU=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlz0EVKmuMnelD+jPOCbPUzTsHxLthOrLTOHgLjSTa xPs9FyKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc9BFQAKCRB33NvayMhJ0UhfD/ oDuWdTNYoa15dCO3oA5HvDkWIEClqPqQZHvjaUyI02QCzOQZbQS7T7thHZbOFed88h2oi6jIbXWzgV KxWH7h8S+J7gQL4u5XD9bhu5Vcgt4wqA+DABnmw2rxLW3UrwVUkiPnnG95WLAheF81uTwWkWjFfgLX y1XQ7DMFEmSUgEubL7Q3WAyicXwmHy26yaqP/Et0eGr7vrRSPwLJuPkXp4JNSZ5itASbwbEItH8PVu SncEDTCd8qFewiyGcpenZiCcy/1KNythe/3892+ASMfBHrU3bfAxkHGusUoG75tHoxkfnA+XpjIx4j YbIjYFCotP4yelFiFH0ll2Jy4japCWmcRYNg9bjZK7cRqXUjuIT1CPtZYllK4RC8JWY5Kg4PxPNFZP kTHo3d3pIPQs1EfRodWBPD3BOM0Vir6ynTmSchUKvskzoG4RUtPx2iu44CEvZ1LWVoe4tj44QQnNtA bs+omtQ3D3SkHCQ/04RN+kLEZtBIXrSzdNOV4eLdvPN6yzDvXq0GpNVUIVAJeTrueIS1tDhmghfzLi F9PuzzDWB+BSPKDkfkYCK6dWICYAjdb02YJuuC1zuN5gBd8r+dBhyuBMRgOBFd2YjERvpVuX9GU5Fd SD5S4DilqNQ8hWaCpNhf6b3skPzzzmSq5FTK+/cGKy8Tn2KWa4l+597zsTdQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the Adreno 750 GMU found on the SM8650 platform. Reviewed-by: Konrad Dybcio Acked-by: Conor Dooley Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 4e1c25b42908..b3837368a260 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -224,6 +224,7 @@ allOf: enum: - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 + - qcom,adreno-gmu-750.1 then: properties: reg: From patchwork Fri Feb 16 11:03:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13559866 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A521058135 for ; Fri, 16 Feb 2024 11:03:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081440; cv=none; b=h2F6G4WTXQNnXqHF31PHItLh9a3IPvBRz8DDGTljH04ec2iUB9Gg/SME/34vQDFKi0NOox247jzj06YGPHoZUH4wZhvYvtsmNd+3JkBHst1Sd3s8/iZ/Pp4PtGgdF4PE/yZFvWf2/9R+Fommp22yUV5G//XmcJ6Vn1s22jne2ZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081440; c=relaxed/simple; bh=bKSwIMquL3ldQeZEbQDg4MhNZo4DD2FIt5FqyCH+Nw0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m6K2jvRofonByeL2ZbqgcC8kPYTIlwK0v/U4ehS7H7cbyCipDMRN8xBgkeTUPkKAvCja5fKm3JzEgcPZz2lWj9vflcjF21AcRfDCU9OBSnP3dYR16KbJ/pKdTwuK/zLHUkaH9INT2fnFYPyERP+lKQyZ8rc0qlW7CctUse40EWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=LUvD8H/0; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LUvD8H/0" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4122a8566e4so9758845e9.2 for ; Fri, 16 Feb 2024 03:03:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708081436; x=1708686236; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AWxHJkBPvh7dfzfYkfpsJVh1kKWdDbAwY9dahQR1fTQ=; b=LUvD8H/062QGeSIqWrLEQKcJ8x0YYWPAuNtYv8DRyIWdDUNCu21KIIr5Ok4l3xgQC3 XfxJyypeo/femfPrkFkYBwFQ1lXxNpIRnHtssNSAIUCEes7ASmN2P32dTarxXPS58yaT goCPXP4Z0aTbUiivvC9TX8pTv3tt2ZoTxWBgNXNwHJwSvyVJSK5XnZt4ekjzvSMbOKPB 3WOeCi4st5PTuhpV2p7BoH/BMmKmy76uDlYPXfohlPl5Pr0TKsz0OafuejXpzvazoQMt 5y5N+R+kOdE8AcY87UZzHwGknbJGdlLJfOhYVmTGCBca8AgBEPXYLhTjtAaGUWrvoKkl E2Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708081436; x=1708686236; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AWxHJkBPvh7dfzfYkfpsJVh1kKWdDbAwY9dahQR1fTQ=; b=PHeM86v3MD2IGRX2KUVZNH9J9zF1DAmQLgAO/aI46N1oTXnsKd6Y54B48Mah6Srh0G q+XgJFRHxSqQvI+FuBEJwy97QsgxWoner+0WeXo9QkuKDRp90KKj0rkPtpifKGJ4a9oS m7VRYOFmwAr4DYPIkskhaQ6p1j3S+jNmLbSr8WrRyrD2x7RLxnZKa1hvJThYcUawGZhQ kp/YYg6gHKpoOXEfnLUkdbBVgFRoQpPwLvBMvAIcAZBZ5mvtkIiKtGeXDIVYvs1vOLG+ 7YBRyUM+rD60YTe94K1qhaVc/K4cI1/pq9BGcbqWgYmMDbRTEMKCMduwUs17f5HH0f6o zmWw== X-Gm-Message-State: AOJu0YzCqeCWVmd4UwWSxmF1444TgRizimqXMLmdRLDslKFtdM7DMVJp UnBtjG1wN1Mhh7flf5/KCK4NGnHUYwNYtrRuJzSEeCzGjFvfxYfvIUFh2UtXYdY= X-Google-Smtp-Source: AGHT+IEibQ/Igt+OBTemdGFhAzHNU82OtjS01cgsM+Rhg5xCut32DRol5sAh63j4m2MM+BVPWD1pCA== X-Received: by 2002:a05:600c:1f89:b0:410:656c:d6d with SMTP id je9-20020a05600c1f8900b00410656c0d6dmr3225887wmb.18.1708081435852; Fri, 16 Feb 2024 03:03:55 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r2-20020a05600c35c200b004123b049f86sm1993174wmq.37.2024.02.16.03.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:03:55 -0800 (PST) From: Neil Armstrong Date: Fri, 16 Feb 2024 12:03:49 +0100 Subject: [PATCH v3 2/7] dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-topic-sm8650-gpu-v3-2-eb1f4b86d8d3@linaro.org> References: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> In-Reply-To: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1499; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=bKSwIMquL3ldQeZEbQDg4MhNZo4DD2FIt5FqyCH+Nw0=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlz0EVlZtPi8kLuM8GFD/opq53aRjm2jON3EvioLGw Pp2Pq6eJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc9BFQAKCRB33NvayMhJ0eJRD/ wMuGubcv5rl5NSZDd1jyjLXF66wVusziyc0Uj6bd6emX+Y5vX8RUWtEKTpyuOGzPk90izPMId0UFzd z9OcL+cud177MKnZ59fRzF2Ceas8GdkdI4TKwhvW2c9NzmPb/k/wDQHKVfRlfAPfoHCYJ+Yth/tDeM aAWpW2YY7srWsK2LY3uOFMHHVDRUvJgIPNZMxgu+m68UpkxK4R+r1nTOPgYD5DDhUXSts8P6PU1r5q bLhP5LCD/OzJQTCo5JOI/FVtFTIY9neCngCQnQQoBuu8g0NXlq2hVCtrH2Q8EK5nIMxony8Px1fJVp 1zhgF7KvBPOv8+ZE5yAs6qEeUaca/GMh6iaQ1eH5voudCNhtlCNllEiuUcH/eWexoqVO96PSjg5h/C 6UBqp7apKCKtQjCbUU1L1aXsdHaJWKL/elXvZGroLEZW8hXjWR+03aD0RwKN9/efIQjhReSzKyyFMb hxLlsCYOdsAmYwoY50+XOvmZZZ8+tfAM1RHCQx45llmq7HcYCg4aypDnMYpAJIOTKjJzI+LrVZIFlk 5+DQbwIN7Ux0ULMwAjTGy69f0f9Ta0cyOs9C3QoAeXrGH8QVgxAEJb3uWYCCfs6vds6LHDr6c1wJx9 GS0yygCa534u2Tc1Y2EdlZgGus1HblB7dz89fVvGMsFZlCXZ3I8lXguGKIYw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The if condition for the SM8[45]50 GPU SMMU is too large, add the other compatible strings to the condition to only allow the clocks for the GPU SMMU nodes. Fixes: 4fff78dc2490 ("dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU") Suggested-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a4042ae24770..38c48131e6e7 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -484,7 +484,12 @@ allOf: - if: properties: compatible: - const: qcom,sm8450-smmu-500 + items: + - const: qcom,sm8450-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: properties: clock-names: @@ -508,7 +513,11 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + items: + - const: qcom,sm8550-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 then: properties: clock-names: From patchwork Fri Feb 16 11:03:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13559867 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8BF158109 for ; Fri, 16 Feb 2024 11:03:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081441; cv=none; b=sQcR8anVm6lv28Mp3MYjSIPjtSUkmVykJDSMpC+CRNrMESQ5XDS07Qi6wpuIWeseu9GxS6/qArRcf5oYOBkcs6uYOZ0leA8PQtw2fgpLhOWjyGK16nmYRwxzsIsV4R4kiQLufxqeVnCgoqjuuJRqTsbb0a7mYlQ73hcDjBnfvZo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081441; c=relaxed/simple; bh=6iOcnqwhICNEx1Y6vAHfd+4RDSuZsONu8Es38mDvAfI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MQvpXe+QCDmpGn3uXVvM24ehyqJhbjPmh+eZaCKwu7cDRW+HDizPa+qKThuyvMpqHo43QwMww+lj+5a9Hs7fEj2vWENjKJR7ObROoh0nFBMfq6axD0G2tswgN+qMJd2M6uYDBBUq4QocoVGrXWcfnefYvvhW/9RxkPfGKIgv7R8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PGROFv7B; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PGROFv7B" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-41243d19ecaso3265765e9.3 for ; Fri, 16 Feb 2024 03:03:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708081437; x=1708686237; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=R8jQXdAWc83YqnRTlVrzU/De4ogxASBLVUqo6LYFo1E=; b=PGROFv7B3+9hX2yR/kn7V3V2d00OkJvGVNXBqj1H2UrOdf1iR2c3s1wy8NUnpIjYG6 7GX2IEC6ISQOdgHIWewPbQboQFFndIN0hJuZikuEKWZP4J0ZF+1aGG3uKNiPNvOuelMz CpAEWYq9K+GVx+3TkMCfn4/ooyMFOjYm+OKJOWs07hTVpnbdg2yP6ZpepYMEjiP/UWq4 Xf/ZRpPsuQPdb4Ok9uOf4y7jOnKZ8Hv7XgPnz9s5UjGzhN02lAV1fPSzx+bxa67PhlwU Cw0sAuB51qXwb5nzGiqxDi+Y5/SmmMr9JppGhhFVo1Z/OMFVFU+IaI1bYXIkXyaIxhIB A6DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708081437; x=1708686237; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R8jQXdAWc83YqnRTlVrzU/De4ogxASBLVUqo6LYFo1E=; b=cACyJuXlEi4cz/TcHHXCjhUh1nRaxgLu3kFmjXqCHhFua9s7FbcMxVL0qEBHl5SmES 7RIJ31QBcqWS5JtnSs91iQZqFY9CZxPLov4PzNS+0eRkITneDGTgzTu3JtBfyCKApJJi rbMY4e28E5jNUp1vOIEiG8ihApVldcfM0USWnuT/QfVGFgC6tiHue7NUPfNvxD+0DARx 1NCcjRqisKAoWELkKTtrj5L1FezXoET6y4yB17rug2OW6Hgl1QDl4AZr1Hw5KrGwtR+L foVhU3M4uYxRUJUjP+9mHdn7U/njVwHIT/ZMxO0enChk4tJvXFeEMN9EVlk7GNoxyjNv /n+A== X-Gm-Message-State: AOJu0YwvFc1y8SbXIeLcBiR6jcSdwiJ1TtayNSGq+a1snB2mO5nbcYTz haszsR/M8m5aQ4MHfEqyKQEQhxwx9/1bIaopw9mXDCGucT2rYmrdlnOwZKSdYjg= X-Google-Smtp-Source: AGHT+IFzz9cIIZTolTBZ+3VO8UaeUFnQ9Pv0L3AFv1B/Cdpl3JFGoVyw6+dpFPhP+R/v9EVwpKUaqw== X-Received: by 2002:a05:600c:4588:b0:411:e0f0:7a71 with SMTP id r8-20020a05600c458800b00411e0f07a71mr3644178wmo.33.1708081437101; Fri, 16 Feb 2024 03:03:57 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r2-20020a05600c35c200b004123b049f86sm1993174wmq.37.2024.02.16.03.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:03:56 -0800 (PST) From: Neil Armstrong Date: Fri, 16 Feb 2024 12:03:50 +0100 Subject: [PATCH v3 3/7] dt-bindings: arm-smmu: Document SM8650 GPU SMMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-topic-sm8650-gpu-v3-3-eb1f4b86d8d3@linaro.org> References: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> In-Reply-To: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1438; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=6iOcnqwhICNEx1Y6vAHfd+4RDSuZsONu8Es38mDvAfI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlz0EWWkZTzHjh7vkQKJ9hbFCgC/WFN7MzqEHvZaxY 8sk4gjyJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc9BFgAKCRB33NvayMhJ0RvZEA Crl2phZ1jwOzdI4NighnxwfVUB8UXbrQi2GpTJhQkO5V+FITUCJ7L2gAkxXOUPc+U3nyAuKEcjoltT J42WrBFVTMuOApzNr/jXoJE4o8uYVPLbeFsz29N8byY6FSUSQ5bCmyAY8d7KtE5YiHBTyIhAzy28XQ C/NCVlTbQFRELxV5xFOyCzFdR3KDEoUvx1CT3J1ZnUVYAaMzAT67hju0duvjxzZ41IHVS3nR6QD7bQ JJRe3hOYw1yIKfzbV/R7nJBEQCa4JGiBh+CMlapH9gpELgXgpI3vsS5ND1xxS++m1cnIA5enyKpha3 ESG8nJ252LOKDPSk2FyhoOQFKNaPfbdnk2btPGRdQHM0dtYuSZcJU+cajnDwavOFHJLhWLosoi7Gly ABqQ/Sf4KX7dFVCLGAOeoI2kC5AKjTMyN2vAObTttURE8LmYrg66hII1WQGAIQbRmtsZFvVs+m0EX5 3hbl11a6AEJ++2Q4+XIbpbiuSpqm6uOqLll92/+Be7DWhCfpq+V4mEeRCbRnLK08GSGvHhgohmf/sZ hcKBZ5qWJjc/SU/Bo3ishf62Vi3fDL6DOkFFjOcgfjW4Uvrc3llb31nEdfwdEYRBSfWizuMZ/4afOz 5xz5YmhER81YC4D06c9p+f4wX2tDWXp0WY7T3lUiu3qIbOGSUzRN9pV55bOQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the GPU SMMU found on the SM8650 platform. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 38c48131e6e7..740631782540 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -93,6 +93,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -514,7 +515,9 @@ allOf: properties: compatible: items: - - const: qcom,sm8550-smmu-500 + - enum: + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -553,7 +556,6 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 then: properties: From patchwork Fri Feb 16 11:03:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13559868 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 233FE58AA5 for ; Fri, 16 Feb 2024 11:03:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081441; cv=none; b=sb75Gra2IiewmeAaLalIDjv4BJgGBSCdNeXm1+7I0+PDpf2Xq3qfZK6njDkbGwEqTlgoqWgh9GLPWpESS0TAlAn7ATdrTvPmwfdysIA5k5A0nQVoDBDMqiNtd1/zd4WiATS3khcWRn51lBgGaDyKIpLKulwMqvRZpmAwb0RB5xc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081441; c=relaxed/simple; bh=B2VkxjrRCyr4kbi/Ih6iBNEXikEKFqg0faRJON0SE+g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FgTMfaiJrouTIO6WZRIETxt6VCK/FtfDXkPl4FgY9sXFjycyiJLn+30REgwd3EcOkt3oEpgdy35dKl2jBAKwdWxqc/YAAVQpRQRM97qR2UgAIV6+ORgrvlMct5bbt8+7bZVdA1LQpFzPbAmVuXtunAwK88ceraAGq4OPbGKRmhI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ZafwBbBC; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZafwBbBC" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-33b29b5ea96so922226f8f.0 for ; Fri, 16 Feb 2024 03:03:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708081438; x=1708686238; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5ygFt5WEvBpqUpx/ZfEWpp/27W6mJ4fXmmus9YC0aao=; b=ZafwBbBCKun+sMxiwhxBJE/xLZNpIW/w9WgF9AjbWEVUoSDZtfyQEKjbIQms8ye8Kf ineE1yy07UpC8e7oUydgIkZQ+612p7oenOGxAUuLondBOjohPUidyxSnI9FTAH0X+T0Q s+GI1quXFqDQNMioIR1z4wt5ptaHVuIqFK7Ny7yzmM5geFBPsSsusMZdz74ie2kLbss/ i9+kpAq1I9k/sFzXGMP+6ezV4EI6ewm3Yp94l9XORqyvZQdvpahSOR+WCykKZEg9VIDP NXCSR5Oq8ttv6raBoUMOqPvAW7p7BU/KsgMioAH37Rwj7WHbWLqTUzhgyie3uIepuoGg 83cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708081438; x=1708686238; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5ygFt5WEvBpqUpx/ZfEWpp/27W6mJ4fXmmus9YC0aao=; b=p22b+CdR3Wyfj3UtqSZkrJMuAsAG62fnu9zQ63x97B/Q57iD+Td6+R0YAfCQCYNyFU cjNWctFvnnQ8U/mMwBrn968t0MHZDNlYbFPt0L48paErQ1yJ/po39yjRtookhKwGA7Oh TXeo/kab/FmBApueLBDyz3q4xlNUaN/df7irPYktVX4MlbO2vwb9ad8pwvL2A4kII+q9 NnkjI5jBn3HBBAc07V4xbcVE2xyGpKNCgtnua5pfyEW0LTDfVBMc+kgjJuSGf8qAcggH fAzNhgRC6a4KmfltyCGhtyJAJE2xB3DNf7yzuAs9nw/ijxcWpVuDepMWM9mBIvc0mhTS 9fLg== X-Gm-Message-State: AOJu0Yx31DHDFelUCu1EhKO6iJQ5ZHP/NbbCK2ps3Ehtqwp3ouQ+zncE iJLNkz0W7E5dAmJwE6V/YG/bMls2opFAaCEWiqpmD57G6E2LqYvJSLfh7W/ssxQ= X-Google-Smtp-Source: AGHT+IEP3yiwcmF/JpddO+6q/ETD/OND3uScQVe3XPgZiAJ6sWVnA1HI/hScYmOVoLQdLn2nwzPXPA== X-Received: by 2002:adf:f9c6:0:b0:33a:d28c:222c with SMTP id w6-20020adff9c6000000b0033ad28c222cmr6833643wrr.11.1708081438346; Fri, 16 Feb 2024 03:03:58 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r2-20020a05600c35c200b004123b049f86sm1993174wmq.37.2024.02.16.03.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:03:57 -0800 (PST) From: Neil Armstrong Date: Fri, 16 Feb 2024 12:03:51 +0100 Subject: [PATCH v3 4/7] drm/msm/a6xx: Add missing regs for A750 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-topic-sm8650-gpu-v3-4-eb1f4b86d8d3@linaro.org> References: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> In-Reply-To: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1661; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=B2VkxjrRCyr4kbi/Ih6iBNEXikEKFqg0faRJON0SE+g=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlz0EWLv15OOt84prn+zzezyX4bsOfCsjeKZ0p7RdD 9nUyGtCJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc9BFgAKCRB33NvayMhJ0QcTEA CS2n5fqoqmYy9GHm6c4t2zLB5dDvZtmceau88GuV5umatO4fIxWOJ2NVqQz0VOvJbPEtS7xPrnA3o7 JAnZ6MUVuh2noUioy3nxLe7FSMkh/ZPU2LRXwfKk4dwEZ0jF+MsRF3ZmZ2Hfw+elII/+aN7mJqw52s W8eyo/MgX0PgcTEKTYrqq0QRtGygwFwY4l1nxJV0IOtMGboM1VDlRq/BxaiUIyjIxFcNjuzz+Xh3w+ Zr3SAVhHwGmNGYJmfIBHL8afHrOBGBloWT4rsKve+hzQ4NQIbt8MAblLGzeUTZSHpwwDPrIMBmO1rF vS+I1A12OTe4bEUDLXkmNEJPSs6NyxRsgGdOySmv3GJakcqJ+nbKW8sg1qR9tiNtCGmARKrnEnGPOL eEcxzYm8wlfIvLMMmxVQCKPv6tvaLo/Y0e5vo2YLoE8hsN1WTcOjSGnKCzxIXdLEeH+y+794HFWyc1 1Dt8glMqWYagPv+aiZhsjdO3gFo0NuovcYjgjuxnr3SQ1nOXsS9q8YT6l+/q4pr47E2lOXRgqNttWo BnMpIc+sS5r8L9x4jpkteunntBHt8+6nQZTtFHCt/zok5FjqaNK/DGrKOiWDRm9xWQtEsBff6yphGC 9JcXauVI9RI/gN52Cv42EbKaIhM09ziGBnkjek3NhTCJGhmUhay3i0Sj6n7A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Sync missing regs for A750 clock gating control related registers from Mesa a6xx.xml.h generated file. Those registers were added in the !27576 merge request [1]. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27576 Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..58877464692a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1725,6 +1725,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 +#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad + #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 @@ -1939,12 +1941,19 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d +#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e + +#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f + #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 +#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff From patchwork Fri Feb 16 11:03:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13559869 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F3E759176 for ; Fri, 16 Feb 2024 11:04:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081443; cv=none; b=l5xnxfh5Gki0WBUe8TU86xm3v3h/gOPNekVrC+5oggN1ZOW9peAztdkZ3UPH08hsmCCh72p+IJvZC5Yx0AJEJlVYYRFOvARVGNNaOwQHuOeNmAG9gScdhpuYO1pLYumX48OPNFRICQaPS2aIceSH3cDIZrSp4d84EB2Yr0k4BQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081443; c=relaxed/simple; bh=pFChiC7/A7TW5nPKOIPDG8EqGL5V1pHjmT0keqleygU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z+Od3gk+QtLRJjxfmxC9EtKHcn6e+M/Esg1Ay6udhrL9D1PJ3yTwoZrRCKY5uktcysmVj9hLdIO4m5hEVbfvtv2UiOrCt8rmDyypWIiM0BgsNbp0AiZzB1AHVqEVIjw4fijYRb2PRPqnBvvBlIyFP1Dei3ztswVrdU3BuuZ5y9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=qKgPLDQd; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qKgPLDQd" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-412393ea2a0so3949485e9.2 for ; Fri, 16 Feb 2024 03:04:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708081439; x=1708686239; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=L+fXQpNXys7p6pXfZBQpQvrvkqt8y/igppueslu3480=; b=qKgPLDQdtZmUpzmPjQFZtbbrjfUcHHPaNvHmwd/ucJFxGcts7H9MqRPuFIJw6xR60f dwcImeVyC0B/96MoUds2buFQDJKdhXgotOF2OI0GSv5HqoQEQq9lSRQqi6B3PKYnpEu8 JDaPmGhwff0pN7LLMMN3np4rq/D+LMxNT+PcN4S2LI+fkXXpgQ3LLyjmqhnU+cn1+/kW e0n+5v17weMjbYRJ34RPVol/fbDanJm7veXWZPr2kAgfWYX+K6g7piWnw+zKim1eHKwe VrbqGxFct4qFNgCunk3jcOwfTzizSKiaG6/qTCVgCig5HtKi+9ZkBQ3AOeuQBcVJYjFT tANg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708081439; x=1708686239; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L+fXQpNXys7p6pXfZBQpQvrvkqt8y/igppueslu3480=; b=V579/Bvq5zgNwiWF4OAaKcyai08NJ+hs98QNaDqy2ZKzJbOLZKYv41jyz+E/SHKem3 dL1ErVHRlY1vNjjHot/wJvktSmwBBDGOCSPoAgfLby9ahru7FtcV5giIN+h2c8XCjA8T vrRTVXcCxqdoczeX2BwRJ3dvAyQI0DaYovxfi37kKHbVNWVqDKx44pHCWU4qbDalc896 1F223GyziTMCcZTWSi0HFe8RXHrmnMaWb4S63BFEMjxBqgKF3c6DkjWNCKisd8ekXpZR vTcdke7bXCnpwDIwOCbJXqkTmRHqqVlptx/s29bAP8bxcGpg0x4fo4ApAK8qf1kQfQsd RNJw== X-Gm-Message-State: AOJu0YzW5HL8wLSnesuIzxDXCV1hAolaFekDyOiPi/Rrty+NeNFp16Zk rb9ohxerZcIQoZMy7Rtep2dfqmbhi8GEk+70YoadmLJ26PWNVl68CJcdkt1ioqM= X-Google-Smtp-Source: AGHT+IGGHfYk38OmLP6ZxKG4wt9HgniAWPkqDvqOxJ8sV5vVtrFa9vXdBrfZeDickxiaWibY/6XQ2w== X-Received: by 2002:a05:600c:3515:b0:412:17dd:a227 with SMTP id h21-20020a05600c351500b0041217dda227mr3578215wmq.15.1708081439551; Fri, 16 Feb 2024 03:03:59 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r2-20020a05600c35c200b004123b049f86sm1993174wmq.37.2024.02.16.03.03.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:03:59 -0800 (PST) From: Neil Armstrong Date: Fri, 16 Feb 2024 12:03:52 +0100 Subject: [PATCH v3 5/7] drm/msm: add support for A750 GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-topic-sm8650-gpu-v3-5-eb1f4b86d8d3@linaro.org> References: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> In-Reply-To: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5340; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=pFChiC7/A7TW5nPKOIPDG8EqGL5V1pHjmT0keqleygU=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlz0EWdFVecwUHFQbFbUD4McTTV0rxugK3zYhW9YDL 6tIc6YeJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc9BFgAKCRB33NvayMhJ0ULoD/ 9qGqDv/JN9u3v7z1bukxgAiCgTVdL7BRdF+3GLlHfDViaQCCC23UIgmRlCJDVFL/8ZGS5qWGOiJA9f gRvjGWhJRgc2TlF8CC9ZS/2dlTZHbeBNsVSGbexGNa+y1c5IAvplEb7F7B4jZEIZnHNxxxZa4EhhvO /K5Qv+KGoRBbHIZZo080D8bIa4mutec/uv5wYsIyj6x8gpnHSjMs3RYOgU4mOt0j9BPCB4TKBqvsdq SKOSdtjpAVe9uhbBwM7nQzpDpBfnCN8aK/ZHqpcHStLkAqgH+X/SJ5TAYLJYRK34LTX2qhMdXcOOm3 i1ehpvHQGKsMGCSZcDhJWTtUNp6TcHcCUHu3RaDOlioDC4AfBkZv5vIvMY/aU4CVtcwX4urL+eyuCh pPbacCzQipbL2RTNZthLiU+tHwu8EnLl3VQjUmeaWpPAQWJ1IiBesYUY4gYInTYNr5Fr6FkeX/xOss R20DYUir14nB1numCQF40b5xBnTyZ6lQGzjVsf/HRANbaV/+yfu9ohRNqL3mqexALk/O5yRiVx7EWt nLUyTyBBgIaXES239C/i45bu7HEElFxk+W1fXxPVYu7vpwxWX8DTINPObpG7E98Qfs6xXB8Ycx0fvw SmmLypJVBDyn3ySzwt8sTlA5XAEts3rXYaZ5qi5b4GbGmsHR5WfXgTaUEaVg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 ++++++++-- 4 files changed, 49 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 8c4900444b2c..325881d8ff08 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -842,6 +842,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) */ if (adreno_is_a740(adreno_gpu)) chipid_min = 2; + else if (adreno_is_a750(adreno_gpu)) + chipid_min = 9; else return -EINVAL; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..475b601a48ee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -961,7 +961,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu))) return; if (adreno_is_a630(adreno_gpu)) @@ -982,6 +982,25 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) state ? 0x5555 : 0); } + if (!adreno_gpu->info->hwcg) { + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); + gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); + + if (state) { + gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); + + if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, + val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { + dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); + return; + } + + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); + } + + return; + } + val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); /* Don't re-program the registers if they are already correct */ @@ -1239,7 +1258,9 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) count = ARRAY_SIZE(a660_protect); count_max = 48; BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) { + } else if (adreno_is_a730(adreno_gpu) || + adreno_is_a740(adreno_gpu) || + adreno_is_a750(adreno_gpu)) { regs = a730_protect; count = ARRAY_SIZE(a730_protect); count_max = 48; @@ -2880,7 +2901,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || - config->info->family == ADRENO_7XX_GEN2; + config->info->family == ADRENO_7XX_GEN2 || + config->info->family == ADRENO_7XX_GEN3; a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..e2582c91d7e7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -522,6 +522,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "gen70900_zap.mbn", + .address_space_size = SZ_16G, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..9e9415df2cea 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -48,6 +48,7 @@ enum adreno_family { ADRENO_6XX_GEN4, /* a660 family */ ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ + ADRENO_7XX_GEN3, /* a750 family */ }; #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -423,12 +424,17 @@ static inline int adreno_is_a740(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x43050a01; } -/* Placeholder to make future diffs smaller */ +static inline int adreno_is_a750(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x43051401; +} + static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return gpu->info->family == ADRENO_7XX_GEN2; + return gpu->info->family == ADRENO_7XX_GEN2 || + gpu->info->family == ADRENO_7XX_GEN3; } static inline int adreno_is_a7xx(struct adreno_gpu *gpu) From patchwork Fri Feb 16 11:03:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13559870 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEFBE5A10A for ; Fri, 16 Feb 2024 11:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081444; cv=none; b=iRlO6cX9g1sTW34PA7v80JUpND8M84sEpRt+OSENxxpB3AHR3zWcClKXfhcR2/ZO+mWnX5azsABGJbqamJq8kAvw2yE6stehCIkvpI3Z3rBjI29PfC7E6iIS2ZIEv21R9f31QCfsOtzzB+Q85sTvSn5EdCdyjXjFItfGPLsAKao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081444; c=relaxed/simple; bh=YnfJMxPEw+Crbp0x61Gr7hpcpYLyCY6opDQJsdz5YLA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=orFR/j554kVpXQ8XWyfhR1yDlaxCtugI7kzfOWPv6DbeUvukRkPgX41RA8cZ53DmTslX4iS4b/6j/F1BRBeKEVO3RgpydDU5UiV45BnzDwNbwskIIEGW/vX/XYcg0fZExZnRi9sQ5i+Pc4ggdYskikdJO5OdYBI+dGpgcidpp7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=oH5WTlgx; arc=none smtp.client-ip=209.85.167.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oH5WTlgx" Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-51197ca63f5so814743e87.1 for ; Fri, 16 Feb 2024 03:04:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708081441; x=1708686241; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eoTug8oI3rc0EGfqabXi49TIa0elLz1yO0hJ7mVAsJQ=; b=oH5WTlgx5e72O57qJqV/awMRLJSqFBGQRKxLsY8KSZF4CsiX65Psr5hc9x9SPMsjYv zNA4yBBP3O/Xk93ejWuSBcRR4tXe3HqxJ2qouY+7r0Co92EmpW1QVRU/bIUtDjQ24iRB fVDnRPVWik5yATKt3GmZPk4OliO9BBVn1WKAA8Pv2aJexdgv7fWn9L+4uFb1iXl2p2gq rE9x5YgkC5MRWVAGce3+EDLuBf2f0LF+ODgLTQR9C3qsrNPmFk6BsaPA7o1+KDBWKbjQ 46LEyjiOOEXPLT1nK2gAjci7Kgjfi6R91cRzZQADVVXZi24cWOFr0Dc3lRokKPee+Px0 AnhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708081441; x=1708686241; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eoTug8oI3rc0EGfqabXi49TIa0elLz1yO0hJ7mVAsJQ=; b=gyx9s6U+mn8EYWU2zlx2aCS/qYQbFYcJLoa1hqBkBqZPOei7I9Rddo5kiXMwdf4rhD eEsjv3PG/W/mQ9dqXdF73GstLGkZv/KiKw1NlYh4Kl+OlDMKeLIk8Pm+3FLDRG9DHstb jQraktPTDwgswD3LYi7zNtmV79AoHab1jua+39I+OrhApaOVZH+UMUMMue9I8YwWuRAn b6u7DSmVdugNFqKQcbH2JbV90Mqpokt+8k7DFU0x/obeDLEJxSxBLplEbxjZ7xXLktoh WpJZt4sShip9NQGruPzeEghw/2HpKLPkqPygRXvdI/C4OkW5500MAlGsPAor8htDhLmz lpJw== X-Gm-Message-State: AOJu0YwFxKbgeVnK+V4cm5hrJtRsMoud3sU20cUu9rbvM+EoD78K1J0M L0RkxJlEcjgXz0emQL6zNOQQyR4RjH3JBeJaHdORfZQaHaJCOdo1MQ2avBFWZNM= X-Google-Smtp-Source: AGHT+IGgy6ifdMfZjZdNLwnOMo0WQysyGJ5gI0bzwsoEE/gUN5DhE5K8JJiVngICStweqFy9QnhFmQ== X-Received: by 2002:a19:7707:0:b0:511:3283:e3af with SMTP id s7-20020a197707000000b005113283e3afmr3198713lfc.27.1708081440926; Fri, 16 Feb 2024 03:04:00 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r2-20020a05600c35c200b004123b049f86sm1993174wmq.37.2024.02.16.03.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:04:00 -0800 (PST) From: Neil Armstrong Date: Fri, 16 Feb 2024 12:03:53 +0100 Subject: [PATCH v3 6/7] arm64: dts: qcom: sm8650: add GPU nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-topic-sm8650-gpu-v3-6-eb1f4b86d8d3@linaro.org> References: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> In-Reply-To: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5727; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=YnfJMxPEw+Crbp0x61Gr7hpcpYLyCY6opDQJsdz5YLA=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlz0EXwDY7Yg7aqci7SJjR9nKSoD54wIwV2Vb+CdAy SVfXnDKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc9BFwAKCRB33NvayMhJ0fq1D/ 0eVUzJBgVh7s/6KY8RP210qpWDN8Vcdh5LSPux3vDXKfQzkirc0B1hlpVU6oWrO9BCE6IFuvisnKAH r7t1p9kHhbErqX9yBsMFoRm+YCOs2lEQtiN7ur+M8r5rbkvy6vycF0UTn1lsu1F6VsK0ADiwqbuaRf 9EmUNyMt1WkvYjQXV0zjBy6GEMj+IW94G6/Y48MHOBzOhcAQq7KnO5I4shutgepEzmFljLC4ZS5BJ8 YO0Me3cggxTS1ltUSANtNpKLHzj4pYcP4gl29/lMj1HPE5MBCkzO9FsZNNexuFQ+dnxsw+Sfm5t7YB 4mLfP/iWaZAHUdo96idrEd4kP/I7oLMA8tB5c2lIJrpvfqQH5vkVBRbbSCRm6W2RehqYriSlemWc1F tYLh8KvL7zWcGxv6VKSH6XT4bPbOfveXv2y/8dKICBEUfGWX+7rNE80o6xraWpAe8B7ToejmrbYPZD qDY5OwNZq8FR+20G8AlHhlWI0WNcIAMtQ17vB8IiLKf4WVi9NynXpoLFV2FjhX/Zp5dcbYB9iuMSt/ jrqLVuTVY/4G7CzBsRs+bF0rKOF1rn60XXS8pZxWy/dQLW6HO10FMeZfKjgCqzTKRvCS9wTSJ5xNPW sBQKAZpB83oGAHXe6xC2l/GViUFra/G2P6u4o7wYIRHIRyxUEFbTgJuvI50A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 62e6ae93a9a8..27dcef27b6ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2589,6 +2589,128 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = ; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = ; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + }; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2602,6 +2724,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; From patchwork Fri Feb 16 11:03:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13559871 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BC3E604DD for ; Fri, 16 Feb 2024 11:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081446; cv=none; b=jlUxKliAQr0m9lox0rHrDGNgN7yu1xD3tTvwxzkNj/JoYk/RIkGkR+KrniJHuCpc49PByzyKEnx5t0mtbrtA/EgeBD4gAbJxr622yD/1rbFPveGA58niSbOznOEz2Pu6RiP3fRF8NSYxRpIk1MaO9TeaGnjam4gYMZwQZ9fdXs4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708081446; c=relaxed/simple; bh=eK619A8Ja/rJOcWssIzBbWM6D0kuHt0880KvRuYuMKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J6Q4TCjw1jixuOyXPYvZVjdmOY8fOObG9zGXsNgze/LZz5FeWms9duuWedM6KOzY93dIag2tHwc+UQJLrpmjqN4RYI5lGLhf379LhLep3dmbK9iKXXrl5vGsB03iBpM9QRGKUC/Yl5f9fZW40TwtIufg9zNJyoD/K0K/Ntub6B8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GttWpwoT; arc=none smtp.client-ip=209.85.167.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GttWpwoT" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-5128d914604so1412503e87.3 for ; Fri, 16 Feb 2024 03:04:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708081442; x=1708686242; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=M4VUVivuxhBItwCnLx0xGdHQH3tLZmkPnVy151EVhso=; b=GttWpwoTOWDDgSFRm6sfSiz0x05xC9e+Wo3/W/bXfyR3UV/2eX21vbeCxrrL2zrYRf x4z3I7egPIhR0sSfmFDRtpT5BgzUysVDDQQoiCXjH8YHRdFv/njEMMEmR6VO2lgP2qV3 sYvk5neM2DBlv14F+gN0lcAJRoIDSqEQODAFp/SW5SUrqy6NEOe43y2xV7OLteVeTVxJ 1l5U/1pgMJh4ClBbTFwiOHS7ztBMjZDycSluiTLa4LjyapF1drrscRQkoev+bSud5FNv yTl/J0wzGyEE8z7eidLXa0eTRRyF5SUGsR20HoKN28RKX0H8vnAliu5UF2BT3Q26u+NL 3Rsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708081442; x=1708686242; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M4VUVivuxhBItwCnLx0xGdHQH3tLZmkPnVy151EVhso=; b=pUxP66EgD1AP9uLeMmBWq5G3Mqm3sPv+hHwtuGXktP/7mQ5K/sbE/ETTQb24qWU94f ylFR5x5vYkWEXMhIMVO4Pnf4ZpknXvCeAD2mfod0BTFVmFm4J5lSROGHtkzSDk+3vn1X yYeHy52TCqLTz5Mt7hEA/jWWOL0dmIXph2LbhfDsJuMCJ+FZXLM7YUFO6h9j8PhGeC8c ZTILBeYwPU579ZQszv8Z6zo6UlG+HzQXjl6zRVSiV4zFCnzk9IijBXj7dEvl/Ee4WUGo mpYzqRPU9WsJSXa+lMM2/kOkBWu/muybeFaRebt76AJ+NS/k2zRv7ItNIXxJMeBWrcFX crzQ== X-Gm-Message-State: AOJu0YyACFoHfe4liFdfFE9MW2ouv/gT7FQm7bOtmVyHHlA9GSZh+JDo kEOKOgCo/8tTaCzYAEzrjIAZwEAGyh5vHE6VVcUpgK48JTHfBlScYFiW0Z8M4wA= X-Google-Smtp-Source: AGHT+IHxB3djXOGZfctfeVjRtqPgl9AKJgisKXW/R9yWRkrHNQlUHO3cV2qVMp5FEgY5CP4mPAbs/A== X-Received: by 2002:a19:5e17:0:b0:511:ac7d:97ea with SMTP id s23-20020a195e17000000b00511ac7d97eamr3150124lfb.64.1708081442471; Fri, 16 Feb 2024 03:04:02 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r2-20020a05600c35c200b004123b049f86sm1993174wmq.37.2024.02.16.03.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:04:01 -0800 (PST) From: Neil Armstrong Date: Fri, 16 Feb 2024 12:03:54 +0100 Subject: [PATCH v3 7/7] arm64: dts: qcom: sm8650-qrd: enable GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-topic-sm8650-gpu-v3-7-eb1f4b86d8d3@linaro.org> References: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> In-Reply-To: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=771; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=eK619A8Ja/rJOcWssIzBbWM6D0kuHt0880KvRuYuMKM=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlz0EXgNVUxVocIorRrq0+P4C1WxED54Xsx9AbKddq wgYEbneJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZc9BFwAKCRB33NvayMhJ0YOAD/ 9ZA0e00w5hdxUVtWcA6R6L8Sgxzl3TGs4M3N2DO257wMbYrseQYYIgISUaSYCbllijwpWn1MBoP8Qd kzme7tsEGbUVLG9O6BJPJbjX09Zv7bXFZVw9RycdKfud7WcBFwmzeqpRbC7QwjLciEp8zDR7znYBqV haPQJktNh0x/DL7qpS5EQ3VaKKLL1pQiTBjBNCKPsGaDS+Cqkam4OmvgE7b/l3cLSdMZrIrLxwMejY uhvkCzU0vPLhb8Jq9mCQ1qtn08KIiyMEcwTKtgmByA1HeGgDfqiaM2g1otALWizNT7rgK4UawovqPd FDd4LqZFqfELA5MCRnccpH6cBKOpygQPnTvNLUDHVnQOmHFYw+Z2mtWZZ1r+OoS8i5Np0BsS8/lVIh eG2fNRzvP2bMWyMNFmvFBaJ7iFLOF1+Hg5rf0p1cmhL0i44NaMJUTU55ETQG07vaI576kx8EySb38r FSYOk1qFs39QNdP0Im4SfbF0JmSDnmfiu8/yTBNkkAjm8hPNqZIk30Ff8E79573ZtHkrk3QT1X02bT S8ktDMv0EQkAkRe5UTAoxMeDd9LRLPU/H1jCPotM9oPddQn5Tu+Eta6m3nz2eAHYhymFLrbRehF+oy /bZ3CeZECCad5xmda0Mz37zofKY/CPQaeae/Pv0QG6vSxXdAsaFD4yNhkLaA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add path of the GPU firmware for the SM8650-QRD board Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..dc91f0bf4b8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -766,6 +766,14 @@ &ipa { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21";