From patchwork Mon Feb 19 13:35:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13562710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C14C8C48BC3 for ; Mon, 19 Feb 2024 13:36:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B27F410E380; Mon, 19 Feb 2024 13:36:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="J/r9hzB7"; dkim-atps=neutral Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FB1D10E2EB for ; Mon, 19 Feb 2024 13:36:06 +0000 (UTC) Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-563c595f968so4984208a12.0 for ; Mon, 19 Feb 2024 05:36:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708349764; x=1708954564; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Vm4+HsWSLi5Bqiq8guveLonPTq6IX1sdSS8MIp6iya8=; b=J/r9hzB7MxMI+Am8GdZ85xwn5PoN7AyUQ8SN63tftVaOa0MYKwp63BF4KlITKszABs pZHvfh12vEkk/CjM0rvPT9RoGmIk5thzlfC+dKIJHvA4pcAnxs6U4UxDuXI0V7I/dM6l w1LpbVj7Fj6qeT8OCTQKWEegzGdUqHA2Dc8+3zy7XeQ0ZnZi1ikJXMlmPOsWaG+spiBG 0snCTyLGRTVx4wgehYPK8VFPxOlXFuCTcS0UHgwz0+PFhLwbnwPNvnqG3AjJUHOTsdqh 9vICSLejyWGxgJ/bZovr2zJ8dAgcneJ8YBCKtDe2P/ynhsMuf/GbSDZYIIr0tq9A6zJA jq5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708349764; x=1708954564; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vm4+HsWSLi5Bqiq8guveLonPTq6IX1sdSS8MIp6iya8=; b=gOyryyZmpWizPoltCi7la7WTMWyENIe7ye3X70o5gGIGAj7wUGRcIGHEBX0cOWB7HP DODudw75PHfLknfC60lmDMxU3MhaB336w0YpFaCQpkE8W4ORrucuu63E2dW6PS6QUomu Qi4726iSOfHEMkUpIsnPtpz5hcvETDIvDBdooY4eo0dG4LZv7807Ts0Ac79JPrpv1716 e0gXTze2yFTfK4PMNSZfWe/7EDWTFaqCPgBFcmrXyVwdf1WIfyqhheEyWEH7sWQq7HVz zjWgR9PfH7MTVF4wzrnMXY56WJP33k0rGbVEjTpmpaHNe0112hcdya5NpK41NaRIwHQv xCdg== X-Forwarded-Encrypted: i=1; AJvYcCVcN1X8J7epeeVPjqklzVxv+B2rzfN7a51bksOB2feouCVSIkh7ViCP2RefIHh86W3v69c+AHxCnyCo4b5uU5PT5u1Z/KY2HA/yRIyln3eP X-Gm-Message-State: AOJu0Yw+oOU4TLoWKLRAPDd2qvGYOMoVHCMndNiJvP7A8AQqI54UTlOs LYBfJDWXxO9/yKJ7Gr/h3mzkFDQWQvjYXzfjmvydqfYfL4nLn6RybPnRnMdxxd8= X-Google-Smtp-Source: AGHT+IHV7bK4ehHh9S5n4E8JdbICBeyKCog4TBxeQJc7jVSQ6sgYL2AGYMpXguUVOZv4iBTFSYicGw== X-Received: by 2002:aa7:d959:0:b0:564:3191:f407 with SMTP id l25-20020aa7d959000000b005643191f407mr4013903eds.12.1708349764412; Mon, 19 Feb 2024 05:36:04 -0800 (PST) Received: from [10.167.154.1] (078088045141.garwolin.vectranet.pl. [78.88.45.141]) by smtp.gmail.com with ESMTPSA id q29-20020a50cc9d000000b00563a3ff30basm2900168edi.59.2024.02.19.05.36.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 05:36:04 -0800 (PST) From: Konrad Dybcio Date: Mon, 19 Feb 2024 14:35:46 +0100 Subject: [PATCH 1/8] dt-bindings: arm-smmu: Add QCM2290 GPU SMMU MIME-Version: 1.0 Message-Id: <20240219-topic-rb1_gpu-v1-1-d260fa854707@linaro.org> References: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708349759; l=1444; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=iLSWFU0PEB/wfyF1Nv5EVeYr19/e5DAihIhWgNDJAow=; b=71RQnNARetoCSKqpzfQqO6Lapq/qBgUH5HXLBQdA6ZcDXcoSaL+2ynFTnCmi9jFSY8Q7b8KzZ O5iL+UfQEyvAPDXeCzVYV8yaVrWJofN/Mv+M8WmxZgIBOjFSCjpHxRD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The GPU SMMU on QCM2290 nicely fits into the description we already have for SM61[12]5. Add it. Signed-off-by: Konrad Dybcio Acked-by: Rob Herring --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a4042ae24770..4a8d4022aebc 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -83,6 +83,7 @@ properties: - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" items: - enum: + - qcom,qcm2290-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8280xp-smmu-500 @@ -462,6 +463,7 @@ allOf: compatible: items: - enum: + - qcom,qcm2290-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - const: qcom,adreno-smmu @@ -534,7 +536,6 @@ allOf: - cavium,smmu-v2 - marvell,ap806-smmu-500 - nvidia,smmu-500 - - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 From patchwork Mon Feb 19 13:35:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13562709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAC0FC48BF8 for ; Mon, 19 Feb 2024 13:36:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E89410E313; Mon, 19 Feb 2024 13:36:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="a/nBPMZK"; dkim-atps=neutral Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F30810E3DD for ; Mon, 19 Feb 2024 13:36:09 +0000 (UTC) Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-563fe793e1cso3561448a12.3 for ; Mon, 19 Feb 2024 05:36:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708349767; x=1708954567; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EDFtd1C6W8+z/D4oBojXzEo0MFOHKoG2NOfGOeLFv6c=; b=a/nBPMZKvMXElPehRP9W3mUofFCxu3aK+ZWMo4pQgoT1gvqtFhtWJkImjrgtxyBtMI 9VnUiKRt3LR0VS6YqE1ux2UkVAPs7dNwpf0bnJX57IlN76Vn5pu82rEzD58GrbMx3SqX OVYxN4Ure7mhOPfZnG0FlI5cGvafjjh+i3ELs4fuGN3n5km30PtrhF8JL0xB2458Ba+z F9QqtyzprhxX+tMRKVpXyEFAvEbP55o6hBMVtGOYKoumFlWD3EoPApwoSuFFdOTfrQuz p419Qtc+K0LcHJuOZ12Tq/wUNGU5HPZujfzDYj1s0QFIpz8HQTwoGDsB3V5U+B1j4xql SMAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708349767; x=1708954567; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EDFtd1C6W8+z/D4oBojXzEo0MFOHKoG2NOfGOeLFv6c=; b=CmkutSVNpo84bWqwPP4jKADxw6w6TwMN/3ft9i6M4SmEiS1XjzY7INFUAv+bGhjUtV nh3pyvZEXCO7aLY5EG0eBbGx9j77G1TnpTfw3uWU5/e2E3OthLvVb6f7ZglrxBqUb+5L CzLkMthDTE9xZWby3fcD8e5eDx4Aov6CMV2zfxnlmIVbE75sI0k34FnHm6YTrV4XRz/Y oNKEgkWWOFOfc/S+A6vsyLJmdMRzXl8M9fuOp6xuIorWYzOGQPiZcIu/Ih648MaUob+W igDsmy8LGpq/HZCOV5Bt0bbDNcnyc4iGNsQbuHxbV9OjzMfQKyz/l/ksfTGR4EEZwtOe msBg== X-Forwarded-Encrypted: i=1; AJvYcCWx2vQ8ULjaJOof9ZqNDkWEgfqW5GTMfchMyHNEBXyAMLxWNFPCuLQtshrYdujNlAOv1fnOTENa0qAbMAayTUEVS6gD3I6HQMXgQ73jVboQ X-Gm-Message-State: AOJu0Yx1SsJsC9ikbAyfSrWyCE0K9bNn6aM24i0H8Y2TFeC1tPVQzXRL +Pk174rYkgREccAzAvDs4D/GLNFiWN41UA0kIk/pF4+35L8oHRehFTU2wbryq+M= X-Google-Smtp-Source: AGHT+IHcY/jmN1CahbTZpalD29/Injnjyxx742wPBMQHK911Hmm+agbpDEvGFC5DMtm4072JH0z4Dg== X-Received: by 2002:aa7:d382:0:b0:564:69be:6e86 with SMTP id x2-20020aa7d382000000b0056469be6e86mr2364504edq.0.1708349767419; Mon, 19 Feb 2024 05:36:07 -0800 (PST) Received: from [10.167.154.1] (078088045141.garwolin.vectranet.pl. [78.88.45.141]) by smtp.gmail.com with ESMTPSA id q29-20020a50cc9d000000b00563a3ff30basm2900168edi.59.2024.02.19.05.36.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 05:36:07 -0800 (PST) From: Konrad Dybcio Date: Mon, 19 Feb 2024 14:35:47 +0100 Subject: [PATCH 2/8] dt-bindings: clock: Add Qcom QCM2290 GPUCC MIME-Version: 1.0 Message-Id: <20240219-topic-rb1_gpu-v1-2-d260fa854707@linaro.org> References: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708349759; l=3746; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=KHcmvINhJktJpppGgwULcqvLybPcSbgdTRhruWN1EGg=; b=NaBvuZXGfNqiXM+yEApolRkCjYx+y/6MOaCnl4/saDR6RxS+H19AcURQQ3xL9s1DIJWPv3piV 7kE09+GRuIVBIzkVJIDvLMhuz1i4zyjDATa4Q78cYVazSmKNUX6FuQw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's QCM2290 SoCs. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,qcm2290-gpucc.yaml | 76 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,qcm2290-gpucc.h | 32 +++++++++ 2 files changed, 108 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml new file mode 100644 index 000000000000..a16cb7e87e26 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCM2290 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,qcm2290-gpucc.h + +properties: + compatible: + - const: qcom,qcm2290-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: AHB interface clock, + - description: SoC CXO clock + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,qcm2290-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd QCM2290_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcm2290-gpucc.h b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h new file mode 100644 index 000000000000..7c76dd05278f --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_GFX3D_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GFX3D_CLK 8 +#define GPU_CC_GX_GFX3D_CLK_SRC 9 +#define GPU_CC_PLL0 10 +#define GPU_CC_SLEEP_CLK 11 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Mon Feb 19 13:35:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13562712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7823C48BC3 for ; Mon, 19 Feb 2024 13:36:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D231E10E397; Mon, 19 Feb 2024 13:36:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="oRz59Syr"; dkim-atps=neutral Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3E4610E3B2 for ; Mon, 19 Feb 2024 13:36:11 +0000 (UTC) Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-564372fb762so2424371a12.0 for ; Mon, 19 Feb 2024 05:36:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708349770; x=1708954570; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7M1e7EmpHdXumiDD0LMXKq+SIP28LzfgFkNX1b4YVQE=; b=oRz59SyrD3yA6/61RE3EUh/wn46+M+TPwua90dnZQSAIvCQY9hYEJy+svYqdJPS68h 8mAjZKY1Md9jw0+56N9wanlLmbZWRFS/vdFbgrwn0kYKZf+9Lrvc4kiK+vy3/l9GzCi7 DwfJOLDOIJhkC3dq7dOdzPYUvebj9qUfly/HI15BYER2AsTIiQ8duvKUeD1pHAgly+1A KmBqvVMA4+reMR3RCSAuqBILurAeGxfmX1RaIwn44zYQA3BcAgU2yL8qH+DR9Oe7s9vW 4kyd+8TfSdY9/GO2zOX4oeNOKr8oFzF0pDa0YuGCuFwpOTF/+4qr66fnXeQB0Ns9S6x/ SeBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708349770; x=1708954570; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7M1e7EmpHdXumiDD0LMXKq+SIP28LzfgFkNX1b4YVQE=; b=k9iPdVo0cr4SJIyYsbezIjJJ4GxhQ4VjOUDm0v3m6Sus1trefZa5qCeIDNGciqcyry MV6bcAeE7WUQiK9EU0QzaSqhk17/LaMo5DTdwyR7EEk4nFeCofQyjyxoEk89IUzavfMu mH0xyXZ3L+rkEr0xwXFDDAKN77sYuPapY6N54zmn8R26d7aYf3svydya9H5bOQiznIe+ aRIDtdy4eG23S62GkgH9hFS1htKKcoFv/eGDkZbIptx5lvBSGKi57KPEvnjWbmYxkFYL J2c2jcDyaxqOTAHC3jAXholPHCU136CgvC+3DH90/irvSQh9Br8f8XkGYUAsuhpodCre KGAQ== X-Forwarded-Encrypted: i=1; AJvYcCUo0dqeR3y8ao6yauGwZGflFJmxWrQGg9Dhxdrh/Hdp3lrlwejrOzSM0G1PfzxpLT5s0B+1myj4l28b10quNrVcl91XWFjABgwJ+4tnyDXb X-Gm-Message-State: AOJu0Yywb0MydTKvkXdB0ltz9tUY38mOiEalBcqrR5DtD6MaFAWH5tcR f0X42Dw06S9G4ZyrPx57X6iz+ujtYoax1470XYmGThdgXprVI0/NLgI/SW0p34U= X-Google-Smtp-Source: AGHT+IGYYROFmdLbUMjFpP9qsW46pO/QmXTyHrKREDj8fB5na2NFI5XZWqwX4q89xnCXQ4xvRWeBEg== X-Received: by 2002:a05:6402:1844:b0:564:3830:b9a5 with SMTP id v4-20020a056402184400b005643830b9a5mr3243810edy.21.1708349769992; Mon, 19 Feb 2024 05:36:09 -0800 (PST) Received: from [10.167.154.1] (078088045141.garwolin.vectranet.pl. [78.88.45.141]) by smtp.gmail.com with ESMTPSA id q29-20020a50cc9d000000b00563a3ff30basm2900168edi.59.2024.02.19.05.36.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 05:36:09 -0800 (PST) From: Konrad Dybcio Date: Mon, 19 Feb 2024 14:35:48 +0100 Subject: [PATCH 3/8] clk: qcom: clk-alpha-pll: Add HUAYRA_2290 support MIME-Version: 1.0 Message-Id: <20240219-topic-rb1_gpu-v1-3-d260fa854707@linaro.org> References: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708349759; l=4133; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=79Y0MxxohdGitgftXN/Ssqm4c/Qk+6TMe7Z4Gt+3Bxg=; b=4nQYbPVeI8Be4nvkpxVfXN4FtQYQuTUrRB6I4LVYY/kCkQW6/OyzfiXXuRABMb+6jrO9nZF9u NlAaZfORH/nBJ6Eq1c667ga2Qun9siLGQF88pnu9nhecTmr3DokAeBS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Commit 134b55b7e19f ("clk: qcom: support Huayra type Alpha PLL") introduced an entry to the alpha offsets array, but diving into QCM2290 downstream and some documentation, it turned out that the name Huayra apparently has been used quite liberally across many chips, even with noticeably different hardware. Introduce another set of offsets and a new configure function for the Huayra PLL found on QCM2290. This is required e.g. for the consumers of GPUCC_PLL0 to properly start. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-alpha-pll.c | 45 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 3 +++ 2 files changed, 48 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 8a412ef47e16..61b5abd13782 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -244,6 +244,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_OPMODE] = 0x30, [PLL_OFF_STATUS] = 0x3c, }, + [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL_U] = 0x14, + [PLL_OFF_CONFIG_CTL_U1] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_TEST_CTL_U] = 0x20, + [PLL_OFF_TEST_CTL_U1] = 0x24, + [PLL_OFF_OPMODE] = 0x28, + [PLL_OFF_STATUS] = 0x38, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -779,6 +792,38 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, return clamp(rate, min_freq, max_freq); } +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + + /* Set PLL_BYPASSNL */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); + + /* Wait 5 us between setting BYPASS and deasserting reset */ + mb(); + udelay(5); + + /* Take PLL out from reset state */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + + /* Wait 50us for PLL_LOCK_DET bit to go high */ + mb(); + usleep_range(50, 55); + + /* Enable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); +} +EXPORT_SYMBOL(clk_huayra_2290_pll_configure); + static unsigned long alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index fb6d50263bb9..91d3d6f19eae 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -29,6 +29,7 @@ enum { CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, CLK_ALPHA_PLL_TYPE_STROMER_PLUS, + CLK_ALPHA_PLL_TYPE_HUAYRA_2290, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -191,6 +192,8 @@ extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, From patchwork Mon Feb 19 13:35:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13562711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3550DC48BF8 for ; Mon, 19 Feb 2024 13:36:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 12D4310E3E2; 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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id q29-20020a50cc9d000000b00563a3ff30basm2900168edi.59.2024.02.19.05.36.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 05:36:12 -0800 (PST) From: Konrad Dybcio Date: Mon, 19 Feb 2024 14:35:49 +0100 Subject: [PATCH 4/8] clk: qcom: Add QCM2290 GPU clock controller driver MIME-Version: 1.0 Message-Id: <20240219-topic-rb1_gpu-v1-4-d260fa854707@linaro.org> References: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708349759; l=13117; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=dO647o6aBNMCZgw8TK/bcr4OlqfgIEZ68OVWZawfZFw=; b=6FlC3qLI5GiuvBX7DPfQOzUATj0eTQ+4qpLx9kjr72XqPDW9NyO6VUVCXuvfZCa+9DV0uh5SA syGcRS9lRs4CBJMY24cLdlDeRgJmVc+DU4By27VO7L/wHptgvjd3/eI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a driver for the GPU clock controller block found on the QCM2290 SoC. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-qcm2290.c | 423 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 433 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 4580edbd13ea..d70ea4548755 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -65,6 +65,15 @@ config CLK_X1E80100_TCSRCC Support for the TCSR clock controller on X1E80100 devices. Say Y if you want to use peripheral devices such as SD/UFS. +config CLK_QCM2290_GPUCC + tristate "QCM2290 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_QCM2290_GCC + help + Support for the graphics clock controller on QCM2290 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config QCOM_A53PLL tristate "MSM8916 A53 PLL" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1da65ca78e24..b8d49c054558 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o +obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c new file mode 100644 index 000000000000..b6e20d63ac85 --- /dev/null +++ b/drivers/clk/qcom/gpucc-qcm2290.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_GCC_AHB_CLK, + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_2X_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_AUX, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco huayra_vco[] = { + { 600000000, 3300000000, 0 }, + { 600000000, 2200000000, 1 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x25, + .config_ctl_val = 0x200d4828, + .config_ctl_hi_val = 0x6, + .test_ctl_val = GENMASK(28, 26), + .test_ctl_hi_val = BIT(14), + .user_ctl_val = 0xf, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = huayra_vco, + .num_vco = ARRAY_SIZE(huayra_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO, }, + { .hw = &gpu_cc_pll0.clkr.hw, }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC, }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC, }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL0_OUT_AUX, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO, }, + { .hw = &gpu_cc_pll0.clkr.hw, }, + { .hw = &gpu_cc_pll0.clkr.hw, }, + { .hw = &gpu_cc_pll0.clkr.hw, }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC, }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(537600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1123200000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_GX_BCR }, + .reset_count = 1, + .pd = { + .name = "gpu_gx_gdsc", + }, + .parent = &gpu_cx_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | AON_RESET | SW_RESET, +}; + +static struct clk_regmap *gpu_cc_qcm2290_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_qcm2290_resets[] = { + [GPU_GX_BCR] = { 0x1008 }, +}; + +static struct gdsc *gpu_cc_qcm2290_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_qcm2290_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + + +static const struct qcom_cc_desc gpu_cc_qcm2290_desc = { + .config = &gpu_cc_qcm2290_regmap_config, + .clks = gpu_cc_qcm2290_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_qcm2290_clocks), + .resets = gpu_cc_qcm2290_resets, + .num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets), + .gdscs = gpu_cc_qcm2290_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs), +}; + +static const struct of_device_id gpu_cc_qcm2290_match_table[] = { + { .compatible = "qcom,qcm2290-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table); + +static int gpu_cc_qcm2290_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = devm_pm_clk_create(&pdev->dev); + if (ret) + return ret; + + ret = pm_clk_add(&pdev->dev, NULL); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire ahb clock\n"); + return ret; + } + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + clk_huayra_2290_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + + regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK */ + + ret = qcom_cc_really_probe(pdev, &gpu_cc_qcm2290_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register display clock controller\n"); + goto out_pm_runtime_put; + } + +out_pm_runtime_put: + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static struct platform_driver gpu_cc_qcm2290_driver = { + .probe = gpu_cc_qcm2290_probe, + .driver = { + .name = "gpucc-qcm2290", + .of_match_table = gpu_cc_qcm2290_match_table, + }, +}; +module_platform_driver(gpu_cc_qcm2290_driver); + +MODULE_DESCRIPTION("QTI QCM2290 GPU clock controller driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Feb 19 13:35:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13562713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BAD7C48BC3 for ; Mon, 19 Feb 2024 13:36:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 30BF410E3F0; Mon, 19 Feb 2024 13:36:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="na2pTi/m"; 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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id q29-20020a50cc9d000000b00563a3ff30basm2900168edi.59.2024.02.19.05.36.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 05:36:14 -0800 (PST) From: Konrad Dybcio Date: Mon, 19 Feb 2024 14:35:50 +0100 Subject: [PATCH 5/8] drm/msm/adreno: Add missing defines for A702 MIME-Version: 1.0 Message-Id: <20240219-topic-rb1_gpu-v1-5-d260fa854707@linaro.org> References: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708349759; l=1379; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=2VUaTHaFXwk9sVr7gsAachnQpNO5KMem0UoFA2HST7g=; b=uy8b7slouVEaFRzlMDQaQuGj6/EdLKuvoxlWss5WCvpYfkQIMuuko+sE6v3X1yKkbgzKjx7sS Sr/e/dPpNpcCFZmvXDeCJmc5sQgAXJeQ/E2oSh1XTeW54gedzNfKZ7t X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add some defines required for A702. Can be substituted with a header sync after merging mesa!27665 [1]. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27665 Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..1ec4dbc0e746 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1945,6 +1945,24 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A6XX_RBBM_CLOCK_CNTL_FCHE 0x00000123 + +#define REG_A6XX_RBBM_CLOCK_DELAY_FCHE 0x00000124 + +#define REG_A6XX_RBBM_CLOCK_HYST_FCHE 0x00000125 + +#define REG_A6XX_RBBM_CLOCK_CNTL_MHUB 0x00000126 + +#define REG_A6XX_RBBM_CLOCK_DELAY_MHUB 0x00000127 + +#define REG_A6XX_RBBM_CLOCK_HYST_MHUB 0x00000128 + +#define REG_A6XX_RBBM_CLOCK_DELAY_GLC 0x00000129 + +#define REG_A6XX_RBBM_CLOCK_HYST_GLC 0x0000012a + +#define REG_A6XX_RBBM_CLOCK_CNTL_GLC 0x0000012b + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff From patchwork Mon Feb 19 13:35:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13562715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8BA9C48BC3 for ; Mon, 19 Feb 2024 13:36:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 868AE10E39A; Mon, 19 Feb 2024 13:36:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="peMmxdN9"; dkim-atps=neutral Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6D65C10E403 for ; Mon, 19 Feb 2024 13:36:19 +0000 (UTC) Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-56454c695e6so1825452a12.0 for ; Mon, 19 Feb 2024 05:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708349777; x=1708954577; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+hQ3SpYizIIEdO8h/cb2gS2gZ6yJ1jbKnG/M424eunA=; b=peMmxdN9btDeIazLKfCaQR7eSgvSzl23Bvb/XKHRI5GNkRAVyBh5xmsclCAc9EEn5N 36Nd8nY/RghZwKXVkiccF+V/eVF7Qle/qNQCSAt+PkH06ZHWtPk8NjPXV+fxXQwwJ2hh oVSE2iXximeExWk4LLsUS8gcqc7Xpy1HUNB2sikW3ci2ox2x4H5WfNg2BjcDPO3xht29 q7jhVdhm/x5iXjWZrIqmYONQRP/bh3DXLBZ6mmYtbRjsr0stbZPGRAGrOJRdINdMZYb/ LcYKgB8xL+t+jtOThtqxLDcdGGCHWWd1sTl2V/Mgvvi1XXWFkulATB1IdUsZ3v36Nonf OPqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708349777; x=1708954577; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+hQ3SpYizIIEdO8h/cb2gS2gZ6yJ1jbKnG/M424eunA=; b=aNpIcoHrwM8Dtr+RiKwpbZQg0UPChTDKDi0aqIA0UHLxdCy12F+Rv4VPP+J8KUIgbe K+f/1DqUAHG6orucbYOwOI6ExfR1wU5FYqJyTNILqJtGj72hutH9IHuritefOQp/donX g8M71fiqA/ZY1MLwSwZkk2MOj8EIHFOWvbsl+odbyHdHI2OOEQLhWrr6JoTCl84OnM+a iTsyq1Oho8C1jVTjzp41Cg+ulPj7uJecHzUm5c5WwGltZ2PjdDppT3XoFLLe7BrPqLUn G+LaKHdj10R0fMnvBfZSELec6bd7Yi+bW/GCIdyXHKBtyucmxXYdjiPelJM1/uaXJw3j ZHyA== X-Forwarded-Encrypted: i=1; AJvYcCXuaGcKkks5g/W3RC2jsSLl8y/UOE9n/xlsbDpFWlRWvdXQULHbg/thhi6JFGR6PkupoURF4YTIG+3DkKsXm/X/VydrnzftIQzXnuSlR0ct X-Gm-Message-State: AOJu0YzkKEnjUoh0u9/YcR2bTsvtJJCzC3siJ5Kw2xa/MOCidNQQBF5q h7sw14UanwBZd05bvcbhkiOA8m8EvefceWwGRzKiVHoqehiSdZ40u8I7r9udrsY= X-Google-Smtp-Source: AGHT+IFtyKubqbVkS2/EGKVIjmdl6/hb5Jk1awJ+nov4aN2l80WWwgt45nlgndmGKF7U2X5okMdPSA== X-Received: by 2002:a05:6402:5207:b0:564:4211:faa3 with SMTP id s7-20020a056402520700b005644211faa3mr4558857edd.1.1708349777655; Mon, 19 Feb 2024 05:36:17 -0800 (PST) Received: from [10.167.154.1] (078088045141.garwolin.vectranet.pl. [78.88.45.141]) by smtp.gmail.com with ESMTPSA id q29-20020a50cc9d000000b00563a3ff30basm2900168edi.59.2024.02.19.05.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 05:36:17 -0800 (PST) From: Konrad Dybcio Date: Mon, 19 Feb 2024 14:35:51 +0100 Subject: [PATCH 6/8] drm/msm/adreno: Add A702 support MIME-Version: 1.0 Message-Id: <20240219-topic-rb1_gpu-v1-6-d260fa854707@linaro.org> References: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708349759; l=11199; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=/obkr4MMIdqspTXLmZcuivEDxO3xqayOzHksqJVGMAk=; b=pC9ZbozvhtAheTgTbHhODa3zv/ScgMjLbvVCtaCW+Bx9TyZuBh7ZvlmsMYXyybffQAMfdiBn+ B1zLGn99G21DmgJjQlkyiv8TbzZ4oR4dXPhhJNaMpg/SIcTJh7PMjy3 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The A702 is a weird mix of 600 and 700 series.. Perhaps even a testing ground for some A7xx features with good ol' A6xx silicon. It's basically A610 that's been beefed up with some new registers and hw features (like APRIV!), that was then cut back in size, memory bus and some other ways. Add support for it, tested with QCM2290 / RB1. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 92 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 18 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 16 +++++- 3 files changed, 117 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..2a491a486ca1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -837,6 +837,65 @@ const struct adreno_reglist a690_hwcg[] = { {} }; +const struct adreno_reglist a702_hwcg[] = { + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 }, + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 }, + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 }, + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, + { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, + { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, + { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 }, + {} +}; + const struct adreno_reglist a730_hwcg[] = { { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 }, @@ -968,6 +1027,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) clock_cntl_on = 0x8aa8aa02; else if (adreno_is_a610(adreno_gpu)) clock_cntl_on = 0xaaa8aa82; + else if (adreno_is_a702(adreno_gpu)) + clock_cntl_on = 0xaaaaaa82; else clock_cntl_on = 0x8aa8aa82; @@ -989,14 +1050,14 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) return; /* Disable SP clock before programming HWCG registers */ - if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) + if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ - if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) + if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); @@ -1224,7 +1285,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) const u32 *regs = a6xx_protect; unsigned i, count, count_max; - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650(adreno_gpu) || adreno_is_a702(adreno_gpu)) { regs = a650_protect; count = ARRAY_SIZE(a650_protect); count_max = 48; @@ -1320,6 +1381,12 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.uavflagprd_inv = 2; } + + if (adreno_is_a702(gpu)) { + gpu->ubwc_config.highest_bank_bit = 14; + gpu->ubwc_config.min_acc_len = 1; + gpu->ubwc_config.ubwc_mode = 2; + } } static void a6xx_set_ubwc_config(struct msm_gpu *gpu) @@ -1453,7 +1520,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, return false; /* A7xx is safe! */ - if (adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu)) return true; /* @@ -1671,7 +1738,7 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); /* VBIF/GBIF start*/ - if (adreno_is_a610(adreno_gpu) || + if (adreno_is_a610_family(adreno_gpu) || adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { @@ -1705,6 +1772,7 @@ static int hw_init(struct msm_gpu *gpu) } if (!(adreno_is_a650_family(adreno_gpu) || + adreno_is_a702(adreno_gpu) || adreno_is_a730(adreno_gpu))) { gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M; @@ -1725,7 +1793,7 @@ static int hw_init(struct msm_gpu *gpu) if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); - } else if (adreno_is_a610(adreno_gpu)) { + } else if (adreno_is_a610_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); } else if (!adreno_is_a7xx(adreno_gpu)) { @@ -1740,13 +1808,18 @@ static int hw_init(struct msm_gpu *gpu) if (adreno_is_a610(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); + } else if (adreno_is_a702(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); } else if (!adreno_is_a7xx(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); /* Setting the primFifo thresholds default values, * and vccCacheSkipDis=1 bit (0x200) for A640 and newer */ - if (adreno_is_a690(adreno_gpu)) + if (adreno_is_a702(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000); + else if (adreno_is_a690(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); @@ -1786,7 +1859,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); else if (adreno_is_a619(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); - else if (adreno_is_a610(adreno_gpu)) + else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); @@ -1822,6 +1895,9 @@ static int hw_init(struct msm_gpu *gpu) else gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); + } else if (adreno_is_a702(adreno_gpu)) { + /* Something to do with the HLSQ cluster */ + gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); } if (adreno_is_a690(adreno_gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..b121abc71338 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -492,6 +492,24 @@ static const struct adreno_info gpulist[] = { .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x07000200), + .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ + .fw = { + [ADRENO_FW_SQE] = "a702_sqe.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a702_zap.mbn", + .hwcg = a702_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 236, 1 }, + { 178, 2 }, + { 142, 3 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x07030001), .family = ADRENO_7XX_GEN1, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..f451881a6ddf 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -77,7 +77,7 @@ struct adreno_reglist { }; extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; -extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[], a740_hwcg[]; +extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[]; struct adreno_speedbin { uint16_t fuse; @@ -382,6 +382,20 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x06090000; } +static inline int adreno_is_a702(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x07000200; +} + +static inline int adreno_is_a610_family(const struct adreno_gpu *gpu) +{ + if (WARN_ON_ONCE(!gpu->info)) + return false; + + /* TODO: A612 */ + return adreno_is_a610(gpu) || adreno_is_a702(gpu); +} + /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { From patchwork Mon Feb 19 13:35:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13562714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A118BC54787 for ; Mon, 19 Feb 2024 13:36:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C2F710E3EC; Mon, 19 Feb 2024 13:36:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Y1m29dwl"; dkim-atps=neutral Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) by gabe.freedesktop.org (Postfix) with ESMTPS id D19CD10E3AF for ; Mon, 19 Feb 2024 13:36:21 +0000 (UTC) Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-563d56ee65cso3716726a12.2 for ; Mon, 19 Feb 2024 05:36:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708349780; x=1708954580; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TfbMb3jj0qItrK4emPJgHKMlXlJN3RIWDWQruK+cJ2c=; b=Y1m29dwli5KfbzrYcgSCKX6TS/IaBgA6y9CrCt2NwuN0XDRInVWRyYdlUtvGHsbUi2 mrLTMj7aCYijeBKl61EySo2AuiXXPuy3e0pbL0aYSgKvkYfp3Iav87beyzs9TEzg4Xz/ 5XD8yZsJNJLse8GlVvPeP0c4snBR+GBvcBOZNpmlLOP5ZkC6fRLoljHH9o41LaTNOZxe B2oFMKe7G8Dslh+1U0wr9QQgdpRTsmyop++ZtlgVRDe0zvfwVJKGCFwTMW5w5XgpwcHa rz50fj+DkUQfUFYSy5MMLFUd88oarOTBgzJEUCLzo2+nN1CrfpVKN/oOkpt6w8osJ9Md HZ/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708349780; x=1708954580; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TfbMb3jj0qItrK4emPJgHKMlXlJN3RIWDWQruK+cJ2c=; b=C+pg6+oHaldTmYtOPUb/O6lgVPVByI2GuX/ToYTxcPTUlN1tVTqZwK+4vCcFlsJY0Q PYVTHjCeE63LtPhEz+Rtc73QKmgCaSKUbTILOn+hEmGmRjCU0J68wBj2RDKkezXxGJot 7hxFWqCymj4lCshH+5B5w83TGlTHA2xokb8KB8kOwkBYC2kJeGc2O1v/r28mkxW0FHPQ i1BnLQEqWguAz5/uate58oVkD1WmuvTs7VwDPJ6k8AK14t9lvgLHh8UoolmqQyAbmxaN k/ZR+29NXq7fNfPvX/a1GGoQBvL75GVwM68CDXFo3j+/EYmIUYIX9bzN36jeSb7+Uw+d UC4w== X-Forwarded-Encrypted: i=1; AJvYcCVspBuRLBTI57X45IKUXe2h1wtSiOi4W7ubO4SM5H5Q38uvc5Wxbs0C9OyWSkQhBQhB95ofKxls3FaYKWlLkFphj6XI0KbUO67Dr9gmMxTX X-Gm-Message-State: AOJu0Yylg7WRirQS/p0VKuQRrvVC1feB7gEfd9+BZumaF1ZD0q4iHvBb NSU0B7PAKQ7CE+Pm/IB5Ftp1juxprbrAwjk4q7opV+FD3oll31pofJ5yZa37VJk= X-Google-Smtp-Source: AGHT+IGVF2NlMcSebY5m3UgwICGV6Y1d5NL0fAQF4zO4ZxHlMwU6m/KrAlCRO8vwbMnsO7021ZaMIw== X-Received: by 2002:a05:6402:358:b0:564:8d2f:505b with SMTP id r24-20020a056402035800b005648d2f505bmr1119514edw.39.1708349780176; Mon, 19 Feb 2024 05:36:20 -0800 (PST) Received: from [10.167.154.1] (078088045141.garwolin.vectranet.pl. [78.88.45.141]) by smtp.gmail.com with ESMTPSA id q29-20020a50cc9d000000b00563a3ff30basm2900168edi.59.2024.02.19.05.36.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 05:36:19 -0800 (PST) From: Konrad Dybcio Date: Mon, 19 Feb 2024 14:35:52 +0100 Subject: [PATCH 7/8] arm64: dts: qcom: qcm2290: Add GPU nodes MIME-Version: 1.0 Message-Id: <20240219-topic-rb1_gpu-v1-7-d260fa854707@linaro.org> References: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708349759; l=5419; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HC/xBfPb+Ge3S4O35AHKQR0tXgYuKOO6Vtq5u/Zvis8=; b=6WqrsuxfLwQscwtWGCN3jaXQS4gD+jRD2N76tzuid6qwF60qAtrmeKNmZwBsDDJYOwXJF/j8X yi7onOH5wJcCDk8DEhMMqf3+8V2WfyVbN7QF698aYfGcH1cr1M7d0IK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Describe the GPU hardware on the QCM2290. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 154 ++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 89beac833d43..ec5aef5d9c69 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -737,6 +738,11 @@ qusb2_hstx_trim: hstx-trim@25b { reg = <0x25b 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu-speed-bin@2006 { + reg = <0x2006 0x2>; + bits = <5 8>; + }; }; pmu@1b8e300 { @@ -1383,6 +1389,154 @@ usb_dwc3: usb@4e00000 { }; }; + gpu: gpu@5900000 { + compatible = "qcom,adreno-07000200", "qcom,adreno"; + reg = <0x0 0x05900000 0x0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0 1>, + <&adreno_smmu 2 0>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + qcom,gmu = <&gmu_wrapper>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ + opp-1123200000 { + opp-hz = /bits/ 64 <1123200000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + turbo-mode; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + required-opps = <&rpmpd_opp_turbo>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + turbo-mode; + }; + + opp-921600000 { + opp-hz = /bits/ 64 <921600000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x7>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + required-opps = <&rpmpd_opp_svs_plus>; + opp-peak-kBps = <3879000>; + opp-supported-hw = <0xf>; + }; + + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + required-opps = <&rpmpd_opp_svs>; + opp-peak-kBps = <2929000>; + opp-supported-hw = <0xf>; + }; + + opp-355200000 { + opp-hz = /bits/ 64 <355200000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <1720000>; + opp-supported-hw = <0xf>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0 0x0596a000 0x0 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,qcm2290-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd QCM2290_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@59a0000 { + compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x059a0000 0x0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,qcm2290-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; From patchwork Mon Feb 19 13:35:53 2024 Content-Type: text/plain; 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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id q29-20020a50cc9d000000b00563a3ff30basm2900168edi.59.2024.02.19.05.36.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 05:36:22 -0800 (PST) From: Konrad Dybcio Date: Mon, 19 Feb 2024 14:35:53 +0100 Subject: [PATCH 8/8] arm64: dts: qcom: qrb2210-rb1: Enable the GPU MIME-Version: 1.0 Message-Id: <20240219-topic-rb1_gpu-v1-8-d260fa854707@linaro.org> References: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v1-0-d260fa854707@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: Marijn Suijten , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708349759; l=852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Qqtg4ojpOawwNYOqVpOvtJgi/pUtWJ369I3bzfKA0X4=; b=7s6b1o0Wbq+2Q9UxmDpWZcz1X+WrOuTL3z3Ndhfv4cWpB+GS8fT0yuSsDnxb4CeS4G3tVFSpH aC1g/6W2UwABvq/j2FmZN37rrNOb1IlvgJD1D3eP0KEN8TNjCvQO0bL X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable the A702 GPU (also marketed as "3D accelerator by qcom [1], lol). [1] https://docs.qualcomm.com/bundle/publicresource/87-61720-1_REV_A_QUALCOMM_ROBOTICS_RB1_PLATFORM__QUALCOMM_QRB2210__PRODUCT_BRIEF.pdf Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 6e9dd0312adc..c9abca5a7e39 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -199,6 +199,14 @@ &gpi_dma0 { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/qcm2290/a702_zap.mbn"; + }; +}; + &i2c2 { clock-frequency = <400000>; status = "okay";