From patchwork Tue Feb 20 09:24:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13563697 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87BE25FDA2 for ; Tue, 20 Feb 2024 09:11:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708420312; cv=none; b=Ho2HMToLvoKj3ctfn4ImvY51DmH1jsnBHdZCymTeKC6/hRhIgGo7t8HJahRsgaiIWTWlEZcmyh5VTpUaSh4tfJz+TBcnACQslIHIv0wXhqqFd5bMgy5GNF8UAKFKCtuClWhCBjkrH++ZQRy/ri38bEw+Pj2tZFlcYyMLGbCl54A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708420312; c=relaxed/simple; bh=f72SFWwq+PohiF2H5sIw0CnPQG3e0SkCa+ntNndt4BU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Y+hxbgHweLwutsALy0lSGZN0scLFI91ZJYe2F3g55dZxQRgyro8N98w1QJcioHy2Jc4WpcFnW2dzuObZKIZBo708ZJb9BIGt2OpPYD4DgTAa3rQAN0kvdTZ74qT3WMFuRZDL7WEpPPy1L0PXAyxdDWKNJ+8B2xRMHswvTTo0Quo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bbtM7tKz; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bbtM7tKz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708420310; x=1739956310; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f72SFWwq+PohiF2H5sIw0CnPQG3e0SkCa+ntNndt4BU=; b=bbtM7tKzjmEwzjDAtya6eBi4JLCWMJ7siRwakMUZWGNQCwFKtJXE4jKq x4NmMfEk42DiVEINaBOPR1zyXGoMJxiqWBSsCj2ulRepry9g3LeZR7WC1 Fzio0rLltJf2YvKUmE9J8urSTotFQdW8rltJzWii22lZr3wLJxh6C7tLZ HsqY4Pm4FTe4T8lKTF99gQKMkD7JKK8vz1P8qALzhUJCwYcHCqtaXoWP/ DlmuOfaca9vekKAy9ze/t4j3zrHXJ2LPwWsRoKh3QBSqcM4v/EsymvdhS KbH5+UF3wxmS7vjOLWMHiKTiwCfdOECJq/6uCGdoPW3e1xqMQnphCx0iw g==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2374959" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2374959" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 01:11:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="5012851" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa007.jf.intel.com with ESMTP; 20 Feb 2024 01:11:45 -0800 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 1/8] hw/core: Rename CpuTopology to CPUTopology Date: Tue, 20 Feb 2024 17:24:57 +0800 Message-Id: <20240220092504.726064-2-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Use CPUTopology to honor the generic style of CPU capitalization abbreviations. Signed-off-by: Zhao Liu --- hw/s390x/cpu-topology.c | 6 +++--- include/hw/boards.h | 8 ++++---- include/hw/s390x/cpu-topology.h | 6 +++--- tests/unit/test-smp-parse.c | 14 +++++++------- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/hw/s390x/cpu-topology.c b/hw/s390x/cpu-topology.c index f16bdf65faa0..016f6c1c15ac 100644 --- a/hw/s390x/cpu-topology.c +++ b/hw/s390x/cpu-topology.c @@ -86,7 +86,7 @@ bool s390_has_topology(void) */ static void s390_topology_init(MachineState *ms) { - CpuTopology *smp = &ms->smp; + CPUTopology *smp = &ms->smp; s390_topology.cores_per_socket = g_new0(uint8_t, smp->sockets * smp->books * smp->drawers); @@ -181,7 +181,7 @@ void s390_topology_reset(void) */ static bool s390_topology_cpu_default(S390CPU *cpu, Error **errp) { - CpuTopology *smp = ¤t_machine->smp; + CPUTopology *smp = ¤t_machine->smp; CPUS390XState *env = &cpu->env; /* All geometry topology attributes must be set or all unset */ @@ -234,7 +234,7 @@ static bool s390_topology_check(uint16_t socket_id, uint16_t book_id, uint16_t drawer_id, uint16_t entitlement, bool dedicated, Error **errp) { - CpuTopology *smp = ¤t_machine->smp; + CPUTopology *smp = ¤t_machine->smp; if (socket_id >= smp->sockets) { error_setg(errp, "Unavailable socket: %d", socket_id); diff --git a/include/hw/boards.h b/include/hw/boards.h index 78dea50054a1..e63dec919da2 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -333,7 +333,7 @@ typedef struct DeviceMemoryState { } DeviceMemoryState; /** - * CpuTopology: + * CPUTopology: * @cpus: the number of present logical processors on the machine * @drawers: the number of drawers on the machine * @books: the number of books in one drawer @@ -345,7 +345,7 @@ typedef struct DeviceMemoryState { * @threads: the number of threads in one core * @max_cpus: the maximum number of logical processors on the machine */ -typedef struct CpuTopology { +typedef struct CPUTopology { unsigned int cpus; unsigned int drawers; unsigned int books; @@ -356,7 +356,7 @@ typedef struct CpuTopology { unsigned int cores; unsigned int threads; unsigned int max_cpus; -} CpuTopology; +} CPUTopology; /** * MachineState: @@ -407,7 +407,7 @@ struct MachineState { const char *cpu_type; AccelState *accelerator; CPUArchIdList *possible_cpus; - CpuTopology smp; + CPUTopology smp; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; }; diff --git a/include/hw/s390x/cpu-topology.h b/include/hw/s390x/cpu-topology.h index c064f427e948..ff09c57a4428 100644 --- a/include/hw/s390x/cpu-topology.h +++ b/include/hw/s390x/cpu-topology.h @@ -63,17 +63,17 @@ static inline void s390_topology_reset(void) extern S390Topology s390_topology; -static inline int s390_std_socket(int n, CpuTopology *smp) +static inline int s390_std_socket(int n, CPUTopology *smp) { return (n / smp->cores) % smp->sockets; } -static inline int s390_std_book(int n, CpuTopology *smp) +static inline int s390_std_book(int n, CPUTopology *smp) { return (n / (smp->cores * smp->sockets)) % smp->books; } -static inline int s390_std_drawer(int n, CpuTopology *smp) +static inline int s390_std_drawer(int n, CPUTopology *smp) { return (n / (smp->cores * smp->sockets * smp->books)) % smp->drawers; } diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c index 24972666a74d..f660d6b0df45 100644 --- a/tests/unit/test-smp-parse.c +++ b/tests/unit/test-smp-parse.c @@ -86,8 +86,8 @@ */ typedef struct SMPTestData { SMPConfiguration config; - CpuTopology expect_prefer_sockets; - CpuTopology expect_prefer_cores; + CPUTopology expect_prefer_sockets; + CPUTopology expect_prefer_cores; const char *expect_error; } SMPTestData; @@ -395,7 +395,7 @@ static char *smp_config_to_string(const SMPConfiguration *config) } /* Use the different calculation than machine_topo_get_threads_per_socket(). */ -static unsigned int cpu_topology_get_threads_per_socket(const CpuTopology *topo) +static unsigned int cpu_topology_get_threads_per_socket(const CPUTopology *topo) { /* Check the divisor to avoid invalid topology examples causing SIGFPE. */ if (!topo->sockets) { @@ -406,7 +406,7 @@ static unsigned int cpu_topology_get_threads_per_socket(const CpuTopology *topo) } /* Use the different calculation than machine_topo_get_cores_per_socket(). */ -static unsigned int cpu_topology_get_cores_per_socket(const CpuTopology *topo) +static unsigned int cpu_topology_get_cores_per_socket(const CPUTopology *topo) { /* Check the divisor to avoid invalid topology examples causing SIGFPE. */ if (!topo->threads) { @@ -416,12 +416,12 @@ static unsigned int cpu_topology_get_cores_per_socket(const CpuTopology *topo) } } -static char *cpu_topology_to_string(const CpuTopology *topo, +static char *cpu_topology_to_string(const CPUTopology *topo, unsigned int threads_per_socket, unsigned int cores_per_socket) { return g_strdup_printf( - "(CpuTopology) {\n" + "(CPUTopology) {\n" " .cpus = %u,\n" " .sockets = %u,\n" " .dies = %u,\n" @@ -438,7 +438,7 @@ static char *cpu_topology_to_string(const CpuTopology *topo, } static void check_parse(MachineState *ms, const SMPConfiguration *config, - const CpuTopology *expect_topo, const char *expect_err, + const CPUTopology *expect_topo, const char *expect_err, bool is_valid) { g_autofree char *config_str = smp_config_to_string(config); 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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 2/8] hw/core: Move CPU topology enumeration into arch-agnostic file Date: Tue, 20 Feb 2024 17:24:58 +0800 Message-Id: <20240220092504.726064-3-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Cache topology needs to be defined based on CPU topology levels. Thus, move CPU topology enumeration into a common header. To match the general topology naming style, rename CPU_TOPO_LEVEL_SMT and CPU_TOPO_LEVEL_PACKAGE to CPU_TOPO_LEVEL_THREAD and CPU_TOPO_LEVEL_SOCKET. Also, enumerate additional topology levels for non-i386 arches, and add helpers for topology enumeration and string conversion. Signed-off-by: Zhao Liu --- MAINTAINERS | 2 ++ hw/core/cpu-topology.c | 56 ++++++++++++++++++++++++++++++++++ hw/core/meson.build | 1 + include/hw/core/cpu-topology.h | 40 ++++++++++++++++++++++++ include/hw/i386/topology.h | 18 +---------- target/i386/cpu.c | 24 +++++++-------- target/i386/cpu.h | 2 +- tests/unit/meson.build | 3 +- 8 files changed, 115 insertions(+), 31 deletions(-) create mode 100644 hw/core/cpu-topology.c create mode 100644 include/hw/core/cpu-topology.h diff --git a/MAINTAINERS b/MAINTAINERS index 7d61fb93194b..4b1cce938915 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1871,6 +1871,7 @@ R: Yanan Wang S: Supported F: hw/core/cpu-common.c F: hw/core/cpu-sysemu.c +F: hw/core/cpu-topology.c F: hw/core/machine-qmp-cmds.c F: hw/core/machine.c F: hw/core/machine-smp.c @@ -1882,6 +1883,7 @@ F: qapi/machine-common.json F: qapi/machine-target.json F: include/hw/boards.h F: include/hw/core/cpu.h +F: include/hw/core/cpu-topology.h F: include/hw/cpu/cluster.h F: include/sysemu/numa.h F: tests/unit/test-smp-parse.c diff --git a/hw/core/cpu-topology.c b/hw/core/cpu-topology.c new file mode 100644 index 000000000000..ca1361d13c16 --- /dev/null +++ b/hw/core/cpu-topology.c @@ -0,0 +1,56 @@ +/* + * QEMU CPU Topology Representation + * + * Copyright (c) 2024 Intel Corporation + * Author: Zhao Liu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/core/cpu-topology.h" + +typedef struct CPUTopoInfo { + const char *name; +} CPUTopoInfo; + +CPUTopoInfo cpu_topo_descriptors[] = { + [CPU_TOPO_LEVEL_INVALID] = { .name = "invalid", }, + [CPU_TOPO_LEVEL_THREAD] = { .name = "thread", }, + [CPU_TOPO_LEVEL_CORE] = { .name = "core", }, + [CPU_TOPO_LEVEL_MODULE] = { .name = "module", }, + [CPU_TOPO_LEVEL_CLUSTER] = { .name = "cluster", }, + [CPU_TOPO_LEVEL_DIE] = { .name = "die", }, + [CPU_TOPO_LEVEL_SOCKET] = { .name = "socket", }, + [CPU_TOPO_LEVEL_BOOK] = { .name = "book", }, + [CPU_TOPO_LEVEL_DRAWER] = { .name = "drawer", }, + [CPU_TOPO_LEVEL_MAX] = { .name = NULL, }, +}; + +const char *cpu_topo_to_string(CPUTopoLevel topo) +{ + return cpu_topo_descriptors[topo].name; +} + +CPUTopoLevel string_to_cpu_topo(char *str) +{ + for (int i = 0; i < ARRAY_SIZE(cpu_topo_descriptors); i++) { + CPUTopoInfo *info = &cpu_topo_descriptors[i]; + + if (!strcmp(info->name, str)) { + return (CPUTopoLevel)i; + } + } + return CPU_TOPO_LEVEL_MAX; +} diff --git a/hw/core/meson.build b/hw/core/meson.build index 67dad04de559..3b1d5ffab3e3 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -23,6 +23,7 @@ else endif common_ss.add(files('cpu-common.c')) +common_ss.add(files('cpu-topology.c')) common_ss.add(files('machine-smp.c')) system_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c')) system_ss.add(when: 'CONFIG_GENERIC_LOADER', if_true: files('generic-loader.c')) diff --git a/include/hw/core/cpu-topology.h b/include/hw/core/cpu-topology.h new file mode 100644 index 000000000000..cc6ca186ce3f --- /dev/null +++ b/include/hw/core/cpu-topology.h @@ -0,0 +1,40 @@ +/* + * QEMU CPU Topology Representation Header + * + * Copyright (c) 2024 Intel Corporation + * Author: Zhao Liu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef CPU_TOPOLOGY_H +#define CPU_TOPOLOGY_H + +typedef enum CPUTopoLevel { + CPU_TOPO_LEVEL_INVALID, + CPU_TOPO_LEVEL_THREAD, + CPU_TOPO_LEVEL_CORE, + CPU_TOPO_LEVEL_MODULE, + CPU_TOPO_LEVEL_CLUSTER, + CPU_TOPO_LEVEL_DIE, + CPU_TOPO_LEVEL_SOCKET, + CPU_TOPO_LEVEL_BOOK, + CPU_TOPO_LEVEL_DRAWER, + CPU_TOPO_LEVEL_MAX, +} CPUTopoLevel; + +const char *cpu_topo_to_string(CPUTopoLevel topo); +CPUTopoLevel string_to_cpu_topo(char *str); + +#endif /* CPU_TOPOLOGY_H */ diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index dff49fce1154..c6ff75f23991 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -39,7 +39,7 @@ * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). */ - +#include "hw/core/cpu-topology.h" #include "qemu/bitops.h" /* @@ -62,22 +62,6 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; -/* - * CPUTopoLevel is the general i386 topology hierarchical representation, - * ordered by increasing hierarchical relationship. - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F]) - * or AMD (CPUID[0x80000026]). - */ -enum CPUTopoLevel { - CPU_TOPO_LEVEL_INVALID, - CPU_TOPO_LEVEL_SMT, - CPU_TOPO_LEVEL_CORE, - CPU_TOPO_LEVEL_MODULE, - CPU_TOPO_LEVEL_DIE, - CPU_TOPO_LEVEL_PACKAGE, - CPU_TOPO_LEVEL_MAX, -}; - /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ac0a10abd45f..725d7e70182d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -247,7 +247,7 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, case CPU_TOPO_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: num_ids = 1 << apicid_pkg_offset(topo_info); break; default: @@ -304,7 +304,7 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, enum CPUTopoLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return 1; case CPU_TOPO_LEVEL_CORE: return topo_info->threads_per_core; @@ -313,7 +313,7 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, case CPU_TOPO_LEVEL_DIE: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die * topo_info->dies_per_pkg; default: @@ -326,7 +326,7 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, enum CPUTopoLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return 0; case CPU_TOPO_LEVEL_CORE: return apicid_core_offset(topo_info); @@ -334,7 +334,7 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, return apicid_module_offset(topo_info); case CPU_TOPO_LEVEL_DIE: return apicid_die_offset(topo_info); - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: return apicid_pkg_offset(topo_info); default: g_assert_not_reached(); @@ -347,7 +347,7 @@ static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) switch (topo_level) { case CPU_TOPO_LEVEL_INVALID: return CPUID_1F_ECX_TOPO_LEVEL_INVALID; - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return CPUID_1F_ECX_TOPO_LEVEL_SMT; case CPU_TOPO_LEVEL_CORE: return CPUID_1F_ECX_TOPO_LEVEL_CORE; @@ -380,7 +380,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, level = CPU_TOPO_LEVEL_INVALID; for (int i = 0; i <= count; i++) { level = find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPO_LEVEL_SOCKET, level + 1); /* @@ -388,7 +388,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, * and it just encode the invalid level (all fields are 0) * into the last subleaf of 0x1f. */ - if (level == CPU_TOPO_LEVEL_PACKAGE) { + if (level == CPU_TOPO_LEVEL_SOCKET) { level = CPU_TOPO_LEVEL_INVALID; break; } @@ -401,7 +401,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, unsigned long next_level; next_level = find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPO_LEVEL_SOCKET, level + 1); num_threads_next_level = num_threads_by_topo_level(topo_info, next_level); @@ -6290,7 +6290,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, /* Share the cache at package level. */ *eax |= max_thread_ids_for_cache(&topo_info, - CPU_TOPO_LEVEL_PACKAGE) << 14; + CPU_TOPO_LEVEL_SOCKET) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { @@ -7756,9 +7756,9 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) env->nr_dies = 1; /* SMT, core and package levels are set by default. */ - set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); + set_bit(CPU_TOPO_LEVEL_THREAD, env->avail_cpu_topo); set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); + set_bit(CPU_TOPO_LEVEL_SOCKET, env->avail_cpu_topo); } static void x86_cpu_initfn(Object *obj) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4b4cc70c8859..fcbf278b49e6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1596,7 +1596,7 @@ typedef struct CPUCacheInfo { * Used to encode CPUID[4].EAX[bits 25:14] or * CPUID[0x8000001D].EAX[bits 25:14]. */ - enum CPUTopoLevel share_level; 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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 3/8] hw/core: Define cache topology for machine Date: Tue, 20 Feb 2024 17:24:59 +0800 Message-Id: <20240220092504.726064-4-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Define the cache topology based on CPU topology level for two reasons: 1. In practice, a cache will always be bound to the CPU container (either private in the CPU container or shared among multiple containers), and CPU container is often expressed in terms of CPU topology level. 2. The x86's cache-related CPUIDs encode cache topology based on APIC ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV relies on also requires CPU containers to help indicate the private shared hierarchy of the cache. Therefore, for SMP systems, it is natural to use the CPU topology hierarchy directly in QEMU to define the cache topology. Currently, separated L1 cache (L1 data cache and L1 instruction cache) with unified higher-level cache (e.g., unified L2 and L3 caches), is the most common cache architectures. Therefore, define the topology for L1 D-cache, L1 I-cache, L2 cache and L3 cache in machine as the basic cache topology support. Signed-off-by: Zhao Liu --- hw/core/machine.c | 5 +++++ include/hw/boards.h | 25 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index b3199c710194..426f71770a84 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1163,6 +1163,11 @@ static void machine_initfn(Object *obj) ms->smp.cores = 1; ms->smp.threads = 1; + ms->smp_cache.l1d = CPU_TOPO_LEVEL_INVALID; + ms->smp_cache.l1i = CPU_TOPO_LEVEL_INVALID; + ms->smp_cache.l2 = CPU_TOPO_LEVEL_INVALID; + ms->smp_cache.l3 = CPU_TOPO_LEVEL_INVALID; + machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); } diff --git a/include/hw/boards.h b/include/hw/boards.h index e63dec919da2..8558b88aea52 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -10,6 +10,7 @@ #include "qemu/module.h" #include "qom/object.h" #include "hw/core/cpu.h" +#include "hw/core/cpu-topology.h" #define TYPE_MACHINE_SUFFIX "-machine" @@ -144,6 +145,12 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @l1_separated_cache_supported - whether l1 data and instruction cache + * topology are supported by the machine + * @l2_unified_cache_supported - whether l2 unified cache topology are + * supported by the machine + * @l3_unified_cache_supported - whether l3 unified cache topology are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -153,6 +160,9 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool l1_separated_cache_supported; + bool l2_unified_cache_supported; + bool l3_unified_cache_supported; } SMPCompatProps; /** @@ -358,6 +368,20 @@ typedef struct CPUTopology { unsigned int max_cpus; } CPUTopology; +/** + * CPUTopology: + * @l1d: the CPU topology hierarchy the L1 data cache is shared at. + * @l1i: the CPU topology hierarchy the L1 instruction cache is shared at. + * @l2: the CPU topology hierarchy the L2 (unified) cache is shared at. + * @l3: the CPU topology hierarchy the L3 (unified) cache is shared at. + */ +typedef struct CacheTopology { + CPUTopoLevel l1d; + CPUTopoLevel l1i; + CPUTopoLevel l2; + CPUTopoLevel l3; +} CacheTopology; + /** * MachineState: */ @@ -408,6 +432,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CPUTopology smp; + CacheTopology smp_cache; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; 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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 4/8] hw/core: Add cache topology options in -smp Date: Tue, 20 Feb 2024 17:25:00 +0800 Message-Id: <20240220092504.726064-5-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Add "l1d-cache", "l1i-cache". "l2-cache", and "l3-cache" options in -smp to define the cache topology for SMP system. Signed-off-by: Zhao Liu --- hw/core/machine-smp.c | 128 ++++++++++++++++++++++++++++++++++++++++++ hw/core/machine.c | 4 ++ qapi/machine.json | 14 ++++- system/vl.c | 15 +++++ 4 files changed, 160 insertions(+), 1 deletion(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 8a8296b0d05b..2cbd19f4aa57 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -61,6 +61,132 @@ static char *cpu_hierarchy_to_string(MachineState *ms) return g_string_free(s, false); } +static bool machine_check_topo_support(MachineState *ms, + CPUTopoLevel topo) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if (topo == CPU_TOPO_LEVEL_MODULE && !mc->smp_props.modules_supported) { + return false; + } + + if (topo == CPU_TOPO_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) { + return false; + } + + if (topo == CPU_TOPO_LEVEL_DIE && !mc->smp_props.dies_supported) { + return false; + } + + if (topo == CPU_TOPO_LEVEL_BOOK && !mc->smp_props.books_supported) { + return false; + } + + if (topo == CPU_TOPO_LEVEL_DRAWER && !mc->smp_props.drawers_supported) { + return false; + } + + return true; +} + +static int smp_cache_string_to_topology(MachineState *ms, + char *topo_str, + CPUTopoLevel *topo, + Error **errp) +{ + *topo = string_to_cpu_topo(topo_str); + + if (*topo == CPU_TOPO_LEVEL_MAX || *topo == CPU_TOPO_LEVEL_INVALID) { + error_setg(errp, "Invalid cache topology level: %s. The cache " + "topology should match the CPU topology level", topo_str); + return -1; + } + + if (!machine_check_topo_support(ms, *topo)) { + error_setg(errp, "Invalid cache topology level: %s. The topology " + "level is not supported by this machine", topo_str); + return -1; + } + + return 0; +} + +static void machine_parse_smp_cache_config(MachineState *ms, + const SMPConfiguration *config, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if (config->l1d_cache) { + if (!mc->smp_props.l1_separated_cache_supported) { + error_setg(errp, "L1 D-cache topology not " + "supported by this machine"); + return; + } + + if (smp_cache_string_to_topology(ms, config->l1d_cache, + &ms->smp_cache.l1d, errp)) { + return; + } + } + + if (config->l1i_cache) { + if (!mc->smp_props.l1_separated_cache_supported) { + error_setg(errp, "L1 I-cache topology not " + "supported by this machine"); + return; + } + + if (smp_cache_string_to_topology(ms, config->l1i_cache, + &ms->smp_cache.l1i, errp)) { + return; + } + } + + if (config->l2_cache) { + if (!mc->smp_props.l2_unified_cache_supported) { + error_setg(errp, "L2 cache topology not " + "supported by this machine"); + return; + } + + if (smp_cache_string_to_topology(ms, config->l2_cache, + &ms->smp_cache.l2, errp)) { + return; + } + + if (ms->smp_cache.l1d > ms->smp_cache.l2 || + ms->smp_cache.l1i > ms->smp_cache.l2) { + error_setg(errp, "Invalid L2 cache topology. " + "L2 cache topology level should not be " + "lower than L1 D-cache/L1 I-cache"); + return; + } + } + + if (config->l3_cache) { + if (!mc->smp_props.l2_unified_cache_supported) { + error_setg(errp, "L3 cache topology not " + "supported by this machine"); + return; + } + + if (smp_cache_string_to_topology(ms, config->l3_cache, + &ms->smp_cache.l3, errp)) { + return; + } + + if (ms->smp_cache.l1d > ms->smp_cache.l3 || + ms->smp_cache.l1i > ms->smp_cache.l3 || + ms->smp_cache.l2 > ms->smp_cache.l3) { + error_setg(errp, "Invalid L3 cache topology. " + "L3 cache topology level should not be " + "lower than L1 D-cache/L1 I-cache/L2 cache"); + return; + } + } +} + /* * machine_parse_smp_config: Generic function used to parse the given * SMP configuration @@ -249,6 +375,8 @@ void machine_parse_smp_config(MachineState *ms, mc->name, mc->max_cpus); return; } + + machine_parse_smp_cache_config(ms, config, errp); } unsigned int machine_topo_get_cores_per_socket(const MachineState *ms) diff --git a/hw/core/machine.c b/hw/core/machine.c index 426f71770a84..cb5173927b0d 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -886,6 +886,10 @@ static void machine_get_smp(Object *obj, Visitor *v, const char *name, .has_cores = true, .cores = ms->smp.cores, .has_threads = true, .threads = ms->smp.threads, .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, + .l1d_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l1d)), + .l1i_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l1i)), + .l2_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l2)), + .l3_cache = g_strdup(cpu_topo_to_string(ms->smp_cache.l3)), }; if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { diff --git a/qapi/machine.json b/qapi/machine.json index d0e7f1f615f3..0a923ac38803 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1650,6 +1650,14 @@ # # @threads: number of threads per core # +# @l1d-cache: topology hierarchy of L1 data cache (since 9.0) +# +# @l1i-cache: topology hierarchy of L1 instruction cache (since 9.0) +# +# @l2-cache: topology hierarchy of L2 unified cache (since 9.0) +# +# @l3-cache: topology hierarchy of L3 unified cache (since 9.0) +# # Since: 6.1 ## { 'struct': 'SMPConfiguration', 'data': { @@ -1662,7 +1670,11 @@ '*modules': 'int', '*cores': 'int', '*threads': 'int', - '*maxcpus': 'int' } } + '*maxcpus': 'int', + '*l1d-cache': 'str', + '*l1i-cache': 'str', + '*l2-cache': 'str', + '*l3-cache': 'str' } } ## # @x-query-irq: diff --git a/system/vl.c b/system/vl.c index a82555ae1558..ac95e5ddb656 100644 --- a/system/vl.c +++ b/system/vl.c @@ -741,6 +741,9 @@ static QemuOptsList qemu_smp_opts = { }, { .name = "clusters", .type = QEMU_OPT_NUMBER, + }, { + .name = "modules", + .type = QEMU_OPT_NUMBER, }, { .name = "cores", .type = QEMU_OPT_NUMBER, @@ -750,6 +753,18 @@ static QemuOptsList qemu_smp_opts = { }, { .name = "maxcpus", .type = QEMU_OPT_NUMBER, + }, { + .name = "l1d-cache", + .type = QEMU_OPT_STRING, + }, { + .name = "l1i-cache", + .type = QEMU_OPT_STRING, + }, { + .name = "l2-cache", + .type = QEMU_OPT_STRING, + }, { + .name = "l3-cache", + .type = QEMU_OPT_STRING, }, { /*End of list */ } }, From patchwork Tue Feb 20 09:25:01 2024 Content-Type: text/plain; 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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 5/8] i386/cpu: Support thread and module level cache topology Date: Tue, 20 Feb 2024 17:25:01 +0800 Message-Id: <20240220092504.726064-6-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Allows cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 725d7e70182d..d7cb0f1e49b4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -241,9 +241,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, uint32_t num_ids = 0; switch (share_level) { + case CPU_TOPO_LEVEL_THREAD: + num_ids = 1; + break; case CPU_TOPO_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPO_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPO_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -251,10 +257,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, num_ids = 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for SMT and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } From patchwork Tue Feb 20 09:25:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13563702 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CBD860DFF for ; Tue, 20 Feb 2024 09:12:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708420339; cv=none; b=Z70iFlreBs3ckeFtgFbM2uIDQk4MHvMI3vQgswt1g9fZbPLEH/MvCtQQEV03Y9Kk8hbiywkcWjQ6nuu72ZAAr2aRMr8Yl1H1WuYq/I5ZttpXw7gRT8IvNaSRFhHw37FW7GknL+AdcGeS8GHfmj7Kq40sB3KF5pxPMGnQ12ZuNis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708420339; c=relaxed/simple; bh=sh2QkQ5wss3HOjZ8fhY8YalRgTw6t25jX5kKa/RtD7I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jtzT+tv6ur+IPmK53KdI2Wy50cwyFfU16KvSwA8utOSqG1hr2O4jjmj77XgyxP0l2TsChLjT0NIE18tuNrgOumsFlGFX5gy+CmbA8dl4WlDj9ETytpNi5kkkqoDqCriuZMu4o4kWcHs0OihagsJGjgSegD1icPKRL4ah9QuRxzc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QnwjI3f0; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QnwjI3f0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708420338; x=1739956338; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sh2QkQ5wss3HOjZ8fhY8YalRgTw6t25jX5kKa/RtD7I=; b=QnwjI3f0fStjKHA/kYFW8iwpqD8zoAR+fkFnGKfypfSR2RQyEFDWH/wT 8X3ErEY/qWDt9njYB4jMm9LXpKnICtEeXvHUMZA2h4/BaXcJqHAuRC+X5 wuhB/PMpl4mi1kTusaj4DqZ91NGqlRsRXJGz5nQhHbcBeN+qK50fkZleq t0glfNMtuzMupVDYnqT161VZsq7buQUjf17+Qvh7Joq+/ZLiUSB/1Enxp aTF+En1NWZl+4WpC3UoKcMCTGEhmRU8bvpWakuXkVYmn6TAE6Ww21TpUn PiBcuiwUvWvMd/pfwnfLGenKuqF5Ml4ZY2FjLyCXAhDDqBmgNpOTR1aVA w==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2375019" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2375019" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 01:12:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="5013057" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa007.jf.intel.com with ESMTP; 20 Feb 2024 01:12:11 -0800 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 6/8] i386/cpu: Update cache topology with machine's configuration Date: Tue, 20 Feb 2024 17:25:02 +0800 Message-Id: <20240220092504.726064-7-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu User will configure SMP cache topology via -smp. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d7cb0f1e49b4..4b5c551fe7f0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7582,6 +7582,27 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + + if (ms->smp_cache.l1d != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l1d_cache->share_level = ms->smp_cache.l1d; + env->cache_info_amd.l1d_cache->share_level = ms->smp_cache.l1d; + } + + if (ms->smp_cache.l1i != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l1i_cache->share_level = ms->smp_cache.l1i; + env->cache_info_amd.l1i_cache->share_level = ms->smp_cache.l1i; + } + + if (ms->smp_cache.l2 != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l2_cache->share_level = ms->smp_cache.l2; + env->cache_info_amd.l2_cache->share_level = ms->smp_cache.l2; + } + + if (ms->smp_cache.l3 != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l3_cache->share_level = ms->smp_cache.l3; + env->cache_info_amd.l3_cache->share_level = ms->smp_cache.l3; + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { From patchwork Tue Feb 20 09:25:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13563703 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38286657B1 for ; Tue, 20 Feb 2024 09:12:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708420344; cv=none; b=M2ZYge+BTLYzEzSIwYtNiY1gmZyxfjH01XamvO5Y2vw8oZCq8f2JNNSuMiUZzD8ndt+ndVYFirqhsDqZOmyBhFmhUzdftMlX7hjkcEfbONvCznKyNyNEcGQ0T5wEg3Wm96rzLDW1wH61qLdnr0E5v2Icee5kGlp3CXjhrLK+Woo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708420344; c=relaxed/simple; bh=N8NOOJ+pARZ8UH7DHP7I4LRh9UGou9oDu+xcL8Vc/Rs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YCAUIzHRRQE5wg9RGUgZEKMzv/jTZYAWyUXY4BB9q7kFeb5sCVCSDoiiJyO127u1FVV90eLORW2SUO7QSZyuJbV79urMib5Shb2E+LQ9m93JsIZUDIDZBJDEcNE7NE0J+PCRffyxc4ImFjpmsbL19V11S+mnsj55zB20f55M6g8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=T5GcXKey; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="T5GcXKey" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708420343; x=1739956343; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N8NOOJ+pARZ8UH7DHP7I4LRh9UGou9oDu+xcL8Vc/Rs=; b=T5GcXKeyZ/8Ifo91q68wiPSBT5SI0nIb4gvcTpt5O3aN/B7dGxdl+swi qGqZbaYIOPBShHyRE/57nCg2ENxIt474jeoyrLjE21gR+Sv54QEO/9xua gKhLZZYi0AXg0M0kFV0ZXHxAQ9tRLTu3PLwZw9b3TGjBwpB8WHDpXJDLZ 9ewDliafsUDaFVxCe6+06rgGhN8mW3KnAdFbJ4xB85yEwDuETPFwlybcV TnmRh5AIqgm/WUl5SIE31IsUiQ6O9XhvWiN4StxGDErXwtKjDiCpkv8ld 2WaKNrgP0qBVXBzZ1Zq8GfpAssS169M711QRGrSNBD25TG+vA8NxRq2ZC Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2375027" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2375027" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 01:12:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="5013100" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa007.jf.intel.com with ESMTP; 20 Feb 2024 01:12:17 -0800 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 7/8] i386/pc: Support cache topology in -smp for PC machine Date: Tue, 20 Feb 2024 17:25:03 +0800 Message-Id: <20240220092504.726064-8-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Signed-off-by: Zhao Liu --- hw/i386/pc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 25124a077eea..76148c3337cf 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1848,6 +1848,9 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->nvdimm_supported = true; mc->smp_props.dies_supported = true; mc->smp_props.modules_supported = true; + mc->smp_props.l1_separated_cache_supported = true; + mc->smp_props.l2_unified_cache_supported = true; + mc->smp_props.l3_unified_cache_supported = true; mc->default_ram_id = "pc.ram"; pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; From patchwork Tue Feb 20 09:25:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13563704 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE2BE65BB8 for ; Tue, 20 Feb 2024 09:12:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708420350; cv=none; b=CyqgT0CzpjIv1nxWXZcJ/hV8wavuyWwx3uO4ZujJ33WKe1h3evfYur2VAR4rbkbCev4C02OGdBzhKitzBV5Pbb40OpywFnBuQXsCvPwqEy6qt1XnA0s+KW+RV5SHyrFZcib9lXfdRmMVHu5sE7ZRvkJsVn+9+Xim+/K8OhYzt1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708420350; c=relaxed/simple; bh=L0AbdOq+EtfWgzb7EW1UTRtjP/6zXcB3r698FBuEvgE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YqbZ9+I3k1AXsTpzi2B9qjpKHQhCY76X/oRQUE877LSaLG+9EQc/iT+bom2QawYgoLhoksoPzZMYkGvysmdQ1nq8JKc/o+9OINFe3n8Bk0SKDog/aCJ+UE1uKFGJJ3CNrNefJHckismTaWdUIc3n2//n+LqvMQ3cL7KTgxGPGW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WFiGKnlY; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WFiGKnlY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708420349; x=1739956349; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L0AbdOq+EtfWgzb7EW1UTRtjP/6zXcB3r698FBuEvgE=; b=WFiGKnlYYf/orMafjcKy3NLuCFxTVQKIHiDbTURI6fEHLyCmYlt2sDwf DVq0kqgwU7HaKjxF/VxyFquto0sXMOOryGspfEt8PNAJ56XleXd3pjG/V C7tBjDyCa/BUvzQ2NF+IvrdrhvVrfLRq8ka80wgn4UiW50cb87x5HKdq7 lsyM/waht5sLMhmwThl6RFNFZZdBqvs0MVewqOH9J5Twu6jlKr+UL7oqj 6+WW67K34Hcyw6yj0/l44CkmIKowEH2eV31dMXnASQ4mhnPIJj8wSi+Tk pFCXlU4q0EWlrOwiZvpUJMOSPeVZCEjZgYh4bsyKBKRoiYiCwv7DRPv/5 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2375051" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2375051" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 01:12:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="5013156" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa007.jf.intel.com with ESMTP; 20 Feb 2024 01:12:23 -0800 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 8/8] qemu-options: Add the cache topology description of -smp Date: Tue, 20 Feb 2024 17:25:04 +0800 Message-Id: <20240220092504.726064-9-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Signed-off-by: Zhao Liu --- qemu-options.hx | 54 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 47 insertions(+), 7 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 70eaf3256685..85c78c99a3b0 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -281,7 +281,9 @@ ERST DEF("smp", HAS_ARG, QEMU_OPTION_smp, "-smp [[cpus=]n][,maxcpus=maxcpus][,drawers=drawers][,books=books][,sockets=sockets]\n" - " [,dies=dies][,clusters=clusters][,cores=cores][,threads=threads]\n" + " [,dies=dies][,clusters=clusters][,modules=modules][,cores=cores]\n" + " [,threads=threads][,l1d-cache=level][,l1i-cache=level][,l2-cache=level]\n" + " [,l3-cache=level]\n" " set the number of initial CPUs to 'n' [default=1]\n" " maxcpus= maximum number of total CPUs, including\n" " offline CPUs for hotplug, etc\n" @@ -290,9 +292,14 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " sockets= number of sockets in one book\n" " dies= number of dies in one socket\n" " clusters= number of clusters in one die\n" - " cores= number of cores in one cluster\n" + " modules= number of modules in one cluster\n" + " cores= number of cores in one module\n" " threads= number of threads in one core\n" - "Note: Different machines may have different subsets of the CPU topology\n" + " l1d-cache= topology level of L1 D-cache\n" + " l1i-cache= topology level of L1 I-cache\n" + " l2-cache= topology level of L2 cache\n" + " l3-cache= topology level of L3 cache\n" + "Note: Different machines may have different subsets of the CPU and cache topology\n" " parameters supported, so the actual meaning of the supported parameters\n" " will vary accordingly. For example, for a machine type that supports a\n" " three-level CPU hierarchy of sockets/cores/threads, the parameters will\n" @@ -306,7 +313,7 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " must be set as 1 in the purpose of correct parsing.\n", QEMU_ARCH_ALL) SRST -``-smp [[cpus=]n][,maxcpus=maxcpus][,sockets=sockets][,dies=dies][,clusters=clusters][,cores=cores][,threads=threads]`` +``-smp [[cpus=]n][,maxcpus=maxcpus][,drawers=drawers][,books=books][,sockets=sockets][,dies=dies][,clusters=clusters][,modules=modules][,cores=cores][,threads=threads][,l1d-cache=level][,l1i-cache=level][,l2-cache=level][,l3-cache=level]`` Simulate a SMP system with '\ ``n``\ ' CPUs initially present on the machine type board. On boards supporting CPU hotplug, the optional '\ ``maxcpus``\ ' parameter can be set to enable further CPUs to be @@ -320,15 +327,34 @@ SRST Both parameters are subject to an upper limit that is determined by the specific machine type chosen. + CPU topology parameters include '\ ``drawers``\ ', '\ ``books``\ ', + '\ ``sockets``\ ', '\ ``dies``\ ', '\ ``clusters``\ ', '\ ``modules``\ ', + '\ ``cores``\ ' and '\ ``threads``\ '. These CPU parameters accept only + integers and are used to specify the number of specific topology domains + under the corresponding topology level. + To control reporting of CPU topology information, values of the topology parameters can be specified. Machines may only support a subset of the - parameters and different machines may have different subsets supported - which vary depending on capacity of the corresponding CPU targets. So - for a particular machine type board, an expected topology hierarchy can + CPU topology parameters and different machines may have different subsets + supported which vary depending on capacity of the corresponding CPU targets. + So for a particular machine type board, an expected topology hierarchy can be defined through the supported sub-option. Unsupported parameters can also be provided in addition to the sub-option, but their values must be set as 1 in the purpose of correct parsing. + Cache topology parameters include '\ ``l1d-cache``\ ', '\ ``l1i-cache``\ ', + '\ ``l2-cache``\ ' and '\ ``l3-cache``\ '. These cache topology parameters + accept the strings of CPU topology levels (such as '\ ``drawer``\ ', '\ ``book``\ ', + '\ ``socket``\ ', '\ ``die``\ ', '\ ``cluster``\ ', '\ ``module``\ ', + '\ ``core``\ ' or '\ ``thread``\ '). Exactly which topology level strings + could be accepted as the parameter depends on the machine's support for the + corresponding CPU topology level. + + Machines may also only support a subset of the cache topology parameters. + Unsupported cache topology parameters will be omitted, and correspondingly, + the target CPU's cache topology will use the its default cache topology + setting. + Either the initial CPU count, or at least one of the topology parameters must be specified. The specified parameters must be greater than zero, explicit configuration like "cpus=0" is not allowed. Values for any @@ -354,6 +380,20 @@ SRST -smp 32,sockets=2,dies=2,modules=2,cores=2,threads=2,maxcpus=32 + The following sub-option defines a CPU topology hierarchy (2 sockets + totally on the machine, 2 dies per socket, 2 modules per die, 2 cores per + module, 2 threads per core) with 3-level cache topology hierarchy (L1 + D-cache per core, L1 I-cache per core, L2 cache per core and L3 cache per + die) for PC machines which support sockets/dies/modules/cores/threads. + Some members of the CPU topology option can be omitted but their values + will be automatically computed. Some members of the cache topology + option can also be omitted and target CPU will use the default topology.: + + :: + + -smp 32,sockets=2,dies=2,modules=2,cores=2,threads=2,maxcpus=32,\ + l1d-cache=core,l1i-cache=core,l2-cache=core,l3-cache=die + The following sub-option defines a CPU topology hierarchy (2 sockets totally on the machine, 2 clusters per socket, 2 cores per cluster, 2 threads per core) for ARM virt machines which support sockets/clusters